 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| preliminary release mobile amd duron processor model 7 data sheet publication # 24068 rev: f issue date: december 2001 tm featuring:
preliminary release trademarks amd, the amd arrow logo, amd athlon, amd duron, and combinations thereof, amd powernow!, and 3dnow! are trademarks of advanced micro devices, inc. hypertransport is a trademark of the hypertransport technology corporation. mmx is a trademark of intel corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2001 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amd?s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. table of contents iii 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information contents list of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 mobile amd duron? processor model 7 upgrades versus the mobile amd duron processor model 3 . . . . . . . . . . . . . . . 2 1.2 mobile amd duron processor model 7 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 signaling technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 push-pull (pp) drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 amd duron system bus signals . . . . . . . . . . . . . . . . . . . . . . . . 6 3 logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 working state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 stop grant states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 probe state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 fid_change state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 processor performance states and the fid_change protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 connect and disconnect protocol . . . . . . . . . . . . . . . . . . . . . . 18 connect protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 connect state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 sysclk multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 cpuid support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.2 interface signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.3 soft voltage identification (softvid[4:0]) . . . . . . . . . . . . . 35 7.4 frequency identification (fid[3:0]) . . . . . . . . . . . . . . . . . . . . 35 7.5 vcca ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . 35 iv table of contents mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 7.6 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.7 valid voltage and frequency combinations . . . . . . . . . . . . . 36 7.8 vcc_core ac and dc characteristics . . . . . . . . . . . . . . . . 37 7.9 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.10 vcc_core voltage and current . . . . . . . . . . . . . . . . . . . . . . 40 7.11 sysclk and sysclk# ac and dc characteristics . . . . . . 41 7.12 amd duron system bus ac and dc characteristics . . . . . . 43 7.13 general ac and dc characteristics . . . . . . . . . . . . . . . . . . . . 45 7.14 open drain test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.15 thermal diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48 7.16 reserved pins dc characteristics . . . . . . . . . . . . . . . . . . . . . 51 7.17 fid_change induced pll lock time . . . . . . . . . . . . . . . . . . 52 8 signal and power-up requirements . . . . . . . . . . . . . . . . . . . . 53 8.1 power-up requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 signal sequence and timing description . . . . . . . . . . . . . . . . 53 clock multiplier selection (fid[3:0]) . . . . . . . . . . . . . . . . . . . 56 8.2 processor warm reset requirements . . . . . . . . . . . . . . . . . . 56 mobile amd duron processor model 7 and northbridge reset pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2 die loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.1 pin diagram and pin name abbreviations . . . . . . . . . . . . . . 61 10.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.3 detailed pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 a20m# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 amd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 amd duron system bus pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78 analog pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 clkfwdrst pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 clkin and rstclk (sysclk) pins . . . . . . . . . . . . . . . . . . . 78 connect pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 corefb and corefb# pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78 cpu_presence# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 dbrdy and dbreq# pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ferr pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 fid[3:0] pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 flush# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ignne# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 init# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 intr pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 k7clkout and k7clkout# pins. . . . . . . . . . . . . . . . . . . . . 80 table of contents v 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information key pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 nc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 nmi pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 pga orientation pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 pll bypass and test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 pwrok pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 rsvd pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 saddin[1:0]# and saddout[1:0]# pins . . . . . . . . . . . . . . . . 81 scan pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 smi# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 softvid[4:0] and vid[4:0] pins. . . . . . . . . . . . . . . . . . . . . . . 81 stpclk# pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 sysclk and sysclk#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 thermda and thermdc pins . . . . . . . . . . . . . . . . . . . . . . . 83 vcca pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 vref_sys pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 zn and zp pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.1 standard mobile amd duron processor model 7 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 appendix a conventions, abbreviations, and references . . . . . . . . . . . . . . . . . . . . 87 signals and bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 data terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 abbreviations and acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 related publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 amd publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 websites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 vi table of contents mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information list of figures vii 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information list of figures figure 1. typical mobile amd duron? processor model 7 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. mobile amd duron processor model 7 power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. softvid transition during the amd duron system bus disconnect for fid_change . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. amd duron system bus disconnect sequence in the stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6. exiting the stop grant state and bus connect sequence . . . . 21 figure 7. northbridge connect state diagram . . . . . . . . . . . . . . . . . . . . . 22 figure 8. processor connect state diagram . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. vcc_core voltage waveform . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 10. sysclk and sysclk# differential clock signals . . . . . . . . . 41 figure 11. sysclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12. general ate open drain test circuit. . . . . . . . . . . . . . . . . . . . 47 figure 13. signal relationship requirements during power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 14. mobile amd duron processor model 7 cpga package. . . . . . 59 figure 15. mobile amd duron processor model 7 pin diagram? topside view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 16. mobile amd duron processor model 7 pin diagram? bottomside view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 17. opn example for the mobile amd duron processor model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 viii list of figures mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information list of tables ix 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information list of tables table 1. fid[4:0] sysclk multiplier combinations . . . . . . . . . . . . . . . 25 table 2. processor special cycle definition . . . . . . . . . . . . . . . . . . . . . . 27 table 3. thermal design power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4. interface signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5. softvid[4:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 35 table 6. fid[3:0] dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7. vcca ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 35 table 8. valid voltage and frequency combinations . . . . . . . . . . . . . . 36 table 9. vcc_core ac and dc characteristics . . . . . . . . . . . . . . . . . . 37 table 10. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. vcc_core voltage and current. . . . . . . . . . . . . . . . . . . . . . . . 40 table 12. sysclk and sysclk# dc characteristics . . . . . . . . . . . . . . . 41 table 13. sysclk and sysclk# ac characteristics . . . . . . . . . . . . . . . 42 table 14. amd duron? system bus dc characteristics . . . . . . . . . . . . . 43 table 15. amd duron system bus ac characteristics . . . . . . . . . . . . . . . 44 table 16. general ac and dc characteristics . . . . . . . . . . . . . . . . . . . . . . 45 table 17. thermal diode electrical characteristics . . . . . . . . . . . . . . . . . 48 table 18. guidelines for platform thermal protection of the processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 19. reserved pins (n1, n3, and n5) dc characteristics . . . . . . . . 51 table 20. fid_change induced pll lock time . . . . . . . . . . . . . . . . . . . . 52 table 21. cpga mechanical loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 22. dimensions for the cpga package . . . . . . . . . . . . . . . . . . . . . . 58 table 23. pin name abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 24. cross-reference by pin location . . . . . . . . . . . . . . . . . . . . . . . . 70 table 25. softvid[4:0] and vid[4:0] code to voltage definition. . . . . 82 table 26. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 27. acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 x list of tables mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information revision history xi 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information revision history date rev description december 2001 f updated data sheet for the 1.0 ghz amd duron processor model 7 release. revised the following sections: table 3, ?thermal design power,? on page 31 table 8, ?valid voltage and frequency combinations,? on page 36 table 11, ?vcc_core voltage and current,? on page 40 ?ordering information? on page 85 november 2001 e revised ?thermal protection characterization? on page 49. november 2001 d updated data sheet for the 950 mhz amd duron processor model 7 release. revised the following sections: ?processor performance states and the fid_change protocol? on page 12 ?sysclk multipliers? on page 24 ?thermal diode characteristics? on page 48 figure 13, ?signal relationship requirements during power-up sequence? on page 53 ?power-up timing requirements? on page 54 ?clock multiplier selectio n (fid[3:0])? on page 56 added the following sections and figures: ?open drain test circuit? and figure 12, ?general ate open drain test circuit? on page 47. ?thermal protection characterization? on page 49 and table 18, ?guidelines for platform thermal protection of the processor,? on page 51 september 2001 c updated figure 9 on page 38. august 2001 b initial public release. xii revision history mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information chapter 1 overview 1 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 1 overview the mobile amd duron? processor model 7 enables an optimized pc solution for value-consci ous business and home users by providing the capability and flexibility to meet their computing needs for both today and tomorrow. the mobile amd duron? processor model 7 is the latest offering from amd designed for the value segment of the notebook pc market. the innovative design was developed to accommodate new and more advanced applications, meeting the requirements of today's mo st demanding value-conscious buyers without compromising their budget. model 7 is the cpu model number returned by the cpuid instruction for this processor. see chapter 5, ?c puid support? on page 29 for more information. delivered in a cpga package, the mobile amd duron processor model 7 is the new amd workhorse processor for value notebook systems, delivering high performance integer, floating-point and 3d multimed ia capabilities for applications running on notebook pc platforms. the mobile amd duron processor model 7 provides value-conscious customers with access to advanced technology that allows their system investment to last for years to come. whether at work or at play, the mobile amd duron processor model 7 provides an optimum balance of performance and value for today?s advanced oper ating system software, business productivity applications, internet computing and digital entertainment. the mobile amd duron processor model 7 features a seventh-generation microarchitecture with a full-speed integrated l2 cache, which supports the growing processor and system bandwidth requirements of emerging software, graphics, i/o, and memory technologies. the high-speed execution core of the processor includes multiple x86 instruction decoders, a dual-ported 128-kbyte split level-one (l1) cache, a 64-kbyte on-chi p l2 cache, three independent integer pipelines, three address calculation pipelines, and a superscalar, fully pipelined, out-of-order, three-way floating-point engine. the floati ng-point engine is capable of delivering 4.0 gigaflops (gflops) of single-precision and more than 2.0 gflops of double-prec ision floating-point results at 2 overview chapter 1 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 1.0 ghz, for superior performance on numerically complex applications. this processor incorporates amd powernow!? technology, enabling performance and power saving modes specifically for notebook designs and is available in a low-profile, lidless cpga package. the mobile amd duron processor model 7 microarchitecture incorporates amd?s 3dnow!? professional technology, a high-performance cache architecture, and the 200-mhz 1.6-gigabyte per second amd duron system bus. the amd duron system bus combines the latest technological advances, such as point-to-point topology, source-synchronous packet-based transfers, and low- voltage signaling, to provide a powerful, scalable bus architecture. the mobile amd duron processor model 7 is binary-compatible with existing x86 software a nd substantially compatible with applications optimized for 3d now! professional, mmx?, and sse instructions. amd?s 3dnow! professional technology implemented in the mobile amd duron processor model 7 includes new integer mult imedia instructions and software-directed data moveme nt instructions to deliver exceptional performance in multimedia applications. 1.1 mobile amd duron? processor model 7 upgrades versus the mobile amd duron? processor model 3 the following features summarize the mobile amd duron processor model 7 feature upgrades and differences from the mobile amd duron processor model 3: amd powernow! technology for improved battery life ? model specific registers (m srs) and softvid and fid control pins which are compatible with the mobile amd athlon? processor model 6 automatic load sense redesigned core, optimized for lower power and improved frequency scalability on-die temperature sensing diode chapter 1 overview 3 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 1.2 mobile amd duron? processo r model 7 microarchitecture summary the following features summarize the mobile amd duron processor model 7 microarchitecture: performance on demand and extended battery life specifically for notebook designs with amd powernow! technology the industry's first nine-issue , superpipelined, superscalar x86 processor microarchitecture designed for high clock frequencies multiple x86 instruction decoders three out-of-order, superscalar, fully pipelined floating-point execution uni ts, which execute all x87 (floating-point), sse, mmx, and 3dnow! professional instructions three out-of-order, superscalar, pipelined integer units three out-of-order, superscalar, pipelined address calculation units 72-entry instruction control unit advanced dynamic branch prediction 3dnow! professional technology with added instructions to enable improved integer math calculations for speech or video encoding and improved data movement for internet plug-ins and other st reaming applications 200-mhz amd duron system bus for high-performance main memory access, multimedia, graphics, and i/o high-performance cache architecture featuring an integrated 128-kbyte l1 cache and a 16-way, on-chip 64-kbyte l2 cache 4 overview chapter 1 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information the mobile amd duron processor model 7 delivers superior notebook pc system performance in a cost-effective, industry-standard socket a comp atible 462-pin cpga package. figure 1 shows a typical mobile amd duron processor model 7 system block diagram. figure 1. typical mobile amd duron? processor model 7 system block diagram sdram or ddr agp bus memory bus agp pci bus lan pc card isa or lpc usb dual eide mobile amd duron? processor model 7 system controller (northbridge) peripheral bus controller (southbridge) docking controller modem / audio programmable voltage regulator thermal monitor amd duron battery super i/o embedded controller system bus chapter 2 interface signals 5 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 2 interface signals 2.1 overview the amd duron? system bus architecture is designed to deliver excellent data movement bandwidth for next- generation x86 platforms as well as the high-performance required by enterprise-class ap plication software. the system bus architecture consists of three high-speed channels (a unidirectional processor reque st channel, a unidirectional probe channel, and a 72-bit bidirectional data channel), source-synchronous clocking, a nd a packet-based protocol. in addition, the system bus supports several control, clock, and legacy signals. the interface signals use an impedance controlled push-pull, low-voltage, swing-signaling technology contained within the socket a socket. for more information, see ?amd duron? system bus signals? on page 6, chapter 10, ?pin descriptions? on page 61, and the amd athlon? and amd duron? system bus specification , order# 21902. 2.2 signaling technology the amd duron system bus uses a low-voltage, swing-signaling technology, that has been enhanced to provide larger noise margins, reduced ringing, and variable voltage levels. the signals are push-pull and impe dance compensated. the signal inputs use differential receivers that require a reference voltage (v ref ). the reference signal is used by the receivers to determine if a signal is asserted or deasserted by the source. termination resistors are not needed because the driver is impedance-matched to the motherboard and a high impedance reflection is used at the receiv er to bring the signal past the input threshold. for more information about pins and signals, see chapter 10, ?pin descriptions? on page 61. 6 interface signals chapter 2 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 2.3 push-pull (pp) drivers the mobile amd duron processo r model 7 supports push-pull (pp) drivers. the system logic configures the processor with the configuration para meter called syspushpull (1=pp). the impedance of the pp drivers is set to match the impedance of the motherboard by two external resistors connected to the zn and zp pins. see ?zn and zp pins? on page 83 for more information. 2.4 amd duron? system bus signals the amd duron system bus is a clock-forwarded, point-to-point interface with the following three point-to-point channels: a 13-bit unidirectional out put address/command channel a 13-bit unidirectional i nput address/command channel a 72-bit bidirectio nal data channel for more information, see chapter 7, ?electrical data? on page 33 and the amd athlon? and amd duron? system bus specification , order# 21902. chapter 3 logic symbol diagram 7 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 3 logic symbol diagram figure 2 is the logic symbol diagram of the processor. this diagram shows the logical grouping of the input and output signals. figure 2. logic symbol diagram sdata[63:0]# sdatainclk[3:0]# sdataoutclk[3:0]# data saddin[14:2]# saddinclk# probe/syscmd saddout[14:2]# saddoutclk# vid[4:0] fid[3:0] a20m# clkfwdrst connect corefb corefb# ferr ignne# init# intr nmi procrdy pwrok reset# sfillvalid# smi# stpclk# sysclk# sysclk clock voltage control frequency control legacy request mobile amd duron? processor model 7 sdatainvalid# sdataoutvalid# power and initialization management thermal diode thermda thermdc flush# softvid[4:0] 8 logic symbol diagram chapter 3 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information chapter 4 power management 9 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 4 power management this chapter describes the power management features of the mobile amd duron? processor model 7. the power management features of the pr ocessor are compliant with the acpi 1.0b and acpi 2.0 specifications and support amd powernow!? technology. 4.1 power management states the mobile amd duron? processor model 7 has a variety of operating states that are design ed to support different power management goals. in addition to the standard operating state, the processor supports low-powe r halt and stop grant states and the fid_change state. these states are used by advanced configuration and power interface (acpi) enabled operating systems, for processor power management. amd powernow! software is used to control processor performance states with operating systems that do not support acpi 2.0-defined processor performance state control. figure 3 on page 10 shows the power management states of the processor. the figure incl udes the acpi ?cx? naming convention for these states. 10 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information figure 3. mobile amd duron? processor model 7 power management states the following sections provide an overview of the power management states. for more details, refer to the amd athlon? and amd duron? system bus specification, order# 21902 . note: in all power management sta tes that the processor is powered, the system must not stop the system clock (sysclk/sysclk#) to the processor. working state the working state is the state in which the processor is executing instructions. halt state when the processor executes the hlt instruction, the processor enters the halt state and issues a halt special cycle to the amd duron system bus. the processor only enters the low power state dictated by the clk_ctl msr if the system controller (northbridge) disconnects th e amd duron system bus in response to the halt special cycle. c1 halt c0 working 4 execute hlt smi#, intr, nmi, init#, reset# incoming probe p r o b e s e r v i c e d stpclk# asserted s t p c l k # a s s e r t e d 2 s t p c l k # d e a s s e r t e d 3 c2 stop grant cache snoopable incoming probe probe serviced probe state 1 stpclk# deasserted (read plvl2 register or throttling) c3/s1 stop grant cache not snoopable sleep s t p c l k # a s s e r t e d s t p c l k # d e a s s e r t e d fid_change write to fidvidctl msr sip stream and system bus connect note: the amd duron tm system bus is connected during the following states: 1) the probe state 2) during transitions between the halt state and the c2 stop grant state 3) during transitions between the c2 stop grant state and the halt state 4) c0 working state software transitions hardware transitions legend chapter 4 power management 11 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information if stpclk# is asserted, the proc essor will exit the halt state and enter the stop grant state. the processor will initiate a system bus connect, if it is disconnected, then issue a stop grant special cycle. when stpclk# is deasserted, the processor will exit the stop grant state and re-enter the halt state. the processor will issue a halt special cycle when re-entering the halt state. the halt state is exited when the processor detects the assertion of init#, intr, nmi, reset#, or smi#. when the halt state is exited the processor will initiate an amd duron system bus connect if it is disconnected. stop grant states when the processor executes the hlt instruction, the processor enters the halt state and issues a halt special cycle to the amd duron system bus. the processor only enters the low power state dictated by the clk_ctl msr if the system controller (northbridge) disconnects the amd duron system bus in response to the halt special cycle. if stpclk# is asserted, the proc essor will exit the halt state and enter the stop grant state. the processor will initiate a system bus connect, if it is disconnected, then issue a stop grant special cycle. when stpclk# is deasserted, the processor will exit the stop grant state and re-enter the halt state. the processor will issue a halt special cycle when re-entering the halt state. the halt state is exited when the processor detects the assertion of init#, intr, nmi, reset#, or smi#. when the halt state is exited the processor will initiate an amd duron system bus connect if it is disconnected. in c2, probes are allowed, as shown in figure 3 on page 10. the operating system places th e processor into the c3 stop grant state by reading the p_lvl3 register in the southbridge. in c3, the operating system an d northbridge hardware enforce a policy that prevents the processor from being probed. the southbridge will deassert st pclk# and bring the processor out of the c3 stop grant state if a bus master request, interrupt, or any other enabled resume event occurs. the stop grant state is also entered for the s1, powered on suspend, system sleep state ba sed on a write to the slp_typ 12 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information and slp_en fields in the ac pi-defined power management 1 control register in the southbrid ge. during the s1 sleep state, system software ensures no bus master or probe activity occurs. the southbridge deasserts stpc lk# and brings the processor out of the s1 stop grant state when any enabled resume event occurs. probe state the probe state is entered when the northbridge connects the amd duron system bus to probe the processor (for example, to snoop the processor caches) when the processor is in the halt or stop grant state. when in the probe state, the processor responds to a probe cycle in th e same manner as when it is in the working state. when the probe has been serviced, the processor returns to the same state as when it entered the probe state (halt or stop grant state). when probe activity is completed the processor only returns to a low-power state after the northbridge disc onnects the amd duron system bus again. fid_change state the fid_change state is part of the amd duron system bus fid_change protocol. duri ng the fid_change state the frequency identification (fid[4:0]) code that determines the core frequency of the processor and voltage identification (vid[4:0]) driven on the softvid[4:0] pins are transitioned to change the core frequency and core voltage of the processor. note: the fid[3:0] pins of the processor do not transition as part of the fid_change protocol. processor performance states and the fid_change protocol the fid_change protocol is used by amd powernow! software to transition the processor from one performance state to another. the fid_change protoc ol is also used for acpi 2.0-compliant processor performance state control. processor performance states are combinations of processor core voltage and core frequency. processor performance states are used in mobile systems to optimize the power consumption of the processor (and therefore battery powered run-time) based upon processor utilization. see ?valid voltage and freque ncy combinations? on page 36 for more information. the core frequency is determined by a 5-bit frequency id (fid) code. the core voltage is determined by a 5-bit voltage id (vid) code. chapter 4 power management 13 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information before pwrok is asserted to the processor, the vid[4:0] outputs of the processor dictate the core voltage level of the processor. after pwrok is asserted, the core voltage of the processor is dictated by the softvid[4:0] outputs. the softvid[4:0] outputs of the processor are not driven to a deterministic value until after pwrok is asserted to the processor. the motherboard therefore must provide a ?vid multiplexer? to drive the vid[4:0] outputs to the dc/dc converter for the core voltage of the processor before pwrok is asserted and drive the softvid[4:0] outputs to the dc to dc converter after pwrok is asserted. the fid[3:0] signals are valid after pwrok is asserted. the chipset must not sample the fid[3:0] signals until they become valid. after reset# is deasserted, the fid[3:0] outputs are not used to transmit fid inform ation for subsequent software controlled changes in the operating frequency of the processor. processor performance state transitions are required to occur as two separate transitions. the order of these transitions depends on whether the transition is to a higher or lower performance state. when transitioning from a lower performance state to a higher performance state the order of the transitions is: 1. the fid_change protocol is used to transition to the higher voltage, while keeping the frequency fixed at the current setting. 2. the fid_change protocol is then used to transition to the higher frequency, while keeping the voltage fixed at the higher setting. when transitioning from a high performance state to a lower performance state the order of the transitions is: 1. the fid_change protocol is used to transition to the lower frequency, while keeping the voltage fixed at its current setting. 2. the fid_change protocol is then used to transition to the lower voltage, while keeping the frequency fixed at the lower setting. the processor provides two msrs to support the fid_change protocol: the fidvidctl msr and the 14 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information fidvidstatus msr. for a definition of these msrs and their use, refer to the mobile amd athlon? and mobile amd duron? processors bios developers application note , order# 24141. fid_change protocol description by example: note: in any fid_change transition only the core voltage or core frequency of the processor is transitioned. two fid_change transitions are required to transition the voltage and frequency to a valid performance state. when the voltage is being transitioned, the frequency is held constant by transitioning to the same fid[3:0] as the current fid reported in the fidvidstatus msr. for detailed information on the optimized voltage and frequency combinations, see ?valid voltage and frequency combinations? on page 36. system software determines that a change in processor performance state is required. system software executes a wrmsr instruction to write to the fidvidctl msr to dictate: the new vid[4:0] code that will be driven to the dc/dc converter from the softvid[4:0] outputs of the processor that selects the new core voltage level. the new fid[4:0] code that will be used by the processor to dictate its new operating frequency. a stop grant timout count (sgtc)[19:0] value that determines how many sysclk/sysclk# 100-mhz clock periods the processor will remain in the fid_change state. this time accounts for th e time that it takes for the pll of the processor to lock to the new core frequency and the time that it takes for the core voltage of the processor to ramp to the new value. the fidchgratio bit must be set to 1. the vidc bit must be set to a 1 if the voltage is going to be changed. the fidc bit must be set to a 1 if the frequency is going to be changed. writing the sgtc field to a non-zero value initiates the fid_change protocol. chapter 4 power management 15 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information on the instruction boundary th at the sgtc field of the fidvidctl msr is written to a non-zero value, the processor stops code execution and issues a fid_change special cycle on the amd duron system bus. the fid_change special cycle has a data encoding of 0007_0002h that is passed on sdata[31:0]. sdata[36:32] contain the new fid[4:0] code during the fid_change special cycle. the northbridge is required to capture this fid[4:0] code when the fid_change special cycle is run. in response to receiving the fid_change special cycle, the northbridge is required to di sconnect. the northbridge will complete any in-progress bus cycles and then disable its arbiter before disconnecting the amd duron system bus so that it will not initiate a amd duron system bus connect based on bus master or other activity. the northbridge must disconnect the amd duron syst em bus or the system will hang because the processor is not executing any operating system or application code and is waiting for the amd duron system bus to disco nnect so that it can continue with the fid_change protocol. the northbridge initiates an amd duron system bus disconnect in the usual manner: it deasserts connect. the processor allows the disconnect to complete by deasserting procrdy. the northbridge completes the disconnect by asserting clkfwdrst. once the amd duron system bus has been disconnected in response to a fid_change special cycle, the northbridge is not allowed to initiate a re-connect, the processor is responsible for the eventual re-connect. after the amd duron system bus is disconnected, the processor enters a low-power state where the clock grid is ramped down by a value specified in the clk_ctl msr. after entering the low-power state, the processor will: begin counting down the va lue that was programmed into the sgtc field drive the new vid[4:0] value on softvid[4:0], causing its core voltage to transition drive the new fid[4:0] value to its pll, causing the pll to lock to the new core frequency. 16 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information when the sgtc count reaches zero, the processor will ramp its entire clock grid to full frequency (the pll is already locked to) and signal that it is ready for the northbridge to transmit the new sip (serial initialization protocol) stream associated with the new processor core operating frequency. the processor signals this by pulsing procrdy high and then low. the northbridge responds to this high pulse on procrdy by pulsing clkfwdrst low and then transferring a sip stream as it does after procrdy is deasserted after the deassertion of reset#. the difference is that the sip stream that the northbridge transmits to the processor now corresponds to the fid[4:0] that was transmitted on sdata[36:32] during the fid_change special cycle. after the sip stream is transmitted, the processor initiates the amd duron system bus co nnect sequence by asserting procrdy. the northbridge responds by deasserting clkfwdrst. the forward clocks are started and the processor issues a connect special cycle. the amd duron system bus conne ction causes the processor to resume execution of operating system and application code at the instruction that follows the wrmsr to the fidvidctl msr that started the fid_change protocol and processor performance state transition. chapter 4 power management 17 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information figure 4 below illustrates the processor softvid transition during the amd duron system bus disconnect in response to a fid_change special cycle. figure 4. softvid transition during the amd duron? system bus disconnect for fid_change 1.4 v cpucorevcc 1.2 v softvid[4:0] from the processor vid combination that selects 1.2 v < 100 s procrdy connect clkfwdrst vid combination that selects 1.4 v the processor core frequency changes and new softvid[4:0] values are driven after the system bus interface disconnect occurs and the processor has entered a low power state. the duration of the disconnect is dictated by software programming the fidvidcontrol msr in the processor. 18 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 4.2 connect and disconnect protocol significant power savings of th e processor only occur if the processor is disconnected from the system bus by the northbridge while in the halt or stop gr ant state. the northbridge can optionally initiate a bus disconne ct upon the receipt of a halt or stop grant special cycle. the option of disconnecting is controlled by an enable bit in the northbridge. if the northbridge requires the processor to service a prob e after the system bus has been disconnected, it must first in itiate a system bus connect. connect protocol in addition to the legacy stpclk# signal and the halt and stop grant special cycles, the amd duron system bus connect protocol includes the connect, procrdy, and clkfwdrst signals and a connect special cycle. amd duron system bus discon nects are initiated by the northbridge in response to the re ceipt of a halt, stop grant, or fid_change special cycle. reconnect is initiated by the processor in response to an interrupt fo r halt, stpclk# deassertion, or completion of a fid_change transi tion. reconnect is initiated by the northbridge to probe the processor. the northbridge contains bios programmable registers to enable the system bus disconnect in response to halt and stop grant special cycles. when the northbridge receives the halt or stop grant special cycle from the processor and, if there are no outstanding probes or data movements, the northbridge d easserts connect a minimum of eight sysclk periods after th e last command sent to the processor. the processor detects the deassertion of connect on a rising edge of sysclk a nd deasserts procrdy to the northbridge. in return, the no rthbridge asserts clkfwdrst in anticipation of reestablishing a connection at some later point. note: the northbridge must disconnect the processor from the amd duron system bus before issuing the stop grant special cycle to the pci bus or passing the stop grant special cycle to the southbridge for systems that connect to the southbridge with hypertransport? technology. this note applies to current chipset implementation? alternate chipset implementations that do not require this are possible. note: in response to halt special cy cles, the northbridge passes the halt special cycle to the pci bus or southbridge immediately. chapter 4 power management 19 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information the processor can receive an interrupt after it sends a halt special cycle, or stpclk# deassertion after it sends a stop grant special cycle to the northbridge but before the disconnect actually occurs. in th is case, the processor sends the connect special cycle to the northbridge, rather than continuing with the disconnect sequence. in response to the connect special cycle, the nort hbridge cancels the disconnect request. the system is required to assert the connect signal before returning the c-bit for the connect special cycle (assuming connect has been deasserted). for more information, see the amd athlon? and amd duron? system bus specification , order# 21902 for the definition of the c-bit and the connect special cycle. 20 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information figure 5 shows stpclk# assertion resulting in the processor in the stop grant state and the amd dur on system bus disconnected. figure 5. amd duron? system bus disconnect sequence in the stop grant state an example of the amd duron syst em bus disconnect sequence is as follows: 1. the peripheral controller (sou thbridge) asserts stpclk# to place the processor in the stop grant state. 2. when the processor recognizes stpclk# asserted, it enters the stop grant state and then issu es a stop grant special cycle. 3. when the special cycle is received by the northbridge, it deasserts connect, assuming no probes are pending, initiating a bus disconnect to the processor. 4. the processor responds to the northbridge by deasserting procrdy. 5. the northbridge asserts clkfwdrst to complete the bus disconnect sequence. 6. after the processor is disconnected from the bus, the processor enters a low-power state. the northbridge passes the stop grant special cycle along to the southbridge. stop grant stop grant stpclk# connect procrdy clkfwdrst pci bus amd duron? system bus chapter 4 power management 21 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information figure 6 shows the signal sequence of events that takes the processor out of the stop grant stat e, connects the processor to the amd duron system bus, and puts the processor into the working state. figure 6. exiting the stop grant state and bus connect sequence the following sequence of events removes the processor from the stop grant state and connect s it to the system bus: 1. the southbridge deasserts stpclk#, informing the processor of a wake event. 2. when the processor recognizes stpclk# deassertion, it exits the low-power state and asserts procrdy, notifying the northbridge to connect to the bus. 3. the northbridge asserts connect. 4. the northbridge deasserts cl kfwdrst, synchronizing the forwarded clocks between the processor and the northbridge. 5. the processor issues a connect special cycle on the system bus and resumes operating system a nd application co de execution. st pclk # procrdy connect clkfwdrst 22 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information connect state diagram figure 7 and figure 8 on page 23 describe the northbridge and processor connect state diagrams, respectively. figure 7. northbridge connect state diagram condition 1 a disconnect is requested and probes are still pending. 2 a disconnect is requested and no probes are pending. 3 a connect special cycle from the processor. 4 no probes are pending. 5 procrdy is deasserted. 6 a probe needs service. 7 procrdy is asserted. 8 three sysclk periods after clkfwdrst is deasserted. although reconnected to the system interface, the northbridge must not issue any non-nop sysdc commands for a minimum of four sysclk periods after deasserting clkfwdrst . action a deassert connect eight sysclk periods after last sysdc sent. bassert clkfwdrst. c assert connect. d deassert clkfwdrst. disconnect pending connect disconnect requested reconnect pending probe pending 2 disconnect probe pending 1 1 3 2/a 4/a 5/b 3/c 7/d,c 8 6/c 7/d 8 chapter 4 power management 23 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information figure 8. processor connect state diagram condition 1 connect is deasserted by the northbridge (for a previously sent halt or stop grant special cycle). 2 processor receives a wake- up event and must cancel the disconnect request. 3 deassert procrdy and slow down internal clocks. 4 processor wake-up event or connect asserted by northbridge. 5 clkfwdrst is deasserted by the northbridge. 6 forward clocks start three sysclk periods after clkfwdrst is deasserted. action a clkfwdrst is asserted by the northbridge. b issue a connect special cycle.* c return internal clocks to full speed and assert procrdy. note: * the connect special cycle is only issued after a processor wake-up event (interrupt or stpclk# deassertion) occurs. if the amd duron? system bus is connected so the northbridge can probe the processor, a connect special cycle is not issued at that time (it is only issued after a subsequent processor wake-up event). connect disconnect pending disconnect connect pending 1 connect pending 2 1 3/a 4/c 5 6/b 2/b 24 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 4.3 clock control the processor implements a clock control (clk_ctl) msr (address c001_001bh) that dete rmines the internal clock divisor when the amd duron system bus is disconnected. refer to the amd athlon? and amd duron? processors bios, software, and debug developers guide , order# 21656, for more details on the clk_ctl register. 4.4 sysclk multipliers the processor provides two mechanisms for communicating processor core operating frequency information to the northbridge. these are the proc essor fid[3:0] outputs and the fid_change special cycle. the fid[3:0] outputs specify the core frequency of the processor as a multiple of the 100-mhz input clock (sysclk/sysclk#) of the processor. the fid[3:0] signals are valid after pwrok is asserted. the chipset must not sample the fid[ 3:0] signals until they become valid.the fid[3:0] outputs of the processor provide processor operating frequency information that th e northbridge uses when creating the sip stream that the northbridge sends to the processor after reset# is deasserted. the fid[3:0] outputs always select a 5x sysclk multiplier: fid[3:0] = 0 1 0 0 software will use the fid_change protocol to transition the processor to the desired performance state. the fid[3:0] outputs are not used as part of the fid_change protocol and do not change fr om their reset# value during software-controlled processor core frequency transitions. the fid_change special cycle is used to communicate processor operating frequency information to the northbridge during software-controlled processor core voltage and frequency (performance state) transitions. the fidvidctl msr allows software to specify a 5-bit fid value during software-controlled processor performance state transitions. the additional bit allows transitions to lower sysclk multipliers of 3x to 4x as well as all other sysclk multipliers supported by the processor. chapter 4 power management 25 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information for a description of the fid_change protocol refer to the earlier section in this chapter. table 1 lists the fid[4:0] sysclk multiplier codes for the processor used by software to di ctate the core frequency of the processor and the 5-bit value driven on sdata[36:32]# by the processor during the fid_change special bus cycle. note: only clock multipliers associated with operating frequencies specified in the ? electrical data ? chapter are valid for this processor. note: software distinguishes the speed grade of the processor by reading the mfid field of the fidvidstatus msr. table 1. fid[4:0] sysclk multiplier combinations 1 fid[4:0] 2,3,5 clock mode sdata[36:32]# 4 00000 11x 11111 00001 11.5x 11110 00010 12x 11101 00011 12.5x 11100 00100 5x 11011 00101 5.5x 11010 00110 6x 11001 00111 6.5x 11000 01000 7x 10111 01001 7.5x 10110 01010 8x 10101 01011 8.5x 10100 notes: 1. on power up, the fid[3:0] balls are set to a cloc k multiplier value of 5x. after reset, software is responsible for transitioning the pr ocessor to the desired frequency. 2. value programmed into the fidvidctl msr. 3. the maximum fid that may be selected by software is reported in the fidvidstatus msr. 4. value driven on sdata[36:32]# balls during the fid_change special bus cycle. the sdata bus is active low, so the sdata[36:32]# va lues listed are what would be observed on the motherboard with a digital storage scope. 5. bios initializes the clk_ctl msr to 6007_9263h during the post routine. this clk_ctl setting is used with all fid combinations and selects a halt disconnect divisor of 128 and a stop?grant disconnect divisor of 512. 26 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 01100 9x 10011 01101 9.5x 10010 01110 10x 10001 01111 10.5x 10000 10000 3x 01111 10001 reserved reserved 10010 4x 01101 10011 reserved reserved 10100 13x 11100 10101 13.5x 11100 10110 14x 11100 10111 reserved reserved 11000 15x 11100 11001 reserved reserved 11010 16x 11100 11011 16.5x 11100 11100 17x 11100 11101 18x 11100 11110 reserved reserved 11111 reserved reserved table 1. fid[4:0] sysclk multiplier combinations 1 fid[4:0] 2,3,5 clock mode sdata[36:32]# 4 notes: 1. on power up, the fid[3:0] balls are set to a cloc k multiplier value of 5x. after reset, software is responsible for transitioning the pr ocessor to the desired frequency. 2. value programmed into the fidvidctl msr. 3. the maximum fid that may be selected by software is reported in the fidvidstatus msr. 4. value driven on sdata[36:32]# balls during the fid_change special bus cycle. the sdata bus is active low, so the sdata[36:32]# va lues listed are what would be observed on the motherboard with a digital storage scope. 5. bios initializes the clk_ctl msr to 6007_9263h during the post routine. this clk_ctl setting is used with all fid combinations and selects a halt disconnect divisor of 128 and a stop?grant disconnect divisor of 512. chapter 4 power management 27 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 4.5 special cycles in addition to the special cycles documented in the amd athlon? and amd duron? system bus specification, order# 21902, the processor su pports the smm enter, smm exit, and fid_change special cycles. table 2 defines the contents of sdata[31:0] during the special cycles. table 2. processor special cycle definition special cycle contents of sdata[31:0] smm enter 0005_0002h smm exit 0006_0002h fid_change * 0007_0002h note: * the new fid[4:0] taken from the fid[4:0] field of the fidvidctl msr is driven on sdata[36:32] during the fid_change special cycle. 28 power management chapter 4 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information chapter 5 cpuid support 29 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 5 cpuid support the mobile amd duron? processor model 7 version and feature set recognition can be pe rformed through the use of the cpuid instruction, that provides complete information about the processor?vendor, type, name , etc., and its capabilities. software can make use of this information to accurately tune the system for maximum perfor mance and benefit to users. for information about the cpui d features supported by the mobile amd duron processor mode l 7, refer to the following documents: amd processor recognition application note , order# 20734 30 cpuid support chapter 5 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information chapter 6 thermal design 31 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 6 thermal design the mobile amd duron? processor model 7 provides a diode that can be used in conjunction with an external temperature sensor to determine the die temperature of the processor. the diode anode (thermda) and cathode (thermdc) are available as pins on the processor. refer to ?thermal diode char acteristics? on page 48 and ?thermda and thermdc pins? on page 83 for more details. for information about the usage of this diode and thermal design, including layout and ai rflow considerations, see the mobile system thermal design guidelines, order# 24383. table 3 shows the thermal design power. table 3. thermal design power frequency (mhz) voltage thermal design power 1 800 1.50 v 25 w 850 1.50 v 25 w 900 1.45 v 25 w 950 1.45 v 25 w 1000 1.40 v 25 w notes: 1. thermal design power represents the maximum sustained power dissipated while executing publicly-available software or instruction sequences under normal system operation at nominal vcc_core. thermal solutions must monitor the temperature of the processor to prevent the processor from exceeding its maximum die temperature. specified through characterization for a die temperature of 95 c. 32 thermal design chapter 6 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information chapter 7 electrical data 33 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7 electrical data 7.1 conventions the conventions used in this chapter are as follows: current specified as being sourced by the processor is negative . current specified as being sunk by the processor is positive . 7.2 interface signal groupings the electrical data in this chap ter is presented separately for each signal group. table 4 defines each group and the signals contained in each group. table 4. interface signal groupings signal group signals notes power vid[4:0], softvid[4:0], vcca, vcc_core, corefb, corefb# see ?? on page 38, ?soft voltage identification (softvid[4:0])? on page 35, ?vcca ac and dc characteristics? on page 35, ?vcc_core ac and dc characteristics? on page 37, ?corefb and corefb# pins? on page 78, ?softvid[4:0] and vid[4:0] pins? on page 81, and ?vcca pin? on page 83. frequency fid[3:0] see ?frequency identification (fid[3:0])? on page 35 and ?fid[3:0] pins? on page 79. system clocks sysclk, sysclk# (tied to clkin/clkin# and rstclk/rstclk#), pllbypassclk, pllbypassclk#, see ?sysclk and sysclk# ac and dc characteristics? on page 41, ?sysclk and sysclk#? on page 83, and ?pll bypass and test pins? on page 80. 34 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information system bus saddin[14:2]#, saddout[14:2]#, saddinclk#, saddoutclk#, sfillvalid#, sdatainvalid#, sdataoutvalid#, sdata[63:0]#, sdatainclk[3:0]#, sdataoutclk[3:0]#, clkfwdrst, procrdy, connect see ?amd duron? system bus ac and dc characteristics? on page 43 and ?clkfwdrst pin? on page 78. southbridge reset#, intr, nmi, smi#, init#, a20m#, ferr, ignne#, stpclk#, flush# see ?general ac and dc characteristics? on page 45, ?intr pin? on page 79, ?nmi pin? on page 80, ?smi# pin? on page 81, ?init# pin? on page 79, ?a20m# pin? on page 78, ?ferr pin? on page 79, ?ignne# pin? on page 79, ?stpclk# pin? on page 82, and ?flush# pin? on page 79. jtag tms, tck, trst#, tdi, tdo see ?general ac and dc characteristics? on page 45. test plltest#, pllbypass#, pllmon1, pllmon2, scanclk1, scanclk2, scanshiften, scaninteval, analog see ?general ac and dc characteristics? on page 45, ?pll bypass and test pins? on page 80, ?scan pins? on page 81, and ?analog pin? on page 78, miscellaneous dbreq#, dbrdy, pwrok see ?general ac and dc characteristics? on page 45, ?dbrdy and dbreq# pins? on page 79, and ?pwrok pin? on page 80. reserved (rsvd) pins n1, n3, and n5 see ?reserved pins dc characteristics? on page 51, and ?rsvd pins? on page 80. thermal thermda, thermdc see ?thermal diode characteristics? on page 48 and ?thermda and thermdc pins? on page 83 table 4. interface signal groupings (continued) signal group signals notes chapter 7 electrical data 35 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.3 soft voltage identification (softvid[4:0]) table 5 shows the softvid[4:0] dc characteristics. for more information, see ?softvid[4:0] and vid[4:0] pins? on page 81. 7.4 frequency identification (fid[3:0]) table 6 shows the fid[3:0] dc characteristics. for more information, see ?fid[3:0] pins? on page 79. 7.5 vcca ac and dc characteristics table 7 shows the ac and dc characteristics for vcca. for more information, see ?vcca pin? on page 83. table 5. softvid[4:0] dc characteristics parameter description min max i ol output current low 16 ma softvid_v oh softvid[4:0] output high voltage ? 2.625v * note: * the softvid pins must not be pulled above this voltage by an external pullup resistor. table 6. fid[3:0] dc characteristics parameter description min max i ol output current low 16 ma v oh output high voltage ? 2.625 v * note: * the fid pins must not be pulled above this voltage by an external pullup resistor. table 7. vcca ac and dc characteristics symbol parameter min nom max units notes v vcca vcca pin voltage (ac and dc) 2.25 2.5 2.75 v 1 i vcca vcca pin current 0 50 ma/ghz 2 notes: 1. minimum and maximum voltages are absolute. no transients below minimum nor above maxiumum voltages are permitted. 2. measured at 2.5 v. 36 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 7.6 decoupling see the amd athlon? processor-ba sed motherboard design guide , order# 24363, or contact your local amd office for information about the decoupling required on the motherboard for use with the mobile amd duron? processor model 7. 7.7 valid voltage and fr equency combinations table 8 specifies the valid voltage and frequency combinations that this processor is characterized to operate. the maximum frequency column corresponds to the rated frequency of the processor. the maximum fid (mfid) field in the fidvidstatus msr is used by software to determine the maximum frequency of the processor. each row in the table shows the maximum frequency allowable at the voltage specified in each column. ?power management? on page 9 describes how amd powernow!? software uses this information to implement processor performance states. table 8. valid voltage and frequency combinations maximum frequency vcc_core_nom voltage 1.50 v 1.45 v 1.40 v 1.35 v 1.30 v 1.25 v 1.20 v 800 mhz 800 mhz 700 mhz 650 mhz 600 mhz 550 mhz 500 mhz 500 mhz 850 mhz 850 mhz 750 mhz 700 mhz 650 mhz 600 mhz 550 mhz 500 mhz 900 mhz n/a 900 mhz 800 mhz 750 mhz 700 mhz 650 mhz 550 mhz 950 mhz n/a 950 mhz 850 mhz 800 mhz 750 mhz 700 mhz 600 mhz 1000 mhz n/a n/a 1000 mhz 900 mhz 850 mhz 800 mhz 700 mhz notes: 1. all voltages listed are nominal. 2. the ? ? symbol indicates that any bios vendor can use any perform ance state equal to or less than the specified frquency at that given voltage. for example, ? 700 mhz? means that the bios may use 700 mhz, 600 mhz, 550 mhz, 500 mhz, 400 mhz, or 300 mhz provided that the chipset and system sup port the chosen processor operating frequencies. 3. the maximum processor die temperature is 95o c for all voltage and frequency combinations. chapter 7 electrical data 37 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.8 vcc_core ac and dc characteristics table 9 shows the ac and dc characteristics for vcc_core. for more information, see table 24, ?cross-reference by pin location,? on page 70 and figure 9 on page 38. table 9. vcc_core ac and dc characteristics symbol parameter limit in working state 2 units v cc_core_dc_max maximum static voltage above v cc_core_nom 1 100 mv v cc_core_dc_min maximum static voltage below v cc_core_nom 1 ?50 mv v cc_core_ac_max maximum excursion above v cc_core_nom 1 150 mv v cc_core_ac_min maximum excursion below v cc_core_nom 1, 3 ?100 mv t max_ac positive excursion time for ac transients 10 s t min_ac negative excursion time for ac transients 5 s notes: 1. vcc_core nominal values are shown in table 8, ?v alid voltage and frequency combinations,? on page 36. 2. all voltage measurements are taken diffe rentially at the corefb/corefb# pins. 3. absolute minimum allowable vcc_core voltage, including all transients, is 1.10 v. 38 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information figure 9 shows the processor core voltage (vcc_core) waveform response to perturbation. the t min_ac (negative ac transient excursion time) and t max_ac (positive ac transient excursion time) represent the maximum allowable time below or above the dc tolerance thresholds. figure 9. vcc_core voltage waveform t min_ac v cc_core_max_ac t max_ac v cc_core_max_dc v cc_core_nom v cc_core_min_dc v cc_core_min_ac i core_min i core_max di /dt chapter 7 electrical data 39 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.9 absolute ratings do not subject the processor to conditions that exceed the absolute ratings listed in table 10, as such conditions may adversely affect long-term reliability or result in functional damage. table 10. absolute ratings parameter description min max vcc_core mobile amd duron? processor model 7 core supply ?0.5 v vcc_core max + 0.5 v vcca amd duron processor model 7 pll supply ?0.5 v vcca max + 0.5 v v pin voltage on any signal pin ?0.5 v vcc_core max + 0.5 v t storage storage temperature of processor ?40oc 100oc 40 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 7.10 vcc_core voltage and current table 11 shows the voltage and current of the processor during normal and reduced power states. table 11. vcc_core voltage and current frequency (mhz) nominal voltage maximum i cc (power supply current) die temperature notes 800 1.50 v 16.70 a 95 c 850 900 1.45 v 17.20 a 950 1000 1.40 v 17.90 halt/stop grant c2 1.20 v 2.00 a 1, 2, 3 stop grant c2 1.07 a 50 c 1, 2, 3, 4 stop grant c3/s1 0.80 a 1, 2, 3, 4 notes: 1. see also figure 3, ?mobile amd duron? processor model 7 power management states? on page 10. 2. the maximum stop grant currents are absolute worst case curre nts for parts that may yield from the worst case corner of the process, and are not representative of the typical stop grant current that is currently about one-third of the maximum specifie d current. 3. these currents occur when the amd duron system bus is disconne cted and a low power ratio of 1/512 is applied to the core clock grid of the processor as dictated by a value of 6007_9263h programmed into the clock control (clk_ctl) msr. 4. the stop grant current consumption is characterized and not tested. chapter 7 electrical data 41 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.11 sysclk and sysclk# ac and dc characteristics table 12 shows the dc characteristics of the sysclk and sysclk# differential clocks. the sysclk signal represents clkin and rstclk tied toget her while the sysclk# signal represents clkin# and rstclk# tied together. figure 10 shows the dc charac teristics of the sysclk and sysclk# signals. figure 10. sysclk and sysclk# differential clock signals table 12. sysclk and sysclk# dc characteristics symbol description min max units v threshold-dc crossing before transition is detected (dc) 400 mv v threshold-ac crossing before transition is detected (ac) 450 mv i leak_p leakage current through p-channel pullup to vcc_core ?250 a i leak_n leakage current through n-channel pulldown to vss (ground) 250 a v cross differential signal crossover vcc_core/2 +/? 100 mv c pin capacitance 4 12 pf v cross v threshold-dc = 400 mv v threshold-ac = 450 mv 42 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information table 13 shows the mobile amd duron processor model 7 sysclk/sysclk# differential clock ac characteristics. figure 11 shows a sample waveform. figure 11. sysclk waveform table 13. sysclk and sysclk# ac characteristics symbol description min max units notes clock frequency 50 100 mhz duty cycle 30% 70% ? t 1 period 10 ns 1, 2 t 2 high time 1.8 ns t 3 low time 1.8 ns t 4 fall time 2 ns t 5 rise time 2 ns period stability 300 ps notes: 1. circuitry driving the sysclk and sysclk# inputs must exhibi t a suitably low closed-loop jitter bandwidth to allow the pll to track the jitter. the ?20 db attenuation point , as measured into a 10-pf or 20-pf load must be less than 500 khz. 2. circuitry driving the sysclk and sysclk# inputs may purposely alter the sysclk and sysclk# period (spread spectrum clock generators). in no cases can the period violate the minimum specification above. sysclk and sysclk# inputs may vary from 100% of the specified period to 99% of the specified period at a maximum rate of 100 khz. t 5 v cross t 2 t 3 t 4 t 1 v threshold-ac chapter 7 electrical data 43 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.12 amd duron? system bus ac and dc characteristics table 14 shows the dc characteristics of the amd duron system bus. table 14. amd duron? system bus dc characteristics symbol parameter condition min max units notes v ref dc input reference voltage (0.5 x vcc_core) ?50 (0.5 x vcc_core) +50 mv 1 i vref_leak_p v ref tristate leakage pullup v in =v refnominal ?100 a i vref_leak_n v ref tristate leakage pulldown v in =v refnominal +100 a v ih input high voltage v ref + 200 vcc_core + 500 mv v il input low voltage ?500 v ref ? 200 mv v oh output high voltage i out = ?200 a 0.85*vcc_core vcc_core+500 mv 2 v ol output low voltage i out = 1 ma ?500 400 mv 2 i leak_p tristate leakage pullup v in = vss (ground) ?250 a i leak_n tristate leakage pulldown v in = vcc_core nominal +250 a c in input pin capacitance 4 12 pf notes: 1. v ref ? v ref is nominally set by a (1%) resistor divider from vcc_core. ? the suggested divider resistor values are 100 ohms over 100 ohms to produce a divisor of 0.50. ? example: vcc_core = 1.4 v, v ref = 750 mv (1.4 x 0.50). ? peak-to-peak ac noise on v ref (ac) should not exceed 2% of v ref (dc). 2. specified at t = 95c and vcc_core. 44 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information the ac characteristics of the amd duron system bus are shown in table 15. the parameters are grouped based on the source or destination of the signals involved. table 15. amd duron? system bus ac characteristics group symbol parameter min max units notes all signals t rise output rise slew rate 1 3 v/ns 1 t fall output fall slew rate 1 3 v/ns 1 forward clocks t skew-sameedge output skew with respect to the same clock edge ?385ps2 t skew-diffedge output skew with respect to a different clock edge ? 770 ps 2 t su input data setup time 300 ? ps 3 t hd input data hold time 300 ? ps 3 c in capacitance on input clocks 4 12 pf c out capacitance on output clocks 4 12 pf sync t val rstclk to output valid 250 2000 ps 4, 5 t su setup to rstclk 500 ? ps 4, 6 t hd hold from rstclk 1000 ? ps 4, 6 notes: 1. rise and fall time ranges are guidelines over which the i/o has been characterized. 2. t skew-sameedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to the same clock edge. t skew-diffedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 3. input su and hd times are with respect to the appropriate clock forward group input clock. 4. the synchronous signals include procrdy, connect, and clkfwdrst. 5. t val is rstclk rising edge to output valid for procrdy. test load is 25 pf. 6. t su is setup of connect/clkfwdrst to rising edge of rstclk. t hd is hold of connect/clkfwdrst from rising edge of rstclk. chapter 7 electrical data 45 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.13 general ac and dc characteristics table 16 shows the mobile amd duron processor model 7 ac and dc characteristics of the southbridge, jtag, test, and miscellaneous pins. table 16. general ac and dc characteristics symbol parameter description condition min max units notes v ih input high voltage (vcc_core/2) + 200mv vcc_core max v 1, 2 v il input low voltage ?300 350 mv 1, 2 v oh output high voltage vcc_core ? 400 vcc_core + 300 mv v ol output low voltage ?300 400 mv i leak_p tristate leakage pullup v in = vss (ground) ?250 a i leak_n tristate leakage pulldown v in = vcc_core nominal 250 a i oh output high current ?16 ma 3 i ol output low current 16 ma 3 t su sync input setup time 2.0 ns 4, 5 t hd sync input hold time 0.0 ps 4, 5 t delay output delay with respect to rstclk 0.0 6.1 ns 5 t bit input time to acquire 20.0 ns 7, 8 notes: 1. characterized across dc supply voltage range. 2. values specified at nominal vcc_core. scale parameters between vcc_core min and vcc_core max. 3. i ol and i oh are measured at v ol maximum and v oh minimum, respectively. 4. synchronous inputs/outputs are specified with respect to rstclk and rstck# at the pins. 5. these are aggregate numbers. 6. edge rates indicate the range ov er which inputs were characterized. 7. in asynchronous operation, the signal mu st persist for this time to enable capture. 8. this value assumes rstclk frequency is 10 ns ==> tbit = 2*frst. 9. the approximate value for standard case in normal mode operation. 10. this value is dependent on rstclk frequency, divisors, low power mode, and core frequency. 11. reassertions of the signal within this time are not guaranteed to be seen by the core. 12. this value assumes that the skew between rstclk and k7clkout is much less than one phase. 13. this value assumes rstclk and k7clkout are running at the same frequency, though the pr ocessor is capable of other configurations. 14. time to valid is for any open drain pins. see requirements 7 a nd 8 in chapter 8, ?power?up timing requirements,? for more information. 46 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information t rpt input time to reacquire 40.0 ns 9?13 t rise signal rise time 1.0 3.0 v/ns 6 t fall signal fall time 1.0 3.0 v/ns 6 c pin pin capacitance 4 12 pf t valid time to data valid 100 ns 14 table 16. general ac and dc characteristics symbol parameter description condition min max units notes notes: 1. characterized across dc supply voltage range. 2. values specified at nominal vcc_core. scale parameters between vcc_core min and vcc_core max. 3. i ol and i oh are measured at v ol maximum and v oh minimum, respectively. 4. synchronous inputs/outputs are specified with respect to rstclk and rstck# at the pins. 5. these are aggregate numbers. 6. edge rates indicate the range ov er which inputs were characterized. 7. in asynchronous operation, the signal mu st persist for this time to enable capture. 8. this value assumes rstclk frequency is 10 ns ==> tbit = 2*frst. 9. the approximate value for standard case in normal mode operation. 10. this value is dependent on rstclk frequency, divisors, low power mode, and core frequency. 11. reassertions of the signal within this time are not guaranteed to be seen by the core. 12. this value assumes that the skew between rstclk and k7clkout is much less than one phase. 13. this value assumes rstclk and k7clkout are running at the same frequency, though the pr ocessor is capable of other configurations. 14. time to valid is for any open drain pins. see requirements 7 a nd 8 in chapter 8, ?power?up timing requirements,? for more information. chapter 7 electrical data 47 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.14 open drain test circuit figure 12 is a test circuit that may be used on automated test equipment (ate) to test for validity on open drain pins. refer to table 16, ?general ac and dc characteristics,? on page 45 for timing requirements. figure 12. general ate open drain test circuit open drain pin v termination 1 50 ? 3% i ol = output current 2 notes: 1. v termination = 1.2 v for vid and fid pins 2. i ol = ?16 ma for vid and fid pins 48 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 7.15 thermal diode characteristics thermal diode electrical characteristics. table 17 shows the mobile amd duron processor model 7 electrical characteristics of the on-die thermal diode. table 17. thermal diode el ectrical characteristics symbol parameter description min nom max units notes i fw forward bias current 5 300 a 1 n diode ideality factor 1.002 1.008 1.016 2, 3, 4, 5 notes: 1. the sourcing current should always be used in forward bias only. 2. characterized at 95c with a for ward bias current pair of 10 a and 100 a. 3. not 100% tested. specified by design and limited characterization. 4. the diode ideality factor, n, is a correction factor to the ideal diode equation. for the following equations, use the following variables and constants: n diode ideality factor k boltzmann constant q electron charge constant t diode temperature (kelvin) v be voltage from base to emitter i c collector current i s saturation current n ratio of collector currents the equation for v be is: by sourcing two currents and using the above equation, a difference in base emitter voltage can be found that leads to the following equation for temperature: 5. if a different sourcing current pair is used other than 10 a and 100 a, the following equation should be used to correct the temperature. su btract this offset from the temperature measured by the temperature sensor. for the following equations, use the following variables and constants: i high high sourcing current i low low sourcing current t offset (in c) can be found using the following equation: v be nkt q --------- i c i s ---- - ln ? = t ? v be nn () ln k q -- - ?? ----------------------------- = t offset 6.0 10 4 ? () i high i low ? () i high i low ----------- ln ------------------------------- - ? 2.34 ? = chapter 7 electrical data 49 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information thermal protection characterization. the following section describes parameters relating to thermal protection. the implementation of thermal control circuitry to control processor temperature is left to the manufacturer to determine how to implement. thermal limits in motherboard design are necessary to protect the processor from thermal damage. t shutdown is the temperature for thermal protection circuitry to initiate shutdown of the processor. t sd_delay is the maximum time allowed from the detection of the over-temperature condition to processor shutdown to prev ent thermal damage to the processor. systems that do not implement thermal protection circuitry or that do not react within the time specified by t sd_delay can cause thermal damage to the processor during the unlikely events of fan failure or powering up the processor without a heat-sink. the processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event. thermal protection circuitry reference designs and thermal solution guidelines are found in the following documents: amd athlon? processor-based motherboard design guide, order# 24363 thermal diode monitoring circuits, order# 25658 amd thermal, mechanical, and chassis cooling design guide , order# 23794 http://www1.amd.com/products/athlon/thermals mobile specific thermal documentation: measuring processor and system power in a mobile system , order# 24353 mobile system thermal design guide , order# 24383 measuring temperature on amd athlon? and amd duron? pin grid array processors with and without an on-die thermal diode , order#24228 50 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information table 18 shows the t shutdown and t sd_delay specifications for circuitry in motherboard design necessary for thermal protection of the processor. table 18. guidelines for platform ther mal protection of the processor symbol parameter description max units notes t shutdown thermal diode shutdown temperature for processor protection 125 c1, 2, 3 t sd_delay maximum allowed time from t shutdown detection to processor shutdown 500 ms 1, 3 notes: 1. the thermal diode is not 100% tested, it is specified by design and limited characterization. 2. the thermal diode is capable of responding to thermal events of 40c/s or faster. 3. the mobile amd duron? processor model 7 provides a thermal diode for measuring die temperature of the processor. the processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a thermal shutdown event. refer to thermal diode monitoring circuits, order# 25658 , for thermal protection circuitry designs. chapter 7 electrical data 51 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 7.16 reserved pins dc characteristics table 19 shows the dc characteri stics of the reserved (rsvd) pins. table 19. reserved pins (n1, n 3, and n5) dc characteristics symbol parameter description min max units note i leak_p tristate leakage pullup ?250 a * i leak_n tristate leakage pulldown 250 a * note: * measured at 2.5 v 52 electrical data chapter 7 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 7.17 fid_change induced pll lock time table 20 shows the time required for the pll of the processor to lock at the new frequency specified in a fid_change transition. software must program the sgtc field of the fidvidctl msr to produce a fid_change duration e qual to or greater than the fid_change induced pll lock time. for more information about the fid_change protocol, see ?power management? on page 9. table 20. fid_change induced pll lock time parameter description max units fid_change induced pll lock time 50 s chapter 8 signal and power-up requirements 53 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 8 signal and power-up requirements this chapter describes the mobile amd duron? processor model 7 power-up requirements during system power-up and warm resets. 8.1 power-up requirements signal sequence and timing description figure 13 shows the relationship between key signals in the system during a power-up sequen ce. this figure details the requirements of the processor. figure 13. signal relationship requirements during power-up sequence 3.3 v supply vcca (2.5 v) (for pll) reset# vcc_core (processor core) nb_reset# pwrok system clock 2 1 3 4 5 6 fid[3:0] 7 8 warm reset condition notes: 1. figure 13 represents several signals generically by using names not necessarily consistent with any pin lists or schematics. 2. requirements 1?8 in figure 13 are described in ?power-up timing requirements? on page 54. 54 signal and power-up requirements chapter 8 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information power-up timing requirements. the signal timing requirements are as follows: 1. reset# must be asserted before pwrok is asserted. the mobile amd duron? proces sor model 7 does not set the correct clock multiplier if pwrok is asserted prior to a reset# assertion. it is recommended that reset# be asserted at least 10 nanoseconds prior to the assertion of pwrok. in practice, southbridges will assert reset# milliseconds before pwrok is deasserted. 2. all motherboard voltage planes must be within specification before pwrok is asserted. pwrok is an output of the voltage regulation circuit on the motherboard. pwrok indicate s that vcc_core and all other voltage planes in the system are within specification. the motherboard is required to delay pwrok assertion for a minimum of 3 milliseconds from the 3.3 v supply being within specification. this ensures that the system clock (sysclk/sysclk#) is operating within specification when pwrok is asserted. the processor core voltage, vcc_core, must be within specification before pwrok is asserted as dictated by the vid[4:0] pins strapped on th e processor package. before pwrok assertion, the processor is clocked by a ring oscillator. before pwrok is asserted, the softvid[4:0] outputs of the processor are not driven to a deterministic value. the processor drives the softvid[4:0] outputs to the same value as dictated by the vid[4:0] pins within 20 nanoseconds of pwrok assertion. the processor pll is powered by vcca. the processor pll does not lock if vcca is not high enough for the processor logic to switch for some period before pwrok is asserted. vcca must be within specification at least 5 microseconds before pwrok is asserted. in practice vcca, vcc_core, and all other voltage planes must be within specification for several milliseconds before pwrok is asserted. after pwrok is asserted, the processor pll locks to its operational frequency. 3. the system clock (sysclk/sysclk#) must be running before pwrok is asserted. chapter 8 signal and power-up requirements 55 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information when pwrok is asserted, the processor switches from driving the internal processor clock grid from the ring oscillator to driving from the pll. the reference system clock must be valid at this time. the system clocks are guaranteed to be running after 3.3 v has been within specification for 3 milliseconds. 4. pwrok assertion to deassertion of reset# the duration of reset# assertion during cold boots is intended to satisfy the time it takes for the pll to lock with a less than 1 ns phase error. the processor pll begins to run after pwrok is asserted and the internal clock grid is switched from the ring oscillator to the pll. the pll lock time may take from hundreds of nanoseconds to tens of microseconds. it is recommended that the minimum time between pwrok assert ion to the deassert ion of reset# be at least 1.0 milliseconds . southbridges enforce a delay of 1.5 to 2.0 milliseconds between pwrgd (southbridge version of pwrok) assertion and nb_reset# deassertion. 5. pwrok must be monotonic and meet the timing requirements as defined in ta ble 16, ?general ac and dc characteristics,? on page 45. the processor should not switch between the ring oscillator and the pll after the initial assertion of pwrok. 6. nb_reset# must be asserted (causing connect to also assert) before reset# is deasserted. in practice all southbridges enforce this requirement. if nb_reset# does not asse rt until after reset# has deasserted, the processor misinterprets the connect assertion (due to nb_reset# being asserted) as the beginning of the sip transfer . there must be sufficient overlap in the resets to ensure that connect is sampled asserted by the processor before reset# is deasserted. 7. the fid[3:0] signals are valid within 100 ns after pwrok is asserted. the chipset must not sample the fid[3:0] signals until they become valid. refer to the amd athlon? processor-based mother board design guide , order# 24363, for the specific implementation and additional circuitry required. 56 signal and power-up requirements chapter 8 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 8. the fid[3:0] signals become valid within 100 ns after reset# is asserted. refer to the amd athlon? processor- based motherboard design guide , order# 24363, for the specific implementation and additional circuitry required. clock multiplier selection (fid[3:0]) the chipset samples the fid[3:0] signals in a chipset-specific manner from the processor a nd uses this information to determine the correct serial init ialization packet (sip). the chipset then sends the sip info rmation to the processor for configuration of the amd duron system bus for the clock multiplier that determines the processor frequency indicated by the fid[3:0] code. the sip is sent to the processor using the sip protocol. this protocol uses the procrdy, connect, and clkfwdrst signals, that are synchronous to sysclk. for more information, seesee ?fid[3:0] pins? on page 79. serial initialization packet (sip) protocol. refer to amd athlon? and amd duron? system bus specification , order# 21902 for details of the sip protocol. 8.2 processor warm reset requirements mobile amd duron? processor model 7 and northbridge reset pins reset# cannot be asse rted to the processor without also being asserted to the northbridge. re set# to the northbridge is the same as pci reset#. the minimum assertion for pci reset# is one millisecond. southbridges enforce a minimum assertion of reset# for the processor, northbridge, and pci of 1.5 to 2.0 milliseconds. chapter 9 mechanical data 57 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 9 mechanical data 9.1 introduction the mobile amd duron processo r model 7 connects to the motherboard through a cpga so cket named socket a. for more information, see the amd athlon? processor-based motherboard design guide, order# 24363. 9.2 die loading the processor die on the cpga package is exposed at the top of the package. this is done to facilitate heat transfer from the die to an approved heat sink. it is critical that the mechanical loading of the heat sink does not exceed the limits shown in table 21. any heat sink design should avoid loads on corners and edges of die. the cpga package has compliant pads that serve to bring surfaces in planar contact. table 21. cpga mechanical loading 1 location dynamic (max) static (max) units note die surface 100 30 lbf 2 die edge 10 10 lbf 3 notes: 1. tool-assisted zero insertion force sockets should be designed such that no load is placed on the ceramic substrate of the package. 2. load specified for coplanar contact to die surface. 3. load defined for a surface at no more than a two degree angle of inclination to die surface. 58 mechanical data chapter 9 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 9.3 package description figure 14 on page 59 shows th e mechanical drawing of the cpga package. table 22 provides the dimensions in millimeters assigned to the letters and symbols shown in the figure 14 diagram. table 22. dimensions for the cpga package letter or symbol minimum dimension 1 maximum dimension 1 letter or symbol minimum dimension 1 maximum dimension 1 d/e 49.27 49.78 e9 1.66 1.96 d1/e1 45.72 bsc g/h ? 4.50 d2 11.698 ref a 2.24 ref d3 3.30 3.60 a1 1.27 1.53 d4 11.84 12.39 a2 0.80 0.88 d5 11.84 12.39 a3 0.116 ? d6 5.91 6.46 a4 ? 1.90 d7 10.65 11.20 p ? 6.60 d8 3.05 3.35 b 0.43 0.50 e2 9.034 ref b1 1.40 ref e3 2.35 2.65 s 1.435 2.375 e4 7.25 7.80 l 3.05 3.31 e5 7.25 7.80 m 37 e6 8.86 9.41 n 453 (pins) e7 8.86 9.41 e 1.27 bsc e8 15.59 16.38 e1 2.54 bsc note: 1. dimensions are given in millimeters. chapter 9 mechanical data 59 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information figure 14. mobile amd duron? processor model 7 cpga package 60 mechanical data chapter 9 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information chapter 10 pin descriptions 61 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 10 pin descriptions 10.1 pin diagram and pin name abbreviations figure 15 on page 62 shows the staggered pin grid array (spga) for the mobile amd duron proce ssor model 7. because some of the pin names are too long to fit in the grid, they are abbreviated. table 23 on page 64 lists all the pins in alphabetical order by pin name , along with the abbreviation where necessary. 62 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 a sao#12 sao#5 sao#3 sd#55 sd#61 sd#53 sd#63 sd#62 nc sd#57 sd#39 sd#35 sd#34 sd#44 nc sdoc#2 sd#40 sd#30 a b vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc b c sao#7 sao#9 sao#8 sao#2 sd#54 sdoc#3 nc sd#51 sd#60 sd#59 sd#56 sd#37 sd#47 sd#38 sd#45 sd#43 sd#42 sd#41 sdoc#1 c d vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vss d e sao#11 saoc# sao#4 sao#6 sd#52 sd#50 sd#49 sdic#3 sd#48 sd#58 sd#36 sd#46 nc sdic#2 sd#33 sd#32 nc sd#31 sd#22 e f vss vss vss svid[0] vss vcc vss vcc vss vcc vss vcc vss vcc nc vcc vcc vcc f g sao#10 sao#14 sao#13 key key nc nc key key nc nc key key nc nc nc sd#20 sd#23 sd#21 g h vcc vcc svid[2] svid[3] svid[4] vcc vss vcc vss vcc vss vcc vss nc nc nc vss vss h j sao#0 sao#1 nc vid[4] nc sd#19 sdic#1 sd#29 j k vss vss vss svid[1] nc vcc vcc vcc k l vid[0] vid[1] vid[2] vid[3] nc sd#26 nc sd#28 l m vcc vcc vcc vcc vss vss vss vss m n rsvd rsvd rsvd key nc sd#25 sd#27 sd#18 n p vss vss vss vss vcc vcc vcc vcc p q tck tms scnsn key nc sd#24 sd#17 sd#16 q r vcc vcc vcc vcc vss vss vss vss r s scnck1 scninv scnck2 thda nc sd#7 sd#15 sd#6 s t vss vss vss vss vcc vcc vcc vcc t u tdi trst# tdo thdc nc sd#5 sd#4 nc u v vcc vcc vcc vcc vss vss vss vss v w fid[0] fid[1] vref_s nc nc sdic#0 sd#2 sd#1 w x vss vss vss vss vcc vcc vcc vcc x y fid[2] fid[3] nc key nc nc sd#3 sd#12 y z vcc vcc vcc vcc vss vss vss vss z aa dbrdy dbreq# nc key nc sd#8 sd#0 sd#13 aa ab vss vss vss vss vcc vcc vcc vcc ab ac stpc# pltst# zn nc nc sd#10 sd#14 sd#11 ac ad vcc vcc vcc nc nc vss vss vss ad ae a20m# pwrok zp nc nc sai#5 sdoc#0 sd#9 ae af vss vss nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc vcc vcc af ag ferr reset# nc key key corefb corefb# key key nc nc nc nc key key nc sai#2 sai#11 sai#7 ag ah vcc vcc amd nc vcc vss vcc vss vcc vss vcc vss vcc vss nc vss vss vss ah aj ignne# init# vcc nc nc nc anlog nc nc nc clkfr vcca plbyp# nc sai#0 sfillv# saic# sai#6 sai#3 aj ak vss vss cpr# nc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vcc ak al intr flush# vcc nc nc nc plmn2 plbyc# clkin# rclk# k7co cnnct nc nc sai#1 sdov# sai#8 sai#4 sai#10 al am vcc vss vss nc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss am an nmi smi# nc nc nc plmn1 plbyc clkin rclk k7co# prcrdy nc nc sai#12 sai#14 sdinv# sai#13 sai#9 an 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 mobile amd duron? processor model 7 topside view figure 15. mobile amd duron? processor model 7 pin diagram?topside view chapter 10 pin descriptions 63 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information a b c d e f g h j k l m n p q r s t u v w x y z aa ab ac ad ae af ag ah aj ak al am an 1 sao#7 sao#11 sao#10 sao#0 vid[0] rsvd tck scnck1 tdi fid[0] fid[2] dbrdy stpc# a20m# ferr ignne# intr 1 2 vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc 2 3 sao#12 sao#9 saoc# sao#14 sao#1 vid[1] rsvd tms scninv trst# fid[1] fid[3] dbreq# pltst# pwrok reset# init# flush# nmi 3 4 vcc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vss 4 5 sao#5 sao#8 sao#4 sao#13 nc vid[2] rsvd scnsn scnck2 tdo vref_s nc nc zn zp nc vcc vcc smi# 5 6 vss vss vss svid[2] vss vcc vss vcc vss vcc vss vcc vss vcc nc amd cpr# vss 6 7 sao#3 sao#2 sao#6 key vid[4] vid[3] key key thda thdc nc key key nc nc key nc nc nc 7 8 vcc vcc svid[0] svid[3] svid[1] vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc 8 9 sd#55 sd#54 sd#52 key keyncncnc 9 10 vss vss vss svid[4] nc vcc vcc vcc 10 11 sd#61 sdoc#3 sd#50 nc corefb nc nc nc 11 12 vcc vcc vcc vcc vss vss vss vss 12 13 sd#53 nc sd#49 nc corefb# anlog plmn2 plmn1 13 14 vss vss vss vss vcc vcc vcc vcc 14 15 sd#63 sd#51 sdic#3 key key nc plbyc# plbyc 15 16 vcc vcc vcc vcc vss vss vss vss 16 17 sd#62 sd#60 sd#48 key key nc clkin# clkin 17 18 vss vss vss vss vcc vcc vcc vcc 18 19 nc sd#59 sd#58 nc nc nc rclk# rclk 19 20 vcc vcc vcc vcc vss vss vss vss 20 21 sd#57 sd#56 sd#36 nc nc clkfr k7co k7co# 21 22 vss vss vss vss vcc vcc vcc vcc 22 23 sd#39 sd#37 sd#46 key nc vcca cnnct prcrdy 23 24 vcc vcc vcc vcc vss vss vss vss 24 25 sd#35 sd#47 nc key nc plbyp# nc nc 25 26 vss vss vss vss vcc vcc vcc vcc 26 27 sd#34 sd#38 sdic#2 nc keyncncnc 27 28 vcc vcc vcc nc nc vss vss vss 28 29 sd#44 sd#45 sd#33 nc key sai#0 sai#1 sai#12 29 30 vss vss nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc vcc vcc 30 31 nc sd#43 sd#32 nc nc nc nc nc nc nc nc nc nc nc nc nc sfillv# sdov# sai#14 31 32 vcc vcc vcc nc vcc vss vcc vss vcc vss vcc vss vcc vss nc vss vss vss 32 33 sdoc#2 sd#42 nc sd#20 sd#19 sd#26 sd#25 sd#24 sd#7 sd#5 sdic#0 nc sd#8 sd#10 sai#5 sai#2 saic# sai#8 sdinv# 33 34 vss vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vcc 34 35 sd#40 sd#41 sd#31 sd#23 sdic#1 nc sd#27 sd#17 sd#15 sd#4 sd#2 sd#3 sd#0 sd#14 sdoc#0 sai#11 sai#6 sai#4 sai#13 35 36 vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss 36 37 sd#30 sdoc#1 sd#22 sd#21 sd#29 sd#28 sd#18 sd#16 sd#6 nc sd#1 sd#12 sd#13 sd#11 sd#9 sai#7 sai#3 sai#10 sai#9 37 a b c d e f g h j k l m n p q r s t u v w x y z aa ab ac ad ae af ag ah aj ak al am an mobile amd duron? processor model 7 bottomside view figure 16. mobile amd duron? proces sor model 7 pin diagram?bottomside view 64 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information table 23. pin name abbreviations abbreviation full name pin a20m# ae1 amd ah6 anlog analog aj13 clkfr clkfwdrst aj21 clkin an17 clkin# al17 cnnct connect al23 corefb ag11 corefb# ag13 cpr# cpu_presence# ak6 dbrdy aa1 dbreq# aa3 ferr ag1 fid[0] w1 fid[1] w3 fid[2] y1 fid[3] y3 flush# al3 ignne# aj1 init# aj3 intr al1 k7co k7clkout al21 k7co# k7clkout# an21 key g7 key g9 key g15 key g17 key g23 key g25 key n7 key q7 key y7 key aa7 key ag7 key ag9 key ag15 key ag17 key ag27 key ag29 nc a19 nc a31 nc c13 nc e25 nc e33 nc f30 nc g11 nc g13 nc g19 nc g21 nc g27 nc g29 nc g31 nc h28 nc h30 nc h32 nc j5 nc j31 nc k30 nc l31 nc l35 nc n31 nc q31 nc s31 nc u31 nc u37 nc w7 nc w31 nc y5 nc y31 nc y33 nc aa5 nc aa31 nc ac7 nc ac31 nc ad8 nc ad30 nc ae7 nc ae31 table 23. pin name abbreviations (continued) abbreviation full name pin chapter 10 pin descriptions 65 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information nc af6 nc af8 nc af10 nc af28 nc af30 nc af32 nc ag5 nc ag19 nc ag21 nc ag23 nc ag25 nc ag31 nc ah8 nc ah30 nc aj7 nc aj9 nc aj11 nc aj15 nc aj17 nc aj19 nc aj27 nc ak8 nc al7 nc al9 nc al11 nc al25 nc al27 nc am8 nc an7 nc an9 nc an11 nc an25 nc an27 nmi an3 plbyp# pllbypass# aj25 plbyc pllbypassclk an15 plbyc# pllbypassclk# al15 plmn1 pllmon1 an13 plmn2 pllmon2 al13 table 23. pin name abbreviations (continued) abbreviation full name pin pltst# plltest# ac3 prcrdy procready an23 pwrok ae3 rsvd n1 rsvd n3 rsvd n5 reset# ag3 rclk rstclk an19 rclk# rstclk# al19 sai#0 saddin[0]# aj29 sai#1 saddin[1]# al29 sai#2 saddin[2]# ag33 sai#3 saddin[3]# aj37 sai#4 saddin[4]# al35 sai#5 saddin[5]# ae33 sai#6 saddin[6]# aj35 sai#7 saddin[7]# ag37 sai#8 saddin[8]# al33 sai#9 saddin[9]# an37 sai#10 saddin[10]# al37 sai#11 saddin[11]# ag35 sai#12 saddin[12]# an29 sai#13 saddin[13]# an35 sai#14 saddin[14]# an31 saic# saddinclk# aj33 sao#0 saddout[0]# j1 sao#1 saddout[1]# j3 sao#2 saddout[2]# c7 sao#3 saddout[3]# a7 sao#4 saddout[4]# e5 sao#5 saddout[5]# a5 sao#6 saddout[6]# e7 sao#7 saddout[7]# c1 sao#8 saddout[8]# c5 sao#9 saddout[9]# c3 sao#10 saddout[10]# g1 sao#11 saddout[11]# e1 sao#12 saddout[12]# a3 sao#13 saddout[13]# g5 table 23. pin name abbreviations (continued) abbreviation full name pin 66 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information sao#14 saddout[14]# g3 saoc# saddoutclk# e3 scnck1 scanclk1 s1 scnck2 scanclk2 s5 scninv scaninteval s3 scnsn scanshiften q5 sd#0 sdata[0]# aa35 sd#1 sdata[1]# w37 sd#2 sdata[2]# w35 sd#3 sdata[3]# y35 sd#4 sdata[4]# u35 sd#5 sdata[5]# u33 sd#6 sdata[6]# s37 sd#7 sdata[7]# s33 sd#8 sdata[8]# aa33 sd#9 sdata[9]# ae37 sd#10 sdata[10]# ac33 sd#11 sdata[11]# ac37 sd#12 sdata[12]# y37 sd#13 sdata[13]# aa37 sd#14 sdata[14]# ac35 sd#15 sdata[15]# s35 sd#16 sdata[16]# q37 sd#17 sdata[17]# q35 sd#18 sdata[18]# n37 sd#19 sdata[19]# j33 sd#20 sdata[20]# g33 sd#21 sdata[21]# g37 sd#22 sdata[22]# e37 sd#23 sdata[23]# g35 sd#24 sdata[24]# q33 sd#25 sdata[25]# n33 sd#26 sdata[26]# l33 sd#27 sdata[27]# n35 sd#28 sdata[28]# l37 sd#29 sdata[29]# j37 sd#30 sdata[30]# a37 sd#31 sdata[31]# e35 sd#32 sdata[32]# e31 table 23. pin name abbreviations (continued) abbreviation full name pin sd#33 sdata[33]# e29 sd#34 sdata[34]# a27 sd#35 sdata[35]# a25 sd#36 sdata[36]# e21 sd#37 sdata[37]# c23 sd#38 sdata[38]# c27 sd#39 sdata[39]# a23 sd#40 sdata[40]# a35 sd#41 sdata[41]# c35 sd#42 sdata[42]# c33 sd#43 sdata[43]# c31 sd#44 sdata[44]# a29 sd#45 sdata[45]# c29 sd#46 sdata[46]# e23 sd#47 sdata[47]# c25 sd#48 sdata[48]# e17 sd#49 sdata[49]# e13 sd#50 sdata[50]# e11 sd#51 sdata[51]# c15 sd#52 sdata[52]# e9 sd#53 sdata[53]# a13 sd#54 sdata[54]# c9 sd#55 sdata[55]# a9 sd#56 sdata[56]# c21 sd#57 sdata[57]# a21 sd#58 sdata[58]# e19 sd#59 sdata[59]# c19 sd#60 sdata[60]# c17 sd#61 sdata[61]# a11 sd#62 sdata[62]# a17 sd#63 sdata[63]# a15 sdic#0 sdatainclk[0]# w33 sdic#1 sdatainclk[1]# j35 sdic#2 sdatainclk[2]# e27 sdic#3 sdatainclk[3]# e15 sdinv# sdatainvalid# an33 sdoc#0 sdataoutclk[0]# ae35 sdoc#1 sdataoutclk[1]# c37 sdoc#2 sdataoutclk[2]# a33 table 23. pin name abbreviations (continued) abbreviation full name pin chapter 10 pin descriptions 67 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information sdoc#3 sdataoutclk[3]# c11 sdov# sdataoutvalid# al31 sfillv# sfillvalid# aj31 smi# an5 svid[0] softvid[0] f8 svid[1] softvid[1] k8 svid[2] softvid[2] h6 svid[3] softvid[3] h8 svid[4] softvid[4] h10 stpc# stpclk# ac1 tck q1 tdi u1 tdo u5 thda thermda s7 thdc thermdc u7 tms q3 trst# u3 vcc vcc_core b4 vcc vcc_core b8 vcc vcc_core b12 vcc vcc_core b16 vcc vcc_core b20 vcc vcc_core b24 vcc vcc_core b28 vcc vcc_core b32 vcc vcc_core b36 vcc vcc_core d2 vcc vcc_core d4 vcc vcc_core d8 vcc vcc_core d12 vcc vcc_core d16 vcc vcc_core d20 vcc vcc_core d24 vcc vcc_core d28 vcc vcc_core d32 vcc vcc_core f12 vcc vcc_core f16 vcc vcc_core f20 vcc vcc_core f24 table 23. pin name abbreviations (continued) abbreviation full name pin vcc vcc_core f28 vcc vcc_core f32 vcc vcc_core f34 vcc vcc_core f36 vcc vcc_core h2 vcc vcc_core h4 vcc vcc_core h12 vcc vcc_core h16 vcc vcc_core h20 vcc vcc_core h24 vcc vcc_core k32 vcc vcc_core k34 vcc vcc_core k36 vcc vcc_core m2 vcc vcc_core m4 vcc vcc_core m6 vcc vcc_core m8 vcc vcc_core p30 vcc vcc_core p32 vcc vcc_core p34 vcc vcc_core p36 vcc vcc_core r2 vcc vcc_core r4 vcc vcc_core r6 vcc vcc_core r8 vcc vcc_core t30 vcc vcc_core t32 vcc vcc_core t34 vcc vcc_core t36 vcc vcc_core v2 vcc vcc_core v4 vcc vcc_core v6 vcc vcc_core v8 vcc vcc_core x30 vcc vcc_core x32 vcc vcc_core x34 vcc vcc_core x36 vcc vcc_core z2 vcc vcc_core z4 table 23. pin name abbreviations (continued) abbreviation full name pin 68 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information vcc vcc_core z6 vcc vcc_core z8 vcc vcc_core ab30 vcc vcc_core ab32 vcc vcc_core ab34 vcc vcc_core ab36 vcc vcc_core ad2 vcc vcc_core ad4 vcc vcc_core ad6 vcc vcc_core af14 vcc vcc_core af18 vcc vcc_core af22 vcc vcc_core af26 vcc vcc_core af34 vcc vcc_core af36 vcc vcc_core ah2 vcc vcc_core ah4 vcc vcc_core ah10 vcc vcc_core ah14 vcc vcc_core ah18 vcc vcc_core ah22 vcc vcc_core ah26 vcc vcc_core aj5 vcc vcc_core ak10 vcc vcc_core ak14 vcc vcc_core ak18 vcc vcc_core ak22 vcc vcc_core ak26 vcc vcc_core ak30 vcc vcc_core ak34 vcc vcc_core ak36 vcc vcc_core al5 vcc vcc_core am2 vcc vcc_core am10 vcc vcc_core am14 vcc vcc_core am18 vcc vcc_core am22 vcc vcc_core am26 vcc vcc_core am30 table 23. pin name abbreviations (continued) abbreviation full name pin vcc vcc_core am34 vcca aj23 vid[0] l1 vid[1] l3 vid[2] l5 vid[3] l7 vid[4] j7 vref_s vref_sys w5 vss b2 vss b6 vss b10 vss b14 vss b18 vss b22 vss b26 vss b30 vss b34 vss d6 vss d10 vss d14 vss d18 vss d22 vss d26 vss d30 vss d34 vss d36 vss f2 vss f4 vss f6 vss f10 vss f14 vss f18 vss f22 vss f26 vss h14 vss h18 vss h22 vss h26 vss h34 table 23. pin name abbreviations (continued) abbreviation full name pin chapter 10 pin descriptions 69 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information vss h36 vss k2 vss k4 vss k6 vss m30 vss m32 vss m34 vss m36 vss p2 vss p4 vss p6 vss p8 vss r30 vss r32 vss r34 vss r36 vss t2 vss t4 vss t6 vss t8 vss v30 vss v32 vss v34 vss v36 vss x2 vss x4 vss x6 vss x8 vss z30 vss z32 vss z34 vss z36 vss ab2 vss ab8 vss ab4 vss ab6 vss ad32 vss ad34 vss ad36 table 23. pin name abbreviations (continued) abbreviation full name pin vss af12 vss af16 vss af2 vss af20 vss af24 vss ah16 vss ah34 vss af4 vss ah12 vss ah20 vss ah24 vss ah28 vss ah32 vss ah36 vss ak2 vss ak4 vss ak12 vss ak16 vss ak20 vss ak24 vss ak28 vss ak32 vss am4 vss am6 vss am12 vss am16 vss am20 vss am24 vss am28 vss am32 vss am36 zn ac5 zp ae5 table 23. pin name abbreviations (continued) abbreviation full name pin 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information chapter 10 pin descriptions 70 10.2 pin list table 24 cross-references socket a pin location to signal name. the ?l? (level) column shows the electrical specification for this pin. ?p? indicates a push-pull mode driven by a single source. ?o? indicates open-drain mode that allows devices to share the pin. note: socket a amd duron processors support push-pull drivers. for more information, see ?push-pull (pp) drivers? on page 6. the ?p? (port) column indicates if this signal is an input (i), output (o), or bidirectional (b) signal. the ?r? (reference) column indicates if this signal should be referenced to vss (g) or vcc_core (p) planes for the purpose of signal routing with respect to the current return path s. the ??? is used to indicate that this description is no t applicable for this pin. table 24. cross-reference by pin location pin name description l p r a1 no pin page 80 ? ? ? a3 saddout[12]# p o g a5 saddout[5]# p o g a7 saddout[3]# p o g a9 sdata[55]# p b p a11 sdata[61]# p b p a13 sdata[53]# p b g a15 sdata[63]# p b g a17 sdata[62]# p b g a19 nc pin page 80 - - - a21 sdata[57]# p b g a23 sdata[39]# p b g a25 sdata[35]# p b p a27 sdata[34]# p b p a29 sdata[44]# p b g a31 nc pin page 80 - - - a33 sdataoutclk[2]# p o p a35 sdata[40]# p b g a37 sdata[30]# p b p b2 vss ? - - b4 vcc_core - - - b6 vss - - - b8 vcc_core - - - b10 vss - - - b12 vcc_core - - - b14 vss - - - b16 vcc_core - - - b18 vss - - - b20 vcc_core - - - b22 vss - - - b24 vcc_core - - - b26 vss - - - b28 vcc_core - - - b30 vss - - - table 24. cross-reference by pin location pin name description l p r chapter 10 pin descriptions 71 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information b32 vcc_core - - - b34 vss - - - b36 vcc_core - - - c1 saddout[7]# p o g c3 saddout[9]# p o g c5 saddout[8]# p o g c7 saddout[2]# p o g c9 sdata[54]# p b p c11 sdataoutclk[3]# p o g c13 nc pin page 80 - - - c15 sdata[51]# p b p c17 sdata[60]# p b g c19 sdata[59]# p b g c21 sdata[56]# p b g c23 sdata[37]# p b p c25 sdata[47]# p b g c27 sdata[38]# p b g c29 sdata[45]# p b g c31 sdata[43]# p b g c33 sdata[42]# p b g c35 sdata[41]# p b g c37 sdataoutclk[1]# p o g d2 vcc_core - - - d4 vcc_core - - - d6 vss - - - d8 vcc_core - - - d10 vss - - - d12 vcc_core - - - d14 vss - - - d16 vcc_core - - - d18 vss - - - d20 vcc_core - - - d22 vss - - - d24 vcc_core - - - table 24. cross-reference by pin location pin name description l p r d26 vss - - - d28 vcc_core - - - d30 vss - - - d32 vcc_core - - - d34 vss - - - d36 vss - - - e1 saddout[11]# p o p e3 saddoutclk# p o g e5 saddout[4]# p o p e7 saddout[6]# p o g e9 sdata[52]# p b p e11 sdata[50]# p b p e13 sdata[49]# p b g e15 sdatainclk[3]# p i g e17 sdata[48]# p b p e19 sdata[58]# p b g e21 sdata[36]# p b p e23 sdata[46]# p b p e25 nc pin page 80 - - - e27 sdatainclk[2]# p i g e29 sdata[33]# p b p e31 sdata[32]# p b p e33 nc pin page 80 - - - e35 sdata[31]# p b p e37 sdata[22]# p b g f2 vss - - - f4 vss - - - f6 vss - - - f8 softvid[0] page 81 o o - f10 vss - - - f12 vcc_core - - - f14 vss - - - f16 vcc_core - - - f18 vss - - - table 24. cross-reference by pin location pin name description l p r (continued) 72 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information f20 vcc_core - - - f22 vss - - - f24 vcc_core - - - f26 vss - - - f28 vcc_core - - - f30 nc pin page 80 - - - f32 vcc_core - - - f34 vcc_core - - - f36 vcc_core - - - g1 saddout[10]# p o p g3 saddout[14]# p o g g5 saddout[13]# p o g g7 key pin page 80 - - - g9 key pin page 80 - - - g11 nc pin page 80 - - - g13 nc pin page 80 - - - g15 key pin page 80 - - - g17 key pin page 80 - - - g19 nc pin page 80 - - - g21 nc pin page 80 - - - g23 key pin page 80 - - - g25 key pin page 80 - - - g27 nc pin page 80 - - - g29 nc pin page 80 - - - g31 nc pin page 80 - - - g33 sdata[20]# p b g g35 sdata[23]# p b g g37 sdata[21]# p b g h2 vcc_core - - - h4 vcc_core - - - h6 softvid[2] page 81 o o - h8 softvid[3] page 81 o o - h10 softvid[4] page 81 o o - h12 vcc_core - - - table 24. cross-reference by pin location pin name description l p r h14 vss - - - h16 vcc_core - - - h18 vss - - - h20 vcc_core - - - h22 vss - - - h24 vcc_core - - - h26 vss - - - h28 nc pin page 80 - - - h30 nc pin page 80 - - - h32 nc pin page 80 - - - h34 vss - - - h36 vss - - - j1 saddout[0]# page 81 p o - j3 saddout[1]# page 81 p o - j5 nc pin page 80 - - - j7 vid[4] page 81 o o - j31 nc pin page 80 - - - j33 sdata[19]# p b g j35 sdatainclk[1]# p i p j37 sdata[29]# p b p k2 vss - - - k4 vss - - - k6 vss - - - k8 softvid[1] page 81 o o - k30 nc pin page 80 - - - k32 vcc_core - - - k34 vcc_core - - - k36 vcc_core - - - l1 vid[0] page 81 o o - l3 vid[1] page 81 o o - l5 vid[2] page 81 o o - l7 vid[3] page 81 o o - l31 nc pin page 80 - - - l33 sdata[26]# p b p table 24. cross-reference by pin location pin name description l p r (continued) chapter 10 pin descriptions 73 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information l35 nc pin page 80 - - - l37 sdata[28]# p b p m2 vcc_core - - - m4 vcc_core - - - m6 vcc_core - - - m8 vcc_core - - - m30 vss - - - m32 vss - - - m34 vss - - - m36 vss - - - n1 rsvd page 80 - - - n3 rsvd page 80 - - - n5 rsvd page 80 - - - n7 key pin page 80 - - - n31 nc pin page 80 - - - n33 sdata[25]# p b p n35 sdata[27]# p b p n37 sdata[18]# p b g p2 vss - - - p4 vss - - - p6 vss - - - p8 vss - - - p30 vcc_core - - - p32 vcc_core - - - p34 vcc_core - - - p36 vcc_core - - - q1 tck page 79 p i - q3 tms page 79 p i - q5 scanshiften page 81 p i - q7 key pin page 80 - - - q31 nc pin page 80 - - - q33 sdata[24]# p b p q35 sdata[17]# p b g q37 sdata[16]# p b g table 24. cross-reference by pin location pin name description l p r r2 vcc_core - - - r4 vcc_core - - - r6 vcc_core - - - r8 vcc_core - - - r30 vss - - - r32 vss - - - r34 vss - - - r36 vss - - - s1 scanclk1 page 81 p i - s3 scaninteval page 81 p i - s5 scanclk2 page 81 p i - s7 thermda page 83 - - - s31 nc pin page 80 - - - s33 sdata[7]# p b g s35 sdata[15]# p b p s37 sdata[6]# p b g t2 vss - - - t4 vss - - - t6 vss - - - t8 vss - - - t30 vcc_core - - - t32 vcc_core - - - t34 vcc_core - - - t36 vcc_core - - - u1 tdi page 79 p i - u3 trst# page 79 p i - u5 tdo page 79 p o - u7 thermdc page 83 - - - u31 nc pin page 80 - - - u33 sdata[5]# p b g u35 sdata[4]# p b g u37 nc pin page 80 - - - v2 vcc_core - - - v4 vcc_core - - - table 24. cross-reference by pin location pin name description l p r (continued) 74 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information v6 vcc_core - - - v8 vcc_core - - - v30 vss - - - v32 vss - - - v34 vss - - - v36 vss - - - w1 fid[0] page 79 o o - w3 fid[1] page 79 o o - w5 vref_sys page 83 p - - w7 nc pin page 80 - - - w31 nc pin page 80 - - - w33 sdatainclk[0]# p i g w35 sdata[2]# p b g w37 sdata[1]# p b p x2 vss - - - x4 vss - - - x6 vss - - - x8 vss - - - x30 vcc_core - - - x32 vcc_core - - - x34 vcc_core - - - x36 vcc_core - - - y1 fid[2] page 79 o o - y3 fid[3] page 79 o o - y5 nc pin page 80 - - - y7 key pin page 80 - - - y31 nc pin page 80 - - - y33 nc pin page 80 - - - y35 sdata[3]# p b g y37 sdata[12]# p b p z2 vcc_core - - - z4 vcc_core - - - z6 vcc_core - - - z8 vcc_core - - - table 24. cross-reference by pin location pin name description l p r z30 vss - - - z32 vss - - - z34 vss - - - z36 vss - - - aa1 dbrdy page 79 p o - aa3 dbreq# page 79 p i - aa5 nc pin page 80 - - - aa7 key pin page 80 - - - aa31 nc pin page 80 - - - aa33 sdata[8]# p b p aa35 sdata[0]# p b g aa37 sdata[13]# p b g ab2 vss - - - ab4 vss - - - ab6 vss - - - ab8 vss - - - ab30 vcc_core - - - ab32 vcc_core - - - ab34 vcc_core - - - ab36 vcc_core - - - ac1 stpclk# page 81 p i - ac3 plltest# page 80 p i - ac5 zn page 83 p - - ac7 nc pin page 80 - - - ac31 nc pin page 80 - - - ac33 sdata[10]# p b p ac35 sdata[14]# p b g ac37 sdata[11]# p b g ad2 vcc_core - - - ad4 vcc_core - - - ad6 vcc_core - - - ad8 nc pin page 80 - - - ad30 nc pin page 80 - - - ad32 vss - - - table 24. cross-reference by pin location pin name description l p r (continued) chapter 10 pin descriptions 75 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information ad34 vss - - - ad36 vss - - - ae1 a20m# p i - ae3 pwrok p i - ae5 zp page 83 p - - ae7 nc pin page 80 - - - ae31 nc pin page 80 - - - ae33 saddin[5]# p i g ae35 sdataoutclk[0]# p o p ae37 sdata[9]# p b g af2 vss - - - af4 vss - - - af6 nc pin page 80 - - - af8 nc pin page 80 - - - af10 nc pin page 80 - - - af12 vss - - - af14 vcc_core - - - af16 vss - - - af18 vcc_core - - - af20 vss - - - af22 vcc_core - - - af24 vss - - - af26 vcc_core - - - af28 nc pin page 80 - - - af30 nc pin page 80 - - - af32 nc pin page 80 - - - af34 vcc_core - - - af36 vcc_core - - - ag1 ferr page 79 p o - ag3 reset# - i - ag5 nc pin page 80 - - - ag7 key pin page 80 - - - ag9 key pin page 80 - - - ag11 corefb page 78 - - - table 24. cross-reference by pin location pin name description l p r ag13 corefb# page 78 - - - ag15 key pin page 80 - - - ag17 key pin page 80 - - - ag19 nc pin page 80 - - - ag21 nc pin page 80 - - - ag23 nc pin page 80 - - - ag25 nc pin page 80 - - - ag27 key pin page 80 - - - ag29 key pin page 80 - - - ag31 nc pin page 80 - - - ag33 saddin[2]# p i g ag35 saddin[11]# p i g ag37 saddin[7]# p i p ah2 vcc_core - - - ah4 vcc_core - - - ah6 amd pin page 78 - - - ah8 nc pin page 80 - - - ah10 vcc_core - - - ah12 vss - - - ah14 vcc_core - - - ah16 vss - - - ah18 vcc_core - - - ah20 vss - - - ah22 vcc_core - - - ah24 vss - - - ah26 vcc_core - - - ah28 vss - - - ah30 nc pin page 80 - - - ah32 vss - - - ah34 vss - - - ah36 vss - - - aj1 ignne# page 79 p i - aj3 init# page 79 p i - aj5 vcc_core - - - table 24. cross-reference by pin location pin name description l p r (continued) 76 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information aj7 nc pin page 80 - - - aj9 nc pin page 80 - - - aj11 nc pin page 80 - - - aj13 analog page 78 - - - aj15 nc pin page 80 - - - aj17 nc pin page 80 - - - aj19 nc pin page 80 - - - aj21 clkfwdrst page 78 p i p aj23 vcca page 83 - - - aj25 pllbypass# page 80 p i - aj27 nc pin page 80 - - - aj29 saddin[0]# page 81 p i - aj31 sfillvalid# p i g aj33 saddinclk# p i g aj35 saddin[6]# p i p aj37 saddin[3]# p i g ak2 vss - - - ak4 vss - - - ak6 cpu_presence# page 78 - - - ak8 nc pin page 80 - - - ak10 vcc_core - - - ak12 vss - - - ak14 vcc_core - - - ak16 vss - - - ak18 vcc_core - - - ak20 vss - - - ak22 vcc_core - - - ak24 vss - - - ak26 vcc_core - - - ak28 vss - - - ak30 vcc_core - - - ak32 vss - - - ak34 vcc_core - - - ak36 vcc_core - - - table 24. cross-reference by pin location pin name description l p r al1 intr page 79 p i - al3 flush# page 79 p i - al5 vcc_core - - - al7 nc pin page 80 - - - al9 nc pin page 80 - - - al11 nc pin page 80 - - - al13 pllmon2 page 80 o o - al15 pllbypassclk# page 80 p i - al17 clkin# page 78 p i p al19 rstclk# page 78 p i p al21 k7clkout page 80 p o - al23 connect page 78 p i p al25 nc pin page 80 - - - al27 nc pin page 80 - - - al29 saddin[1]# page 81 p i - al31 sdataoutvalid# p o p al33 saddin[8]# p i p al35 saddin[4]# p i g al37 saddin[10]# p i g am2 vcc_core - - - am4 vss - - - am6 vss - - - am8 nc pin page 80 - - - am10 vcc_core - - - am12 vss - - - am14 vcc_core - - - am16 vss - - - am18 vcc_core - - - am20 vss - - - am22 vcc_core - - - am24 vss - - - am26 vcc_core - - - am28 vss - - - am30 vcc_core - - - table 24. cross-reference by pin location pin name description l p r (continued) chapter 10 pin descriptions 77 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information am32 vss - - - am34 vcc_core - - - am36 vss - - - an1 no pin page 80 - - - an3 nmi p i - an5 smi# p i - an7 nc pin page 80 - - - an9 nc pin page 80 - - - an11 nc pin page 80 - - - an13 pllmon1 page 80 o b - an15 pllbypassclk page 80 p i - an17 clkin page 78 p i p an19 rstclk page 78 p i p an21 k7clkout# page 80 p o - an23 procrdy p o p an25 nc pin page 80 - - - an27 nc pin page 80 - - - an29 saddin[12]# p i g an31 saddin[14]# p i g an33 sdatainvalid# p i p an35 saddin[13]# p i g an37 saddin[9]# p i g table 24. cross-reference by pin location pin name description l p r (continued) 78 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 10.3 detailed pin descriptions the information in this section pertains to table 23 on page 64 and table 24 on page 70. a20m# pin a20m# is an input from the syst em used to simulate address wrap-around in the 20-bit 8086. amd pin amd socket a processors do no t implement a pin at location ah6. all socket a designs must have a top plate or cover that blocks this pin location. when the cover plate blocks this location, a non-amd part (e.g., pga370) does not fit into the socket. however, socket manufacturers are allowed to have a contact loaded in the ah6 posi tion. therefore, motherboard socket design should account for the possibility that a contact could be loaded in this position. amd duron? system bus pins see the amd athlon? and amd duron? system bus specification , order# 21902 for information about the system bus pins?procrdy, pwrok, reset#, saddin[14:2]#, saddinclk#, saddout[14:2]#, saddoutclk#, sdata[63:0]#, sdatainclk[3:0]#, sdatainvalid#, sdataoutclk[3:0]#, sdataoutvalid#, sfillvalid#. analog pin treat this pin as a nc. clkfwdrst pin clkfwdrst resets clock-forward circuitry for both the system and processor. clkin and rstclk (sysclk) pins connect clkin (an17) with rstclk (an19) and name it sysclk. connect clkin# (al17) with rstclk# (al19) and name it sysclk#. length match the clocks from the clock generator to the northbridge and processor. see ?sysclk and sysclk#? on page 83 for more information. connect pin connect is an input from the system used for power management and clock-forwar d initialization at reset. corefb and corefb# pins corefb and corefb# are outputs to the system that provide processor core voltage feedback to the system. cpu_presence# pin cpu_presence# is connected to vss on the processor package. if pulled-up on the motherboard, cpu_presence# may be used to detect the presence or absence of a processor. chapter 10 pin descriptions 79 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information dbrdy and dbreq# pins dbrdy (aa1) and dbreq# (aa3) are routed to the debug connector. dbreq# is tied to vcc_core with a pullup resistor. ferr pin ferr is an output to the syst em that is asserted for any unmasked numerical exception i ndependent of the ne bit in cr0. ferr is a push-pull active high signal that must be inverted and level shifted to an active low signal. for more information about ferr and ferr#, see the ?required circuits? chapter of the amd athlon? processor-based motherboard design guide , order# 24363. fid[3:0] pins the fid[3:0] pins drive a value of: fid[3:0] = 0 1 0 0 that corresponds to a 5x sy sclk multiplier after pwrok is asserted to the processor. this information is used by the northbridge to create the sip stream that the northbridge sends to the processor afte r reset# is deasserted. for more information, see ?sysclk multipliers? on page 24 and ?frequency identification (fid[3:0])? on page 35 for the ac and dc characteristics for fid[3:0]. flush# pin flush# must be tied to vcc_core with a pullup resistor. if a debug connector is implemente d, flush# is routed to the debug connector. ignne# pin ignne# is an input from the syst em that tells the processor to ignore numeric errors. init# pin init# is an input from the system that resets the integer registers without affecting the fl oating-point registers or the internal caches. execution starts at 0ffff fff0h. intr pin intr is an input from the system that causes the processor to start an interrupt acknowledge transaction that fetches the 8-bit interrupt vector and starts execution at that location. jtag pins tck (q1), tms (q3), tdi (u1), trst# (u3), and tdo (u5) are the jtag interface. connect these pins directly to the motherboard debug connector. pullup tdi, tck, tms, and trst# to vcc_core with pullup resistors. 80 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information k7clkout and k7clkout# pins k7clkout (al21) and k7clkout# (an21) are each run for 2 to 3 inches and then terminated with a resistor pair, 100 ohms to vcc_core and 100 ohms to vss. the effective termination resistance and voltage are 50 ohms and vcc_core/2. key pins these 16 locations are for processor type keying for forwards and backwards compatibility (g7, g9, g15, g17, g23, g25, n7, q7, y7, aa7, ag7, ag9, ag15, ag17, ag27, and ag29). motherboard designers should treat key pins like nc (no connect) pins. a socket designer has the option of creating a top mold piece that allows pga key pins only where designated. however, sockets that populate a ll 16 key pins must be allowed, so the motherboard must always provide for pins at all key pin locations. nc pins the motherboard should provide a plated hole for an nc pin. the pin hole should not be elec trically connected to anything. nmi pin nmi is an input from the syst em that causes a non-maskable interrupt. pga orientation pins no pin is present at pin loca tions a1 and an1. motherboard designers should not allow for a pga socket pin at these locations. for more information, see the amd athlon? processor-based motherboard design guide , order# 24363. pll bypass and test pins plltest# (ac3), pllbypass# (aj25), pllmon1 (an13), pllmon2 (al13), pllbypassclk (an15), and pllbypassclk# (al15) are the pll bypass and test interface. this interface is ti ed disabled on the motherboard. all six pin signals are routed to the debug connector. all four processor inputs (plltest#, pllbypass#, pllmon1, and pllmon2) are tied to vcc_c ore with pullup resistors. pwrok pin the pwrok input to the processo r must not be asserted until all voltage planes in the system are within specification and all system clocks are running within specification. for more information, see ?signal and power-up requirements? on page 53. rsvd pins reserved pins (n1, n3, and n5) must have pulldown resistors to ground on the motherboards. chapter 10 pin descriptions 81 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information saddin[1:0]# and saddout[1:0]# pins the mobile amd duron processor model 7 does not support saddin[1:0]# or saddout[1:0]#. saddin[1]# is tied to vcc with pullup resistors, if this bit is not supported by the northbridge (future models of the mobile amd duron processors may support saddin[1]#). saddout[1:0]# are tied to vcc with pullup resistors if these pins are supported by the northbridge. for more information, see the amd athlon? and amd duron? system bus specification , order# 21902. scan pins scanshiften (q5), scanclk1 (s1), scaninteval (s3), and scanclk2 (s5) are the scan interface. this interface is amd internal and is tied disabled with pulldown resistors to ground on the motherboard. smi# pin smi# is an input that causes the processor to enter the system management mode. softvid[4:0] and vid[4:0] pins the vid[4:0] (voltage id) and softvid[4:0] (software driven voltage id) outputs are used by the dc to dc power converter to select the processor core voltage. the vid[4:0] pins are strapped to ground or left unconnected on the package and must be pulled up on the motherboard. the softvid[4:0] pins are open drain and 2.5-v tolerant. the softvid[4:0] pins of the processor must not be pulled to voltages higher than 2.5 v. the motherboard is required to implement a vid multiplexer to select a deterministic voltage for the processor at power?up before the pwrok input is asserted. before pwrok is asserted, the vid multiplexer drives the vid value from vid[4:0] pins to the dc to dc converter for vcc_core. after pwrok is asserted, the vid multiplexer drives the vid value from the softvid[4:0] pins to the dc to dc converter for vcc_core of the processor. refer to the amd athlon? processor-based motherboard design guide , order# 24363 for the recommended vid multiplexer circuit. the softvid[4:0] pins are driven by the processor to select the maximum vcc_core of the processor as reported by the maximum vid field of the fidvidstatus msr within 20 ns of pwrok assertion. before pwrok is asserted, the softvid[4:0] outputs are not driven to a deterministic value. the softvid[4:0] outputs must be used to select vcc_core after pwrok is asserted. any time the reset# input is asserted, the softvid[4:0] pins will be driven to select the maximum voltage. 82 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information note: the start?up vid and maximum vid fields of the fidvidstatus msr report the same value that corresponds to the nominal voltage that the processor requires to operate at maximum frequency. amd powernow!? technology can use the fid_change protocol described in section on page 9 to transition the softvid[4:0] outputs and therefore vcc_core as part of processor performance state transitions. the vid codes used by the mobile amd duron processor model 7 are defined in table 25. note: vid codes for the mobile amd duron processors are different from the vid codes for the desktop amd duron processors. stpclk# pin stpclk# is an input that causes the processor to enter a lower power mode and issue a stop grant special cycle. table 25. softvid[4:0] and vid[4:0] code to voltage definition vid[4:0] vcc_core (v) vid[4:0] vcc_core (v) 00000 2.000 10000 1.275 00001 1.950 10001 1.250 00010 1.900 10010 1.225 00011 1.850 10011 1.200 00100 1.800 10100 1.175 00101 1.750 10101 1.150 00110 1.700 10110 1.125 00111 1.650 10111 1.100 01000 1.600 11000 1.075 01001 1.550 11001 1.050 01010 1.500 11010 1.025 01011 1.450 11011 1.000 01100 1.400 11100 0.975 01101 1.350 11101 0.950 01110 1.300 11110 0.925 01111 shutdown 11111 shutdown chapter 10 pin descriptions 83 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information sysclk and sysclk# sysclk and sysclk# are differential input clock signals provided to the processor?s pll from a system-clock generator. see ?clkin and rstclk (sysclk) pins? on page 78 for more information. thermda and thermdc pins thermal diode anode (thermda) and cathode (thermdc) pins are used to monitor th e actual temperature of the processor die, providing more accurate temperature control to the system. see table 17 on page 48 for more details. vcca pin vcca is the processor pll supply. for information about the vcca pin, see table 7, ?vcca ac and dc characteristics,? on page 35 and the amd athlon? processor-based motherboard design guide , order# 24363. vref_sys pin vref_sys (w5) drives the th reshold voltage for the system bus input receivers. the value of vref_sys is system specific. in addition, to minimize v cc_core noise rejection from vref_sys, include decoupling capacitors. for more information, see the amd athlon? processor-based motherboard design guide , order# 24363. zn and zp pins zn (ac5) and zp (ae5) are the push-pull compensation circuit pins. in push-pull mode (selected by the sip parameter syspushpull asserted), zn is ti ed to vcc_core with a resistor that has a resistance matching the impedance z 0 of the transmission line. zp is tied to vss with a resistor that has a resistance matching the impedance z 0 of the transmission line. 84 pin descriptions chapter 10 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information chapter 11 ordering information 85 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information 11 ordering information 11.1 standard mobile amd duron? processor model 7 products amd standard products are available in several operating ranges. the ordering part nu mber (opn) is formed by a combination of the elemen ts shown in figure 17. t h is o pn is g iven as an example o nly. figure 17. opn example for the mobile amd duron? processor model 7 d 1000 a v s 1 b note: spaces are added to the number shown above for viewing clarity only. c pga opn h m max fsb: b= 200 mhz size of l2 cache: 1=64kbytes die temperature: s=95oc operating voltage: l=1.50 v, q=1.45 v, v=1.40 v package type: a = cpga speed: 0800=800 mhz, 0850=850, 0900=900 mhz, 0950=950 mhz, 1000=1000 mhz generation: hm = high-performance processor for mobile systems family/architecture: d = amd duron? processor architecture 86 ordering information chapter 11 mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information appendix a 87 appendix a conventions, abbreviations, and references this section contains informat ion about the conventions and abbreviations used in this document. signals and bits active-low signals?signal names containing a pound sign, such as sfill#, indicate active-low signals. they are asserted in their low-voltage state and negated in their high-voltage state. when used in this context, high and low are written with an initial upper case letter. signal ranges?in a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (for example, d[63:0]). reserved bits and signals? signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descri ptions. these bits and signals are reserved by amd for future implementations. when software reads registers with reserved bits, the reserved bits must be masked. when software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. three-state?in timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels. 88 appendix a mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information invalid and don?t-care?in timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. data terminology the following list defines data terminology: quantities a word is two bytes (16 bits) a doubleword is four bytes (32 bits) a quadword is eight bytes (64 bits) a mobile amd duron processor model 7 cache line is eight quadwords (64 bytes) addressing?memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. abbreviations?the following notation is used for bits and bytes: kilo (k, as in 4-kbyte page) mega (m, as in 4 mbits/sec) giga (g, as in 4 gbytes of memory space) see table 26 for more abbreviations. little-endian convention?the byte with the address xx...xx00 is in the least-significant byte position (little end). in byte diagrams, bit positions are numbered from right to left?the little end is on the right and the big end is on the left. data structure diagrams in memory show low addresses at the bottom and high addresses at the top. when data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. because byte addresses increase from right to left, strings appear in reverse order when illustrated. bit ranges?in text, bit ranges are shown with a dash (for example, bits 9?1). when accompanied by a signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a co lon (for example, ad[31:0]). bit values?bits can either be set to 1 or cleared to 0. hexadecimal and binary numbers?unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b. appendix a 89 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information abbreviations and acronyms table 26 contains the definitions of abbreviations used in this document. table 26. abbreviations abbreviation meaning aampere f farad ggiga? gbit gigabit gbyte gigabyte hhenry h hexadecimal k kilo? kbyte kilobyte m mega? mbit megabit mbyte megabyte mhz megahertz m milli? ms millisecond mw milliwatt micro? a microampere f microfarad h microhenry s microsecond v microvolt nnano? na nanoampere nf nanofarad nh nanohenry ns nanosecond ohm ohm pf picofarad ph picohenry ps picosecond 90 appendix a mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information table 27 contains the definitions of acronyms used in this document. s second vvolt wwatt table 27. acronyms abbreviation meaning acpi advanced configuration and power interface agp accelerated graphics port apci agp peripheral component interconnect api application programming interface bios basic input/output system bist built-in self-test biu bus interface unit cpga ceramic pin grid array ddr double-data rate dimm dual inline memory module dma direct memory access dram direct random access memory eide enhanced integrated device electronics eisa extended industry standard architecture eprom enhanced programmable read only memory fifo first in, first out gart graphics address remapping table hstl high-speed transistor logic ide integrated device electronics isa industry standard architecture jedec joint electron device engineering council jtag joint test action group lan large area network lru least-recently used lvttl low voltage transistor to transistor logic msb most significant bit mtrr memory type and range registers table 26. abbreviations (continued) abbreviation meaning appendix a 91 24068f?december 2001 mobile amd duron? processor model 7 data sheet preliminary information mux multiplexer nmi non-maskable interrupt obga organic ball grid array od open drain pbga plastic ball grid array pa physical address pci peripheral component interconnect pde page directory entry pdt page directory table pll phase locked loop pmsm power management state machine pos power-on suspend post power-on self-test ram random access memory rom read only memory rxa read acknowledge queue sdi system dram interface sdram synchronous direct random access memory sip serial initialization packet smbus system management bus spd serial presence detect sram synchronous random access memory srom serial read only memory tlb translation lookaside buffer tom top of memory ttl transistor to transistor logic vas virtual address space vpa virtual page address vga video graphics adapter usb universal serial bus zdb zero delay buffer table 27. acronyms (continued) abbreviation meaning 92 appendix a mobile amd duron? processor model 7 data sheet 24068f?december 2001 preliminary information related publications the following books discuss various aspects of computer architecture that may enhanc e your understanding of amd products: amd publications mobile amd athlon? and mobile amd duron? processor system requirements, order# 24106 mobile amd athlon? and mobile amd duron? processor power module supply design guide, order# 24125 mobile system thermal design guide, order# 24383 measuring temperature on amd athlon? and amd duron? pin grid array processors with and without an on-die thermal diode, order# 24228 thermal characterization of notebook pcs, order# 24382 methodologies for measuring power, order# 24353 methodologies for measuring temperature on amd athlon? and amd duron? processors, order# 24228 instruction sheet for mobile thermal kits, order# 24400 amd mobile thermal kit documentation and software cd?rom, order# 24406 websites visit the amd website for documentation of amd products. www.amd.com other websites of interest include the following: jedec home page?www.jedec.org ieee home page?www.computer.org agp forum?www.agpforum.org |
Price & Availability of DHM0950AQS1B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |