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plls - smt 6 6 - 1 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: phone: pll@hittite.com typical applications the HMC703LP4E is ideal for: ? microwave point-to-point radios ? base stations for mobile radio (gsm, pcs, dcs, cdma, wcdma) ? wireless lans, wimax ? communications test equipment ? catv equipment ? automotive sensors ? aesa - phased arrays ? fmcw radar systems functional diagram features wide band: dc - 8 ghz rf input best phase noise and spurious in the industry: -112 dbc/hz @ 8 ghz fractional, 50 khz offset figure of merit -230 dbc/hz fractional mode -233 dbc/hz integer mode high pfd rate: 100 mhz < 50 fs rms jitter frequency and phase modulation integrated frequency sweeper triggered frequency hopping external triggering 24 lead 4x4 mm smt package: 16 mm 2 general description the HMC703LP4E fractional synthesizer is built upon the high performance pll platform also contained in the hmc704lp4e and hittites latest generation of pll+vco products. this platform has the best phase- noise and spurious performance in the industry - enabling higher order modulation schemes while minimizing blocker effects in high performance radios. in addition, the HMC703LP4E offers frequency sweep and modulation features, external triggering, double- buffering, exact frequency control, phase modulation and more - while maintaining pin compatibility with the hmc700lp4e pll. exact frequency mode with a 24-bit fractional mod - ulator provides the ability to generate fractional frequencies with zero frequency error and very low channel spurious, an important feature for digital pre- distortion systems. the serial interface offers read back capability and is compatible with a wide variety of protocols.
plls - smt 6 6 - 2 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 1. electrical specifcations unless otherwise specifed, data is collected at 3.3 v, and 5.0 v (on charge-pump), 100 mhz reference, 50 mhz f pd . min and max are specifed across temperature range from -40 c to 85 c ambient. parameter conditions min. typ. max. units rf input characteristics [6][7] rf input frequency range [1] dc 8000 mhz prescaler input freq range [1] dc 4000 mhz power range [13] -15 -10 -3 dbm return loss [15] -18 -12 -7 db ref input characteristics frequency range (3.3v) [1][8] dc 50 350 mhz power from 50 ? source [12] with 100 ? termination off chip 6 dbm return loss [15] -16 -8 db ref divider range (14 bit) 1 16,383 phase detector rate [1] integer mode dc 50 115 mhz fractional mode b dc 50 100 mhz fractional mode a dc 50 80 mhz charge pump cp output current 20 a steps, charge pump gain = cp current/2 amps/rad 0.02 2.5 ma cp hik see charge pump gain section 3.5 6 ma power supplies rvdd, avdd, vccps, vcchf, vccpd, dvdd, vddio 2.7 3.3 3.5 v vddls, vppcp charge pump vddls, vppcp must be equal 2.7 5.0 5.2 v 3.3v - current consumption [9] 100 khz pd 50 mhz pd 100 mhz pd 34 54 74 45 70 95 ma ma ma 5v - current consumption all modes 100 khz pd 50 mhz pd w/ cp hik 100 mhz pd w/ cp hik 3 7 13 5 12 16 ma ma ma power down current [10] 100 ua bias reference voltage pin 12. measured with 10 g? meter 1.880 1.920 1.960 v
plls - smt 6 6 - 3 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com parameter conditions min. typ. max. units phase noise [14] flicker figure of merit (fom)[2] -270 dbc/hz floor figure of merit [11] integer hik mode integer normal mode fractional hik mode [3] fractional normal mode [3] -236 -232 -232 -228 -233 -230 -230 -227 -231 -228 -227 -225 dbc/hz dbc/hz dbc/hz dbc/hz flicker noise at f offset pn fick = flicker fom +20log(f vco ) -10log(f offset ) dbc/hz phase noise floor at f vco with f pd pn foor = floor fom + 10log(f pd ) +20log(f vco /f pd ) dbc/hz vco referred phase noise contribution of the pll vs f offset , f vco, f pd pn = 10log(10 (pnfick /10) + 10 (pnfoor /10) ) dbc/hz jitter ssb 100hz to 100mhz with hmc508lp5e vco 50 fs spurious [4][5] integer boundary spurs @~8ghz offsets less than loop band - width, f pd = 50mhz -60 -52 dbc logic inputs switching theshold (vsw) vih/vil within 50 mv of vsw 38 47 54 % vddio logic output voh output high voltage vddio v vol output low voltage 0 v output impedance : pull up vddio=3.3 v 115 150 180 ohm output impedance : pull dn vddio=3.3 v 130 135 210 ohm dc load 1.5 ma digital output driver delay sck to digital output delay 1.7nsec with a 3 pf load 0.5ns+0.2ns/pf 8.2ns+0.2ns/pf ns ns rf divider range >4ghz integer mode 16 bit , even values only 32 131,070 < 4ghz integer mode 16 bit , all values 16 65,535 > 4ghz fractional mode 16 bit 40.0 131,065.0 < 4ghz fractional mode 16 bit 20.0 65,531.0 [1] frequency is guaranteed across process, voltage and temperature from -40 0 c to 85 0 c. [2] with high charge-pump current, +12dbm 100mhz sine reference [3] fractional fom degrades about 3db/octave for prescaler input frequencies below 2ghz [4] using 50mhz reference with vco tuned to within one loop bandwidth of an integer multiple of the pd frequency. larger offsets produce better results. see the spurious performance section for more information. [5] measured with the HMC703LP4E evaluation board. board design and isolation will affect performance. [6] internal divide-by-2 should be enabled for frequencies >4ghz [7] at low rf frequency, rise and fall times should be less than 1ns to maintain performance [8] slew rate of greater or equal to 0.5 v/ns [9] current consumption depends upon operating mode and frequency of the vco. typical values are for fractional mode. [10] reference input disconnected [11] min/max versus temperature and supply, under typical reference & rf frequencies and power levels [12] slew > 0.5v/ns is recommended , see table 7 , figure 5 , figure 6 for more information. [13] operable with reduced spectral performance outside of this range. [14] this section specifes the phase noise contribution of the pll, solution phase noise with a given vco, loop flter and reference requires a closed loop calculation using hittite pll design tool. [15] as measured on HMC703LP4E evaluation board, with 100ohm external termination. table 34. electrical specifcations (continued)
plls - smt 6 6 - 4 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com typical performance characteristics unless otherwise specifed, plots are measured with a 50 mhz pd rate, vco near 8 ghz, rf power -10 dbm, and a wenzel 100 mhz sinusoid reference. the operating modes in the following plots refer to integer (int), fractional modes a and b, hikcp (hik). figure 1. floor fom vs. mode and temp, 2.5 ma cp current figure 2. flicker fom vs. mode and temp, 2.5 ma cp current figure 3. floor fom vs. output frequency and mode, 2.5 ma cp current figure 4. flicker fom vs. output frequency and mode, 2.5 ma cp current -236 -234 -232 -230 -228 -226 -40 0 40 80 floor fom (dbc/hz) temperature (c) integer mode frac mode a hik integer hik frac mode a -273 -272 -271 -270 -269 -268 -267 -266 -40 -20 0 20 40 60 80 flicker fom (dbc/hz) temperature (c) integer mode frac mode a hik frac mode a hik integer -234 -232 -230 -228 -226 -224 -222 -220 1 2 4 8 floor fom (dbc/hz) frequency (ghz) integer hik integer mode b hik mode b mode a hik mode a -270 -269 -268 -267 -266 -265 1 2 4 8 frequency (ghz) flicker fom (dbc/hz) int hik frac mode a frac mode b frac mode a hik frac mode b -234 -232 -230 -228 -226 -4 -2 0 2 4 6 8 10 12 reference power (dbm) floor fom (dbc/hz) integer mode frac mode b hik frac mode b hik integer 2 1.59 1.26 1 0.63 0.50 0.40 2.52 0.80 reference power (vpp) -272 -271 -270 -269 -268 -4 -2 0 2 4 6 8 10 12 reference power (dbm) flicker fom (dbc/hz) frac mode b hik frac mode b integer mode hik integer mode 2 1.59 1.26 1 0.63 0.50 0.40 2.52 0.80 reference power (vpp) figure 5. floor fom vs. reference power and mode, 2.5 ma cp current [1] figure 6. flicker fom vs. reference power and mode, 2.5 ma cp current [1] [1] 100 mhz sinusoidal wenzel reference.
plls - smt 6 6 - 5 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 7. flicker fom vs. cp current, fractional mode b, 2.5 ma cp current figure 8. floor fom vs. cp current, fractional mode b, 2.5 ma cp current figure 9. flicker fom vs. cp voltage, cp current = 2.5 ma [1] figure 10. floor fom vs. cp voltage, cp current = 2.5 ma [1] figure 11. flicker fom vs. cp voltage, hikcp + cp current = 6 ma [2] figure 12. floor fom vs. cp voltage, hikcp + cp current = 6 ma [2] -232 -230 -228 -226 -224 -222 0 1 2 3 4 5 integer fractional floor fom (dbc/hz) cp voltage (v) -234 -232 -230 -228 -226 -224 -222 0 1 2 3 4 5 floor int fom floor frac fom floor fom (dbc/hz) cp voltage (v) -230 -228 -226 -224 -222 -220 -218 -216 0.5 1 1.5 2 2.5 3 cp current (ma) floor fom (dbc/hz) -270 -268 -266 -264 -262 -260 0.5 1 1.5 2 2.5 3 cp current (ma) flicker fom (dbc/hz) -272 -270 -268 -266 -264 -262 -260 0 1 2 3 4 5 flicker fom (dbc/hz) cp voltage (v) -276 -274 -272 -270 -268 -266 0 1 2 3 4 5 floor fom (dbc/hz) cp voltage (v) [2] active loop filter, with dc bias point on -ve leg of op-amp swept.
plls - smt 6 6 - 6 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 16. rf input limits [6] figure 17. modelled vs. measured phase noise, integer mode hik at 8 ghz [7] figure 18. modelled vs. measured phase noise, fractional mode b, hik at ~ 8 ghz [8] figure 13. typical phase noise & spur performance at 8 ghz + 200 khz [3] -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset(hz) -180 -160 -140 -120 -100 -80 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) -90 -80 -70 -60 -50 -40 -30 -20 -800 -600 -400 -200 0 200 400 600 800 20 khz offset spur 10 khz offset spur spur magnitude (dbc) cp offset current (ua) recommended operating range [3] output frequency = 8 ghz + 200 khz using hmc508lp5e vco, reference input = 100 mhz, pd frequency = 100 mhz, cp current = 2.5 ma, fractional mode b, 20 khz bandwidth loop filter. spur at 200khz due to rf signal at 8ghz + 200khz, spur at 100khz due to prescaler input at 4ghz+100khz. reference feedthrough spur at 100 mhz offset. [4] exact frequency mode channel spacing 100 khz, fractional n, rfout = 8013.6 mhz using hmc508lp5e vco, reference input = 100 mhz, pd frequency = 100 mhz, prescaler divide-by-2 selected. 20 khz loop filter bandwidth, reference feedthrough spur at 100 mhz offset. [5] tuned to 8 ghz + 20 khz, prescaler at 4 ghz + 10 khz, loop bandwidth >> 20 khz , reference frequency 50 mhz. offset polarity should be positive for inverting confgurations and negative otherwise. [6] low frequency minimum power levels not characterized. low frequency limitation is only a function of external ac coupling capacitance signal slew rate. [7] hik integer mode measured at 8 ghz, prescalar at 4 ghz, 50 mhz reference frequency. [8] active fractional b mode (prescalar @ 4 ghz + 2.5 khz), reference frequency 50 mhz. -40 -30 -20 -10 0 10 20 30 0 2000 4000 6000 8000 10000 input power (dbm) rf input frequency at prescalar (mhz) recommended operating range no divider divide by 2 figure 15. integer boundary spur at 8 ghz + 20 khz vs. charge pump offset [5] figure 14. fractional performance, exact frequency mode on at 8013.6 mhz [4] -180 -160 -140 -120 -100 -80 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) modelled pll floor total noise simulated using hittite pll design software measured total noise integrated rms jitter = 44.2 fs 100 hz to 100 mhz -180 -160 -140 -120 -100 -80 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) modelled pll floor total noise simulated using hittite pll design software measured total noise integrated rms jitter = 36.1 fs 100 hz to 100 mhz
plls - smt 6 6 - 7 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com -234 -232 -230 -228 -226 -224 -25 -20 -15 -10 -5 0 5 floor fom (dbc/hz) rf power (dbm) frac mode b frac mode a hik mode b hik mode a hik integer -271 -270.5 -270 -269.5 -269 -268.5 -268 -267.5 -267 -25 -20 -15 -10 -5 0 5 flicker fom (dbc/hz) rf power (dbm) frac mode a hik mode b hik mode a integer hik integer frac mode b figure 19. floor fom near 8 ghz vs rf input power and mode figure 20. flicker fom near 8 ghz vs. rf input power and mode [9] measured with a 100 ? external resistor termination, resulting in 50ohm effective input impedance.. see reference input stage for more details. full fom performance up to maximum 3.3 vpp input voltage. [10] measured with a 100 ? external termination ac coupled on HMC703LP4E evaluation board, as in figure 35 . [11] measured with a 100 ? external termination ac coupled on HMC703LP4E evaluation board, as in figure 37 . -20 -15 -10 -5 0 0 50 100 150 200 250 300 350 return loss (db) reference input frequency (mhz) figure 21. reference input sensitivity, square wave, 50 ? [9] -235 -230 -225 -220 -215 -15 -10 -5 0 5 10 14 mhz sq 25 mhz sq 50 mhz sq 100 mhz sq floor fom (dbc/hz) reference power (dbm) 100 mhz 14 mhz 50 mhz 25 mhz -235 -230 -225 -220 -215 -210 -205 -200 -20 -15 -10 -5 0 5 reference power (dbm) floor fom (dbc/hz) 14 mhz 25 mhz 50 mhz 100 mhz figure 22. reference input sensitivity sinusoid wave, 50 ? [9] figure 23. reference input return loss [10] figure 24. rf input return loss [11] -20 -15 -10 -5 0 0 2000 4000 6000 8000 10000 return loss (db) rf input frequency (mhz)
plls - smt 6 6 - 8 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 25. 2-way auto sweep 3350 3400 3450 3500 3550 3600 3650 3700 3750 0 5 10 15 20 output frequency (mhz) time (milliseconds)
plls - smt 6 6 - 9 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 2. pin descriptions pin number function description 1 sck cmos input: serial port clock 2 sdi cmos input: serial port data 3 dvdd power supply for digital - nominal 3.3 v max 25 ma, f pd dependent 4 vddio power supply for digital io - 3.3 v, 8 ma max (only when driving ld_sdo) 5 ld_sdo cmos output: general purpose output - lock detect, serial data out, others, selectable 6 trig cmos input : external trigger pin. 7 n/c no connect 8 vccps power supply for rf divider, nominal 3.3 v 35 ma max 9 n/c no connect 10 vcoip differential rf inputs. normally ac coupled, 2 v dc bias generated internally. for single ended operation, rfn must be ac coupled to the ground plane, typically 100 pf ceramic. dc bias of 2.3 v is generated internally 11 vcoin 12 vcchf power supply for rf buffer, nominal 3.3 v, 6 ma max 13 vddls power supply for pfd to cp level shifters, nominal 5 v, 5 ma max, f pd dependent. 14 vppcpa power supply for charge pump, nominal 5 v, 10 ma max 15 cp charge pump output 16 avdd power supply for analog bias generation, nominal 3.3 v, 2 ma max 17 bias external bypass decoupling for precision bias circuits, 1.920 v +/-2 mv note: bias ref voltage cannot drive an external load. must be measured with 10 g? meter such as agilent 34410a, normal 10 m? dvm will read erroneously. 18 rvdd power supply for reference path, nominal 3.3 v. 15 ma max reference dependent 19 n/c no connect 20 xrefp reference input. dc bias is generated internally. normally ac coupled externally. 21 vddpd power supply for phase detector. nominally 3.3 v. decoupling for this supply is critical. 5 ma max, f pd dependent 22 n/c no connect 23 cen cmos input: hardware chip enable 24 sen cmos input: serial port latch enable
plls - smt 6 6 - 10 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 3. absolute maximum ratings parameter rating max vdc to paddle on sup p ly pins 3,4,8,12,16,18,21 -0.3 v to +3.6 v vddls, vppcp -0.3 v to +5.5 v vcoin, vcoip single ended dc vcchf -0.2 v vcoin, vcoip differential dc 5.2 v vcoin, vcoip single ended ac 50ohm +7 dbm vcoin, vcoip differential ac 50ohm +13 dbm digital load 1 k? min digital input 1.4 v to 1.7 v min rise time 20 nsec digital input voltage range -0.25 to vddio+0,5 v thermal resistance (jxn to gnd paddle) 25 0 c/w operating temperature range -40 o c to +85 o c storage temperature range -65 o c to + 125 o c maximum junction temperature +125 o c refow soldering peak temperature 260 o c time at peak temperature 40 sec esd sensitivity hbm class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
plls - smt 6 6 - 11 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com outline drawing table 4. package information part number package body material lead finish msl rating package marking [1] HMC703LP4E rohs-compliant low stress injection molded plastic 100% matte sn msl1 [2] h703 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260c notes: [1] package body material: low stress injection molded plastic silica and silicon impregnated. [2] lead and ground paddle material: copper alloy. [3] lead and ground paddle plating: 100% matte tin. [4] dimensions are in inches [millimeters]. [5] lead spacing tolerance is non-cumulative. [6] pad burr length shall be 0.15mm max. pad burr height shall be 0.05mm max. [7] package warp shall not exceed 0.05mm [8] all ground leads and ground paddle must be soldered to pcb rf ground. [9] refer to hittite application note for suggested pcb land pattern.
plls - smt 6 6 - 12 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com evaluation pcb the circuit board used in the application should use rf circuit design techniques. signal lines should have 50 ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. table 5. evaluation order information item contents part number evaluation pcb only HMC703LP4E evaluation pcb eval01-HMC703LP4E evaluation kit HMC703LP4E evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software, hittite pll design software) ekit01 - HMC703LP4E
plls - smt 6 6 - 13 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com evaluation pcb block diagram evaluation pcb schematic to view evaluation pcb schematic please visit www.hittite.com and choose HMC703LP4E from search by part number pull down menu to view the product splash page.
plls - smt 6 6 - 14 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com theory of operation pll basics in its most trivial form, a synthesizer ic, such as the HMC703LP4E forms the heart of the control loop to multiply a low frequency reference source up to a higher frequency. the phase detector (pd) and charge-pump (cp) drive the tuning signal of a voltage-controlled oscillator in an attempt to bring the phases, at the phase-detector input, into alignment. if the loop can manage this, it means that the phase detector inputs (reference and div) must also be at the same frequency. since the frequency of the div signal = fvco / n, this means the control loop must have forced the frequency of the vco output must be locked to n x fpd. figure 26. typical pll in integer synthesizers, n can only take on discrete values (eg. 200, 201, etc.). in fractional synthesizers, such as the HMC703LP4E and others, n can also take on fractional levels, eg. n=20.4. in theory, the fractional divider normally permits higher phase-detector frequencies for a given output frequency, with associated improvements in signal quality (phase-noise). unfortunately, fractional synthesizers suffer from imperfections which do not effect integer synthesizers. these problems can effect the phase noise, but more seriously they tend to manifest as spurious emissions - and these spurs are the most serious drawback of fractional synthesis. hittites fractional synthesizer family (including the HMC703LP4E) offer drastic performance advantages over other fractional synthesizers in the industry. the HMC703LP4E synthesizer consists of the following functional blocks: 1. reference path input buffer and r divider 2. vco path input buffer, rf divide-by-2 and multi-modulus n divider 3. fractional modulator 4. phase detector 5. charge pump 6. main serial port 7. lock detect and register control 8. power on reset circuit
plls - smt 6 6 - 15 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com high performance low spurious operation the HMC703LP4E has been designed for the best phase noise and low spurious content possible in an integrated synthesizer. spurious signals in a synthesizer can occur in any mode of operation and can come from a number of sources. figure of merit, noise floor, and flicker noise models the phase noise of an ideal phase locked oscillator is dependent upon a number of factors: a. frequency of the vco, and the phase detector b. vco sensitivity, kvco, vco and reference oscillator phase noise profles c. charge pump current, loop filter and loop bandwidth d. mode of operation: integer, fractional modulator style the contributions of the pll to the output phase noise can be characterized in terms of a figure of merit (fom) for both the pll noise foor and the pll ficker (1/f) noise regions, as follows: where: p 2 ph ase noise contribution of the pll (rads 2 /hz) f o fr equency of the vco (hz) f pd fr equency of the phase detector (hz) f m fr equency offset from the carrier (hz) f po fi gure of merit (fom) for the phase noise foor f p1 fi gure of merit (fom) for the ficker noise region figure 27. figure of merit noise models for the pll if the free running phase noise of the vco is known, it may also be represented by a fgure of merit for both 1/f 2 , f v2 , and the 1/f 3 , f v3 , regions. ( ) 2 2 0 0 2 0 1 0 , , p p p m pd m pd f f f f f f f f f = + pll phase noise contribution (eq 1)
plls - smt 6 6 - 16 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com the figures of merit are essentially normalized noise parameters for both the pll and vco that can allow quick esti - mates of the performance levels of the pll at the required vco, offset and phase detector fre qu ency. normally, the pll ic noise dominates inside the closed loop bandwidth of the synthesizer, and the vco dominates outside the loop band - width at offsets far from the carrier. hence a quick estimate of the closed loop performance of the pll can be made by setting the loop bandwidth equal to the frequency where the pll and free running phase noise are equal. the figure of merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such as hittite pll design, which can give a much more accurate estimate of the closed loop phase noise and pll loop flter component values. given an optimum loop design, the approximate closed loop performance is simply given by the minimum of the pll and vco noise contributions. ( ) 2 2 2 min , p = an example of the use of the fom values to make a quick estimate of pll performance: estimate the phase noise of an 8 ghz closed loop pll with a 100 mhz reference operating in fractional mode b with the vco operating at 8 ghz and the vco divide by 2 port driving the pll at 4 ghz. assume an hmc509 vco has free running phase noise in the 1/f 2 region at 1 mhz offset of -135 dbc/hz and phase noise in the 1/f 3 region at 1 khz offset of -60 dbc/hz. f v1_db = -1 35 fr ee running vco pn at 1mhz offset +2 0*log10(1e6) pn oise normalized to 1hz offset -20 *log10(8e9) pn oise normalized to 1hz carrier = -2 13.1 dbc/hz at 1hz vc o fom f v3 _db = -6 0 fr ee running vco pn at 1khz offset +3 0*log10(1e3) pn oise normalized to 1hz offset -20 *log10(8e9) pn oise normalized to 1hz carrier = - 168 dbc/hz at 1hz vc o flicker fom we can see from figure 3 and figure 4 respectively that the pll fom foor and fom ficker parameters in fractional mode a: fpo_db = -227 dbc/hz at 1hz fp1_db = -266 dbc/hz at 1hz each of the figure of merit equations result in straight lines on a log-frequency plot. we can see in the example below the resulting pll foor at 8 ghz = f po_db +20log10(fvco) -10log10(fpd) = -227+198 -80 = -109 dbc/hz pll flicker at 1 khz = f p1_db +20log10(fvco)-10log10(fm) = -266 +198-30 = -98 dbc/hz vco at 1 mhz = f v1_db +20log10(fvco)-20log10(fm)= -213 +198-120 = -135 dbc/hz vco ficker at 1 khz = f v3_db +20log10(fvco)-30log10(fm)= -168 +198-90 = -60 dbc/hz these four values help to visualize the main contributors to phase noise in the closed loop pll. each falls on a linear line on the log-frequency phase noise plot shown in figure 27 . (eq 2) ( ) 2 2 0 2 2 0 3 0 2 3 , m m m f f f f f f f f = + vco phase noise contribution (eq 3) pll-vco noise
plls - smt 6 6 - 17 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 28. -180 -160 -140 -120 -100 -80 -60 -40 -20 100 1000 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) frequency offset (hz) pll at 1 khz vco at 1 khz pll floor vco at 1 mhz figure of merit example it should be noted that actual phase noise near the corner frequency of the loop bandwidth is affected by loop parame - ters and one should use a more complete design tool such as hittite pll design for better esti ma tes of the phase noise performance. noise models for each of the components in hittite pll design can be derived from the fom equations or can be provided by hittite applications engineering. spurious performance integer operation the vco always operates at an integer multiple of the pd frequency in an integer synthesizer. in general, spurious signals originating from an integer synthesizer can only occur at multiples of the pd frequency. these unwanted outputs are often simply referred to as reference sidebands. spurs unrelated to the reference frequency must originate from outside sources. external spurious sources can modulate the vco indirectly through power supplies, ground, or output ports, or bypass the loop flter due to poor isolation of the flter. it can also simply add to the output of the synthesizer. the HMC703LP4E has been designed and tested for ultra-low spurious performance. reference spuri ou s levels are typically below -100 dbc with a well designed board layout. a regulator with low noise and high power supply rejection, such as the hmc860lp3e, is recommended to minimize external spurious sources. reference spurious levels of below -100 dbc require superb board isolation of power supplies, isolation of the vco from the digital switching of the synthesizer and isolation of the vco load from the synthesizer. typical board layout, regulator design, demo boards and application information are available for very low spurious operation. operation with lower levels of isolation in the application circuit board, from those rec om mended by hittite, can result in higher spurious levels. of course, if the application environment contains other interfering frequencies unrelated to the pd fre qu ency, and if the application isolation from the board layout and regulation are insufficient, then the unwanted interfering frequencies will mix with the desired synthesizer output and cause additional spurs. the level of these spurs is dependant upon isolation and supply regulation or rejection (psrr).
plls - smt 6 6 - 18 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com fractional operation unlike an integer synthesizer, spurious signals in a fractional synthesizer can occur due to the fact that the vco operates at frequencies unrelated to the pd frequency. hence intermodulation of the vco and the pd harmonics can cause spurious sidebands. spurious emissions are largest when the vco operates very close to an integer multiple of the pd. when the vco operates exactly at a harmonic of the pd then, no in-close mixing products are present. interference is always present at multiples of the pd frequency, f pd , and the vco frequency, f vco . if the fractional mode of operation is used, the difference, , between the vco frequency and the nearest har mo nic of the reference, will create what are referred to as integer boundary spurs. depending upon the mode of operation of the synthesizer, higher order, lower power spurs may also occur at multiples of integer fractions (sub-harmonics) of the pd frequency. that is, fractional vco frequencies which are near nf pd + f pd d/m, where n, d and m are all integers and dm (mathematicians refer to d/m as a rational num be r). we will refer to f pd d/m as an integer fraction. the denominator, m, is the order of the spurious product. higher values of m produce smaller amplitude spurious at offsets of m and usually when m>4 spurs are very small or unmeasurable. the worst case, in fractional mode, is when d=1, and the vco frequency is offset from nf pd by less than the loop bandwidth. this is the in-band fractional boundary case. figure 29. fractional spurious example characterization of the levels and orders of these products is not unlike a mixer spur chart. exact levels of the products are dependent upon isolation of the various synthesizer parts. hittite can offer guidance about expected levels of spurious with our pll and vco application boards. regulators with high power supply rejection ratios (psrr) are recommended, especially in noisy applications. when operating in fractional mode, charge pump and phase detector linearity is of paramount importance. any non- linearity degrades phase noise and spurious performance. phase detector linearity degrades when the phase error is very small and is operating back and forth between reference lead and vco lead. to mitigate these non-linearities in fractional mode it is critical to operate the phase detector with some fnite phase offset such that either the reference or vco always leads. to provide a fnite phase error, extra current sources can be enabled which provide a constant dc current path to vdd (vco leads always) or ground (reference leads always). these current sources are called charge pump offset and they are controlled via reg 09h . the time offset at the phase detector should be ~2.5 ns + 4 t ps , where t ps is the rf period at the fractional prescaler input in nanoseconds (ie. after the optional fxed divide by 2). the specifc level of charge pump offset current is determined by this time offset, the comparison frequency and the charge pump current and can be calculated from:
plls - smt 6 6 - 19 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com required cp offset = (2.5 ? 10 -9 + 4 t ps ) ? ( f comparison ) ? i cp where: t ps : is the rf period at the fractional prescaler input i cp : is the full scale current setting of the switching charge pump note that this calculation can be performed for the center frequency of the vco, and does not need refnement for small differences (<25%) in center frequencies. also, operation with unreasonably large charge pump offset may cause lock detect to incorrectly indicate an unlocked condition. to correct, reduce the offset to recommended levels. another factor in fractional spectral performance is the choice of the delta-sigma modulator mode. mode b is normally recommended, as it allows higher pd frequencies and makes it easier to flter the fractional quantization noise. for low prescaler frequencies (<1.5ghz), however, mode a can offer better in-band spectral performance. see reg 06h [0] for dsm mode selection. finally, all fractional synthesizers cre at e fractional spurs at some level. hittite offers the lowest level fractional spurious in the indus tr y in an integrated solution. operational modes the HMC703LP4E can operate in a eight of different modes ( reg 06h [7:5]), and supports triggering from 3 different sources. the modes of operation include: integer mode fractional mode exact frequency mode frequency modulation fm mode phase modulation pm mode frequency sweep mode (3 types) all modes require fractional mode to be enabled except for integer mode. fractional mode allows fne frequency steps. exact frequency mode allows precise fractional frequency steps with zero frequency error. fm and pm modes can be used for simple communications links, with data rate limitations set by the loop flter bandwidth. the pm mode also allows for precise incremental phase adjustments, which can be important in phased arrays and other systems. frequency sweep supports built-in one-way, two-way, or user defned frequency sweeps, useful in fmcw radar applications. depending on the mode, the auxiliary registers reg 0ah , reg 0ch and reg 0dh are used for different functions, as shown in table 6 . (eq 4)
plls - smt 6 6 - 20 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 6. operational modes register number register name pll operating mode (sd_mode = reg 06h [7:5]) 0 1 2 3 4 5 to 7 fractional mode integer mode exact frequency mode fm (frequency modulation) mode pm (phase modulation) mode ramp mode function of reg 03h n integer part nint n nint freq 1: nint nint start nint function of reg 04h n fractional part nfrac nfrac freq 1: nfrac nfrac start nfrac function of reg 0ah aux register phase step frequency step / reference clock function of reg 0ch alternate integer freq 2: nint stop nint function of reg 0dh alternate fractional channels / pd frequency freq 2: nfrac stop nfrac additional functionality double buffer yes no yes yes yes yes on trigger updates frequency, optionally initiates phase updates frequency, optionally initiates phase toggles frequency (level sensitive) increments / decrements phase proceeds to next stage of ramp those registers which are unused in a particular mode can take on any value, and are ignored. triggering depending on the operating mode, a trigger event is used to change frequency, fm modulate the frequency, modulate the phase, or advance the frequency ramp profle to its next state. in general the HMC703LP4E can be triggered via one of three methods. not all modes support all trigger methods. 1. an external hardware trigger pin-6 (trig) 2. spi write to trig bit in reg 0eh [0] 3. spi write to fractional register reg 04h (frequency hopping triggers only). depending on the mode, the part is sensitive to either the rising edge, or the level of the trigger. the spis trig bit emulates the external trig pin, and so it must typically be written to 1 for a trigger, and then back to 0 in preparation for another trigger cycle. to use the external trig pin, it must be enabled via exttrig_en ( reg 06h [9]). fractional mode or exact frequency mode frequency updates in non-modulated fractional modes ( reg 06h [7:5] = 0 or 2), if the external trigger is enabled, writes to n int and n frac ( reg 03h and reg 04h ) are internally buffered and wait for an explicit trigger via either the trig pin or the spis trig bit before taking effect. if exttrig_en = 0, the write to n int is double-buffered, and waits for a fractional write to reg 04h so that both n int and n frac are internally recognized together. see the fractional mode section for more information on calculating the fractional multiplier for your application. initial phase control on the HMC703LP4E, the user has control of the initial phase of the vco via the 24-bit seed reg 05h . this seed phase is loaded on the 1st clock cycle following a trigger event, provided that autoseed ( reg 06h [8] = 1 ) is enabled. the value in reg 05h represents the phase of the vco. for example, if two synthesizers are triggered in parallel, but one has a seed of 0.2 (0.2x2 24 ) and the other has a seed of 0.7 (0.7x2 24 ), the steady state outputs of the two vcos
plls - smt 6 6 - 21 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com (not accounting for any mismatch) will be 180 out of phase = ((0.7-0.2) x 360). the user can take advantage of this for phase control of the outputs of multiple synthesizers. if phase control is not needed, the best spurious operation is achieved with the seed set to a busy binary number, for example 50f1cdh, or b29d08h. note that in exact frequency mode with an exact step of f step , if autoseed is off, there can be a delay of up to 1/f step after a trigger before a new fractional frequency is recognized. frequency tuning integer mode in integer mode the vco step size is fxed to that of the pd frequency, f pd . integer mode typically has lower phase noise than fractional mode for a given pd operating frequency. the advantage is usually of the order of 2 to 3 db. integer mode, however, often requires a lower pd frequency to meet channel step size requirements. the fractional mode advantage is that higher pd frequencies can be used, hence lower phase noise can often be realized. charge pump offset should be disabled in integer mode. in integer mode the ? modulator is shut off and the n divider ( reg 03h ) may be programmed to any integer value in the range 16 to 2 16 -1. to use the HMC703LP4E in integer mode program reg 06h [7:5] = 1, then program the integer portion of the frequency (as per (eq 5) ), ignoring the fractional part. there is no double buffering in integer mode, i.e. write data then trigger the frequency change later. a write to the n int register ( reg 03h ) immediately starts the rf frequency hop. there is no external trigger available in this mode. if double buffering is required, use fractional mode ( reg 06h [7:5] = 0), with n frac ( reg 04h ) = 0, and seed ( reg 05h ) = 0. fractional mode the HMC703LP4E is placed into fractional mode by setting sd_mode ( reg 06h [7:5] ) = 0 the frequency of a locked vco controlled by the HMC703LP4E, f vco , is given by f ps = ( n int + n frac ) = f int + f frac f xtal r (eq 5) f vco = k f ps (eq 6) where: f ps is t he frequency at the prescalar input after any potential rf divide by 2 f vco is t he frequency at the HMC703LP4Es rf port k is 1 i f the rf divide by 2 is bypassed, 2 if on ( reg 08h [17]) n int is t he integer division ratio, reg 03h , an integer between 20 and 2 16 - 1 n frac is t he fractional part, from 0.0 to 0.99999...,n frac = reg 04h /2 24 r is t he reference path division ratio, reg 02h f xtal is t he frequency of the reference oscillator input f pd is t he pd operating frequency, f xtal /r
plls - smt 6 6 - 22 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com as an example, suppose we want to tune a vco to 7910 mhz. since the input frequency is > 4 ghz, the rf divide-by-2 must be engaged, so k=2: f vco 7, 910 mhz k 2 f ps 3, 955 mhz f xtal = 50 m hz r = 1 f pd = 50 m hz n int = 79 n frac = 0. 1 reg 04h = ro und(0.1 x 2 24 ) = round(1677721.6) = 1677722 f ps = ( 79 + ) = 3955 mhz + 1.2 hz error 1677722 2 24 50e6 1 (eq 7) f vco = 2 (3955 +1.2 hz) = 7910 mhz + 2.4 hz error (eq 8) in this example the output frequency of 7910 mhz is achieved by programming the 16-bit binary value of 79d = 4fh = 0000 0000 0100 1111 into intg_reg in reg 03h , and the 24-bit binary value of 1677722d = 19999ah = 0001 1001 1001 1001 1001 1010 into frac_reg in reg 04h . the 2.4 hz quantization error can be eliminated using the exact frequency mode if required. exact frequency mode the absolute frequency precision of a fractional pll is normally limited by the number of bits in the fractional modulator. for example a 24 bit fractional modulator has frequency resolution set by the phase detector (pd ) comparison rate divided by 2 24 . in the case of a 50 mhz pd rate, this would be approximately 2.98 hz, or 0.0596 ppm. in some applications it is necessary to have exact frequency steps, and even an error of 3 hz cannot be tol er ated. in some fractional synthesizers it is necessary to shorten the length of the accumulator (the denominator or the modulus) to accommodate the exact period of the step size. the shortened accumula tor often leads to very high spurious levels at multiples of the channel spacing, f step = f pd /modulus. for example 200 khz channel steps with a 10 mhz pd rate requires a modulus of just 50. the hittite method achieves the exact frequency step size while using the full 24 bit modulus, thus achiev in g exact frequency steps with very low spurious and a high comparison rate, which maintains excellent phase noise. fractional plls are able to generate exact frequencies (with zero frequency error) if n can be exactly represented in binary (eg. n = 50.0,50.5,50.25,50.75 etc.). unfortunately, some common frequencies cannot be exactly represented. for example, n frac = 0.1 = 1/10 must be approximated as round((0.1 x 2 24 )/ 2 24 ) 0.100000024. at f pd = 50 mhz this translates to 1.2 hz error. HMC703LP4E exact frequency mode addresses this issue, and can eliminate quantization error by programming the n channels ( reg 0dh ) to 10 (in this example). more generally, this feature can be used whenever the prescaler frequency, f ps , can be exactly represented on a step plan where there are an integer number (n channels ) of frequency steps across integer-n boundaries. assuming the rf divide by 2 is disabled so that f ps = f vco , this holds when the vco frequency, f vco satisfes (eq 9) , shown graphically in figure 30 .
plls - smt 6 6 - 23 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com 24 gcd gcd , and 2 gcd mod 0, where gcd( , ) / channels pd channels vco vco pd f f f f f n f f n ? ? ? ? ? ? < = = = (eq 9) where: f pd = frequency of the phase detector f vco is the desired output frequency f n , f n +1 are integer multiples of the phase detector f gcd stands for greatest common divisor eg . f gcd (4000.200mhz, 50mhz) = 200khz th erefore n channels = 50 mhz/200 khz = 250 f vcon are other vco frequencies we can exactly tune to, given this f gcd spacing figure 30. exact frequency tuning in the previous paragraph, it was assumed that a single frequency was to be achieved with zero error. exact frequency mode also applies to cases where many exact frequencies are required, all of which ft on a particular channel spacing. example: to achieve exactly 50 khz channel steps with a 61.44 mhz reference, calculate f gcd and n channels : f pd = 61.44 mhz f step = 50 khz f gcd (61.44 mhz, 50 khz) us ing the euclidean algorithm to fnd the greatest common denominator: 61 .440 mhz = 50 khz x 1228 + 50 khz 50 k hz = 40 k hz x 1 + 10 khz 40 k hz = 10 k hz x 4 + 0 (0 remainder, algorithm complete) f gcd (61.44 mhz, 50 khz) = 10 khz n channels = 61.44 mhz / 10 khz = 6144 for improved spectral performance (to keep spurs low and further out of band), it is best to keep f gcd as high as pos - sible ( n channels as low possible) for a given application. using hittite exact frequency mode to use exact frequency mode, we recommend the following procedure: 1. calculate the required f gcd as either gcd( f vco , f pd ) or gcd( f pd , f step ) depending on your application 2. calculate the number of channels per integer boundary, n channels = f pd / f gcd and program into reg 0dh 3. set the modulator mode to exact frequency ( sd_mode in reg 06h [7:5] = 2)
plls - smt 6 6 - 24 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com then, for each frequency of interest, f vco : 4 calculate the approximate value of n that is required: n = f vco /f pd = n int + n frac 5. program n int into integer register reg 03h no te: there is no need to re-program n int if it has not changed from the previous set-point. 6. program the fractional register, reg 04h = ceiling(n frac *2 24 ) wh ere the ceiling function means round up to the nearest integer. example: to confgure HMC703LP4E for exact frequency mode with channel spacing of 50 khz, vco frequency = 2000.200 mhz and f pd =61.44 mhz: 1. f gcd (61.44 mhz, 50 khz) = 10 khz (as above) 2. calculate n channels = f pd / f gcd = 6144. program into reg 0dh (6144 dec = 1800 hex) 3. set the modulator mode to exact frequency ( sd_mode in reg 06h [7:5] = 2) 4. calculate n = 2000.2 mhz / 61.44 mhz = 32.55533854 = 32 + 0.55533854 5. program integer divisor n int ( reg 03h ) = 32d = 20h 6. program fractional divisor reg 04h = ceiling(0.55533854 x 2 24 ) = 9,317,035 = 8e2aabh in the above example, without exact frequency mode, there would have been a -1.2 hz error due to quantization. fm mode the HMC703LP4E pm mode supports simple fsk modulation via a level sensitive trigger. fm mode can be used for simple communications links, with data rate limitations set by the loop flter bandwidth. the HMC703LP4E is confgured to operate in fm mode by writing reg 06h [7:5] = 3. the fm mode allows the user to toggle between two frequencies f 0 = n 1 *f pd and f 1 = n 2 *f pd based on the level of the trig. the following procedure is recommended to confgure HMC703LP4E to fm mode: 1. lock in fractional mode ( reg 06h [7:5]= 0) to f 0 = f pd x ( reg 03h . reg 04h ). 2. program ( reg 0ch . reg 0dh ) for f 1 . 3. change mode to fm ( reg 06h [7:5] = 3). 4. select the trigger source reg 06h [9] = 1, trig (pin-6), or reg 06h [9] = 0 - trigger from spi bit reg 0eh [0] 5. switch between f 0 and f 1 on a trigger state 0/1 = f 0 /f 1 . it is possible to change the next frequency state between trigger events, without affecting the output - ie. write the f 0 value while on f 1 , or f 1 while on f 0 . pm mode the HMC703LP4E pm mode supports simple bi-phase modulation via a level sensitive trigger. pm mode also supports programmable phase steps via an edge sensitive trigger. pm modes can be used for simple communications links, with data rate limitations set by the loop flter bandwidth. the HMC703LP4E is confgured to operate in all pm mode by writing reg 06h [7:5] = 4. in general the modulation phase step, q , in either pm mode is given by 24 x 360 (deg) 2 ?q = where x = reg 0ah .
plls - smt 6 6 - 25 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com bi-phase modulation phase step is programmed in reg 0ah as a fraction of 2, where 2 24 = 2. for example, for bi-phase modulation a phase step of 180, program reg 0ah = round( (180/360) x 2 24 = 8388608d = 800000h). phase modulation data is input via a trigger source, where the trigger is level dependent ( reg 06h [8] = 0), high trigger advances the phase and low trigger returns the phase. phase step control phase may also be advanced on the rising edge of the trigger only. phase step is programmed in reg 0ah as a fraction of 360, where 2 24 = 2. for example, for a 1 phase step, program reg 0ah = round( (1/360) x 2 24 = 46603d =b60bh) in summary the following procedure is recommended to confgure HMC703LP4E for pm mode: 1. lock in fractional mode ( reg 06h [7:5] = 0) to f = f pd x ( reg 03h . reg 04h ). 2. program ( reg 0ah ) to the intended phase step. 3. change mode to pm ( reg 06h [7:5] = 4). 4. change trigger option to edge or level ( reg 06h [8]) 5. select the trigger source reg 06h [9] = 1, trig (pin-6), or reg 06h [9] = 0 - trigger from spi write to reg 0eh ). frequency sweep mode the HMC703LP4E features a built-in sweeper mode, that supports external or automatic triggered sweeps. the maximum sweep range is only limited by the vco dynamics and range. sweeper mode includes: a. automatic 2-way sweep mode initial trigger, ramp, ramp back, ramp, ramp back, ... selected by writing reg 06h [7:5] = 7 b. triggered 2-way sweep mode initial trigger, ramp, wait for trigger, ramp back, wait for trigger, ramp, ... selected by writing reg 06h [7:5] = 6 c. triggered 1-way sweep mode - initial trigger, ramp, wait for trigger, hop back to initial frequency, wait for trigger, ramp, ... selected by writing reg 06h [7:5] = 5 applications include test instrumentation, fmcw sensors, automotive radars and others. the parameters of the sweep function are illustrated in figure 31 . the HMC703LP4E generates a sweep by implementing miniature frequency steps in time. a smooth and continuous sweep is then generated, at the output of the vco, after the stepped signal is filtered by the loop filter, as shown in figure 31 . the stepped sweep approach enables the HMC703LP4E to be in lock for entire duration of the sweep. this gives the HMC703LP4E a number of advantages over conventional methods including: ? the ability to generate a linear sweep. ? the ability to have phase coherence between different ramps, so that the phase profile of each sweep is identical. ? the ability to generate sweeps with identical phase and phase noise performance. ? the ability to generate user defined sweeps in single-step ramp mode.
plls - smt 6 6 - 26 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com the HMC703LP4E sweep function cycles through a series of discrete frequency values which may be a. stepped by an automatic sequencer or, b. single stepped by individual triggers in single step mode. triggering of each sweep, or step, may be configured to operate: a. via a serial port write of 1 to reg 0eh [0] (it should then be returned to 0) b. automatically generated internally c. triggered via trig pin-6 figure 31. HMC703LP4E sweep function 2-way sweeps the HMC703LP4E can be configured to operate in 2-way sweep mode by programming reg 06h [7:5] = 6 or 7. a 2-way sweep is shown in figure 32 . the start of the sweep can be triggered by external trig pin-6 if exttrig_en = 1, or the spi_trig ( reg 0eh ). in automatic 2-way sweep ( reg 06h [7:5] = 7), the ramp restarts immediately, without waiting for an external trigger. figure 32. 2-way triggered sweep
plls - smt 6 6 - 27 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com 1-way sweeps the HMC703LP4E can be configured to operate in triggered 1-way sweep mode by programming reg 06h [7:5] = 6. triggered 1-way sweeps are shown in figure 33 . unlike 2-way sweeps, triggered 1-way sweeps force the vco to hop back to the start frequency upon the next trigger. triggered 1-way sweeps also require a 3 rd trigger to start the new sweep. the 3 rd trigger should be timed appropriately to allow the vco to settle after the large frequency hop back to the start frequency. subsequent odd numbered triggers will start the 1-way sweep and repeat the process. 1-way sweep can be triggered by external trig pin-6 if exttrig_en = 1, or the spi_trig ( reg 0eh ). figure 33. 1-way sweep control single step ramp mode with any of the sweeper profiles, the HMC703LP4E can be configured to operate in single step mode. this causes it to wait for an explicit trigger before every change in the frequency setpoint. a single step 1-way ramp is shown in figure 34 . in this mode, a trigger is required for each step of the ramp. similar to autosweep, the ramp_busy fag will go high on the frst trigger, and will stay high until the n th trigger. the n+1 trigger will cause the ramp to jump to the start frequency in 1-way ramp mode. the n+2 trigger will restart the 1-way ramp. single step ramp mode can be triggered by external trig pin-6 if exttrig_en = 1, or the spi_trig ( reg 0eh ). in single-step mode ( reg 06h [23] = 1), the HMC703LP4E has the capability to generate arbitrarily shaped profles defned by the timing density of the trigger pulses. on each trigger event the frequency is stepped by the step value programmed in reg 0ah . in addition, the HMC703LP4E allows the fexibility to change the step size ( reg 0ah ) during the ramp, between steps, adding another degree of freedom to ramp profle generation. note that the maximum trigger rate where operation can be guaranteed is f pd /5. in addition, the step register ( reg 0ah ) should not be updated via the spi during the frst two reference clock cycles after the trigger. the discrete nature of the frequency updates is smoothed by the loop flter, and should not pose a problem provided that update rate is > 10 x the loop bandwidth.
plls - smt 6 6 - 28 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 34. single step ramp mode the user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. if the loop bandwidth in use is much wider than the rate of the steps then the locking will be fast and the ramp will have a staircase shape. if the update rate is higher than the loop bandwidth, as is normally the case, then the loop will not fully settle before a new frequency step is received. hence the swept output will have a small lag and will sweep in a near continuous fashion. detailed sweeper configuration the following procedure is recommended to configure the frequency sweep in HMC703LP4E: 1. lock in fractional mode ( reg 06h [7:5] = 0) to the start frequency (f 0 ). 2. program frequency step reg 0ah and stop n ( reg 0ch , reg 0dh ). note that stop n must be exactly equal to start n plus an integer number of steps ( reg 0ah ). if it is not, the sweeper function will not terminate properly. this normally means rounding the stop n up or down slightly to ensure it falls on a step boundary. 3. change mode to reg 06h [7:5] = 5,6, or 7 - depending on the desired profile. note that the ramp step reg 0ah is signed twos complement. if negative, the first ramp has a negative slope, and vice-versa. setting autoseed ( reg 06h [8] = 1) ensures that different sweeps have identical phase profile. this is achieved by loading the seed ( reg 05h ) into the phase accumulator at the beginning of each ramp setting reg 06h [22] = 1 ensures identical phase and quantization noise performance on each sweep by resetting the entire delta-sigma modulator at the beginning of each ramp. note that, while the HMC703LP4E can enforce phase coherence between different frequency sweeps, there will be a phase discontinuity if the start phase that is programmed in seed ( reg 05h ) is different from the phase state that the pll finds itself in at the end of the ramp. this discontinuity can be prevented by tailoring the sweep profile such that the phase of the pll at the start of the ramp is equal to phase at the end of the ramp. example: configure a sweep from f 0 = 3000 mhz to f f = 3105 mhz in tramp 2 ms, with f pd = 50 mhz: 1. start in fractional mode (program reg 06h [7:5] = 0 ) 1. calculate start n and stop n, program start n ( reg 03h , reg 04h) st art n = 3000.0 mhz / 50.0 mhz = 60.0 st op n = 3105.0 mhz / 50.0 mhz = 62.1
plls - smt 6 6 - 29 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com pr ogram reg 03h = 60, reg 04h = 0 2. calculate how many reference cycles will occur in 2 ms. given that tref = 1 / f pd = 20ns, nb r of steps = tramp/tref = 2ms/20ns = 100,000 3. calculate the desired n step size, given start n, stop n and nbr of steps n_ step_size_desired = (62.1 - 60.0) / 100,000 = 21u [fractions of n] 4. quantize the fractional n step into the 24 bit step size pr ogram reg 0ah = 21u x 2 24 = round(352.32) = 352 5. readjust the stop frequency slightly to ensure it falls exactly on a step boundary due to step quantization,there will be some finite error in either the sweep time or sweep span. we have 3 choices: a) t arget an accurate sweep time, sacrifice resolution on stop frequency sw eep time = 100k cycles = 2 ms st op n = start n + 100,000 x 352/2 24 (keep 100k cycles) stop n = 60.000 + 35,200,000 / 2 24 62.09808 pr ogram reg 0ch = 62 , reg 0dh = 35,200,000 mod 2 24 = 1,645,568 0.09808 f f 3104.904 (96 khz lower stop frequency then desired) b) t arget an accurate stop frequency, at the expense of sweep time accuracy gi ven step size of 352/2 24 , how many cycles to get from 60.0 to 62.1 nb r of steps = (62.1 - 60.0) / (352/2 24 ) = 100,091.345 mu st round to 100,091 steps. sw eep time = tref * 100,091 = 2.00182ms (1.82 us longer than desired) st op n = 60.0 + 100,091 x 352/2 24 62.0999927 pr ogram reg 0ch = 62 , reg 0dh = 35,232,032 mod 2 24 = 1,677,600 0.0999927 f f = 3104.99964 mhz (362 hz lower stop frequency then desired) c) a c ombination of situation a and b 6. program sd_mode based on desired trigger and ramp/hop profile ( reg 06h [7:5] = 5,6, or 7) 7. trigger via either the external pin or spi trig bit. co ntinue to issue triggers to advance the ramp profile to the next stage... sweeper confguration for ultra fine step sizes in cases where fner step size resolution is desired, it is possible to reduce the f pd , along with performance implications it has, or use a single-step mode ( reg 06h [23] = 1) and provide a lower frequency clock on the external trigger pin to reduce the update rate. the HMC703LP4E can generate a lower frequency clock by programming the r divider appropriately, and not using it for the pd ( reg 06h [21] = 1), but rather routing it out of the HMC703LP4E via the gpo. the r divider output can then be looped back to the trig pin of the HMC703LP4E to use as a low rate trigger. see ref path r divider for more details.
plls - smt 6 6 - 30 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com reference input stage the reference buffer provides the path from an external reference source (generally crystal based) to the r divider, and eventually to the phase detector. the buffer has two modes of operation. high gain (recommended below 200 mhz), and high frequency, for 200 to 350 mhz operation. the buffer is internally dc biased, with 100 ? internal termination. for 50 ? match, an external 100 ? resistance to ac ground should be added, followed by an ac coupling capacitance (impedance < 1 ohm), then to the xrefp pin of the part. at low frequencies, a relatively square reference is recommended to keep the input slew rate high. at higher frequencies, a square or sinusoid can be used. the following table shows the recommended operating regions for different reference frequencies. if operating outside these regions the part will normally still operate, but with degraded performance. minimum pulse width at the reference buffer input is 2.5 ns. for best spur performance when r = 1, the pulse width should be > (2.5 ns + 8 tps), where tps is the period of the vco at the prescaler input. when r > 1 minimum pulse width is 2.5 ns. table 7. reference sensitivity table square input sinusoidal input frequency (mhz) slew > 0.5v/ns recommended swing (vpp) recommended power range (dbm) recommended min max recommended min max < 10 yes 0.6 2.5 x x x 10 yes 0.6 2.5 x x x 25 yes 0.6 2.5 ok 8 15 50 yes 0.6 2.5 yes 6 15 100 yes 0.6 2.5 yes 5 15 150 ok 0.9 2.5 yes 4 12 200 ok 1.2 2.5 yes 3 8 200 to 350 x x x yes 1 5 10 note: for greater than 200 mhz operation, use buffer in high frequency mode. reg 08h [18] = 1 input referred phase noise of the pll when operating at 50 mhz is between -150 and -156 dbc/hz at 10 khz offset depending upon the mode of operation. the input reference signal should be 10db better than this foor to avoid deg - radation of the pll noise contribution. it should be noted that such low levels are only necessary if the pll is the dominant noise contributor and these levels are required for the system goals. figure 35. reference path input stage
plls - smt 6 6 - 31 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com ref path r divider the reference path r divider is based on a 14 bit counter and can divide input signals of up to 350 mhz input by values from 1 to 16,383 and is controlled by reg 02h [13:0]. the reference divider output may be viewed in test mode on the ld_sdo pin, by setting reg 0fh [4:0] = 9d. the HMC703LP4E can use the undivided reference, while exporting a divided version for auxiliary purposes (eg. ramp triggers, fpgas etc.) on the gpo, if reg 06h [21] = 1. rf path the rf path is shown in figure 36 . this path features a low noise 8 ghz rf input buffer followed by an 8 ghz rf divide-by-2 with a selectable bypass. if the vco input is below 4 ghz the rf divide-by-2 should be by-passed for improved performance in fractional mode. the rf divide-by-2 is followed by the n divider, a 16 bit divider that can operate in either integer or fractional mode with up to 4 ghz inputs. finally the n divider is followed by the phase detector (pd), which has two inputs, the rf path from the vco (v) and the reference path (r) from the crystal. the pd can operate at speeds up to 100 mhz in fractional mode b (recommended ), 80 mhz in fractional mode a and 115 mhz in integer mode. figure 36. rf path rf input stage the rf input stage provides the path from the external vco to the phase detector via the rf or n divider. the rf input path is rated to operate up to 8 ghz across all conditions. the rf input stage is a differential common emitter stage with internal dc bias, and is protected by esd diodes as shown in figure 37 . this input is not matched to 50 ?. a 100 ? resistor placed across the inputs can be used for a better match to 50 ?. in most applications the input is used single-ended into either the vcoip or vcoin pin with the other input connected to ground through a dc blocking capacitor. the preferred input level for best spectral performance is -10 dbm nominally.
plls - smt 6 6 - 32 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 37. rf input stage- shown with single ended device rf path n divider the main rf path n divider is capable of divide ratios anywhere between 2 16 -1 (524,287) and 16 . this divider for example could divide a 4 ghz input to a pd frequency anywhere between its maximum output limit of 115 mhz to as low as 7.6 khz. the n divider output may be viewed in test mode on ld_sdo by set ti ng reg 0fh [4:0] = 10d. when operating in fractional mode the n divider can change by up to +/-4 from the average value. hence the selected divide ratio in fractional mode is restricted to values between 2 16 -5 (65,531) and 20. if the vco input is above 4 ghz then the 8 ghz fxed rf divide-by-2 should be used, reg 08h [17] = 1. in this case the integer division range is restricted to even numbers over the range 2*(2 16 -5) (131,062) down to 40. pll jitter the standard deviation of the arrival time of the vco signal, or the jitter, may be estimated with a simple approximation if we assume that the locked vco has a constant phase noise, ( ) 2 0 f , at offsets less than the loop 3db bandwidth and a 20db per decade roll off at greater offsets. the simple locked vco phase noise approximation is shown on the left of figure 38 . figure 38. pll phase noise and jitter
plls - smt 6 6 - 33 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com with this simplifcation the total integrated vco phase noise, 2 v , in rads 2 is given by 2 v = 2 (f 0 ) where 2 is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, and is the 3 db corner frequency of the closed loop pll the integrated phase noise at the phase detector, 2 pd , is just scaled by n 2 ie. 2 pd = 2 v /n 2 the rms phase jitter of the vco ( v ) in rads, is just the square root of the phase noise integral. since the simple integral of (eq 10) is just a product of constants, we can easily do the integral in the log domain. for example if the phase noise inside the loop is -110 dbc/hz at 10 khz offset and the loop band wi dth is 100 khz, and the division ratio is 100, then the integrated phase noise at the phase detector, in db, is given by; 2 pd = 10log( 2 (f 0 ) /n 2 ) = -110 + 5 + 50 - 40 = -95 dbrads, or equivalently 95 20 10 ? = = 18 rads = 1 milli-degrees rms. while the phase noise reduces by a factor of 20logn after division to the reference, due to the increased period of the pd reference signal, the jitter is constant. the rms jitter from the phase noise is then given by t jpn =t pd 2 pd /2 in this example if the pd reference was 50 mhz, t pd = 20 nsec, and hence t jpn = 56 femto-sec. charge pump and phase detector the phase detector or pd has two inputs, one from the reference path divider and one from the rf path divider. when in lock these two inputs are at the same average frequency and are fxed at a constant aver ag e phase offset with respect to each other. we refer to the frequency of operation of the pd as f pd . most formula related to step size, delta- sigma modulation, timers etc., are functions of the operating frequency of the pd, f pd is sometimes referred to as the comparison frequency of the pd. the pd compares the phase of the rf path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the out pu t current varies in a linear fashion over nearly 2 radians (360) of input phase difference. charge pump and phase detector functions phase detector register reg 0bh allows manual access to control special phase detector features. reg 0bh [2:0] allows fne tuning of the pd reset path delay. this adjustment can be used to improve perfor ma nce at very high pd rates. most often this register is set to the recommended value only. reg 0bh [5] and [6] enables the pd up and dn outputs respectively. disabling prevents the charge pump from pumping up or down respectively and effectively tri-states the charge pump while leaving all other functions operating internally. cp force up reg 0bh [7] and cp force dn reg 0bh [8] allows the charge pump to be forced up or down respectively. this will force the vco to the ends of the tuning range which can be useful for testing of the vco. (eq 10)
plls - smt 6 6 - 34 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com pd force mid reg 0bh [9] will disable the charge pump current sources and place a voltage source on the loop flter at approximately vppcp/2. if a passive flter is used this will set the vco to the mid-voltage tun in g point which can be useful for testing of the vco. lock detect each pd (phase detector) cycle, the HMC703LP4E measures phase error at the pd. the measured phase error must be: ? < ~220 degrees if 40 mhz <= f pd <= 120 mhz, and ? < ~14 ns if f pd < 40 mhz, for a number of consecutive cycles (number of cycles is programmable in reg 07h [2:0]), in order for HMC703LP4E to declare a lock. a single phase error outside of these criteria disqualifes lock, and the lock counter (maximum value of lock counter = reg 07h [2:0]) is restarted. note that in some cases, the pll may be locked with a phase error that exceeds 180 degrees, or 12 ns, whichever is smaller. this can occur if the offset current is inappropriately programmed too high. it is not recommended to operate in this condition because it leads to degraded phase noise performance. in such a case the lock detect circuit would not declare a locked condition, even though the pll is locked. the HMC703LP4E lock-detect functionality is self-calibrating relative to the reference frequency. typically the lock-detect training is only required once on power-up, or each time the reference frequency or the r divider value ( reg 02h ) is changed. to train the lock-detect circuitry of the HMC703LP4E on power-up, set: ? set reg 07h [11] = 1 to enable lock-detect counters ? set reg 07h [14] = 1 to enable the lock-detect timer ? set reg 07h [20] = 1 to train the lock-detect timer these bits can all be written simultaneously. on any change of the pd frequency (via either the external reference frequency, or the r divider setting ( reg 02h )), the lock-detect circuit should be retrained by toggling reg 07h [20] off and then back on. the lock-detect indication can be read from the spi via reg 12h [1], or can be exported on the ld_sdo pin via the gpo mux( reg 0fh [4:0]). see ld_sdo pin description for more information. cycle slip prevention (csp) when changing frequency and the vco is not yet locked to the reference, the instantaneous frequencies of the two pd inputs are different, and the phase difference of the two inputs at the pd varies rapidly over a range much greater than +/-2 radians. since the gain of the pd varies linearly with phase up to +/-2, the gain of a conventional pd will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than 0 radians. the output current from the charge pump will cycle from maximum to minimum even though the vco has not yet reached its fnal frequency. the charge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. this can make the vco frequency actually reverse temporarily during locking. this phenomenon is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically. cycle slipping increases the time to lock to a value much greater than that predicted by normal small signal laplace analysis. the HMC703LP4E mitigates the effects of cycle-slips by increasing the charge-pump current when the phase error is larger than ~220 degrees or ~14 ns (whichever is less as measured by the lock-detect circuit). the circuit is normally most effective for pd frequencies <= 50 mhz.
plls - smt 6 6 - 35 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com pd polarity reg 0bh [4]=0 sets the pd polarity for use with a passive loop flter together with a vco with a positive tuning slope (increasing tuning voltage increases vco frequency). reg 0bh [4]=1 inverts the pd polarity. this is most often used if an inverting op-amp is used in an active loop flter together with a vco with a positive tuning slope. charge pump tri-state reg 0bh [5]= reg 0bh [6]=0 tri-states the charge pump. this effectively freezes charge on the loop flter and allows the vco to run open loop, provided that cp offset is also disabled. charge pump gain reg 09h [6:0] and reg 09h [13:7] program current gain settings for the charge pump. pump ranges can be set from 0 a to 2.54 ma in 20ua steps. charge pump gain affects the loop bandwidth. the product of vco gain (k vco ) and charge pump gain (k cp ) can be held constant for vcos that have a wide ranging k vco by adjusting the charge pump gain. this compensation helps to keep the loop bandwidth constant. in addition to the normal cp current as described above, there is also an extra output source of current that offers improved noise performance. hik cp provides an output current that is proportional to the loop flter voltage. this being the case, hik cp should only be operated with active op-amp loop flters that defne the voltage as seen by the charge pump pin. with 2.5 v as observed at the charge pump pin, the hik cp current is 3.5 ma. there are several confgurations that could be used with the hik cp feature. for lowest noise, hik cp could be used without the normal charge pump current (the charge pump current would be set to 0). in this case, the loop flter would be designed with 3.5 ma as the effective charge pump current. another possible confguration is to operate with both the hik cp and normal charge pump current sources. in this case the effective charge pump current would be 3.5ma + programmed normal charge pump current which could offer a maximum of 6 ma. with passive loop flters the voltage seen by the charge pump pin will vary which would cause the hik cp current to vary widely. as such, hik cp should not be used on passive loop flter implementations. a simplifed diagram of the charge pump is shown in figure 39 . the current gain of the pump in amps/radian is equal to the gain setting of this register divided by 2. charge pump offset reg 09h [20:14] controls the charge pump current offsets. reg 09h [21] and reg 09h [22] enable the up and dn offset currents respectively. normally, only one is used at a time. as mentioned earlier charge pump offsets affect fractional mode linearity . offset polarity should be chosen such that the divided vco lags the reference signal. this means down for non-inverting loop flters.
plls - smt 6 6 - 36 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 39. charge pump gain and offset control - reg09h seed register and autoseed mode the start phase of the fractional modulator digital phase accumulator (dpa) may be set to any values via the seed register reg 05h . if autoseed reg 06h [8] is set, then the pll will automatically reload the start phase from reg 05h [23:0] into the dpa every time a new fractional fre qu ency is selected. if autoseed is not set, then the pll will start new fractional frequencies with the value left in the dpa from the last frequency. hence the start phase will effectively be random. certain zero or binary seed values may cause spurious energy correlation at specifc frequencies. correlated spurs are advantageous only in very special cases where the spurious are known to be far out of band and are removed in the loop flter. for most cases a pseudo-random seed setting is recom me nded. further, since the autoseed always starts the accumulators at the same place, performance is repeatable if autoseed is used. reg 05h s default value typically provides good performance. power on reset the HMC703LP4E features a hardware power on reset (por) on the digital supply dvdd. all chip reg is ters will be reset to default states approximately 250 s after power up of dvdd. once the supply is fully up, if the power supply then drops below 0.5 v the digital portion will reset. note that the spi control inputs must also be 0 at power-down, otherwise they will inadvertently power the chip via the esd protection network. power down mode hardware power down chip enable may be controlled from the hardware cen pin 23, or it may be controlled from the serial port. reg 01h [0] =1 assigns control to the cen pin. reg 01h [0] =0 assigns control to the serial port reg 01h [1]. for hardware test reasons or some special applications it is possible to force certain blocks to remain on inside the chip , even if the chip is disabled. see the register reg 01h description for more details. chip identifcation version information may be read from the synthesizer by reading the content of chip_id in reg 00h .
plls - smt 6 6 - 37 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com general purpose output (gpo) pin the pll shares the ld_sdo (lock-detect/serial data out) pin to perform various functions. while the pin is most commonly used to read back registers from chip via the spi, it is also capable of exporting a variety of interesting signals and real time test waveforms (including lock detect). it is driven by a tri-state cmos driver with ~200 rout. it has logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export from the chip. in its default confguration, after power-on-reset, the output driver is disabled, and only drives during appropriately addressed spi reads. this allows it to share the output with other devices on the same bus. depending on the spi mode, the read section of spi cycle is recognized differently hmc spi mode: the driver is enabled during the last 24 bits of spi read cycle (not during write cycles). open spi mode: the driver is enabled if the chip is addressed - ie. the last 3 bits of spi cycle = 000b before the rising edge of sen (note a). to consistently monitor any of the gpo signals, including lock detect, set reg 0fh [7] = 1 to keep the sdo driver always on. this stops the ldo driver from tri-stating and means that the sdo line cannot be shared with other devices. the chip will naturally switch away from the gpo data and export the sdo during an spi read (note b). to prevent this automatic data selection, and always select the gpo signal, set prevent automux of sdo ( reg 0fh [6] = 1). the phase noise performance at this output is poor and uncharacterized. also, the gpo output should not be toggling during normal operation. otherwise the spectral performance may degrade. note that there are additional controls available, which may be helpful if sharing the bus with other devices: ? to allow the driver to be active (subject to the conditions above) even when the chip is disabled - set reg 01h [7] = 0. ? to disable the driver completely, set reg 08h [5] = 0 (it takes precedence over all else). ? to disable either the pull-up or pull-down sections of the driver, reg 0fh [8] = 0 or reg 0fh [9] = 0 respectively. note a: if sen rises before sck has clocked in an invalid (non-zero) chip -address, the part will start to drive the bus. note b: in open mode, the active portion of the read is defned between the 1 st sck rising edge after sen, to the next rising edge of sen. example scenarios: ? drive sdo during reads, tri-state otherwise (to allow bus-sharing) ? no action required. ? drive sdo during reads, lock detect otherwise ? set gpo select reg 0fh [4:0] = 00001 (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1) ? always drive lock detect ? set prevent automux of sdo reg 0fh [6] = 1 ? set gpo select reg 0fh [4:0]= 00001 (which is default) ? set prevent gpo driver disable ( reg 0fh [7] = 1)) the signals available on the gpo are selected by changing gpo select, reg 0fh [4:0].
plls - smt 6 6 - 38 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com vco tuning passive filter the HMC703LP4E is targeted for high performance applications with an external vco. the synthe si zer charge pump has been designed to work directly with vcos that can be tuned nominally over 1.0 to 4.0 volts on the varactor tuning port with a +5 v charge pump supply voltage. slightly wider ranges are pos si ble with a +5.2 v charge pump supply or with slightly degraded performance. hittite pll design soft wa re is available to design passive loop flters driven directly from the pll charge pump. high voltage tuning, active filter optionally an external op-amp may be used in the loop flter to support vcos requiring higher voltage tuning ranges. loop flter design is highly application specifc, and can have signifcant impact on the pll performance. its impact on pll performance should be well characterized, and optimized for best pll performance. hittites pll design software is available to design active loop flters with external op-amps. various flter con fg urations are supported. figure 40. synthesizer with active loop filter and conventional external vco main serial port serial port modes of operation the hmc pll-vco serial port interface can operate in two different modes of operation. a. hmc mode (hmc legacy mode) - single slave per hmcspi bus. b. open mode - up to 8 slaves per hmcspi bus. the HMC703LP4E only uses 5 bits of address space. both protocols support 5 bits of register address space. hmc mode can support up to 6 bits of register address but, is restricted to 5 bits when compatibility with open mode is offered. register 0 modes register 0 has a dedicated function in each mode. open mode allows wider compatibility with other manu fa cturers spi protocols.
plls - smt 6 6 - 39 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 8. register 0 comparison - single vs multi-user modes single user hmc mode single or multi-user open mode read chip id 24 bits chip id 24bits write soft reset, general strobes read address [4:0] soft reset [5] general strobes [24:6] serial port mode decision after power-on reset on power up, both types of modes are active and listening. all digital io must be low at power-up. a decision to select the desired serial port mode (protocol) is made on the frst occurrence of sen or sck , after which the serial port mode is fxed and only changeable by a power down. a. if a rising edge on sen is detected frst hmc mode is selected. b. if a rising edge on sck is detected frst open mode is selected. serial port hmc mode - single pll hmc mode (legacy mode) serial port operation can only address and communicate with a single pll, and is compat - ible with most hmc plls and plls with integrated vcos. the hmc mode protocol for the serial port is designed for a 4 wire interface with a fxed protocol featuring a. 1 read/write bit b. 6 address bits c. 24 data bits serial port open mode the serial port open mode features: a. compatibility with general serial port protocols that use a shift and strobe approach to communication. b. compatible with hmc multi-chip solutions, useful to address multiple chips of various types from a single serial port bus. the hmc open mode protocol has the following general features: a. 3 bit chip address, can address up to 8 devices connected to the serial bus ( = 000 on HMC703LP4E) b. wide compatibility with multiple protocols from multiple vendors c. simultaneous write/read during the spi cycle d. 5 bit register address space e. 3 wire for write only capability, 4 wire for read/write capability. hmc rf plls with integrated vcos also support hmc open mode. hmc700, hmc701, hmc702 and some genera - tions of microwave plls with integrated vcos do not support open mode.
plls - smt 6 6 - 40 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com typical hmc open mode serial port operation can be run with sck at speeds up to 50 mhz. serial port hmc mode details typical serial port hmc mode operation can be run with sck at speeds up to 50mhz. hmc mode - serial port write operation avdd = dvdd = 3.3v +/-10%, agnd = dgnd = 0v table 9. spi hmc mode - write timing characteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 sen to sck setup time sdi to sck setup time sck to sdi hold time sen low duration sck to sen fall max spi clock frequency 8 3 3 20 10 50 nsec nsec nsec nsec nsec mhz a typical hmc mode write cycle is shown in figure 41 . a. the master (host) both asserts sen (serial port enable) and clears sdi to indicate a write cycle, followed by a rising edge of sck. b. the slave (synthesizer) reads sdi on the 1st rising edge of sck after sen. sdi low indi ca tes a write cycle (/wr). c. host places the six address bits on the next six falling edges of sck, msb frst. d. slave shifts the address bits in the next six rising edges of sck (2-7). e. host places the 24 data bits on the next 24 falling edges of sck, msb frst. f. slave shifts the data bits on the next 24 rising edges of sck (8-31). g. the data is registered into the chip on the 32nd rising edge of sck. h. sen is cleared after a minimum delay of t 5 . this completes the write cycle. figure 41. serial port timing diagram - hmc mode write
plls - smt 6 6 - 41 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com hmc mode - serial port read operation a typical hmc mode read cycle is shown in figure 42 . a. the master (host) asserts both sen (serial port enable) and sdi to indicate a read cycle, followed by a rising edge sck. note: the lock detect (ld) function is usually mul ti plexed onto the ld_sdo pin. it is suggested that ld only be considered valid when sen is low. in fact ld will not toggle until the frst active data bit toggles on ld_sdo, and will be restored immediately after the trailing edge of the lsb of serial data out as shown in figure 42 . b. the slave (synthesizer) reads sdi on the 1st rising edge of sck after sen. sdi high ini ti ates the read cycle (rd) c. host places the six address bits on the next six falling edges of sck, msb frst. d. slave registers the address bits on the next six rising edges of sck (2-7). e. slave switches from lock detect and places the requested 24 data bits on sd_ldo on the next 24 rising edges of sck (8-31), msb frst . f. host registers the data bits on the next 24 falling edges of sck (8-31). g. slave restores lock detect on the 32nd rising edge of sck. h. sen is cleared after a minimum delay of t 6 . this completes the cycle. table 10. spi hmc mode - read timing characteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 t6 sen to sck setup time sdi setup to sck time sck to sdi hold time sen low duration sck to sdo delay sck to sen fall 8 3 3 20 10 8.2ns+0.2ns/pf ns ns ns ns ns ns figure 42. hmc mode serial port timing diagram - read
plls - smt 6 6 - 42 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com serial port open mode details open mode - serial port write operation table 11. spi open mode - write timing characteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 t 6 sdi setup time sdi hold time sen low duration sen high duration sck 32 rising edge to sen rising edge serial port clock speed sen to sck recovery time 3 3 10 10 10 dc 10 50 ns ns ns ns ns mhz ns a typical write cycle is shown in figure 43 . a. the master (host) places 24 bit data, d23:d0, msb frst, on sdi on the frst 24 falling edges of sck. b. the slave (synthesizer) shifts in data on sdi on the frst 24 rising edges of sck c. master places 5 bit register address to be written to, r4:r0, msb frst, on the next 5 falling edges of sck (25-29) d. slave shifts the register bits on the next 5 rising edges of sck (25-29). e. master places 3 bit chip address, a2:a0, msb frst, on the next 3 falling edges of sck (30-32). the HMC703LP4E chip address is fxed at 000. f. slave shifts the chip address bits on the next 3 rising edges of sck (30-32). g. master asserts sen after the 32nd rising edge of sck. h. slave registers the sdi data on the rising edge of sen. figure 43. open mode - serial port timing diagram - write open mode - serial port read operation a typical read cycle is shown in figure 44 . in general, in open mode the ld_sdo line is always active during the write cycle. during any open mode spi cycle ld_sdo will contain the data from the address pointed to by reg 00h [4:0]. if reg 00h [4:0] is not changed then the same data will always be present on ld_sdo when an open mode cycle is in progress. if it is desired to read from a spe -
plls - smt 6 6 - 43 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com cifc address, it is necessary in the frst spi cycle to write the desired address to reg 00h [4:0], then in the next spi cycle the desired data will be available on ld_sdo. an example of the open mode two cycle procedure to read from any random address is as follows: a. the master (host), on the frst 24 falling edges of sck places 24 bit data, d23:d0, msb frst, on sdi as shown in figure 44 . d23:d5 should be set to zero. d4:d0 = address of the register to be read on the next cycle. b. the slave (synthesizer) shifts in data on sdi on the frst 24 rising edges of sck c. master places 5 bit register address , r4:r0, ( the address the write address register), msb frst, on the next 5 falling edges of sck (25-29). r4:r0=00000. d. slave shifts the register bits on the next 5 rising edges of sck (25-29). e. master places 3 bit chip address, a2:a0, msb frst, on the next 3 falling edges of sck (30-32).the HMC703LP4E chip address is fxed at 000. f. slave shifts the chip address bits on the next 3 rising edges of sck (30-32). g. master asserts sen after the 32nd rising edge of sck. h. slave registers the sdi data on the rising edge of sen. i. master clears sen to complete the address transfer of the two part read cycle. j. if we do not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on sdi to register zero on the read back part of the cycle. k. master places the same sdi data as the previous cycle on the next 32 falling edges of sck. l. slave (synthesizer) shifts the sdi data on the next 32 rising edges of sck. m. slave places the desired data (i.e. data from address in reg 00h [4:0 ]) on ld_sdo on the next 32 rising edges of sck. lock detect is disabled. n. master asserts sen after the 32nd rising edge of sck to complete the cycle and revert back to lock detect on ld_sdo. note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the ld_sdo output to prevent a pos - sible bus contention issue. table 12. spi open mode - read timing characteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 t6 t7 sdi setup time sdi hold time sen low duration sen high duration sck rising edge to sdo time sen to sck recovery time sck 32 rising edge to sen rising edge 3 3 10 10 10 10 8.2+0.2ns/pf ns ns ns ns ns ns ns
plls - smt 6 6 - 44 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com figure 44. open mode - serial port timing diagram - read operation 2-cycles
plls - smt 6 6 - 45 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com register map table 13. reg 00h id register (read only) bit type name w deflt description [23:0] ro chip_id 24 97370h pll id table 13. reg 00h open mode read address/rst strobe register (write only) (continued) bit type name w deflt description [4:0] wo readaddr 5 0 write the intended read address to this register for open mode register reads. on the 1st spi clock of the next cycle the data is read and the shift-out begins. table 13. reg 00h open mode read address register (write only) (continued ) bit type name w deflt description 5 wo softrst 1 0 soft-reset. when 1, it resets the registers to por state, and is - sues por to analog. table 14. reg 01h rst register bit type name w deflt description 0 r/w enpinsel 0 0 if 1, the master chip enable is taken from the pin rather than from the spi. 1 r/w enfromspi 1 1 the master enable from the spi. write a 0 to power-down the chip. [9:2] r/w enkeepons 8 0 while the chip is disabled, the user has the option to keep the following sub-circuits active by writing a 1 to the appropriate bits. [2] bias, [3] pfd, [4] chp, [5] refbuf, [6] vcobuf, [7] gpo, [8] vcodiva, [9] vcodivb 10 r/w ensyncchpdis 1 0 if 1, then following a disable event, the charge-pump is disabled synchronously on the falling edge of the divided reference to tri- state the charge pump without transient. table 15. reg 02h refdiv register bit type name w deflt description [13:0] r/w rdiv 14 1 reference divider r value divider use also requires refbufen reg08[3]=1 min 1d max 16383d
plls - smt 6 6 - 46 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 16. reg 03h frequency register - integer part bit type name w deflt description [15:0] r/w intg 16 25d the (base) integer portion of the prescaler divide ratio. in any of the fractional modes of operation, this value is double buffered, and does not take effect until a trigger event. see operation modes for more information. in integer mode, this value can range from 16 to 65535. in fractional mode it should be restricted between 20 and 65531. table 17. reg 04h frequency register - fractional part bit type name w deflt description [23:0] r/w frac 24 0 vco divider fractional part (24 bit unsigned) see fractional frequency tuning n frac = reg 04h /2 24 used in fractional modes only min 0d max 2^24-1 = ffffffh = 16,777,215d table 18. reg 05h seed bit type name w deflt description [23:0] r/w seed 24 654321h the initial starting point for the fractional modulator at the trigger position. this value effects the phase of the output, and can effect some types of spurious content. during sweeps, the modulator can optionally be reloaded with this value at the start of each ramp.
plls - smt 6 6 - 47 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 19. reg 06h sd cfg register bit type name w deflt description [0] r/w modulator type 1 1 modulator type a (1) or type b(0) type b is easier to flter out of band, but can have reduced in-band spectral performance at prescaler frequencies <1.5ghz. [4:1] r/w reserved 1 4 15 program 15 [7:5] r/w sd mode 3 0 see operational modes for mode information. 0 - fractional 1 - integer 2 - exact freq fractional (program reg 0dh appropriately) 3 - fm mode (program reg 0ch / reg 0dh for f2) 4 - pm mode (program phase step in reg 0ah ) 5 - sweep - 1 way - ramp then hop (triggered) 6 - sweep - 2 way - ramp both directions (triggered) 7 - sweep - 2 way auto - ramp both directions continuously [8] r/w autoseed (frac modes) unidirectional phase (pm) 1 1 non pm mode 1: the modulator phase is initialized on trigger events or at the start of a frequency ramp. 0: the modulator is not re-initialized in pm mode (reg06h[7:5]=4) 1: trigger on rising edge only 0: bi-phase modulation, level dependent [9] r/w external trigger enable (exttrig_en) 1 1 chooses to use the external trig pin for trigger events (frequency hops, ramp movement, phase or fm modulation). the function of this bit and the trigger system vary depending on sd mode. see operational modes for more information. [12:10] r/w reserved 7 3 7 program to 7 [13] r/w force dsm clock on 1 0 forces the modulator clock on, despite being in integer mode. this is useful to test coupling from digital to analog. [14] r/w bist enable 1 0 internal use only - program to 0 [16:15] r/w number of bist cycles 2 0 internal use only [18:17] r/w dsm clock source 2 0 0 - sd clock from mcounter (recommended > 50mhz) 1 - vdiv pfd clock 2 - rdiv pfd clock - use for phase coherence 3 - xtal (use for bist) [19] r/w invert dsm clock 1 0 test/bist only [20] r/w reserved 0 1 0 program to 0 [21] r/w force rdiv bypass 1 0 if 1, the rdivider can be used (and exported on gpo), but the pfd still uses the undivided xtal [22] r/w disable reset of extra accumulators on ramp 1 0 the autoseed bit determines if the phase accumulator of the dsm is reset at the start of a frequency ramp. normally the other accu - mulators are also reset - allowing for exact repeatability from cycle- to-cycle. this extra initialization is avoided if this bit is set - which can lead to more graceful transients at the start of a ramp. [23] r/w single step ramp mode 1 0 single step ramp mode. advances the ramp one step per trigger. can be used to generate arbitrary sweep profles with an external trigger. can also be used for sweep synchronization with the system.
plls - smt 6 6 - 48 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 20. reg 07h lock detect register bit type name w deflt description [2:0] r/w lkdcounts 3 5 lock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect window to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [10:3] r/w reserved 8 12d program 12d [11] r/w lockdetect counters enable 1 1 enable lock detect counters (r07[14] should also = 1) [13:12] r/w reserved 2 0 program 0 [14] r/w lock detect timer enable 1 1 enable lock detect timer (r07[11] should also = 1) [15] r/w cycle slip prevention enable 1 0 increases charge pump gain for phase errors larger than lock- detect timer. [19:16] r/w reserved 0 4 0 reserved [20] r/w train lock detect timer 1 0 this bit must be programmed from 0 to 1 after a change of pd reference clock frequency (via either the external reference or a change to the rdivider). [21] r/w reserved 1 0 reserved - program to 1 table 21. reg 08h analog en register bit type name w deflt description [0] r/w enbias 1 1 bias [1] r/w encp 1 1 charge-pump [2] r/w enpfd 1 1 pfd [3] r/w enxtal 1 1 reference buffer [4] r/w envco 1 1 vco buffer [5] r/w engpo 1 1 gpo output buffer enable (if 0 the buffer is hiz, if 1 the buffer may be hiz depending on gposel and spi activity) [6] r/w enmcnt 1 1 mcounter [7] r/w enps 1 1 prescaler [8] r/w envcobias 1 1 vco divider related biases [9] r/w enopamp 1 1 charge-pump amplifer [12:10] r/w vcooutbiasa 3 3 rf divider bias a sel [15:13] r/w vcooutbiasb 3 3 rf divider bias b sel [16] r/w vcobwsel 1 1 rf buffer bias sel [17] r/w rfdiv2sel 1 0 enables rf divide/2 [18] r/w xtallowgain 1 0 lowers the gain (and extends bw) of the xtal buffer [19] r/w xtaldissat 1 0 disables saturation protection on the xtal buffer
plls - smt 6 6 - 49 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 22. reg 09h charge pump register bit type name w deflt description [6:0] r/w cpidn 7 100 main sink current (20ua steps) [13:7] r/w cpiup 7 100 main source current (20ua steps) [20:14] r/w cpoffset 7 0 offset current (5ua steps) - see "charge-pump phase offset" for more information. [21] r/w cpsrcen 1 0 offset current polarity (source offset current) recommended 0 in integer mode , pfdinv in frac modes. [22] r/w cpsnken 1 1 offset current polarity (sink offset current) recommended 0 in integer mode ,not pfdinv in frac modes. [23] r/w cphik 1 0 hi gain mode (~4ma cp i boost depending on vcp) - use only with active loop flter confgurations, where vcp is controlled to offer better phase-noise. table 23. reg 0ah modulation step register bit type name w deflt description [23:0] r/w modstep 24 0 fractional modulation step size for ramp/phase modulation modes (ignored in integer, normal fractional, fm, or exact freq modes) this value is signed twos complement. positive values ramps up, negative values ramp down. table 24. reg 0bh pd register bit type name w deflt description [2:0] r/w pfddly 3 1 dead-zone avoidance delay (0~1 ns, 3~3 ns. > 3 is unused) [3] r/w pfdshort 1 0 tie both pd inputs to ref or div based on phase select. [4] r/w pfdinv 1 0 swap pd inputs for use in inverting loop confgurations. 0- use with a positive tuning slope vco and passive loop flter (default) 1- use with a negative tuning slope, or with an inverting active loop flter with a positive tuning slope vco [5] r/w pfdupen 1 1 0 will disable up pulses from propagating to the cp [6] r/w pfddnen 1 1 0 will disable dn pulses from propagating to the cp [7] r/w pfdforceup 1 0 1 will force to the top rail. [8] r/w pfdforcedn 1 0 1 will force to the bottom rail. [9] r/w pfdforcemid 1 0 1 will force to mid-rail [12:10] r/w psbiassel 3 0 ps bias current [14:13] r/w opampbiassel 2 3 opamp bias current [16:15] r/w mcntclkgatesel 2 3 if the quantized divide ratio is guaranteed to be within a certain range, this feature can be enabled to reduce toggle activity and power consumption slightly. (0: 16 to 31, 1: 16 to 127, 2: 16 to 1023, 3: 16 to max) [17] r/w vdivext 1 0 extend vco divider output pulse width [18] r/w lkdproctesttocp 1 0 muxes the lock-detect oscillator to the cp force up/dn for observa - tion.
plls - smt 6 6 - 50 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 25. reg 0ch altint bit type name w deflt description [15:0] r/w altint 16 25d stop freq for ramp mode, alternate freq for fm mode. see opera - tion modes for more information. table 26. reg 0dh altfrac bit type name w deflt description [23:0] r/w altfrac 24 0 stop freq for ramp mode, alternate freq for fm mode, number of channels/boundary for exact frequency mode. see operation modes for more information. table 27. reg 0eh spi trig bit type name w deflt description [0] r/w spitrig 1 0 this bit can be used as an alternative to the external trig pin. if reg06h[9] (exttrig_en)= 0 then this bit is used to trigger sweep, fm, or pm modes, trigger requires initial state of 0 followed by a write of 1. register must be reset to 0 before subsequent triggers. if reg06[8] = 0, then in pm mode this register is level sensitive and modulates the phase. see operating modes for more information.
plls - smt 6 6 - 51 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 28. reg 0fh gpo register bit type name w deflt description [4:0] r/w gposel 5 1 0: static test voltage - as defned by reg 0fh [5] 1: lock detect 2: lkd trigger 3: lkd window 4: process osc test 5: csp up control 6: csp dn control 7: rdiv core 8: xtal 9: rdiv_pfd 10: vdiv_pfd 11: mcnt_sd 12: ramp_busy 13: ramp_started 14: ramp_trig_pulse 15:bist_busy 16: dn 17: up 18: bist_clk 19: ramp_clk 20: intg strobe 21: frac strobe 22: spi strobe 23: spi sle 24: sd reload 25: sd full-reload 29 lkd training 30 outbuf en [5] r/w gpotest 1 0 static test signal for output when gposel=1 [6] r/w gpoalways 1 0 prevents auto-muxing the gpo with sdo. it always stays gpo. [7] r/w gpoon 1 0 keeps the gpo driver in output mode (rather than selective drive based on chipaddr), unless engpo=0. [8] r/w gpopullupdis 1 0 disables the gpo pull-up transistor (suitable for wired or with exter - nal pull-up or analog lock-detect methods) [9] r/w gpopulldndis 1 0 disables the gpo pull-dn transistor (suitable for wired or with exter - nal pull-dn or analog lock-detect methods) table 29. reg 10h reserve register (read only) bit type name w deflt description [8:0] ro reserved 9 0 reserved table 30. reg 11h reserve register (read only) bit type name w deflt description [18:0] ro reserved 19 0 reserved
plls - smt 6 6 - 52 HMC703LP4E v00.0311 8 gh z fractional synthesizer for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 ? 978-250-3373 fax ? order on-line at www.hittite.com application support: pll@hittite.com table 31. reg 12h gpo2 register (read only) bit type name w deflt description [0] ro gpo 1 0 gpo [1] ro lock detect 1 0 lock detect [2] ro ramp busy 1 0 ramp busy table 32. reg 13h bist status (read only) bit type name w deflt description [15:0] ro bist signature 16 internal use only [16] ro bist busy 1 internal use only table 33. reg 14h lock detect timer status (read only) bit type name w deflt description [2:0] ro lkdspeed 3 0 lock detect timer trained speed [3] ro lkdtraining 1 0 lock detect timer is busy training

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