View ICS950901YFLFT_2421627.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated circuit systems, inc. ics950901 block diagram 0474f?05/25/05 pin configuration recommended application: via p4x266 chipset with pc133 or ddr memory. output features: 2 - pair of differential cpu clocks @ 3.3v 1 - pair of differential push pull cpu_cs clocks @ 2.5v 3 - agp @ 3.3v 9 - pci @ 3.3v 2 - ioapic @ 2.5v 1 - 48mhz @ 3.3v fixed 1 - 24_48mhz @ 3.3v 1 - ref @ 3.3v, 14.318mhz features/benefits: programmable output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i 2 c index read/write and block read/write operations. for ddr and or pc133 sdram system use ics93718 as the memory buffer. uses external 14.318mhz crystal. key specifications: ? cpu_cs - cpu0: <250ps cpu_cs - agp: <250ps pci - pci: <500ps cpu - pci: min = 1.0ns, typ = 2.0ns, max = 4.0ns programmable timing control hub? for p4? 1. these outputs have 2x drive strength. * these inputs have a internal pull-up resistor of 120k to vdd ** these inputs have a internal pull-down to gnd 48-pin 300-mil ssop frequency table i ref i ref pll2 pll2 pll1 pll1 spread spread spectr spectr um um 48mhz 48mhz 24_48mhz 24_48mhz io io apic (1:0) apic (1:0) pciclk (7:0) pciclk (7:0) a a gpclk (2:0) gpclk (2:0) reset# reset# pciclk_f pciclk_f 3 3 x1 x1 x2 x2 xt xt al al osc osc cpu cpu divder divder cpu cpu divder divder io io apic apic divder divder pci pci divder divder a a gp gp divder divder stop stop stop stop stop stop sel24_48 sel24_48 sd sd a a t t a a sclk sclk fs (3:0) fs (3:0) pd# pd# pci_st pci_st op# op# cpu_st cpu_st op# op# mul mul ti_sel ti_sel vtt_pwrgd# vtt_pwrgd# control control logic logic config. config. reg. reg. / 2 / 2 ref ref cpuclkt_(1:0) cpuclkt_(1:0) cpuclkc_(1:0) cpuclkc_(1:0) cpuclkt_cs cpuclkt_cs cpuclkc_cs cpuclkc_cs 3 s f2 s f1 s f0 s f k l c u p c z h m p g a z h m k l c i c p z h m 0000 7 6 . 6 66 6 . 6 63 3 . 3 3 0001 0 0 . 0 0 17 6 . 6 63 3 . 3 3 0010 3 3 . 3 3 17 6 . 6 63 3 . 3 3 0011 0 0 . 0 0 26 6 . 6 63 3 . 3 3 0100 0 9 . 0 0 17 2 . 7 63 6 . 3 3 0101 0 0 . 3 0 17 6 . 8 63 3 . 4 3 0110 0 0 . 7 0 13 3 . 1 77 6 . 5 3 0111 0 0 . 0 1 13 3 . 3 77 6 . 6 3 1000 0 9 . 3 3 15 9 . 6 68 4 . 3 3 1001 3 3 . 7 3 16 6 . 8 63 3 . 4 3 1010 0 0 . 0 4 10 0 . 0 70 0 . 5 3 1011 6 6 . 2 4 13 3 . 1 77 6 . 5 3 1100 3 3 . 5 4 16 6 . 2 73 3 . 6 3 1101 6 6 . 6 4 13 3 . 3 77 6 . 6 3 1110 3 3 . 3 5 16 6 . 6 73 3 . 8 3 1111 0 0 . 0 6 10 0 . 0 80 0 . 0 4 1 *sel24_48/ref vddref gnd x1 x2 vdd48 **fs3/48mhz **fs2/24_48mhz gnd *fs0/pciclk_f **fs1/pciclk0 pciclk1 gnd pciclk2 pciclk3 vddpci pciclk4 pciclk5 pciclk6 gnd pciclk7 *pd# agpclk0 vddagp vddapic (2.5v) gnd ioapic0 ioapic1 gnd vddcpu_cs (2.5v) cpuclkt_cs cpuclkc_cs cpuclkt_0 cpuclkc_0 vddcpu (3.3v) i ref gnd cpuclkt_1 cpuclkc_1 vtt_pwrgd# cpu_stop#* pci_stop#* reset# sdata sclk agpclk2 agpclk1 gnd ics9509 01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 33 32 31 30 2 9 28 27 26 25
2 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 pin description the ics950901 is a single chip clock solution for desktop designs using the via p4x266 chipset with pc133 or ddr memory. with pc133 or ddr memory. when used with a fanout buffer such as the ics93712, ics93715 or the ics93718 provides all the necessary clock signals for such a system. the ics950901 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. general description r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1 8 4 _ 4 2 l e sn i. t u p t u o z h m 8 4 r o 4 2 r e h t i e s t c e l e s f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 8 3 , 4 2 , 6 1 , 6 , 2d d vr w p. y l p p u s r e w o p v 3 . 3 41 xn i . 2 x m o r f r o t s i s e r k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 52 xt u o . ) f p 3 3 ( p a c d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c 7 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 8 4t u o. . t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 8 2 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 8 4 _ 4 2t u o. t u p t u o z h m 8 4 r o 4 2 e l b a t c e l e s , 5 2 , 0 2 , 3 1 , 9 , 3 7 4 , 4 4 , 6 3 d n gr w p. y l p p u s v 3 . 3 r o f s n i p d n u o r g 0 1 0 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l f _ k l c i c pt u ot u p t u o k c o l c i c p g n i n n u r e e r f v 3 . 3 1 1 1 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 0 k l c i c pt u o. t u p t u o k c o l c i c p v 3 . 3 2 2# d pn i e h t . e t a t s r e w o p w o l a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a r e w o p e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a o c v e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i . s m 3 n a h t r e t a e r g e b t o n l l i w n w o d 4 1 , 5 1 , 7 1 , 8 1 , 9 1 , 1 2) 2 : 7 ( k l c i c pt u o. s t u p t u o k c o l c i c p v 3 . 3 3 2 , 6 2 , 7 2) 0 : 2 ( p g at u o. d e p p o t s e b t o n y a m e s e h t . i c p x 2 s a d e n i f e d s t u p t u o p g a 8 2k l c sn ii r o f n i p k c o l c 2 . t n a r e l o t v 5 y r t i u c r i c c 9 2a t a d so / ii r o f n i p a t a d 2 . t n a r e l o t v 5 y r t i u c r i c c 0 3# t e s e rt u o e v i t c a s i l a n g i s s i h t . t u o e m i t r e m m i t g o d h c t a w r o e u l a v y c n e u q e r f r o f l a n g i s t e s e r m e t s y s e m i t l a e r . w o l 3 3# d g r w p _ t t vn i y d a e r d n a d i l a v s i ) 0 : 3 ( s f n e h w e n i m r e t e d o t d e s u e b o r t s e v i t i s n e s l e v e l a s i t u p n i l t t v l v 3 . 3 s i h t . ) w o l e v i t c a ( d e l p m a s e b o t 9 3 , 4 3) 0 : 1 ( _ c k l c u p ct u o l a n r e t x e d n a s t u p t u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r 0 4 , 5 3) 0 : 1 ( _ t k l c u p ct u o e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o t n e r r u c e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . s a i b e g a t l o v r o f d e r i u q e r 7 3f e r it u o d e x i f a s e r i u q e r n i p s i h t . s r i a p k l c u p c e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i l b a t s e n i p s i h t . t n e r r u c e t a i r p o r p p a e h t h s i l b a t s e o t r e d r o n i d n u o r g o t d e i t r o t s i s e r n o i s i c e r p 1 4s c _ c k l c u p ct u o . s t u p t u o l l u p - h s u p v 5 . 2 e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " " y r o t n e m e l p m o c 2 4s c _ t k l c u p ct u o . s t u p t u o l l u p - h s u p v 5 . 2 e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " " e u r t 3 4) v 5 . 2 ( s c _ u p c d d vr w p. v 5 . 2 s t u p t u o s c _ k l c u p c r o f r e w o p 6 4 , 5 4) 0 : 1 ( c i p a o it u os t u p t u o k c o l c v 5 . 2 8 4) v 5 . 2 ( c i p a d d vr w p. v 5 . 2 s k c o l c c i p a r o f r e w o p
3 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 general i 2 c serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit *see notes on the following page . ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack
4 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 byte 0: functionality and frequency select register (default=0) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. t i b n o i t p i r c s e d d w p t i b ) 4 : 7 , 2 ( 2 t i b 7 t i b6 t i b5 t i b4 t i b k l c u p c z h m k l c p g a z h m k l c i c p z h m % d a e r p s 1 e t o n 3 s f2 s f1 s f0 s f 00000 7 6 . 6 66 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 00001 0 0 . 0 0 17 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 00010 3 3 . 3 3 17 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 00011 0 0 . 0 0 26 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 00100 0 9 . 0 0 17 2 . 7 63 6 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 00101 0 0 . 3 0 17 6 . 8 63 3 . 4 3d a e r p s r e t n e c % 0 3 . 0 - / + 00110 0 0 . 7 0 13 3 . 1 77 6 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 00111 0 0 . 0 1 13 3 . 3 77 6 . 6 3d a e r p s r e t n e c % 0 3 . 0 - / + 01000 0 9 . 3 3 15 9 . 6 68 4 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 01001 3 3 . 7 3 16 6 . 8 63 3 . 4 3d a e r p s r e t n e c % 0 3 . 0 - / + 01010 0 0 . 0 4 10 0 . 0 70 0 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 01011 6 6 . 2 4 13 3 . 1 77 6 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 01100 3 3 . 5 4 16 6 . 2 73 3 . 6 3d a e r p s r e t n e c % 0 3 . 0 - / + 01101 6 6 . 6 4 13 3 . 3 77 6 . 6 3d a e r p s r e t n e c % 0 3 . 0 - / + 01110 3 3 . 3 5 16 6 . 6 73 3 . 8 3d a e r p s r e t n e c % 0 3 . 0 - / + 01111 0 0 . 0 6 10 0 . 0 80 0 . 0 4d a e r p s r e t n e c % 0 3 . 0 - / + 10000 7 6 . 6 66 6 . 6 63 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 1000 1 0 0 . 0 0 17 6 . 6 63 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 100 10 3 3 . 3 3 17 6 . 6 63 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 100 11 0 0 . 0 0 26 6 . 6 63 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 10 100 7 6 . 6 66 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 5 . 0 - / + 10 10 1 0 0 . 0 0 17 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 5 . 0 - / + 10 110 3 3 . 3 3 17 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 5 . 0 - / + 10 111 0 0 . 0 0 26 6 . 6 63 3 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 11000 0 0 . 1 0 20 0 . 7 60 5 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 11001 0 0 . 3 0 27 6 . 7 63 8 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 11010 0 0 . 5 0 23 3 . 8 67 1 . 4 3d a e r p s r e t n e c % 0 3 . 0 - / + 11011 0 0 . 7 0 20 0 . 9 60 5 . 4 3d a e r p s r e t n e c % 0 3 . 0 - / + 11100 0 0 . 9 0 27 6 . 9 63 8 . 4 3d a e r p s r e t n e c % 0 3 . 0 - / + 11101 0 0 . 1 1 23 3 . 0 77 1 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 11110 0 0 . 3 1 20 0 . 1 70 5 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 11111 0 0 . 5 1 27 6 . 1 73 8 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b s t u p n i h c t a l y b d e t c e l e s e b l l i w y c n e u q e r f e f a s g o d h c t a w - 0 ) 0 : 4 ( t i b 0 1 e t y b y b d e m m a r g o r p e b l l i w y c n e u q e r f e f a s g o d h c t a w - 1 0
5 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 byte 1: cpu active/inactive register (1 = enable, 0 = disable) byte 3: active/inactive register (1 = enable, 0 = disable) byte 2: pci active/inactive register (1 = enable, 0 = disable) byte 4: frequency select active/inactive register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b11 z h m 8 4 = 1 z h m 4 2 = 0 , 8 4 _ 4 2 l e s 5 t i b-1 ) d e v r e s e r ( 4 t i b6 41 0 c i p a o i 3 t i b5 41 1 c i p a o i 2 t i b3 21 0 k l c p g a 1 t i b6 21 1 k l c p g a 0 t i b7 21 2 k l c p g a t i b# n i pd w pn o i t p i r c s e d 7 t i b1 21 ) e v i t c a n i / e v i t c a ( 7 k l c i c p 6 t i b9 11 ) e v i t c a n i / e v i t c a ( 6 k l c i c p 5 t i b8 11 ) e v i t c a n i / e v i t c a ( 5 k l c i c p 4 t i b7 11 ) e v i t c a n i / e v i t c a ( 4 k l c i c p 3 t i b5 11 ) e v i t c a n i / e v i t c a ( 3 k l c i c p 2 t i b4 11 ) e v i t c a n i / e v i t c a ( 2 k l c i c p 1 t i b2 11 ) e v i t c a n i / e v i t c a ( 1 k l c i c p 0 t i b1 11 ) e v i t c a n i / e v i t c a ( 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b0 11 ) e v i t c a n i / e v i t c a ( f _ k l c i c p 5 t i b-1 ) d e v r e s e r ( 4 t i b-0 ) d e v r e s e r ( 3 t i b-0 ) d e v r e s e r ( 2 t i b4 3 , 5 31 ) e v i t c a n i / e v i t c a ( 1 c / t k l c u p c 1 t i b9 3 , 0 41 ) e v i t c a n i / e v i t c a ( 0 c / t k l c u p c 0 t i b1 4 , 2 41 ) e v i t c a n i / e v i t c a ( s c _ c / t k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-x # 3 s f d e h c t a l 6 t i b-x # 2 s f d e h c t a l 5 t i b-x # 1 s f d e h c t a l 4 t i b-x # 0 s f d e h c t a l 3 t i b71 ) e v i t c a n i / e v i t c a ( z h m 8 4 2 t i b81 ) e v i t c a n i / e v i t c a ( z h m 8 4 _ 4 2 1 t i b-0 d e v r e s e r 0 t i b11 ) e v i t c a n i / e v i t c a ( f e r
6 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 byte 7: revision id and device id register byte 8: byte count read back register byte 5: peripheral active/inactive register (1 = enable, 0 = disable) byte 6: vendor id register (1 = enable, 0 = disable) t i be m a nd w pn o i t p i r c s e d 7 t i b7 e t y b0 w o h d n a t n u o c e t y b e r u g i f n o c l l i w r e t s i g e r s i h t o t g n i t i r w : e t o n s i t l u a f e d , k c a b d a e r e b l l i w s e t y b y n a m f 0 h . s e t y b 5 1 = 6 t i b6 e t y b0 5 t i b5 e t y b0 4 t i b4 e t y b0 3 t i b3 e t y b1 2 t i b2 e t y b1 1 t i b1 e t y b1 0 t i b0 e t y b1 t i be m a nd w pn o i t p i r c s e d 7 t i b7 d i e c i v e d1 e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i e c i v e d . e s a c s i h t n i " h 1 0 " 6 t i b6 d i e c i v e d0 5 t i b5 d i e c i v e d0 4 t i b4 d i e c i v e d1 3 t i b3 d i e c i v e d1 2 t i b2 d i e c i v e d0 1 t i b1 d i e c i v e d1 0 t i b0 d i e c i v e d0 t i be m a nd w pn o i t p i r c s e d 7 t i b3 t i b d i n o i s i v e rx n o i s i v e r s ' e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i n o i s i v e r 6 t i b2 t i b d i n o i s i v e rx 5 t i b1 t i b d i n o i s i v e rx 4 t i b0 t i b d i n o i s i v e rx 3 t i b3 t i b d i r o d n e v0) d e v r e s e r ( 2 t i b2 t i b d i r o d n e v0) d e v r e s e r ( 1 t i b1 t i b d i r o d n e v0) d e v r e s e r ( 0 t i b0 t i b d i r o d n e v1) d e v r e s e r ( t i b# n i pd w pn o i t p i r c s e d 7 t i bx- ) d e v r e s e r ( 6 t i bx- ) d e v r e s e r ( 5 t i bx- ) d e v r e s e r ( 4 t i bx- ) d e v r e s e r ( 3 t i bx- ) d e v r e s e r ( 2 t i bx- ) d e v r e s e r ( 1 t i bx- ) d e v r e s e r ( 0 t i bx- ) d e v r e s e r (
7 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 byte 10: programming enable bit 8 watchdog control register byte 11: vco frequency m divider (reference divider) control register byte 12: vco frequency n divider (vco divider) control register byte 9: watchdog timer count register t i be m a nd w pn o i t p i r c s e d 7 t i b7 d w0 ? x o t d n o p s e r r o c s t i b 8 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t e d o m m r a l a o t s e o g t i e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t s m 0 9 2 s i p u r e w o p t a t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f e h t t e s e r d n a . s d n o c e s 3 . 2 = s m 0 9 2 ? 8 6 t i b6 d w0 5 t i b5 d w0 4 t i b4 d w0 3 t i b3 d w1 2 t i b2 d w0 1 t i b1 d w0 0 t i b0 d w0 t i be m a nd w pn o i t p i r c s e d 7 t i b8 v i d nx 8 t i b r e d i v i d n 6 t i b6 v i d mx e h t o t d s o p s e r r o c ) 0 : 6 ( v i d m f o n o i t a t n e s e r p s e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d e c n e r e f e r . n o i t c e l e s s t u p n i d e h c t a l 5 t i b5 v i d mx 4 t i b4 v i d mx 3 t i b3 v i d mx 2 t i b2 v i d mx 1 t i b1 v i d mx 0 t i b0 v i d mx t i be m a nd w pn o i t p i r c s e d 7 t i b7 v i d nx e h t o t d n o p s e r r o c ) 0 : 8 ( v i d n f o n o i t a t n e s e r p e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d o c v . 1 1 e t y b n i d e t a c o l s i 8 v i d n e c i t o n . n o t c e l e s s t u p n i d e h c t a l 6 t i b6 v i d nx 5 t i b5 v i d nx 4 t i b4 v i d nx 3 t i b3 v i d nx 2 t i b2 v i d nx 1 t i b1 v i d nx 0 t i b0 v i d nx t i be m a nd w pn o i t p i r c s e d 7 t i b m a r g o r p e l b a n e 0 t i b e l b a n e g n i m m a r g o r p 1 0 e t y b r o s e h c t a l w h y b d e t c e l e s e r a s e i c n e u q e r f . g n i m m a r g o r p o n = 0 i l l a e l b a n e = 2 . g n i m a r g o r p c 6 t i be l b a n e d w0 . t i b e l b a n e g o d h c t a w . e l b a n e = 1 , e l b a s i d = 0 . e u l a v d e h c t a l n e d w e t i r w r e v o l l i w t i b s i h t 5 t i bm r a l a d w0 s u t a t s m r a l a = 1 l a m r o n = 0 s u t a t s m r a l a g o d h c t a w 4 t i b4 f s0 e f a s e h t e r u g i f n o c l l i w s t i b e s e h t o t g n i t i r w . s t i b y c n e u q e r f e f a s g o d h c t a w e l b a t 4 : 7 , 2 t i b 0 e t y b o t g n i d n o p s r r o c y c n e u q e r f 3 t i b3 f s1 2 t i b2 f s0 1 t i b1 f s0 0 t i b0 f s0
8 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 byte 14: spread spectrum control register byte 15: output divider control register byte 13: spread spectrum control register byte 16: output divider control register t i be m a nd w pn o i t p i r c s e d 7 t i b7 s sx d a e r p s e h t m a r g o r p l l i w t i b ) 0 : 2 1 ( m u r t c e p s d a e r p s e h t e h t n o d e s a b d e t a l u c l a c e b o t s d e e n t n e c e r p d a e r p s . e g a t n e c e r p d a e r p s d n a t n u o m a g n i d a e r p s , e l i f o r p g n i d a e r p s , y c n e u q e r f o c v d a e r p s r o f e r a w t f o s s c i e s u o t d e d n e m m o c e r s i t i . y c n e u q e r f . r e d i v i d s f d e h c t a l s i n o r e w o p t l u a f e d . g n i m m a r g o r p 6 t i b6 s sx 5 t i b5 s sx 4 t i b4 s sx 3 t i b3 s sx 2 t i b2 s sx 1 t i b1 s sx 0 t i b0 s sx t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rxd e v r e s e r 6 t i bd e v r e s e rxd e v r e s e r 5 t i bd e v r e s e rxd e v r e s e r 4 t i b2 1 s sx 2 1 t i b m u r t c e p s d a e r p s 3 t i b1 1 s sx 1 1 t i b m u r t c e p s d a e r p s 2 t i b0 1 s sx 0 1 t i b m u r t c e p s d a e r p s 1 t i b9 s sx 9 t i b m u r t c e p s d a e r p s 0 t i b8 s sx 8 t i b m u r t c e p s d a e r p s t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d 1 / 0 u p c0 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c 1 / 0 u p c o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t 6 t i b2 v i d 1 / 0 u p c1 5 t i b1 v i d 1 / 0 u p c0 4 t i b0 v i d 1 / 0 u p c1 3 t i b3 v i d s c _ u p c0 a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c s c _ u p c r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t 2 t i b2 v i d s c _ u p c1 1 t i b1 v i d s c _ u p c0 0 t i b0 v i d s c _ u p c1 t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d p g a0 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c p g a o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t 6 t i b2 v i d p g a1 5 t i b1 v i d p g a0 4 t i b0 v i d p g a1 3 t i b3 v i d c i p a0 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c c i p a o i o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 2 e l b a t 2 t i b2 v i d c i p a1 1 t i b1 v i d c i p a0 0 t i b0 v i d c i p a1
9 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 byte 17: output divider control register byte 18: group skew control register byte 19: group skew control register table 1 table 2 ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 02 /4 /8 /6 1 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 04 /8 /6 1 /2 3 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 19 /8 1 /6 3 /2 7 / t i be m a nd w pn o i t p i r c s e d 7 t i bv n i _ p g a0 t i b n o i s r e v n i e s a h p p g a 6 t i bv n i _ c i p a0 t i b n o i s r e v n i e s a h p c i p a 5 t i bv n i _ 1 / 0 u p c0 t i b n o i s r e v n i e s a h p 1 / 0 u p c 4 t i bv n i _ s c _ u p c0 t i b n o i s r e v n i e s a h p s c _ u p c 3 t i b 3 v i d i c p1 s t i b 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c i c p . 2 e l b a t o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d 2 t i b 2 v i d i c p0 1 t i b 1 v i d i c p0 0 t i b 0 v i d i c p1 t i be m a nd w pn o i t p i r c s e d 7 t i bc i p a o i1 l o r t n o c w e k s p u o r g 6 t i bc i p a o i0 5 t i bc i p a o i0 4 t i bc i p a o i0 3 t i b) 0 : 7 ( k l c i c p1 2 t i b) 0 : 7 ( k l c i c p0 1 t i b) 0 : 7 ( k l c i c p0 0 t i b) 0 : 7 ( k l c i c p0 t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e k s _ u p c1 o t t c e p s e r h t i w s c _ t / c k l c u p c e h t y a l e d s t i b 2 e s e h t ) 0 : 1 ( t / c k l c u p c s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 6 t i b0 w e k s _ u p c0 5 t i b1 w e k s _ u p c1 e h t y a l e d s t i b 2 e s e h t) 0 : 1 ( t / c k l c u p co t t c e p s e r h t i w k c o l c s c _ t / c k l c u p c s p 0 5 2 = 1 0 s p 0 = 0 0s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 4 t i b0 w e k s _ u p c0 3 t i bk l c p g a1 l o r t n o c w e k s p u o r g 2 t i bk l c p g a0 l o r t n o c w e k s p u o r g 1 t i bk l c p g a1 l o r t n o c w e k s p u o r g 0 t i bk l c p g a0 l o r t n o c w e k s p u o r g
10 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 byte 20: group skew control register byte 21: slew rate control register byte 22: slew rate control register byte 23: slew rate control register t i be m a nd w pn o i t p i r c s e d 7 t i b3 w e k s _ i c p1 - s n 4 . 1 m o r f w e k s ) 0 : 7 ( i c p o t u p c e h t e g n a h c n a c s t i b 4 e s e h t r o t n e m e r c n i y r a n i b h c a e . s n 5 . 2 - s i p u r e w o p t a t l u a f e d . s n 9 . 2 e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w ) 0 : 3 ( s t i b f o t n e m e r c e d . s p 0 0 1 y b s k c o l c i c p 6 t i b2 w e k s _ i c p0 5 t i b1 w e k s _ i c p0 4 t i b0 w e k s _ i c p0 3 t i b3 w e k s _ f i c p1 - s n 4 . 1 m o r f w e k s f i c p o t u p c e h t e g n a h c n a c s t i b 4 e s e h t r o t n e m e r c n i y r a n i b h c a e . s n 5 . 2 - s i p u r e w o p t a t l u a f e d . s n 9 . 2 e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w ) 0 : 3 ( t i b f o t n e m e r c e d . s p 0 0 1 y b s k c o l c i c p 2 t i b2 w e k s _ f i c p0 1 t i b1 w e k s _ f i c p0 0 t i b0 w e k s _ f i c p0 t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e l s f e r0 . s t i b l o r t n o c e t a r w e l s k c o l c f e r k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 6 t i b0 w e l s f e r1 5 t i b1 w e l s ) 4 : 7 ( i c p0 . s t i b l o r t n o c e t a r w e l s k c o l c ) 4 : 6 ( i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s ) 4 : 7 ( i c p1 3 t i b ) 1 : 3 ( i c p1 w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c ) 1 : 3 ( i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b ) 1 : 3 ( i c p0 w e l s 1 1 t i b 0 i c p1 w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c 0 i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b 0 i c p0 w e l s 1 t i be m a nd w pn o i t p i r c s e d 7 t i b1 w e l s _ 1 _ f i c p0 . s t i b l o r t n o c e t a r w e l s k c o l c f i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 6 t i b0 w e l s _ 1 _ f i c p1 5 t i b1 w e l s _ 0 _ f i c p0 . s t i b l o r t n o c e t a r w e l s k c o l c i c p k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 4 t i b0 w e l s _ 0 _ f i c p1 3 t i b1 w e l s _ ) 1 : 2 ( p g a0 ) 1 : 2 ( p g a. s t i b l o r t n o c e t a r w e l s k c o l c k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b1 w e l s _ ) 1 : 2 ( p g a1 1 t i b1 w e l s _ 0 _ p g a0 . s t i b l o r t n o c e t a r w e l s k c o l c 0 _ p g a k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b0 w e l s _ 0 _ p g a1 t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rx d e v r e s e r 6 t i bd e v r e s e rx 5 t i bd e v r e s e rx d e v r e s e r 4 t i bd e v r e s e rx 3 t i b1 w e l s 4 2 - 8 40 . s t i b l o r t n o c e t a r w e l s k c o l c 4 2 - 8 4 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i b0 w e l s 4 2 - 8 41 1 t i b1 w e l s 4 2 - 8 40 . s t i b l o r t n o c e t a r w e l s k c o l c 4 2 - 8 4 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i b0 w e l s 4 2 - 8 41
11 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters. t a = 0 - 70c; supply voltage v dd = 3.3 v + - 5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with no pull-up resistors -200 ma operating i dd3.3op c l = 0 pf; select @ 66m 100 ma supply current c l = full load @ 133.3 mhz 181 280 ma power down i ref =2.32ma 13 20 ma supply current i dd3.3pd i ref = 5ma 37 ma input frequency f i v dd = 3.3 v; mhz pin inductance l p in 7nh c in logic inputs 5 pf input capacitance 1 c out output pin capacitance 6 pf c inx x 1 & x 2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3v to 1% target freq. 3 ms t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay (all outputs) 1 10 ns 1 guarenteed by design, not 100% tested in production. delay
12 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 electrical characteristic - cpuclkc/t ta = 0 - 70o c; vdd = 3.3 v +/-5%; (unless otherwise stated) parameter symbol conditions min typ max units current source output impedance z o v o = v x 3000 ? output high voltage v oh v r = 475w +1%; i ref =2.32ma; ioh = 6*iref 0.71 1.2 v output high current i oh -13.92 ma rise time 1 t r v ol = 20%, v oh = 80%, 0.175 - 0.525 v 175 263 700 ps differential crossover v x 45 50 55 % duty cycle 1 d t v t = 50% 45 51 55 % skew1, cpu to cpu t sk v t = 50% 55 150 ps jitter, cycle-to-cycle 1 t jcyc-cyc v t = v x 105 200 ps notes: 1 - guaranteed by design, not 100% tested in production. electrical characteristics - cpuclktc_cs t a = 0 - 70o c; v dd = 2.5v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12.0 ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v output high current i oh2b v oh = 1.7 v -19 ma output low current i ol2b v ol = 0.7 v 19 ma rise time t r2b v ol = 0.4 v, v oh = 2.0 v 0.75 1.6 ns differential crossover v x 45 50 55 % duty cycle d t2b v t = 1.25 v, typ: crossing 45 50.9 55 % skew t sk2b v t = 1.25 v 175 ps jitter, cycle-to-cycle t j c y c-c y c2b v t = 1.25 v 155 250 ps jitter, one sigma t j 1s2b v t = 1.25 v 150 ps jitter, absolute t jabs2b v t = 1.25 v -250 250 ps 1 guaranteed by design, not 100% tested in production.
13 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f 01 33.33 mhz output impedance r dsn1 vo = v d d *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -33 -33 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0.4 v 30 38 ma rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.91 2 ns fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.68 2 ns duty cycle d t1 v t = 1.5 v 45 49.7 55 % skew t sk1 v t = 1.5 v 332 500 ps jitter t jcyc-cyc v t = 1.5 v 116 250 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - agp t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -33 -33 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0.4 v 30 38 ma rise time t r1 v ol = 4 v, v oh = 2.4 v 0.5 1.16 2 ns fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.22 2 ns duty cycle d t1 v t = 1.5 v 45 51.8 55 % skew t sk1 v t = 1.5 v 175 ps jitter t jcyc-cyc v t = 1.5 v 84 500 ps 1 guarenteed by design, not 100% tested in production.
14 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 electrical characteristics - ioapic t a = 0 - 70o c; v dd = 3.3v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -12 ma 2 v output low voltage v ol4b i ol = 12 ma 0.4 v output high current i oh4b v oh = 1.7 v -19 ma output low current i ol4b v ol = 0.7 v 19 ma rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 1.16 2 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 1.09 2 ns duty cycle 1 d t4b v t = 1.25 v 45 49.9 55 % jitter, one sigma 1 t j 1s4b v t = 1.25 v 0.5 ns jitter, absolute 1 t j abs4b v t = 1.25 v -1 1 ns jitter, cycle to cycle normal v t = 1.25 v 89 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 48mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o v o = v dd *(0.5) 48 mhz output impedance r dsn1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -29 -23 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0.4 v 29 27 ma 48dot rise time t r1 v ol = 0.4 v, v oh = = 2.4 v 0.5 1.32 1 ns 48dot fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.28 1 ns vch 48 usb rise time t r v ol = 0.4 v, v oh = 2.4 v 1 1.32 2 ns vch 48 usb fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.26 2 ns 48 dot to 48 usb skew t skew1 v t = 1.5 v 0.3 1 ns duty cycle d t1 v t = 1.5 v 45 52.7 55 % jitter t jcyc-cyc v t = 1.5 v 119 350 ps 1 guarenteed by design, not 100% tested in production
15 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =10-20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r ds p 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.4 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -29 -23 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0.4 29 27 ma rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 0.89 4 ns fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 0.72 4 ns duty cycle d t1 v t = 1.5 v 45 54.6 55 % jitter t jcyc-cyc v t = 1.5 v 234 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 ? output impedance r dsn2b 1 v o = v dd *(0.5) 13.5 45 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v output high current i oh2b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 50 55 ns skew t sk2b 1 v t = 1.25 v 175 ps jitter t jcyc-cyc 1 v t = 1.25 v 250 ps 1 guarenteed by design, not 100% tested in production.
16 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
17 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 power down waveform note 1. after pd# is sampled active (low) for 2 consective rising edges of cpuclks, all the output clocks are driven low on their next high to low tranistiion. 2 . power-up latency <3ms. 3. waveform shown for 100mhz vco internal 0ns 12 25ns 50ns cpu 100mhz 3.3v 66mhz pci 33mhz apic 16.7mhz pd# sdram 100mhz ref 14.318mhz 48mhz
18 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.5v 66mhz pci 33mhz apic 16.7mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
integrated circuit systems, inc. 19 ics950901 for more information on integrated circuit systems inc. or any of our products please visit our web site at: http://www.icst.com registered company 9001 index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) designation for tape and reel packaging rohs compliant (optional) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) prefix ics, av = standard device ics xxxx y f lf - t example: ics950901 y flft ordering information
20 third party brands and names are the property of their respective owners. integrated circuit systems, inc. ics950901 revision history rev. issue date description page # f 5/25/2005 added lf ordering information. 19

▲Up To Search▲

Price & Availability of ICS950901YFLFT

	To Download ICS950901YFLFT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .