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reprogrammable asynchronous cmos logic device pldc20ra10 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 december 1987 - revised march 26, 1997 0ra10 features ? advanced-user programmable macrocell cmos eprom technology for reprogrammability up to 20 input terms 10 programmable i/o macrocells output macrocell programmable as combinatorial or asynchronous d-type registered output product-term control of register clock, reset and set and output enable register preload and power-up reset four data product terms per output macrocell fast ? commercial t pd = 15 ns t co = 15 ns t su = 7 ns ? military t pd = 20 ns t co = 20 ns t su = 10 ns low power ?i cc max - 80 ma (commercial) ?i cc max = 85 ma (military) high reliability ? proven eprom technology ? >2001v input protection ? 100% programming and functional testing windowed dip, windowed lcc, dip, lcc, plcc avail- abl e functional description the cypress pldc20ra10 is a high-performance, sec- ond-generation programmable logic device employing a flexi- ble macrocell structure that allows any individual output to be configured independently as a combinatorial output or as a fully asynchronous d-type registered output. the cypress pldc20ra10 provides lower-power operation with superior speed performance than functionally equivalent bipolar devices through the use of high-performance 0.8-mi- cron cmos manufacturing technology. the pldc20ra10 is packaged in a 24 pin 300-mil molded dip, a 300-mil windowed cerdip, and a 28-lead square leadless chip carrier, providing up to 20 inputs and 10 outputs. when the windowed device is exposed to uv light, the 20ra10 is erased and can then be reprogrammed. logic block diagram 4 987 65 4321 10 15 16 17 18 19 20 21 22 23 24 iiiiiii i 4 4 4 4 4 4 4 v cc 11 12 13 14 i v ss oe 4 4 i i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 4 4 4 4 4 4 4 4 44 macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell 9 87 65 4 321 0 pl ra10?1
pldc20ra10 2 macrocell architecture figure 1 illustrates the architecture of the 20ra10 macrocell. the cell dedicates three product terms for fully asynchronous control of the register set, reset, and clock functions, as well as, one term for control of the output enable function. the output enable product term output is anded with the input from pin 13 to allow either product term or hardwired external control of the output or a combination of control from both sources. if product-term-only control is selected, it is automat- ically chosen for all outputs since, for this case, the external output enable pin must be tied low. the active polarity of each output may be programmed independently for each out- put cell and is subsequently fixed. figure 2 illustrates the out- put enable options available. when an i/o cell is configured as an output, combinatorial-only capability may be selected by forcing the set and reset product term outputs to be high under all input conditions. this is achieved by programming all input term programming cells for these two product terms. figure 3 illustrates the available out- put configuration options. an additional four uncommitted product terms are provided in each output macrocell as resources for creation of user-de- fined logic functions. programmable i/o because any of the ten i/o pins may be selected as an input, the device input configuration programmed by the user may vary from a total of nine programmable plus ten dedicated in- puts (a total of nineteen inputs) and one output down to a ten-input, ten-output configuration with all ten programmable i/o cells configured as outputs. each input pin available in a given configuration is available as an input to the four control product terms and four uncommitted product terms of each programmable i/o macrocell that has been configured as an output. an i/o cell is programmed as an input by tying the output en- able pin (pin 13) high or by programming the output enable product term to provide a low, thereby disabling the output buffer, for all possible input combinations. when utilizing the i/o macrocell as an output, the input path functions as a feedback path allowing the output signal to be fed back as an input to the product term array. when the output cell is configured as a registered output, this feedback path may be used to feed back the current output state to the device inputs to provide current state control of the next output state as required for state machine implementation. preload and power-up reset functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of each register to be set by loading each register from an external source prior to exercising the device. testing of com- plex state machine designs is simplified by the ability to load an arbitrary state without cycling through long test vector se- quences to reach the desired state. recovery from illegal states can be verified by loading illegal states and observing recovery. preload of a particular register is accomplished by impressing the desired state on the register output pin and lowering the signal level on the preload control pin (pin1) to a logic low level. if the specified preload set-up, hold and pulse width minimums have been observed, the desired state is loaded into the register. to insure predictable system initializa- tion, all registers are preset to a logic low state upon pow- er-up, thereby setting the active low outputs to a logic high. note: 1. the cg7c324 is the pldc20ra10 packaged in the jedec-compatible 28-pin plcc pinout. pin function and pin order is identical fo r both plcc pinouts. the principal difference is in the location of the ? no connect ? (nc) pins selection guide generic part number t pd ns t su ns t co ns t cc ns com ? l mil com ? l mil com ? l mil com ? l mil 20ra10-15 15 7 15 80 20ra10-20 20 20 10 10 20 20 80 85 20ra10-25 25 15 25 85 20ra10-35 35 20 35 85 pin configurations lcc top view std plcc/hlcc jedec plcc/hlcc top view top view 5 6 7 8 9 10 11 4 3 2 282726 12131415161718 25 24 23 22 21 20 19 i/o i/o i/o i/o i/o i/o 2 3 4 5 6 7 25 24 23 22 21 20 19 5 6 7 8 9 10 11 121314 1516 1718 4 3 2 2827 26 i/o i/o i/o i/o i/o i/o 2 3 4 5 6 7 pldc20ra10 pldc20ra10 nc 9 i v i/o i/o 8 i/o i/o v i i ss v i/o i/o 0 1 0 1 cc cc 9 8 i/o i/o v i i ss 1 1 pl ra10 ? 2 ra10 ? 3ra10 ? 4 i 0 1 i i i i i i 2 3 4 5 6 7 8 9 oe nc nc nc 25 24 23 22 21 20 19 5 6 7 8 9 10 11 121314 1516 1718 4 3 2 2827 26 i/o i/o i/o i/o i/o i/o 2 3 4 5 6 7 pldc20ra10 i i v i/o i/o 0 1 cc 9 8 i/o i/o v ss 1 i 3 i i 4 5 nc nc i 6 oe i 9 8 7 nc pl i i 0 1 i 2 i 3 i i 4 5 nc i 6 i 7 i i 9 8 nc oe nc nc i 2 0 1 nc pl cg7c324 [1]
pldc20ra10 3 . figure 1. pldc20ra10 macrocell preload (from pin 1) output enable (from pin 13 ) c0 r s p q d pl 1 s o to i/o pi n ra10 ? 5 o figure 2. four possible output enable alternatives for the pldc20ra10 programmable oe ra10 ? 6 ra10 ? 7 ra10 ? 8 ra10 ? 9 output always enabled external pin combination of programmable and hardwired
pldc20ra10 4 figure 3. four possible macrocell configurations for the pldc20ra10 registered/activelow combinatorial/active low registered/active high combinatorial/active high d s q r d s q r ra10 ? 10 ra10 ? 11 ra10 ? 12 ra10 ? 13
pldc20ra10 5 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential (pin 24 to pin 12) ........................................... ? 0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage ......................................... ? 3.0 v to + 7.0 v output current into outputs (low) ............................. 16 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma dc program voltage..................................................... 13.0v ] operating range range ambient temperature v cc commercial 0 c to +75 c 5v 10% military [2] ? 55 c to +125 c 5v 10% electrical characteristics over the operating range [3] parameter description test conditions min. max. unit v oh output high voltage v cc = min., v in =v ih or v il i oh = ? 3.2 ma com ? l 2.4 v i oh = ? 2 ma mil v ol output low voltage v cc = min., v in = v ih or v il i ol = 8 ma 0.5 v v ih input high level guaranteed input logical high voltage for all inputs [4] 2.0 v v il input low level guaranteed input logical low voltage for all inputs [4] 0.8 v i ix input leakage current v ss v in v cc , v cc = max ? 10 +10 a i oz output leakage current v cc = max., v ss v out v cc ? 40 +40 a i sc output short circuit current [5] v cc = max., v out = 0.5v [6] ? 30 ? 90 ma i cc1 standby power supply current v cc = max., v in = gnd outputs open com ? l 75 ma mil 80 ma i cc2 power supply current at frequency [5] v cc = max., outputs disabled (in high z state) device operating at f max com ? l 80 ma mil 85 ma capacitance [5] parameter description test conditions max. unit c in input capacitance v in = 2.0 v @ f = 1 mhz 10 pf c out output capacitance v out = 2.0 v @ f = 1 mhz 10 pf notes: 2. t a is the ? instant on ? case temperature. 3. see the last page of this specification for group a subgroup testing information. 4. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 5. tested initially and after any design or process changes that may affect these parameters. 6. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation.
pldc20ra10 6 ac test loads and waveforms (commercial) ra10 ? 14 ra10 ? 15 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 50 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) <5ns <5 ns output r1 457 ? (470 ? mil) r2 270 ? (319 ? mil) 170 ? equivalent to: th venin equivalent(commercial) 1.86v=v thc r1 457 ? (470 ? mil) r2 270 ? (319 ? mil) output 190 ? equivalent to: th venin equivalent(military) 2.02v=v thc ra10 ? 16 ra10 ? 17 parameter v th output w aveform measurement level t pxz( ? ) 1.5v v oh 0.5v v x 0.5v t pxz(+) 2.6v v ol v x t pzx(+) v thc 0.5v t pzx( ? ) v thc v ol 0.5v v x v oh ra10 ? 18 ra10 ? 19 ra10 ? 20 ra10 ? 21 v x 0.5v v x ra10 ? 22 v oh 0.5v v ol v x 0.5v v x v oh ra10 ? 23 ra10 ? 24 0.5v v ol ra10 ? 25 v x t er( ? ) t er(+) t ea(+) t ea( ? ) 1.5v 2.6v v thc v thc (c)
pldc20ra10 7 switching characteristics over the operating range [3, 7, 8] parameter description commercial military unit ? 15 ? 20 ? 20 ? 25 ? 35 min. max. min. max. min. max. min. max. min. max. t pd input or feedback to non-registered output 15 20 20 25 35 ns t ea input to output enable 15 20 20 30 35 ns t er input to output disable 15 20 20 30 35 ns t pzx pin 13 to output enable 12 15 15 20 25 ns t pxz pin 13 to output disable 12 15 15 20 25 ns t co clock to output 15 20 20 25 35 ns t su input or feedback set-up time 7 10 10 15 20 ns t h hold time 3 5 3 5 5 ns t p clock period (t su + t co) 22 30 30 40 55 ns t wh clock width high [5] 10 13 12 18 25 ns t wl clock width low [5] 10 13 12 18 25 ns f max maximum frequency (1/t p ) [5] 45.5 33.3 33.3 25.0 18.1 mhz t s input of asynchronous set to registered output 15 20 20 25 40 ns t r input of asynchronous reset to registered output 15 20 20 25 40 ns t arw asynchronous reset width [5] 15 20 20 25 25 ns t asw asynchronous s-width [5] 15 20 20 25 25 ns t ar asynchronous set/ reset recovery time 10 12 12 15 20 ns t wp preload pulse width 15 15 15 15 15 ns t sup preload set-up time 15 15 15 15 15 ns t hp preload hold time 15 15 15 15 15 ns notes: 7. part (a) of ac test loads was used for all parameters except t ea , t er , t pzx and t pxz , which use part (b). 8. the parameters t er and t pxz are measured as the delay from the input disable logic threshold transition to v oh - 0.5 v for an enabled high output or v ol +0.5v for an enabled low output. please see part (c) of ac test loads and waveforms for waveforms and measurement reference lev els.
pldc20ra10 8 switching waveform cp reset asynchronous asynchronous outputs (highasserted) set output enable inputpin inputs,registered feedback t ar t pd t co t wh t wl t su t er t ea t p ra10 ? 26 t h preload switching waveform asynchronous reset asynchronous set t ea t er t hp t sup t wp ra10 ? 27 pin 13 output enable register outputs pin 1 preload clock ra10 ? 28 t r t arw asynchronous reset output ra10 ? 29 t s t asw asynchronous set output
pldc20ra10 9 functional logic diagram
pldc20ra10 10 military specifications group a subgroup testing document #: 38-00073-f ordering information i cc2 t pd (ns) t su (ns) t co (ns) ordering code package name package type operating range 80 15 7 15 pldc20ra10-15jc j64 28-lead plastic leaded chip carrier commercial pldc20ra10-15pc p13 24-lead (300-mil) molded dip CG7C324-A15JC j64 28-lead plastic leaded chip carrier 20 10 20 pldc20ra10-20pc p13 24-lead (300-mil) molded dip cg7c324-a20jc j64 28-lead plastic leaded chip carrier 85 20 10 20 pldc20ra10-20dmb d14 24-lead (300-mil) cerdip military pldc20ra10-20wmb w14 24-lead (300-mil) windowed cerdip 25 15 25 pldc20ra10-25dmb d14 24-lead (300-mil) cerdip pldc20ra10-25wmb w14 24-lead (300-mil) windowed cerdip 35 20 35 pldc20ra10-35dmb d14 24-lead (300-mil) cerdip pldc20ra10-35wmb w14 24-lead (300-mil) windowed cerdip dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t pd 9, 10, 11 t pzx 9, 10, 11 t co 9, 10, 11 t su 9, 10, 11 t h 9, 10, 11
pldc20ra10 11 package diagrams 24-lead (300-mil) cerdip d14 mil-std-1835 d- 9config.a 28-lead plastic leaded chip carrier j64 28-square leadless chip carrier l64 mil-std-1835 c-4 28-pin windowed leadless chip carrier q64 mil-std-1835 c-4
pldc20ra10 12 package diagrams (continued) 28-pin windowed leaded chip carrier h64
pldc20ra10 ? cypress semiconductor corporation, 1997. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 24-lead (300-mil) molded dip p13/p13a 24-lead (300-mil) windowed cerdip w14 mil-std-1835 d- 9 config.a

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