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vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 1 18065 fast low profile (2.5 mm) infrared transceiver module (mir, 1.152 mbit/s) for irda ? applications description the TFDU5307 is an infrared transceiver module compliant to the latest irda physical layer standard, supporting irda speeds up to 1.152 mbit/s (mir) and carrier based remote control modes up to 2 mhz. inte- grated within the transceiver module are a pin photo- diode, an infrared emitter (ired), and a low-power control ic to provide a total front-end solution in a sin- gle package. this vishay mir transceiver is built in a low profile package using the experiences of the lead frame babyface technology. the transceivers are capable of directly interfacing with a wide variety of i/o devices, which perform the modulation/ demodu- lation function. at a minimum, a v cc bypass capacitor and a serial resistor for current control are the only external components required implementing a com- plete solution. TFDU5307 has a tri-state output and is floating in shutdown mode with a weak pull-up. features ? compliant to the latest irda physical layer specification (up to 1.152 mbit/s) and tv remote control, bi-directional operation included. sensitivity covers full irda range. recommended operating range is from nose to nose to 70 cm operates from 2.7 v to 5.5 v within specification low power consumption (typ. 0.55 ma supply current in receive mode, no signal) power shutdown mode (< 5 a shutdown current in full temperature range, up to 85 c) surface mount package, low profile universal (l 8.5 mm x w 2.9 mm x h 2.5 mm) capable of surface mount soldering to side and top view orientation backward pin compatible to vishay semiconductors sir and mir infrared transceivers high efficiency emitter directly interfaces with various super i/o and controller devices tri-state-receiver output, floating in shut down with a weak pull-up split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, us patent no. 6,157,476 logic voltage 1.5 v to 5.5 v is independent of ired driver and analog supply voltage only one external component required tv remote control supported transmitter intensity can be adjusted by an external resistor for extended range (> 0.7 m) or minimum low power (> 0.2 m) irda compliance. applications telecommunication products (cellular phones, pagers) digital still and video cameras printers, fax machines, photocopiers, screen projectors medical and industrial data collection notebook computers, desktop pcs, palmtop computers (win ce, palm pc), pdas internet tv boxes, video conferencing systems external infrared adapters (dongles) kiosks, pos, point and pay devices including irfm - applications
www.vishay.com 2 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors parts table functional bloc k diagram pin description part description qty / reel TFDU5307-tr1 oriented in carrier tape for side view surface mounting 750 pcs TFDU5307-tr3 oriented in carrier tape for side view surface mounting 2500 pcs TFDU5307-tt1 oriented in carrier tape for top view surface mounting 750 pcs TFDU5307-tt3 oriented in carrier tape for top view surface mounting 2500 pcs ired driver tri-state driver gnd txd rxd vcc2 vcc1 amplifier comparator sd v logic logic & control ired c 18509 pin number function description i/o active 1ired anode connect ired anode to the v cc2 power supply through an external current limiting resistor. a separate unregulated power supply can be used at this pin. 2ired cathode ired cathode, internally connected to the driver transistor 3 txd this schmitt-trigger input is used to transmit serial data when sd is low. an on- chip protection circuit disables the led dr iver if the txd pin is asserted for longer than 80 s. when used in conjunction with the sd pin, this pin is also used to control receiver output pulse duration. the input threshold voltage adapts to and follows the logic voltage reference applied to the v logic pin (pin 7). ihigh 4 rxd received data output, push-pull cmos driver output capable of driving standard cmos or ttl loads. no external pull-up or pull-down resistor is required. floating with a weak pull-up of 500 k ? (typ.) in shutdown mode. the voltage swing is defined by the applied v logic voltage olow 5 sd shutdown. also used for setting the output pulse duration. setting this pin active for more than 1.5 ms places the module into shutdown mode. before that (t < 0.7 ms) on the falling edge of this signal, the state of the txd pin is sampled and used to set the receiver output to long pulse duration (2 s) or to short pulse duration (0.4 s) mode. the input threshold voltage adapts to and follows the logic voltage reference applied to the v logic pin (pin 7). ihigh 6v cc1 supply voltage 7v logic v logic defines the logic voltage levels for input and output. the rxd output range is from 0 v to v logic , for optimum noise suppression the inputs? logic decision level is 0.5 x v logic i 8 gnd ground
vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 3 pinout TFDU5307 weight 75 mg definitions: in the vishay transceiver data sheets the following nomenclature is used for defining the irda operating modes: sir: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version irphy 1.0 mir: 576 kbit/s to 1152 kbit/s fir: 4 mbit/s vfir: 16 mbit/s mir and fir were implemented with irphy 1.1, followed by irphy 1.2, adding the sir low power standard. irphy 1.3 extended the low power option to mir and fir and vfir was added with irphy 1.4.a new version of the standard in any case obsoletes the former version. with introducing the updated versions the old versions are obso- lete. therefore the only valid irda standard is the actual version irphy 1.4 (in oct. 2002). absolute maximum ratings reference point ground (pin 8) unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. 18101 1234 56 7 8 ired a txd rxd sd vcc vlog gnd ired c parameter test conditions symbol min ty p. max unit supply voltage range, transceiver - 0.3 v < v cc2 < 6 v - 0.5 v < v logic < 5.5 v v cc1 - 0.3 + 6.0 v supply voltage range, transmitter - 0.5 v < v cc1 < 6 v - 0.5 v < v logic < 5.5 v v cc2 - 0.3 + 6.5 v supply voltage range, v logic - 0.5 v < v cc1 < 6 v - 0.3 v < v cc2 < 6.5 v v logic - 0.3 + 5.5 v input current for all pins, except ired anode pin 10 ma output sinking current 25 ma power dissipation see derating curve, figure 4 p d 500 mw junction temperature t j 125 c ambient temperature range (operating) t amb - 25 + 85 c storage temperature range t stg - 25 + 85 c soldering temperature see recommended solder profile (figure 3) 240 c average output current, pin 1 i ired(dc) 125 ma repetitive pulsed output current, pin 1 to pin 2 t < 90 s, t on < 20 % i ired(rp) 600 ma ired anode voltage, pin 1 v ireda - 0.5 + 6.5 v voltage at all inputs and outputs v in < v cc1 is allowed v in - 0.5 + 5.5 v load at mode pin when used as mode indicator 50 pf
www.vishay.com 4 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors eye safety information *) due to the internal limitation meas ures the device is a "class 1" device. **) irda specifies the max. intensity with 500 mw/sr. electrical characteristics transceiver t amb = 25 c, v cc1 = v cc2 = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) standard illuminant a **) the typical threshold level is 0.5 x v logic . it is recommended to use the specified min/ma x values to avoid increased operating current. the inputs in low state are actively loaded for noise protection. see for that the "controlled pull down current" spec. equival ently a pull up current stabilizes the state when the inputs are in high state. parameter test conditions symbol min ty p. max unit virtual source size method: (1-1/e) encircled energy d1.82.0 mm maximum intensity for class 1 iec60825-1 or en60825-1, edition jan. 2001, operating below the absolute maximum ratings i e *) (500) **) mw/sr parameter test conditions symbol min ty p. max unit supply voltage v cc1 2.7 5.5 v idle supply current sd = low, e e = 1 klx i cc1 550 900 a average dynamic supply current, transmitting i ired = 500 ma, 25 % duty cycle i cc 1100 1500 a shutdown supply current sd = high, t = 25 c, e e = 0 klx i sd 1 a sd = high, t = 25 c, e e = 1 klx *) i sd 2.5 a standby supply current sd = high, t = 85 c, not ambient light sensitive i sd 5 a operating temperature range t a - 25 + 85 c output voltage low, rxd c load = 15 pf, i ol = 1 ma v ol 0.4 v output voltage high, rxd i oh = - 500 av oh 0.8 x v logic v i oh = - 250 a, c load = 15 pf v oh 0.9 x v logic v rxd to v cc1 impedance r rxd 400 500 600 k ? input voltage low (txd, sd) v il - 0.5 0.5 v input voltage high (txd, sd) cmos level **) v ih v logic - 0.5 v logic + 0.5 v input leakage current (txd, sd) v in = 0.9 x v logic i ich - 2 + 2 a controlled pull down current sd, txd = "0" to "1", 0 < v in < 0.15 v logic i irtx + 150 a sd, txd = "0" to "1", v in > 0.7 v logic i irtx - 1 0 1 a input capacitance (txd, sd) c in 5pf
vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 5 optoelectronic characteristics receiver t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) some endecs are not able to decode shor t pulses as valid sir pulses. therefore this additional mode was added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (sd must ha ve been longer active than 1.5 ms). for mode changing see the chapt er "programming" parameter test conditions symbol min ty p. max unit minimum detection threshold irradiance 9.6 kbit/s to 1.152 mbit/s = 850 nm - 900 nm e e 40 (4) 90 (9) mw/m 2 ( w/cm 2) maximum detection threshold irradiance = 850 nm - 900 nm e e 5 (500) kw/m 2 (mw/cm 2 ) no detection receiver input irradiance threshold! no rxd output below this irradiance value allowed e e 4 (0.4) mw/m 2 ( w/cm 2) rise time of output signal 10 % to 90 %, c l = 15 pf, v logic = v cc t r(rxd) 20 60 ns fall time of output signal 90 % to 10 %, c l = 15 pf, v logic = v cc t f(rxd) 20 60 ns rxd pulse width of output signal, default mode after power on or reset input pulse length p wopt > 200 ns t pw 300 400 500 ns sir endec compatibility mode *) : rxd pulse width of output signal input pulse length p wopt > 200 ns, see chapter "programming" t pw 1.7 2.0 2.9 s stochastic jitter, leading edge input irradiance = 100 mw/m 2 , 1.152 mbit/s, 576 kbit/s 80 ns input irradiance = 100 mw/m 2 , 115.2 kbit/s 350 ns standby /shutdown delay after shutdown active or (sd low to high transition) 0.6 1.5 ms shutdown active time window for programming during this time the pulse duration of the output can be programmed to the application mode. see chapter "programming" 600 s receiver start up time power on delay shutdown recovery delay after shutdown inactive (sd high to low transition) and after power-on 300 s latency t l 200 s
www.vishay.com 6 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors transmitter t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) note: due to this wavelength restriction compared to the irda s pec of 850 nm to 900 nm the transmitter is able to operate as s ource for the standard remote control applications with codes as e.g. philips rc5/rc6 ? or recs 80. when operated under irda full range con- ditions (>120 mw/sr) the rc range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used. **) typ. conditions for i f = 420 ma, v cc2 = 3.3 v, r s = 2.3 ? , v cc2 = 5.0 v, r s = 6.4 ? parameter test conditions symbol min ty p. max unit ired operating current, recommended serial resistor for mir applications v cc2 = 3.3 v: r s = 2.0 ? v cc2 = 5.0 v: r s = 5.6 ? i d 450 500 ma output leakage ired current txd = 0 v, 0 < v cc1 < 5.5 v i ired - 1 1 a output radiant intensity recommended application circuit, see figure 1 = 0 , i f =420 ma txd = high, sd = low **) i e 110 500 mw/sr = 0 , 15 , i f =420 ma txd = high, sd = low **) i e 70 120 500 mw/sr output radiant intensity v cc1 = 5.0 v, = 0 , 15 txd = low or sd = high (receiver is inactive as long as sd = high) i e 0.04 mw/sr output radiant intensity, angle of half intensity 24 peak - emission wavelength *) p 880 900 nm spectral bandwidth ? 45 nm optical rise time, fall time t ropt , t fopt 640ns optical output pulse duration input pulse width 217 ns, 1.152 mbit/s note: irda specification for mir t opt 190 (147.6) 217 240 (260) ns ns input pulse width t txd < 80 st opt 20 t txd s input pulse width t txd 80 st opt 20 85 s optical overshoot 25 %
vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 7 recommended circuit diagram used with a clean low impedance power supply the TFDU5307 only needs an external series current lim- iting resistor. however, depending on the entire sys- tem design and board layout, additional components may be required (see figure 1). the capacitor c1 is buffering the supply voltage and eliminates the inductance of the power supply line. this one should be a tantalum or other fast capacitor to guarantee the fast rise time of the ired current. the resistor r1 is the current limiting resistor and this is supply voltage dependent, see derating curve in fig- ure 4, to avoid too high internal power dissipation. vishay?s transceivers integrate a sensitive receiver and a built-in power driver. the combination of both needs a careful circuit board layout. the use of thin, long, resistive and inductive wiring should be avoided. the inputs (txd, sd) and the output rxd should be directly (dc) coupled to the i/o circuit. the capacitor c2 combined with the resistor r2 is the low pass filter for smoothing the supply voltage. r2, c1 and c2 are optional and dependent on the quality of the supply voltages and injected noise. an unstable power supply with dropping voltage during transmission may reduce the sensitivity (and trans- mission range) of the transceiver. the placement of these parts is critical. it is strongly recommended to position c2 as close as possible to the transceiver power supply pins. a tantalum capac- itor should be used for c1 while a ceramic capacitor is used for c2. in addition, when connecting the described circuit to the power supply, low impedance wiring should be used. when extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at v cc2 . often some power supplies are not apply to follow the fast current rise time. in that case another 4.7 f (type, see table under c1) at v cc2 will be help- ful. under extreme emi conditions as placing an rf- transmitter antenna on top of the transceiver, we rec- ommend to protect all inputs by a low-pass filter, as a minimum a 12 pf capacitor, especially at the rxd port. keep in mind that basic rf - design rules for circuit design should be taken into account. especially longer signal lines should not be used without termi- nation. see e.g. "the art of electronics" paul horow- itz, winfield hill, 1989, cambridge university press, isbn: 0521370957. table 1. recommended application circuit components figure 1. recommended application circuit ired anode v cc ground sd txd rxd v ired v cc gnd sd txd rxd r1 r2 c1 c2 18147 v logic v logic ired cathode component recommended value vishay part number c1 4.7 f, 16 v, tantalum 293d 475x9 016b c2 0.1 f, ceramic vj 1206 y 104 j xxmt r1 5 v supply voltage: 5.6 ? s. text 0.25 w (recommended using two 2.8 ? , 0.125 w resistors in series). 3.3 v supply voltage: 2.0 ? s. text 0.25 w e.g. 2 x crcw-1206-2r0-f-rt1 for 3.3 v supply voltage r2 47 ? , 0.125 w crcw-1206-47r0-f-rt1
www.vishay.com 8 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors i/o and software in the description, already different i/os are men- tioned. different combinations are tested and the function verified with the special drivers available from the i/o suppliers. in special cases refer to the i/ o manual, the vishay application notes, or contact directly vishay sales, marketing or application. programming pulse duration switching after power-on the TFDU5307 is in the default short rxd pulse duration mode. some endecs are not able to decode short pulses as valid sir pulses. therefore an additional mode with extended pulse duration (same as in standard sir transceivers) is added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, and after recovering from the shutdown mode (sd being active longer than 1.5 ms). to switch the transceivers from the short rxd pulse duration mode to the long pulse duration mode and vice versa, follow the procedure described below. setting to the endec compatibility mode with an rxd pulse duration of 2 s 1. set sd input to logic "high". 2. set txd input to logic "high". wait t s 200 ns. 3. set sd to logic "low" (this negative edge latches state of txd, which determines speed setting). 4. after waiting t h 200 ns. after that txd is enabled as normal txd input and the rxd output is set for the longer rxd - pulse duration mode. setting back to the default mode with a 400 ns pulse duration 1. set sd input to logic "high". 2. set txd input to logic "low". wait t s 200 ns. 3. set sd to logic "low" (this negative edge latches state of txd, which determines speed setting). 4. after waiting t h 200 ns txd can be set to logic "low". the hold time of txd is limited by the maxi- mum allowed pulse length. after that txd is now enabled as normal txd input and the rxd output is set for the short rxd - pulse duration mode. the timing of the pulse duration changing procedure is quite uncritical. however, the whole change must not take more than 600 s. see in the spec. "shut- down active time window for programming" simplified method setting the device to the long pulse duration is simply applying a short active (less than 600 s) pulse to sd. in any case a short sd pulse will force the device to leave the default mode and go the compatibility mode. vice versa applying a 1.5 ms (minimum) pulse at sd will cause the device to go back to the default mode by activating a power-on-reset and setting the device to the default short pulse mode. this simplified method takes more time but may be easier to handle. figure 2. timing diagram for changing the output pulse duration sd 50% t s t h high: txd 50% 50% 18150 low: 400 ns 2 s
vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 9 table 2. truth table recommended solder profile solder profile for sn/pb soldering inputs outputs remark sd txd optical input irradiance mw/m 2 rxd transmitte r operation high < 600 s x x weakly pulled (500 k ? ) to v cc1 0 time window for pulse duration setting high > 1.5 ms x x weakly pulled (500 k ? ) to v cc1 0 shutdown low high x low (active) i e transmitting high > 80 s x high inactive 0 protection is active low < 4 high inactive 0 ignoring low signals below the irda defined threshold for noise immunity low > min. detection threshold irradiance < max. detection threshold irradiance low (active) 0 response to an irda compliant optical input signal low > max. detection threshold irradiance undefined 0 overload conditions can cause unexpected outputs figure 3. recommended solder profile time(s) 14874 0 20 40 60 80 100 120 140 160 180 200 220 240 0 50 100 150 200 250 300 350 2 c-4 c/s 10 s max. @ 230 c 90 s max 120 s - 180 s 2 c-4 c/s temperature (c)
www.vishay.com 10 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors lead-free, recommended solder profile the TFDU5307 is a lead-free transceiver and quali- fied for lead-free processing. for lead-free solder paste like sn (3.0 - 4.0) ag (0.5 - 0.9) cu, there are two standard reflow profiles: ramp-soak-spike (rss) and ramp-to-spike (rts). the ramp-soak-spike profile was developed primarily for reflow ovens heated by infrared radiation. shown below in figure 4 is vishay?s recommended profile for use with the TFDU5307 transceivers. for more details please refer to application note: smd assembly instruction. current derating diagram figure 5 shows the maximum operating temperature when the device is operated without external current limiting resistor. a power dissipating resistor of 2 ? is recommended from the cathode of the ired to ground for supply voltages above 4 v. in that case the device can be operated up to 85 c, too. t = 250c for 20 s max 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 0 50 100 150 200 250 300 350 time/s 20 s max. 2c...4c/s 2c...4c/s t = 217c for 50 s max t peak = 260c max. 50 s max. 90 s...120 s 19048 temperature/ c figure 4. solder profile, rss recommendation figure 5. temperature derating diagram 50 55 60 65 70 75 80 85 90 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 operating voltage [v] @ duty cycle 20% ambient temperature ( c) 18097
vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 11 figure 6. intensity i e vs. current control resistor r2, 5 v applications figure 7. intensity i e vs. current control resistor r1, 3 v applications 0 100 200 300 400 500 0246810121416 current control resistor ( ) 14379 intensity (mw/sr) min. intensity in emission cone 15 max.r dson , max.v f max. intensity in emission cone 15 v cc =4.75v min. r dson , min. v f 5.0v 5.0v 5.25v 0 100 200 300 400 500 600 700 024681012 current control resistor ( ) 15111 intensity (mw/sr) emission cone 15 v cc =3.0v min. r dson , min. v f 3.3v 3.3v 3.6v max. intensity in emission cone 15 max. r dson , max. v f min. intensity in
www.vishay.com 12 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors package dimensions in mm 18100
vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 13 reel dimensions 14017 w 1 w 2 reel hub tape width a max. n w 1 min. w 2 max. w 3 min. w 3 max. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4
www.vishay.com 14 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors tape dimensions in mm 18306
vishay TFDU5307 document number 82616 rev. 1.4, 24-jun-04 vishay semiconductors www.vishay.com 15 18307
www.vishay.com 16 document number 82616 rev. 1.4, 24-jun-04 vishay TFDU5307 vishay semiconductors ozone depleting substances policy statement it is the policy of vishay semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol (1987) and its london amendments (1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. vishay semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. vishay semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice. parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use vishay semiconductors products for any unintended or unauthorized application, the buyer shall indemnify vishay semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. vishay semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2831, fax number: 49 (0)7131 67 2423

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