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rev. a a adn2811 oc-48/oc-48 fec clock and data recovery ic with integrated limiting amp information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? 2002 analog devices, inc. all rights reserved. features meets sonet requirements for jitter transfer/ generation/tolerance quantizer sensitivity: 4 mv typ adjustable slice level: 100 mv 1.9 ghz minimum bandwidth patented clock recovery architecture loss of signal detect range: 3 mv to 15 mv single reference clock frequency for both native sonet and 15/14 (7%) wrapper rate choice of 19.44 mhz, 38.88 mhz, 77.76 mhz, or 155.52 mhz refclk lvpecl/lvds/lvcmos/lvttl compatible inputs (lvpecl/lvds only at 155.52 mhz) 19.44 mhz oscillator on-chip to be used with external crystal loss of lock indicator loopback mode for high speed test data output squelch and bypass features single-supply operation: 3.3 v low power: 540 mw typical 7 mm 7 mm 48-lead lfcsp applications sonet oc-48, sdh stm-16, and 15/14 fec wdm transponders regenerators/repeaters test equipment backplane applications functional block diagram level detect data retiming fractional divider frequency lock detector loop filter phase shifter phase det. vco xtal osc loop filter qu antizer /n adn2811 slicep/n vcc vee cf1 cf2 lol refsel[0..1] refclkp/n xo1 xo2 refsel rate clkoutp/n data outp/n sdout thradj vref nin pin 2 2 2 2 2 product description the adn2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at oc-48 and oc -48 fec rates. all sonet jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. all specifications are quoted for ?0 c to +85 c ambient temperature, unless otherwise noted. the device is intended for wdm system applications and can be used with either an external reference clock or an on-chip oscillator with external crystal. both the 2.48 gb/s and 2.66 gb/s digital wrapper rate is supported by the adn2811, without any change of reference clock. this device, together with a pin diode and a tia preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver. the receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. the signal detect circuit has hysteresis to prevent chat ter at the output. the adn2811 is available in a compact 7 mm 7 mm 48-lead chip scale package.
rev. a ?2? adn2811especifications (t a = t min to t max , vcc = v min to v max , v ee = 0 v, c f = 4.7 f, slicep = slicen = vcc, unless otherwise noted.) parameter conditions min typ max unit quantizeredc characteristics input voltage range @ pin or nin, dc-coupled 0 1.2 v peak-to-peak differential input 2.4 v input common-mode level dc-coupled. (see figure 22) 0.4 v differential input sensitivity pinenin, ac-coupled 1 , ber = 1 10 e10 410 mv p-p input overdrive figure 4 2 5 mv p-p input offset 500 v input rms noise ber = 1 10 e10 244 v rms quantizereac characteristics upper e3 db bandwidth 1.9 ghz small signal gain differential 54 db s11 @ 2.5 ghz e15 db input resistance differential 100 input capacitance 0.65 pf pulsewidth distortion 2 10 ps quantizer slice adjustment gain slicepeslicen = 0.5 v 0.115 0.200 0.300 v/v control voltage range slicepeslicen e0.8 +0.8 v control voltage range @ slicep or slicen 1.3 vcc v slice threshold offset 1.0 mv level signal detect (sdout) level detect range (see figure 2) r thresh = 2 k 9.4 13.3 18.0 mv r thresh = 20 k 2.5 5.3 7.6 mv r thresh = 90 k 0.7 3.0 5.2 mv response timedc-coupled 0.1 0.3 5 s hysteresis (electrical), prbs 2 23 r thresh = 2 k 5.6 6.6 7.8 db r thresh = 20 k 3.9 6.1 8.5 db r thresh = 90 k 3.2 6.7 9.9 db loss of lock detect (lol) lol response time from f vco error > 1000 ppm 60 s power supply voltage 3.0 3.3 3.6 v power supply current 150 164 215 ma phase-locked loop characteristics pinenin = 10 mv p-p jitter transfer bw oc-48 590 880 khz jitter peaking oc-48 0.025 db jitter generation oc-48, 12 khze20 mhz 0.003 3 ui rms 0.05 0.09 ui p-p jitter tolerance oc-48 (see figure 9) 600 hz 92 3 ui p-p 6 khz 20 3 ui p-p 100 khz 5.5 ui p-p 1 mhz 1.0 3 ui p-p
rev. a adn2811 ?3? parameter conditions min typ max unit cml outputs (clkoutp/n, dataoutp/n) single-ended output swing v se (see figure 3) 300 455 600 mv differential output swing v diff (see figure 3) 600 910 1200 mv output high voltage v oh vcc v output low voltage v ol vcc e 0.6 vcc e 0.3 v rise time 20%e80% 84 150 ps fall time 80%e20% 84 150 ps setup time t s (see figure 1) oc-48 140 ps hold time t h (see figure 1) oc-48 150 ps refclk dc input characteristics input voltage range @ refclkp or refclkn 0 vcc v peak-to-peak differential input 100 mv common-mode level dc-coupled, single-ended vcc/2 v test data dc input characteristics 4 (tdinp/n) cml inputs peak-to-peak differential input voltage 0.8 v lvttl dc input characteristics input high voltage v ih 2.0 v input low voltage v il 0.8 v input current v in = 0.4 v or v in = 2.4 v e5 +5 lvttl dc output characteristics output high voltage v oh , i oh = e2.0 ma 2.4 v output low voltage v ol , i ol = +2.0 ma 0.4 v notes 1 pin and nin should be differentially driven, ac-coupled for optimum sensitivity. 2 pwd measurement made on quantizer outputs in bypass mode. 3 measurement is equipment limited. 4 tdinp/n are cml inputs. if the drivers to the tdinp/n inputs are anything other than cml, they must be ac-coupled. specifications subject to change without notice.
rev. a ?4? adn2811 absolute maximum ratings * supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v minimum input voltage (all inputs) . . . . . . . . . . vee e 0.4 v maximum input voltage (all inputs) . . . . . . . . vcc + 0.4 v maximum junction temperature . . . . . . . . . . . . . . . . . 165 c storage temperature . . . . . . . . . . . . . . . . . . e65 c to +150 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics thermal resistance 48-lead lfcsp, four-layer board with exposed paddle soldered to vcc ja = 25 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adn2811 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package option ADN2811ACP-CML e40?c to +85?c 48-lead lfcsp cp-48 ADN2811ACP-CML-rl e40?c to +85?c 48-lead lfcsp cp-48 tape-reel, 2500 pcs
rev. a adn2811 ?5? pin configuration pin 1 indicator top view adn2811 thradj 1 vcc 2 vee 3 vref 4 pin 5 nin 6 slicep 7 slicen 8 vee 9 lol 10 xo1 11 xo2 12 refclkn 13 refclkp 14 refsel 15 vee 16 tdinp 17 tdinn 18 vee 19 vcc 20 cf1 21 vee 22 refsel1 23 refsel0 24 36 vcc 35 vcc 34 vee 33 vee 32 nc 31 nc 30 rate 29 vee 28 vcc 27 vee 26 vcc 25 cf2 48 loopen 47 vcc 46 vee 45 sdout 44 bypass 43 vee 42 vee 41 clkoutp 40 clkoutn 39 squelch 38 dataoutp 37 dataoutn nc = no connect pin function description pin no. mnemonic type description 1 thradj ai los threshold setting resistor 2, 26, 28, pad vcc p analog supply 3, 9, 16, 19, 22, 27, 29, vee p ground 33, 34, 42, 43, 46 4 vref ao internal v ref voltage. decouple to gnd with 0.1 f capacitor. 5 pin ai differential data input. cml. 6n in ai differential data input. cml. 7 slicep ai differential slice level adjust input 8 slicen ai differential slice level adjust input 10 lol do loss of lock indicator. lvttl active high. 11 xo1 ao crystal oscillator 12 xo2 ao crystal oscillator 13 refclkn di differential refclk input. lvttl, lvcmos, lvpecl, lvds (lvpecl, lvds only at 155.52 mhz). 14 refclkp di differential refclk input. lvttl, lvcmos, lvpecl, lvds (lvpecl, lvds only at 155.52 mhz). 15 refsel di reference source select. 0 = on-chip oscillator with external crystal; 1 = external clock source, lvttl. 17 tdinp ai differential test data input 18 tdinn ai differential test data input 20, 47 vcc p digital supply 21 cf1 ao frequency loop capacitor 23 refsel1 di reference frequency select (see table ii) lvttl. 24 refsel0 di reference frequency select (see table ii) lvttl. 25 cf2 ao frequency loop capacitor 30 rate di data rate select (see table i) lvttl. 31, 32 nc di no connect 35, 36 vcc p output driver supply 37 dataoutn do differential retimed data output. cml. 38 dataoutp do differential retimed data output. cml. 39 squelch di disable clock and data outputs. active high. lvttl. 40 clkoutn do differential recovered clock output. cml. 41 clkoutp do differential recovered clock output. cml. 44 bypass di bypass cdr mode. active high. lvttl. 45 sdout do loss of signal detect output. active high. lvttl. 48 loopen di enable test data inputs. active high. lvttl. type: p = power, ai = analog input, ao = analog output, di = digital input, do = digital output
rev. a ? adn2811 t s t h clkoutp data outp/n figure 1. output timing resistance ?k 0 100 10 20 30 40 50 60 70 80 90 18 16 0 mv 8 6 4 2 12 10 14 thradj resistor vs. los trip point figure 2. los comparator trip point programming outp outn v se v cml 0v outp?utn v se v diff figure 3. single-ended vs. differential output specs
rev. a adn2811 ?7? definition of terms maximum, minimum, and typical specifications specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. typical specifications are the mean of the distribution of the data for that parameter. if a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribu- tion. this procedure is intended to tolerate production variations. if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. for all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. input sensitivity and input overdrive sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. the relationship between the logic output of the quantizer and the analog voltage input is shown in figure 4. for sufficiently large positive input voltage, the output is always logic 1; similarly for negative inputs, the output is always logic 0. however, the transitions between output logic levels 1 and 0 are not at precisely defined input voltage levels but occur over a range of input voltages. within this zone of confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. the width of this zone is determined by the input voltage noise of the quantizer. the center of the zone of confusion is the quantizer input offset voltage. input overdrive is the magnitude of signal required to guarantee the correct logic level with 1 10 e10 confidence level. 0 1 input (v p-p) ou tput n oise sensitivity (2 overdrive) o ffset o verdrive figure 4. input sensitivity and input overdrive single-ended vs. differential ac-coupling is typically used to drive the inputs to the quan- tizer. the inputs are internally dc biased to a common-mode potential of ~0.6 v. driving the adn2811 single-ended and observing the quantizer input with an oscilloscope probe at the point indicated in figure 5 shows a binary signal with an average value equal to the common-mode potential and instantaneous values both above and below the average value. it is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the quantizer sensitivity. referring to figure 4, since both positive and negative offsets need to be accommodated, the sensitivity is twice the overdrive. 50 50 qu antizer + adn2811 vref pin scope probe vref 10mv p-p figure 5. single-ended sensitivity measurement 50 50 qu antizer + adn2811 vref nin pin scope probe vref 5mv p-p figure 6. differential sensitivity measurement driving the adn2811 differentially (see figure 6), sensitivity seems to improve by observing the quantizer input with an oscilloscope probe. this is an illusion caused by the use of a single-ended probe. a 5 mv pep signal appears to drive the adn2811 quantizer. however, the single-ended probe mea- sures only half the signal. the true quantizer input signal is twice this value since the other quantizer input is a complemen- tary signal to the signal being observed. los response time the los response time is the delay between the removal of the input signal and the indication of loss of signal (los) at sdout. the los response time of the adn2811 is 300 ns typ when the inputs are dc-coupled. in practice, the time con- stant of the ac-coupling at the quantizer input determines the los response time.
rev. a ?8? adn2811 jitter specifications the adn2811 cdr is designed to achieve the best bit-error-rate (ber) performance and has exceeded the jitter generation, trans- fer, and tolerance specifications proposed for sonet/sdh equipment defined in the telcordia technologies specification. jitter is the dynamic displacement of digital signal edges from their long-term average positions measured in ui (unit inter vals), where 1 ui = 1 bit period. jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. jitter on the recovered clock causes jitter on the retimed data. the following section briefly summarizes the specifications of the jitter generation, transfer, and tolerance in accordance with the telcordia document (gr-253-core, issue 3, september 2000) for the optical interface at the equipment level and the adn2811 performance with respect to those specifications. jitter generation the jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. for oc-48 devices, the band-pass filter has a 12 khz high-pass cutoff frequency with a roll-off of 20 db/ decade and a low-pass cutoff frequency of at least 20 mhz. the jitter generated should be less than 0.01 ui rms and less than 0.1 ui p-p. jitter transfer the jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal versus the fre- quency. this parameter measures the limited amount of jitter on an input signal that can be transferred to the output signal (see figure 7). slope = e20db/decade jitter frequency e khz 0.1 jitter gain e db f c a cceptable range figure 7. jitter transfer curve jitter tolerance the jitter tolerance is defined as the peak-to-peak amplitude of the sinusoidal jitter applied on the input signal that causes a 1 db power penalty. this is a stress test that is intended to ensure no additional penalty is incurred under the operating conditions (see figure 8). figure 9 shows the typical oc-48 jitter tolerance performance of the adn2811. slope = e20db/decade f 0 f 1 f 2 f 3 f 4 jitter frequency e hz 15 1.5 0.15 input jitter amplitude e ui p-p figure 8. sonet jitter tolerance mask modulation frequency e hz 1.00e+01 1.00e+03 1.00e+05 1.00e+07 1.00e+02 1.00e+01 1.00ee01 amplitude e ui p-p 1.00e+00 1.00e+02 1.00e+04 1.00e+06 1.00e+00 adn2811 oc-48 sonet mask figure 9. oc-48 jitter tolerance curve
rev. a adn2811 ?9? theory of operation the adn2811 is a delay-locked and phase-locked loop circuit for clock recovery and data retiming from an nrz encoded data stream. the phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. a high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of the input jitter. a separate phase control loop, comprised of the vco, tracks the low frequency components of the input jitter. the initial frequency of the vco is set by yet a third loop, w hich compares the vco frequency with the reference frequency and sets the coarse tuning voltage. the jitter tracking phase-locked loop controls the vco by the fine tuning control. the delay-locked and phase-locked loops together track the phase of the input data signal. for example, when the clock lags input data, the phase detector drives the vco to a higher frequency and also increases the delay through the phase shifter. both of these actions both serve to reduce the phase error between the clock and data. the faster clock picks up phase while the delayed data loses phase. since the loop filter is an integrator, the static phase error will be driven to zero. another view of the circuit is that the phase shifter implements the zero required for the frequency compensation of a second- order phase-locked loop, and this zero is placed in the feedback path and thus does not appear in the closed-loop transfer func- tion. jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. since this circuit has no zero in the closed- loop transfer, jitter peaking is minimized. the delay-locked and phase-locked loops together simultaneously provide wideband jitter accommodation and narrow-band jitter filtering. the linearized block diagram in figure 10 shows the jitter transfer function, z(s)/x(s) , is a second-order low-pass providing excellent filtering. note the jitter transfer has no zero, unlike an ordinary second-order phase-locked loop. this means that the main pll loop has low jitter peaking (see figure 11), which makes this circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. d/sc psh e(s) x(s) input data z(s) recovered clock d = phase detector gain o = vco gain c = loop integrator psh = phase shifter gain n = divide ratio jitter transfer function z(s) x(s) 1 s 2 + s +1 cn do n psh o = tracking error transfer function e(s) x(s) s 2 s 2 + s + do cn d psh c = o/s figure 10. pll/dll architecture the error transfer, e(s)/x(s) , has the same high-pass form as an ordinary phase-locked loop. this transfer function is free to be optimized to give excellent wideband jitter accommodation since the jitter transfer function, z(s)/x(s) , provides the narrow- band jitter filtering. the delay-locked and phase-locked loops contribute to overall jitter accommodation. at low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. in this case, the vco is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. the amount of low frequency jitter that can be tracked is a function of the vco tuning range. a wider tuning range gives larger accommodation of low fre- quency jitter. the internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range and thus contributes little to the low fre- quency jitter accommodation. at medium jitter frequencies, the gain and tuning range of the vco are not large enough to track the input jitter. in this case, the vco control voltage becomes large and saturates, and the vco frequency dwells at one or the other extreme of its tuning range. the size of the vco tuning range therefore has only a small effect on the jitter accommodation. the delay-locked loop control voltage is now larger, and so the phase shifter takes on the burden of tracking the input jitter. the phase shifter range, in ui, can be seen as a broad plateau on the jitter tolerance curve. the phase shifter has a minimum range of 2 ui at all data rates. the gain of the loop integrator is small for high jitter frequen- cies, so larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. large phase errors at high jitter frequencies cannot be tolerated. in this region, the gain of the integrator determines the jitter accommodation. since the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. at the highest frequencies, the loop gain is very small and little tuning of the phase shifter can be expected. in this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. the jitter accommodation is roughly 0.5 ui in this region. the corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 5 mhz. jitter peaking in ordinary pll adn2811 z(s) x(s) f (khz) jitter gain (db) o n psh d psh c figure 11. jitter response vs. conventional pll
rev. a ?10? adn2811 functional description clock and data recovery the adn2811 will recover clock and data from serial bit streams at oc-48 as well as the 15/14 fec rates. the data rate is selected by the rate input (see table i). table i. data rate selection rate data rate frequency (mhz) 0 oc-48 2488.32 1 oc-48 fec 2666.06 limiting amplifier the limiting amplifier has differential inputs (pin/nin) that are internally terminated with 50 to an on-chip voltage reference (vref = 0.6 v typically). these inputs are normally ac -coupled, although dc-coupling is possible as long as the input common-mode voltage remains above 0.4 v (see figures 20e22). input offset is factory trimmed to achieve better than 4 mv typical sensitivity with minimal drift. the limiting amplifier can be driven differ entially or single-ended. slice adjust the quantizer slicing level can be offset by 100 mv to mitigate the effect of ase (amplified spontaneous emission) noise by applying a differential voltage input of 0.8 v to slicep/n inputs. if no adjustment of the slice level is needed, slicep/n should be tied to vcc. loss of signal (los) detector the receiver front end level signal detect circuit indicates when the input signal level has fallen below a user adjustable thresh old. the threshold is set with a single external resistor from pin 1, thradj, to gnd. the los comparator trip point versus the resistor value is illustrated in figure 2 (this is only valid for slicep = slicen = vcc). if the input level to the adn2811 drops below the programmed los threshold, sdout (pin 45) will indicate the loss of signal condition with a logic 1. the los response time is ~300 ns by design but will be dominated by the rc time constant in ac-coupled applications. if the los detector is used, the quantizer slice adjust pins must both be tied to vcc. this is to avoid interaction with the los threshold level. note that it is not expected to use both los and slice adjust at the same time; systems with optical amplifiers need the slice adjust to evade ase. however, a loss of signal in an optical link that uses optical amplifiers causes the optical amplifier output to be full-scale noise. under this condition, the los would not detect the failure. in this case, the loss of lock signal will indi- cate the failure because the cdr circuitry will not be able to lock onto a signal that is full-scale noise. reference clock there are three options for providing the reference frequency to the adn2811: differential clock, single-ended clock, or crystal oscillator. see figures 12e14 for example configurations. the adn2811 can accept any of the following reference clock frequencies: 19.44 mhz, 38.88 mhz, 77.76 mhz at lvttl/ lvcmos/lvpecl/lvds levels or 155.52 mhz at lvpecl/ lvds levels via the refclkn/p inputs, independent of data rate. the input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mv (e.g., lvpecl or lvds) or a standard single-ended low volt- age ttl input, providing maximum system flexibility. the appropriate division ratio can be selected using the refsel0/1 pins, according to table ii. phase noise and duty cycle of the reference clock are not critical and 100 ppm accuracy is suffi cient. 100k 100k bu ffer adn2811 vcc/2 refclkn refclkp crystal oscillator xo1 xo2 vcc vcc vcc refsel figure 12. differential refclk configuration out 100k 100k bu ffer adn2811 vcc/2 refclkp crystal oscillator xo1 xo2 vcc vcc vcc refsel clk osc vcc refclkn nc figure 13. single-ended refclk configuration 100k 100k bu ffer adn2811 vcc/2 refclkn refclkp crystal oscillator xo1 xo2 refsel nc 19.44mhz vcc figure 14. crystal oscillator configuration
rev. a adn2811 ?11? an on-chip oscillator to be used with an external crystal is also provided as an alternative to using the refclkn/p inputs. details of the recommended crystal are given in table iii. table ii. reference frequency selection applied reference refsel refsel[1..0] frequency (mhz) 10 0 19.44 10 1 38.88 11 0 77.76 11 1 155.52 0x x refclkp/n inactive. use 19.44 mhz xtal oscillator on pins xo1, xo2 (pull refclkp to vcc). table iii. required crystal specifications parameter value mode series resonant frequency/overall stability 19.44 mhz 100 ppm frequency accuracy 100 ppm temperature stability 100 ppm aging 100 ppm esr 20 max recommended manufacturer: raltron (305) 593-6033 part number: h10s-19.440-s-ext refsel must be tied to vcc when the refclkn/p inputs are active or tied to vee when the oscillator is used. no connection between the xo pin and refclk input is neces sary (see figures 12e14). note that the crystal should operate in series resonant mode, which renders it insensitive to external parasitics. no trimming capacitors are required. lock detector operation the lock detector monitors the frequency difference between the vco and the reference clock and deasserts the loss of lock signal when the vco is within 500 ppm of center frequency (see figure 15). this enables the phase loop, which pulls the vco frequency in the remaining amount and also acquires phase lock. once locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and con- trol returns to the frequency loop, which will reacquire and maintain a stable clock signal at the output. 1000 500 0 500 1000 f vco error ( ppm) lol 1 figure 15. transfer function of lol the frequency loop requires a single external capacitor between cf1 and cf2. the capacitor specification is given in table iv. table iv. recommended c f capacitor specification parameter value temperature range e40 c to +85 c capacitance >3.0 f leakage <80 na rating >6.3 v recommended manufacturer: murata electronics (770) 436-1300 part number: grm32rr71c475lc01 squelch mode when the squelch input is driven to a ttl high state, both the clock and data outputs are set to the zero state to suppress downstream processing. if desired, this pin can be directly driven by the los detecto r output, sdout. if the squ elch func- tion is not required, the pin should be tied to vee. test modes: bypass and loopback when the bypass input is driven to a ttl high state, the quantizer output is connected directly to the buffers driving the data out pins, thus bypassing the clock recovery circuit (see figure 16). this feature can help the system to deal with nonstandard bit rates. the loopback mode can be invoked by driving the loopen pin to a ttl high state, which facilitates system diagnostic test- ing. this will connect the test inputs (tdinp/n) to the clock and data recovery circuit (per figure 16). the test inputs have internal 50 terminations and can be left floating when not in use. tdinp/n are cml inputs and can only be dc-coupled when being driven by cml outputs. the tdinp/n inputs must be ac-coupled if being driven by anything other than cml out- puts. bypass and loopback modes are mutually exclusive. only one of these modes can be used at any given time. the adn2811 will be put into an indeterminate state if both bypass and loopen pins are set to logic 1 at the same time.
?2 rev. a adn2811 applications information pcb design guidelines proper rf pcb design techniques must be used for optimal performance. power supply connections and ground planes use of one low impedance ground plane to both analog and digital grounds is recommended. the vee pins should be sol- dered directly to the ground plane to reduce series inductance. if the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias may be used in parallel to reduce the series inductance, especially on pins 33 and 34, which are the ground returns for the output buffers. use of a 10 f electrolytic capacitor between vcc and gnd is recommended at the location where the 3.3 v supply enters the pcb. use of 0.1 f and 1 nf ceramic chip capacitors should be placed between ic power supply vcc and gnd as close as possible to the adn2811 vcc pins. again, if connections to the supply and ground are made through vias, the use of multiple vias in parallel will help to reduce series inductance, especially on pins 35 and 36, which supply power to the high speed clkoutp/n and dataoutp/n output buffers. refer to the schematic in fi g ure 17 for recommended connections. transmission lines use of 50 ? transmission lines are required for all high fre- quency input and output signals to minimize reflections, including pin, nin, clkoutp, clkoutn, dataoutp, and dataoutn (also refclkp, refclkn for a 155.2 mhz refclk). it is also recommended that the pin/nin input traces are matched in length and that the 50 50 qu antizer + adn2811 vref nin pin 50 50 vcc tdinp/n loopen bypass cdr retimed data clk 0 1 10 data outp/n clkoutp/n squelch from qu antizer output figure 16. test modes clkoutp/n and dataoutp/n output traces are matched in length. all high speed cml outputs, clkoutp/n and dataoutp/n, also require 100 ? back termination chip resistors connected betw een the output pin and vcc. these resistors should be placed as close as possible to the output pins. these 100 ? resistors are in parallel with on-chip 100 ? termination resistors to create a 50 ? back termination (see figure 18). the high speed inputs, pin and nin, are internally terminated with 50 ? to an internal reference voltage (see figure 19). a 0.1 f capacitor is recommended between vref, pin 4, and gnd to provide an ac ground for the inputs. as with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. soldering guidelines for chip-scale package the lands on the 48-lead lfcsp are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this will ensure that the solder joint size is maximized. the bottom of the chip- scale package has a central exposed pad. the pad on the printed circuit board should be at least as large as this exposed pad. the user must connect t he exposed pad to analog vcc. if vias are used, they should be incorporated into the pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via.
rev. a adn2811 ?13? adn2811 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 1nf 0.1 f 1nf 0.1 f thradj vcc vee vref pin nin slicep slicen vee lol xo1 xo2 vcc c in 50 r th 1nf 0.1 f 0.1 f 50 tia vcc 19.44mhz c refclkn refclkp refsel vee tdinp tdinn vee vcc cf1 vee refsel1 refsel0 nc vcc nc nc c c 4.7 f (see table iv for specs) 1nf 0.1 f vcc vcc vcc vee vee nc nc rate vee vcc vee vcc cf2 vcc loopen vcc vee sdout bypass vee vee clkoutp clkoutn squelch data outp data outn c 1nf 0.1 f 10 f vcc 50 transmission lines clkoutp clkoutn data outp data outn vcc 4 100 exposed pad tied off to vcc plane with vias 1nf 0.1 f c vcc figure 17. typical application circuit 100 50 adn2811 50 50 100 vcc 100 100 vcc 0.1 f 0.1 f 50 v term v term figure 18. ac-coupled output configuration 50 50 adn2811 0.1 f nin pin c in c in 50 tia vref vcc 50 figure 19. ac-coupled input configuration
?14? rev. a adn2811 choosing ac-coupling capacitors the choice of ac-coupling capacitors at the input (pin, nin) and output (dataoutp, dataoutn) of the adn2811 must be chosen carefully. when choosing the capacitors, the time constant formed with the two 50 resistors in the signal path must be considered. when a large number of con secutive identical digits (cids) are applied, the capacitor voltage can drop due to baseline wander (see figure 20), causing pattern dependent jitter (pdj). for the adn2811 to work robustly at oc-48, a minimum capacitor of 0.1 f to pin/nin and 0.1 f on dataoutp/ dataoutn should be used. this is based on the assumption that 1000 cids must be tolerated and that the pdj should be limited to 0.01 ui p-p. 50 adn2811 nin pin 50 v ref c in c in v2 v1 v2b v1b tia limamp cdr c out c out data outp data outn + 4 3 2 1 v1 v1b v2 v2b v diff v diff = v2ev2b vth = adn2811 quantizer threshold v ref vth notes 1. during data paterns with high transition density, differential dc voltage at v1 and v2 is zero. 2. when the output of the tia goes to cid, v1 and v1b are driven to different dc levels. v2 and v2b discharge to the v ref level, which effectively introduces a differential dc offset across the ac-coupling capacitors. 3. when the burst of data starts again, the differential dc offset across the ac-coupling capacitors is applied to the input le vels, causing a dc shift in the differential input. this shift is large enough such that one of the states, either high or low depen ding on the levels of v1 and v1b when the tia went to cid, is cancelled out. the quantizer will not recognize this as a valid state. 4. the dc offset slowly discharges until the differential input voltage exceeds the sensitivity of the adn2811. the quantizer wi ll be able to recognize both high and low states at this point. figure 20. example of baseline wander dc-coupled application the inputs to the adn2811 can also be dc-coupled. this may be necessary in burst mode applications where there are long periods of cids and baseline wander cannot be tolerated. if the inputs to the adn2811 are dc-coupled, care must be taken not to violate the input range and common-mode level requirements of the adn2811 (see figures 21e23). if dc-coupling is required, and the output levels of the tia do not adhere to the levels shown in figures 22 and 23, then there will need to be level shifting and/or an attenuator between the tia outputs and the adn2811 inputs.
rev. a adn2811 ?15? 50 50 adn2811 0.1 f nin pin 50 tia vref vcc 50 figure 21. adn2811 with dc-coupled inputs lol toggling during loss of input data if the input data stream is lost due to a break in the optical link (or for any reason), the clock output from the adn2811 will stay within 1000 ppm of the vco center frequency as long as there is a valid reference clock. the lol pin will toggle at a rate of several khz. this is because the lol pin will toggle between a logic 1 and a logic 0 while the frequency loop and phase loop swap control of the vco. the chain of events are as follows: ? the adn2811 is locked to the input data stream; lol = 0. ? the input data stream is lost due to a break in the link. the vco frequency drifts until the frequency error is greater than 1000 ppm. lol is asserted to a logic 1 as control of the vco is passed back to the frequency loop. ? the frequency loop pulls the vco to within 500 ppm of its center frequency. control of the vco is passed back to the phase loop and lol is deasserted to a logic 0. ? the phase loop tries to acquire, but there is no input data present so the vco frequency drifts. ? the vco frequency drifts until the frequency error is greater than 1000 ppm. lol is asserted to a logic 1 as control of the vco is passed back to the frequency loop. this process is repeated until a valid input data stream is re-established. v cm = 0.4v min ( dc-coupled) v se = 5mv min pin nin v p-p = pin e nin = 2 v se = 10mv at sensitivity inpu t (v) figure 22. minimum allowed dc-coupled input levels input (v) pin nin v cm = 0.6v ( dc-coupled) v se = 1.2v max v p-p = pin e nin = 2 v se = 2.4v max figure 23. maximum allowed dc-coupled input levels
c03019??2/02(a) printed in u.s.a. ?6 adn2811 rev. a outline dimensions 48-lead frame chip scale package [lfcsp] 7 mm 7 mm body (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 1.00 max 0.65 nom 1.00 0.90 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 sq seating plane compliant to jedec standards mo-220-vkkd-2 revision history location page 1 2 /02?ata sheet changed from rev. 0 to rev. a. change to functional description reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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