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publication# 18459 rev. b amendment /0 issue date: june 1995 www: 6/7/95 this document contains information on a product under development at advanced micro devices, inc. the information is intended to help you evaluate this product. amd ? reserves the right to change or discontinue work on this proposed product without notice. AM29040 high-performance risc microprocessor with instruction and data caches advanced micro devices preliminary ? distinctive characteristics full 32-bit architecture 66.8 vax mips sustained at 50 mhz 4-kbyte, two-way set-associative data cache 8-kbyte, two-way set-associative instruction cache two cycle 32-bit multiplier for fast integer math; three-cycle multiply accumulate (mac) function 32-entry on-chip memory management unit with dual translation look-aside buffers multiprocessor support instruction/data parity on external bus with mmu control of parity checking on page basis data cache control on page basis mmu-programmable 16- or 32-bit data bus width on page basis streamlined system interface for simplified, high-frequency operation 33-, 40-, and 50-mhz cpu operating frequencies scalable clocking ? feature with optional clock doubling digital delay-locked loop (dll) feature for accurate clocking control 3.3-v operation with 5-v-tolerant i/o low-power snooze and sleep modes fully static 8-, 16-, or 32-bit rom interface burst-mode and page-mode access support pin and bus compatibility with am29030 ? and am29035 ? microprocessors binary compatibility with all 29k ? family microprocessors and microcontrollers cmos technology/ttl-compatible 192 general-purpose registers fully pipelined three-address instruction architecture 4-gbyte virtual address space with demand paging on-chip timer facility hardware instruction and data breakpoints for advanced debugging support traceable cache ? instruction and data cache tracing feature ieee std 1149.1-1990 (jtag) compliant standard test access port and boundary scan architecture implementation AM29040 microprocessor block diagram am29000 cpu 32 x 32 multiplier mmu addr inst data addr inst/data 8-kbyte instruction cache (2x1kx32) bits 4-kbyte data cache (2x512x32) bits
amd p r e l i m i n a r y 2 AM29040 microprocessor table of contents distinctive characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general description 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . customer service 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ordering information 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . related amd products 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29k family development support products 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . third-party development support products 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . key features and benefits 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . performance overview 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . connection diagrams 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145-lead pga 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pga pin designations by pin number 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pga pin designations by pin name 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144-lead pqfp 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pqfp pin designations by pin number 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pqfp pin designations by pin name 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic symbol 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin descriptions 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ranges 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc characteristics over commercial operating range 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capacitance 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching characteristics over commercial operating range 22 . . . . . . . . . . . . . . . . . . . . . . . . . switching waveforms 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . switching test circuit 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal characteristics 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical dimensions 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cgm 145 pin grid array 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pdr 144 plastic quad flat pack 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
amd p r e l i m i n a r y 3 AM29040 microprocessor general description the AM29040 ? risc microprocessor is a high-perfor- mance, general-purpose 32-bit microprocessor imple- mented in cmos technology. designed to extend the price/performance of the 29k family, the AM29040 mi- croprocessor provides an easy upgrade path for am29035 and am29030 microprocessor-based prod- ucts that require enhanced integer performance. the on- chip data and instruction caches, hardware multiplier, enhanced mmu, and speed upgrades of the AM29040 microprocessor provide the embedded systems design- er with increasing levels of performance and software compatibility throughout a range of products. the AM29040 microprocessor was designed to meet the common requirements of network and color printer ap- plications and other embedded applications such as raid disk controllers, local area network (lan) intelli- gent hubs, multimedia controllers, and interactive tv. high-speed telecommunications and networking ap- plications such as central office switches, low-end pbxs, and wireless lans will benefit from the data parity, high throughput, the enhanced mmu, and the high-speed fea- tures of the AM29040 microprocessor. high-performance integer applications, especially those that share the bus with other intelligent peripher- als, are strong candidates for AM29040 microproces- sor-based designs. coupled with hardware and software development tools from amd and the amd fusion29k partners, the AM29040 microprocessor provides the embedded systems designer with the cost and performance edge required in today's market- place. for a complete description of the technical fea- tures, programming interface, and instruction set, please refer to the AM29040 microprocessor user's manual (order #18458). the AM29040 microprocessor is available in a 145-lead pin grid array (pga) package and a 144-pin plastic quad flat pack (pqfp) package. the pga pack- age has 117 signal pins, 26 power and ground pins, 1 alignment/ground pin, and 1 reserved pin. the pqfp package has 117 signal pins, 26 power and ground pins, and 1 reserved pin. customer service amd's customer service network includes u.s. offices, international offices, and a customer training center. ex- pert technical assistance is available from amd's world- wide staff of field application engineers and factory support staff. hotline, e-mail, and bulletin board support for answers to technical questions, amd provides a toll- free number for direct access to our engineering support staff. for overseas customers, the easiest way to reach the engineering support staff with your questions is via fax with a short description of your question. amd 29k family customers also receive technical support through electronic mail. this worldwide service is avail- able to 29k family product users via the international in- ternet e-mail service. also available is the amd bulletin board service, which provides the latest 29k family product information, including technical information and data on upcoming product releases. engineering support staff (800) 292-9263, ext. 2 toll-free for u.s. 0031-11-1163 toll-free for japan (512) 602-4118 direct dial worldwide 44-(0)256-811101 u.k. and europe hotline (512) 602-5031 fax epd.support@amd.com e-mail bulletin board (800) 292-9263, ext. 1 toll-free for u.s. (512) 602-7604 direct dial worldwide documentation and literature a simple phone call gets you free 29k family informa- tion, such as data books, user's manuals, data sheets, application notes, the fusion29k partner solutions catalog and newsletter, and other literature. interna- tionally, contact your local amd sales office for com- plete 29k family literature. literature request (800) 292-9263, ext. 3 toll-free for u.s. (512) 602-5651 direct dial worldwide (512) 602-7639 fax for u.s. (800) 222-9323, option 1 amd facts-on-demand ? fax information service toll-free for u.s.
amd p r e l i m i n a r y 4 AM29040 microprocessor ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. AM29040 40 c temperature range c = commercial (t c =0 c to +85 c) package type g = 145-lead pin grid array without heat sink (cgm145) k = 144-lead pqfp (pdr144) speed option device number/description AM29040 risc microprocessor with 8 kbyte of instruction cache and 4 kbyte of data cache valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM2904040 kc\w k AM2904033 gc 33 = 33 mhz 40 = 40 mhz 50 = 50 mhz blank = for pga package only \w = for pqfp package only: trimmed/formed leads \w pqfp lead forming AM2904033 AM2904040 AM2904050 valid combinations AM2904050
amd p r e l i m i n a r y 5 AM29040 microprocessor related amd products 29k family devices product description am29000 32-bit risc microprocessor am29005 ? low-cost 32-bit risc microprocessor with no mmu and no branch target cache am29030 ? 32-bit risc microprocessor with 8-kbyte instruction cache am29035 ? 32-bit risc microprocessor with 4-kbyte instruction cache am29050 ? 32-bit risc microprocessor with on-chip floating point am29200 ? 32-bit risc microcontroller am29202 ? low-cost 32-bit risc microcontroller with ieee-1284-compliant parallel interface am29205 ? low-cost 32-bit risc microcontroller am29240 ? 32-bit risc microcontroller with 4-kbyte instruction cache and 2-kbyte data cache am29245 ? low-cost 32-bit risc microcontroller with 4-kbyte instruction cache am29243 ? 32-bit data risc microcontroller with instruction and data caches and dram parity 29k family development support products contact your local amd representative for information on the complete set of development support tools. the following software and hardware development products are available on several hosts: optimizing compilers for common high-level languages assembler and utility packages source- and assembly-level software debuggers target-resident development monitors simulators demonstration and evaluation boards third-party development support products the fusion29k program of partnerships for application solutions provides the user with a vast array of products designed to meet critical time-to-market needs. prod- ucts and solutions available from the amd fusion29k partners include silicon products emulators hardware and software debuggers modeling/simulation tools software development tools real-time operating systems (rtos) application-specific hardware and software board-level products manufacturing and prototyping support custom support training
amd p r e l i m i n a r y 6 AM29040 microprocessor key features and benefits the AM29040 microprocessor extends the family of two-bus risc processors based on amd's 29k archi- tecture, providing powerful performance upgrades to the am29030 and am29035 microprocessors. the product designer can choose from among several differ- ent design strategies to gain significant cost and perfor- mance improvements. upgrading to maximal performance efor exam- ple, the clock-doubling feature on a 50-mhz AM29040 microprocessor can be configured to de- liver up to twice the performance of a 25-mhz am29030 microprocessor at a small increase in sys- tem cost, keeping the external bus speed and memory system the same. upgrading to minimize system cost efor exam- ple, the clock-doubling feature on a 40-mhz AM29040 microprocessor can be combined with a reduction in external bus speed to deliver up to 77% more performance than a 25-mhz am29030 micro- processor, at similar or less system cost (by reducing the cost of the memory system). specific performance enhancements include an on-chip data cache, a two-cycle hardware multiplier, an en- hanced mmu, speed upgrades, and multiprocessing features. general system enhancements include on- chip support for parity generation and checking, low- power snooze and sleep modes, and expanded clocking control. debug and test enhancements include hardware instruction and data breakpoints, as well as instruction and data cache tracing. on-chip caches the AM29040 microprocessor incorporates an 8-kbyte, two-way set-associative instruction cache that supplies most processor instructions without wait states at the in- ternal processor frequency. for best performance, the instruction cache supports critical-word-first reloading with fetch-through, so that the processor receives the required instruction and the pipeline restarts with mini- mum delay. the instruction cache has a valid bit per word to minimize reload overhead and pipeline stalls. all instruction cache array elements are visible to software for testing and preload. the AM29040 microprocessor also incorporates a 4-kbyte, two-way set-associative data cache. cache- able and noncacheable regions are specified by the mmu. the data cache is physically addressed and oper- ates in the write-back stage of the processor pipeline, so that loaded data is available to the second instruction following the load without causing a pipeline stall. the data cache uses a copy-back policy with no-write al- location. this reduces the amount of time the processor waits on data that is not in the cache. as an option, re- gions of memory can use a write-through policy, as con- trolled by the mmu. a cache consistency protocol facilitates the implementation of multiprocessing sys- tems and of input/output or dma to cacheable memory. byte, half-word, and word reads and writes are sup- ported. all data cache array elements are visible to soft- ware for testing and preload. two-cycle multiplier the AM29040 microprocessor incorporates a full com- binatorial multiplier that accepts two 32-bit input oper- ands and produces a 32-bit result in two cycles. high-performance multiplication benefits imaging, sig- nal processing, and state modeling applications. scalable clocking technology with expanded clocking control the AM29040 microprocessor offers expanded clock- ing control features that aid in the design of low-cost, high-frequency designs. these features include a full or double-speed clocking option and a highly precise clock control mechanism. clock doubling allows the processor to run at twice the frequency of the external bus. for example, the inter- face can operate at 25 mhz, while the processor oper- ates at 50 mhz. this feature allows the use of slower, lower-cost memory without significant degradation of processor performance. a 40-mhz processor could be combined with a 20-mhz memory system with only a slight loss in performance relative to a full-speed bus. another advantage is that system performance can be upgraded by simply replacing the processor with a high- er-speed processor. for example, a processor can be re- placed with a faster processor while utilizing the existing memory system, running at half-speed if necessary. the AM29040 microprocessor uses an extremely pre- cise digital version of a phase-locked loop to control fre- quency multiplication and phase generation for the input clock. this allows the processor to use oscillators with duty cycles of 30/70 to 70/30. relaxed timing specifica- tions reduce the cost and complexity of the external sys- tem design. high-frequency operation is further simplified through the use of a hardwired wait state, which is enforced dur- ing the initial cycle of all simple data accesses and the initial cycle of a burst-mode access. the main benefit of this approach is that the address and data pins are not required to change state during the same cycle. this reduces electrical noise and provides great benefits for high-frequency designs.
amd p r e l i m i n a r y 7 AM29040 microprocessor parity the AM29040 microprocessor provides byte parity checking and generation on the instruction/data bus. when parity is supplied by the system, the processor checks for valid parity during the cycle after the data is received, and parity is checked only for those bytes ac- tually involved in the transfer. the AM29040 micropro- cessor allows parity errors on instruction and data accesses to be differentiated from one another. enhanced memory management unit the AM29040 microprocessor provides an enhanced memory-management unit (mmu) for translating virtual addresses into physical addresses. the page size for translation ranges from 1 kbyte to 16 mbyte in powers of four. the AM29040 microprocessor has dual 16-entry tlbs, each capable of mapping pages of different size. in addition to the traditional functions, the AM29040 mi- croprocessor's mmu includes several features that en- hance the performance of the entire system. parity checking ethe mmu allows the designer to define which parts of memory are checked for parity. data cacheability by page ethough the data cache uses a copy-back policy for most blocks, indi- vidual virtual pages can be marked as write-through by the mmu. the mmu also allows pages to be marked as noncacheable, so that all accesses to the page are performed on the external bus. programmable bus sizing eusing the mmu, the AM29040 processor's instruction/data bus can be dynamically programmed to be either 16 or 32 bits wide for data transfers. this enables the AM29040 microprocessor to write either 16-bit or 32-bit devices. the processor automatically performs multiple 16-bit writes when writing more than 16 bits to a 16-bit external device. this unique feature provides a flexible interface to low-cost memory, as well as a convenient, flexible upgrade path. for example, a system can start with a 16-bit memory design and can subsequently im- prove performance by migrating to a 32-bit memory design. of particular advantage is the ability to add memory in half-megabyte increments. this provides significant cost savings for applications that do not require larger memory upgrades. low-power snooze and sleep modes within the wait mode, the AM29040 microprocessor of- fers two special standby modes for low power dissipa- tion: snooze mode and sleep mode. the snooze mode has slightly higher power dissipation than sleep mode, but is invoked automatically without external hardware, whereas sleep mode requires external hardware to gate off clocks. because the processor's internal clocks are disabled, the power dissipated in snooze mode is only that associated with internal leakage, trap and interrupt syn- chronization, and on-chip clock generation. minimum power dissipation is achieved in sleep mode by holding the input clock high or low. in this case, the power dissi- pated is only that associated with internal leakage. both snooze and sleep modes can be used by product de- signers interested in gaining the u.s. environmental protection agency's aenergy staro certification. narrow read interface the AM29040 microprocessor can be connected to 8-, 16-, or 32-bit memories. if the data size accessed is larg- er than that supported by memory, the processor auto- matically generates the necessary sequencing to perform multiple reads. this ability to perform narrow reads is particularly useful for a rom interface. using narrow reads, the processor can execute a bootstrap program from a small boot rom to download the application program into ram. this not only allows the use of low-cost roms, it also conserves board space and allows easy revision of ap- plication code. streamlined system interface the AM29040 microprocessor employs a streamlined, two-bus external interface, which comprises an ad- dress bus and an instruction/data bus. the large on- chip instruction and data caches of the AM29040 microprocessor satisfy the instruction and data band- width requirements. this allows the use of lower-per- formance and lower-cost memory, provides a reduction in the memory-system parts count, and re- duces the board area required for the memory system. in addition, the simplified design requirements reduce development costs. pin, bus, and binary compatibility compatibility within a processor family is critical for achieving a rational, easy upgrade path. the AM29040 microprocessor provides compatibility on several lev- els. the processors are pin, bus, and binary compatible with the am29030 and am29035 processors. pin and bus compatibility ensures a convenient upgrade path, without hardware or software redesign, for embedded applications. in addition, the processors are binary com- patible with the existing members of the 29k family (the am29000, am29005, and am29050 microprocessors, and the am29200, am29202, am29205, am29240, am29243, and am29245 microcontrollers).
amd p r e l i m i n a r y 8 AM29040 microprocessor wide range of price/performance points to reduce design costs and time-to-market, one basic system design can be used as the foundation for an en- tire product line. using amd's two-bus processors, the am29030, am29035, and AM29040 microprocessors, numerous implementations of a product at various price/performance levels can be derived with minimum time, effort, and cost. the AM29040 microprocessor allows the product de- signer to significantly expand the performance range of a product line through its on-chip caches, extended mmu, hardware multiplier, and speed upgrades. pro- cessors can be upgraded without hardware and soft- ware redesign and combined with high-performance or mid-performance memory. the narrow read interface accommodates numerous rom configurations. in addi- tion, programmable bus sizing allows AM29040 micro- processor-based systems to support memory upgrades in half-megabyte increments. this provides significant cost savings for applications that do not require larger memory upgrades. complete development and support environment a complete development and support environment is vi- tal for reducing a product's time-to-market. advanced micro devices has created a standard development en- vironment for the 29k family of processors. in addition, the fusion29k program's third-party support organiza- tion provides the most comprehensive customer/part- ner program in the embedded processor market. advanced micro devices offers a complete set of hard- ware and software tools for design, integration, debug- ging, and benchmarking. these tools, which are available now for the 29k family, include the following: software development kit, including the high c 29k optimizing c compiler with assembler, linker, ansi li- brary functions, 29k family architectural simulator, and minimon29k debug monitor xray29k ? source-level debugger a complete family of demonstration and develop- ment boards in addition, advanced micro devices has developed a standard host interface (hif) specification for operating system services, the universal debug interface (udi) for seamless connection of debuggers to ices and tar- get hardware, and extensions for the unix common ob- ject file format (coff). this support is augmented by an engineering hotline, an on-line bulletin board, and field application engineers. debugging and testing the AM29040 microprocessor provides debugging and testing features at both the software and hard- ware levels. software debugging is facilitated by the instruction trace facility and instruction breakpoints. instruction tracing is accomplished by forcing the processor to trap after each instruction has been executed. instruction breakpoints are implemented by the halt instruction or by a software trap. the AM29040 microprocessor provides two hardware instruction breakpoints and one hardware data break- point that can suspend execution of the current pro- gram on a specified instruction or data access. suspension either forces a trace trap or forces a halt if the system is under emulator control. the processor provides several additional features to assist system debugging and testing. test/development interface ethis interface is composed of a group of pins that indicate the state of the processor and control the operation of the processor. traceable cache feature ethis feature permits a hardware-development system to track accesses to the on-chip caches, permitting a high level of visi- bility into processor operation. ieee std 1149.1-1990 (jtag) compliant stan- dard test access port and boundary-scan ar- chitecture ethis feature provides a scan interface for testing processor and system hardware in a pro- duction environment. it contains extensions that al- low a hardware-development system to control and observe the processor without interposing hard- ware between the processor and system.
amd p r e l i m i n a r y 9 AM29040 microprocessor performance overview the AM29040 microprocessor provides a significant margin of performance over other processors in its class, since the majority of processor features were de- fined for the maximum achievable performance at a rea- sonable cost. this section describes the features of the AM29040 microprocessor from the point of view of sys- tem performance. instruction timing the AM29040 microprocessor uses an arithmetic/logic unit, a field shift unit, and a prioritizer to execute most instructions. each of these is organized to operate on 32-bit operands and provide a 32-bit result. the performance degradation of load and store opera- tions is minimized in the AM29040 microprocessor by overlapping them with instruction execution, by taking advantage of pipelining, by using the on-chip data cache, and by organizing the flow of external data into the processor so that the impact of external accesses is minimized. pipelining instruction operations are overlapped with instruction fetch, instruction decode, operand fetch, and result write-back to the register file. pipeline forwarding logic detects pipeline dependencies and routes data as re- quired, avoiding delays that might arise from these dependencies. pipeline interlocks are implemented by processor hard- ware. except for a few special cases, it is not necessary to rearrange programs to avoid pipeline dependencies, although this is sometimes desirable for performance. on-chip instruction and data caches on-chip instruction and data caches satisfy most proces- sor fetches without wait states, even when the processor operates at twice the system frequency. the caches are pipelined for best performance. the reload policies mini- mize the amount of time spent waiting for reload while op- timizing the benefit of locality of reference. burst-mode and page-mode memories the AM29040 microprocessor directly supports burst- mode memories. the burst-mode memory supplies instructions at the maximum bandwidth, without the complexity of an external cache or the performance degradation due to cache misses. the processor can also use the page-mode capability of common drams to improve the access time in cases where page-mode accesses can be used. this is partic- ularly useful in very low-cost systems with 16-bit-wide drams, where the dram must be accessed twice for each 32-bit operand. instruction set overview all 29k family members employ a three-address instruction set architecture. the compiler or assembly- language programmer is given complete freedom to al- locate register usage. there are 192 general-purpose registers, allowing the retention of intermediate calcula- tions and avoiding needless data destruction. instruc- tion operands can be contained in any of the general-purpose registers, and the results can be stored into any of the general-purpose registers. the AM29040 microprocessor instruction set contains 117 instructions that are divided into nine classes. these classes are integer arithmetic, compare, logical, shift, data movement, constant, floating point, branch, and miscellaneous. the floating-point instructions are not executed directly, but are emulated by trap handlers. all directly implemented instructions are capable of executing in one processor cycle, with the exception of interrupt returns, loads, stores, and integer multiplies. data formats the AM29040 microprocessor defines a word as 32 bits of data, a half-word as 16 bits, and a byte as 8 bits. the hardware provides direct support for word-integer (signed and unsigned), word-logical, word-boolean, half-word integer (signed and unsigned), and byte data (signed and unsigned). word-boolean data is based on the value contained in the most significant bit of the word. the values true and false are represented by the most significant bit values 1 and 0, respectively. other data formats, such as character strings, are sup- ported by instruction sequences. floating-point formats (single and double precision) are defined for the proces- sors; however, there is no direct hardware support for these formats in the AM29040 microprocessor. protection the AM29040 microprocessor offers two mutually ex- clusive modes of execution, the user and supervisor modes, that restrict or permit accesses to certain pro- cessor registers and external storage locations. memory access protection is provided by the mmu. four protection bits determine whether or not an access is permitted to the page associated with the entry. for the same virtual page, the access authority of programs executing in supervisor mode can be different from the authority of programs executing in user mode. the register file can be configured to restrict accesses to supervisor-mode programs on a bank-by-bank basis.
amd p r e l i m i n a r y 10 AM29040 microprocessor memory management two 16-entry translation look-aside buffers (tlbs) perform virtual-to-physical address translation. a num- ber of enhancements improve the performance of ad- dress translation: pipelining ethe operation of the tlbs is pipelined with other processor operations. task identifiers etask identifiers allow tlb entries to be matched to different processes, so that tlb in- validation is not required during task switches. least-recently used hardware ethis hardware al- lows immediate selection of a tlb entry to be replaced. software reload esoftware reload allows the oper- ating system to use a page-mapping scheme that is best matched to its environment. one of paged-seg- mented, one-level-page mapping, two-level-page mapping, or any other user-defined page-mapping scheme can be supported. because AM29040 mi- croprocessor instructions execute at an average rate of nearly one instruction per cycle, software reload has performance approaching that of hardware tlb reload without imposing restrictions on the system designer. dual-tlb configuration ethis configuration allows system architects to configure one tlb to map most of the system and configure the other tlb to map the exceptions (noncacheable data areas, for example). interrupts and traps when the AM29040 microprocessor takes an interrupt or trap, operation continues from a shadow set of state reg- isters while the interrupted program state registers are frozen. this eliminates the need to save interrupted pro- gram state in many cases. this lightweight interrupt and trap facility greatly improves the performance of tempo- rary interruptions such as tlb reload or other simple op- erating-system calls that require no saving of state information. in cases where the processor state must be saved, the saving and restoring of state information is under the con- trol of software. the methods and data structures used to handle interruptseand the amount of state savedecan be tailored to the needs of a particular system. interrupts and traps are dispatched through a 256-entry vector table that directs the processor to a routine that handles a given interrupt or trap. the vector table can be relocated in memory by the modification of a processor register. there can be multiple vector tables in the sys- tem, though only one is active at any given time. the vector table is a table of pointers to the interrupt and trap handlers, requiring only 1 kbyte of memory. this structure requires that the processors perform a vector fetch every time an interrupt or trap is taken. the vector fetch requires at least three cycles, in addition to the num- ber of cycles required for the basic memory access.
amd p r e l i m i n a r y 11 AM29040 microprocessor connection diagrams 145-lead pga bottom view abcdefghjklmnpq 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 note: pinout observed from pin side of package (pins facing viewer). pin number e4 is defined for emulator access and is not a physical pin on the package (see the AM29040 microprocessors user's manual, order #18458, signal description section).
amd p r e l i m i n a r y 12 AM29040 microprocessor pga pin designations (sorted by pin number) pin no. pin name pin no. pin name pin no. pin name pin no. pin name a-1 id4 c-8 gnd h-14 memclk n-12 v cc a-2 id0 c-9 v cc h-15 div2 n-13 a1 a-3 trst c-10 gnd j-1 id21 n-14 erlya a-4 tdi c-11 v cc j-2 id22 n-15 err a-5 tck c-12 stat1 j-3 gnd p-1 id31 a-6 test c-13 wbc j-13 inclk p-2 a30 a-7 i/d c-14 hit j-14 clkdrv p-3 a27 a-8 io/mem c-15 intr 0 j-15 breq p-4 a24 a-9 bwe 0 d-1 id12 k-1 id23 p-5 a22 a-10 bwe 2 d-2 id11 k-2 id24 p-6 a20 a-11 sup/us d-3 id9 k-3 v cc p-7 a18 a-12 opt0 d-4 ? gnd k-13 gnd p-8 a15 a-13 opt2 d-13 di k-14 req p-9 a13 a-14 mpgm1 d-14 intr 1 k-15 burst p-10 a10 a-15 stat2 d-15 intr 2 l-1 id25 p-11 a8 b-1 id7 e-1 id14 l-2 id26 p-12 a6 b-2 id6 e-2 id13 l-3 v cc p-13 a4 b-3 id3 e-3 gnd l-13 v cc p-14 a2 b-4 id1 e-13 gnd l-14 bgrt p-15 a0 b-5 tdo e-14 intr 3 l-15 pgmode q-1 a31 b-6 tms e-15 trap 1 m-1 id27 q-2 a29 b-7 r/w f-1 id16 m-2 id28 q-3 a25 b-8 warn f-2 id15 m-3 idp2 q-4 a23 b-9 bwe 1 f-3 idp1 m-13 gnd q-5 a21 b-10 bwe 3 f-13 v cc m-14 rdn q-6 a19 b-11 lock f-14 reset m-15 rdy q-7 a17 b-12 opt1 f-15 trap 0 n-1 id29 q-8 a16 b-13 mpgm0 g-1 id18 n-2 id30 q-9 a14 b-14 stat0 g-2 id17 n-3 idp3 q-10 a12 b-15 no connect g-3 v cc n-4 a28 q-11 a11 c-1 id10 g-13 v cc n-5 a26 q-12 a9 c-2 id8 g-14 cntl0 n-6 gnd q-13 a7 c-3 idp0 g-15 cntl1 n-7 v cc q-14 a5 c-4 id5 h-1 id20 n-8 gnd q-15 a3 c-5 id2 h-2 id19 n-9 gnd c-6 v cc h-3 gnd n-10 gnd c-7 gnd h-13 gnd n-11 v cc notes: ? pin number d-4 is the alignment/ground pin and must be electrically connected to ground. pin number e-4 is defined for emulator access and is not a physical pin on the package. (see AM29040 microprocessor user's manual, signal description section.)
amd p r e l i m i n a r y 13 AM29040 microprocessor pga pin designations (sorted by pin name) pin name pin no. pin name pin no. pin name pin no. pin name pin no. a0 p-15 bwe 2 a-10 id11 d-2 opt1 b-12 a1 n-13 bwe 3 b-10 id12 d-1 opt2 a-13 a2 p-14 clkdrv j-14 id13 e-2 pgmode l-15 a3 q-15 cntl0 g-14 id14 e-1 rdn m-14 a4 p-13 cntl1 g-15 id15 f-2 rdy m-15 a5 q-14 di d-13 id16 f-1 reset f-14 a6 p-12 div2 h-15 id17 g-2 req k-14 a7 q-13 erlya n-14 id18 g-1 r/w b-7 a8 p-11 err n-15 id19 h-2 stat0 b-14 a9 q-12 gnd c-7 id20 h-1 stat1 c-12 a10 p-10 gnd c-8 id21 j-1 stat2 a-15 a11 q-11 gnd c-10 id22 j-2 sup/us a-11 a12 q-10 gnd d-4 ? id23 k-1 tck a-5 a13 p-9 gnd e-3 id24 k-2 tdi a-4 a14 q-9 gnd e-13 id25 l-1 tdo b-5 a15 p-8 gnd h-3 id26 l-2 test a-6 a16 q-8 gnd h-13 id27 m-1 tms b-6 a17 q-7 gnd j-3 id28 m-2 trap 0 f-15 a18 p-7 gnd k-13 id29 n-1 trap 1 e-15 a19 q-6 gnd m-13 id30 n-2 trst a-3 a20 p-6 gnd n-6 id31 p-1 v cc c-6 a21 q-5 gnd n-8 idp0 c-3 v cc c-9 a22 p-5 gnd n-9 idp1 f-3 v cc c-11 a23 q-4 gnd n-10 idp2 m-3 v cc f-13 a24 p-4 hit c-14 idp3 n-3 v cc g-3 a25 q-3 i/d a-7 inclk j-13 v cc g-13 a26 n-5 id0 a-2 intr 0 c-15 v cc k-3 a27 p-3 id1 b-4 intr 1 d-14 v cc l-3 a28 n-4 id2 c-5 intr 2 d-15 v cc l-13 a29 q-2 id3 b-3 intr 3 e-14 v cc n-7 a30 p-2 id4 a-1 io/mem a-8 v cc n-11 a31 q-1 id5 c-4 lock b-11 v cc n-12 bgrt l-14 id6 b-2 memclk h-14 warn b-8 breq j-15 id7 b-1 mpgm0 b-13 wbc c-13 burst k-15 id8 c-2 mpgm1 a-14 bwe 0 a-9 id9 d-3 no connect b-15 bwe 1 b-9 id10 c-1 opt0 a-12 notes: ? pin number d-4 is the alignment/ground pin and must be electrically connected to ground. pin number e-4 is defined for emulator access and is not a physical pin on the package. (see AM29040 microprocessor user's manual, signal description section.)
amd p r e l i m i n a r y 14 AM29040 microprocessor connection diagrams (continued) 144-lead pqfp top view pin 1 pin 36 pin 73 pin 108 pin 109 pin 144 pin 37 pin 72
amd p r e l i m i n a r y 15 AM29040 microprocessor pqfp pin designations (sorted by pin number) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 v cc 37 v cc 73 v cc 109 a1 2 gnd 38 gnd 74 gnd 110 a0 3 no connect 39 id5 75 a29 111 erlya 4 stat2 40 id6 76 a28 112 err 5 stat1 41 id7 77 a27 113 rdn 6 stat0 42 id8 78 a26 114 rdy 7 mpgm1 43 id9 79 a25 115 bgrt 8 mpgm0 44 id10 80 a24 116 gnd 9 opt2 45 id11 81 a23 117 v cc 10 opt1 46 id12 82 a22 118 pgmode 11 opt0 47 id13 83 a21 119 burst 12 lock 48 id14 84 a20 120 req 13 sup/us 49 id15 85 a19 121 breq 14 bwe 3 50 v cc 86 a18 122 gnd 15 bwe 2 51 gnd 87 a17 123 inclk 16 bwe 1 52 id16 88 a16 124 v cc 17 bwe 0 53 id17 89 idp2 125 clkdrv 18 v cc 54 id18 90 gnd 126 memclk 19 gnd 55 id19 91 v cc 127 gnd 20 warn 56 id20 92 idp3 128 v cc 21 io/mem 57 id21 93 a15 129 idp0 22 i/d 58 id22 94 a14 130 div2 23 gnd 59 id23 95 a13 131 cntl0 24 v cc 60 gnd 96 a12 132 cntl1 25 r/w 61 v cc 97 a11 133 v cc 26 test 62 idp1 98 a10 134 gnd 27 tck 63 id24 99 a9 135 reset 28 tms 64 id25 100 a8 136 trap 0 29 tdi 65 id26 101 a7 137 trap 1 30 tdo 66 id27 102 a6 138 intr 3 31 trst 67 id28 103 a5 139 intr 2 32 id0 68 id29 104 a4 140 intr 1 33 id1 69 id30 105 a3 141 intr 0 34 id2 70 id31 106 a2 142 di 35 id3 71 a31 107 gnd 143 hit 36 id4 72 a30 108 v cc 144 wbc
amd p r e l i m i n a r y 16 AM29040 microprocessor pqfp pin designations (sorted by pin name) pin name pin no. pin name pin no. pin name pin no. pin name pin no. a0 110 bwe 1 16 id11 45 opt0 11 a1 109 bwe 2 15 id12 46 opt1 10 a2 106 bwe 3 14 id13 47 opt2 9 a3 105 clkdrv 125 id14 48 pgmode 118 a4 104 cntl0 131 id15 49 rdn 113 a5 103 cntl1 132 id16 52 rdy 114 a6 102 di 142 id17 53 reset 135 a7 101 div2 130 id18 54 req 120 a8 100 erlya 111 id19 55 r/w 25 a9 99 err 112 id20 56 stat0 6 a10 98 gnd 2 id21 57 stat1 5 a11 97 gnd 19 id22 58 stat2 4 a12 96 gnd 23 id23 59 sup/us 13 a13 95 gnd 38 id24 63 tck 27 a14 94 gnd 51 id25 64 tdi 29 a15 93 gnd 60 id26 65 tdo 30 a16 88 gnd 74 id27 66 test 26 a17 87 gnd 90 id28 67 tms 28 a18 86 gnd 107 id29 68 trap 0 136 a19 85 gnd 116 id30 69 trap 1 137 a20 84 gnd 122 id31 70 trst 31 a21 83 gnd 127 idp0 129 v cc 1 a22 82 gnd 134 idp1 62 v cc 18 a23 81 hit 143 idp2 89 v cc 24 a24 80 i/d 22 idp3 92 v cc 37 a25 79 id0 32 inclk 123 v cc 50 a26 78 id1 33 intr 0 141 v cc 61 a27 77 id2 34 intr 1 140 v cc 73 a28 76 id3 35 intr 2 139 v cc 91 a29 75 id4 36 intr 3 138 v cc 108 a30 72 id5 39 io/mem 21 v cc 117 a31 71 id6 40 lock 12 v cc 124 bgrt 115 id7 41 memclk 126 v cc 128 breq 121 id8 42 mpgm0 8 v cc 133 burst 119 id9 43 mpgm1 7 warn 20 bwe 0 17 id10 44 no connect 3 wbc 144
amd p r e l i m i n a r y 17 AM29040 microprocessor logic symbol 4 2 2 r/w sup/us mpgm1mpgm0 bwe 3bwe 0 opt2opt0 stat2stat0 pgmode io/mem a31a0 id31id0 memclk intr 3intr 0 cntl1cntl0 reset test inclk trap 1trap 0 2 4 3 3 clkdrv req tdo i/d idp3idp0 4 32 32 wbc hit di AM29040 microprocessor bgrt rdn erlya err warn div2 tck tdi tms trst breq lock burst rdy
amd p r e l i m i n a r y 18 AM29040 microprocessor pin descriptions note: certain outputs are described in the following sec- tion as being three-state or bidirectional. however, all outputs can be placed in a high-impedance state by the test mode. the three-state and bidirectional terminolo- gy in this section is for those outputs that are disabled when an external device is granted the bus. a31a0 address bus (bidirectional, synchronous) the address bus transfers the byte address for all ac- cesses, including burst-mode accesses. breq bus request (output, synchronous) this output indicates that the processor needs to per- form an external access. bgrt bus grant (input, synchronous) this input signals the processor that it has control of the external bus. this signal can be asserted even when breq is not active, in which case the processor still has control of the bus. the processor drives req high when granted an unrequested bus. bwe 3bwe 0 byte write enables (bidirectional, synchronous) these signals are asserted during an external write to indicate which bytes should be written. an assertion of bwe 3 indicates that the most significant byte (corre- sponding to id31id24) should be written, and so on. burst burst request (three-state output, synchronous) this signal indicates a burst-mode access. the ad- dresses for burst-mode accesses appear on the ad- dress bus. the burst signal is provided to aid the implementation of high-bandwidth transfers by inform- ing the external system that the processor can complete an access as often as every cycle after the first cycle. clkdrv enable memclk drive (input) this pin determines whether memclk is an output (clkdrv high) or an input (clkdrv low). the clkdrv pin is the same physical pin as pwrclk on the am29030 microprocessor, and it performs the same function as pwrclk except that it is a logic pin rather than a power-supply pin. cntl1cntl0 cpu control (inputs, asynchronous) these inputs specify the processor mode: load test instruction, step, halt, or normal. di data intervention (bidirectional, synchronous) this output is driven by a bus slave that is the owner of data being requested by the bus master. because it is asserted on a read of cacheable data, and because the data cache is block-oriented, the intervening device drives an entire block of data. div2 divide clock by 2 (input) on the AM29040 microprocessor, memclk is used as the frequency reference for the processor and is always half of inclk. if div2 is high, the processor's operating frequency is the same as the memclk frequency. if div2 is low, the processor's operating frequency is double the memclk frequency. note that div2 on the AM29040 microprocessor operates differently than div2 on the am29030 microprocessor, since the clock- ing scheme is different. erlya early address (input, synchronous) the erlya input is used to request the early transmis- sion of burst-mode addresses for interleaved memories. note that this functionality is different from how erlya operates on the am29030 microprocessor. err error (input, synchronous) this input indicates that an error occurred during the current access. for a read, the processor ignores the instruction/data bus. for a store, the access is termi- nated. in either case, a data access exception or instruction access exception trap can occur. the pro- cessor ignores this signal if there is no pending access. this signal cannot end an access; it is sampled only when the rdy input is active. hit hit (bidirectional, synchronous) this output is driven by a bus slave to indicate that the slave has a cached copy of the data. it is driven for any accesseread or writeethat hits in the slave's data cache. i/d instruction or data access (bidirectional, synchronous) this signal is high during an access to indicate that the access is for an instruction or low to indicate that the ac- cess is for data.
amd p r e l i m i n a r y 19 AM29040 microprocessor id31id0 instruction/data bus (bidirectional, synchronous) the instruction/data bus transfers instructions to, and data to and from, the processor. idp3idp0 instruction/data bus parity (bidirectional, synchronous) these are byte parity bits for the instruction/data bus. idp3 is the parity bit for id3124, idp2 is the parity bit for id 2316, idp1 is the parity bit for id15id8, and ipd0 is the parity bit for id7id0. if parity checking is enabled, the processor drives idp3idp0 with valid parity during writes and expects idp3idp0 to be driven with valid parity during reads of either instructions or data. inclk input clock (input) this is an oscillator input at twice the memclk frequen- cy. it is used only to generate memclk, and is used only if memclk is an output. if memclk is an input, inclk is unused and can be left disconnected. note that inclk on the AM29040 microprocessor operates differently than inclk on the am29030 microprocessor. intr 3intr 0 interrupt requests (inputs, asynchronous) these inputs generate prioritized interrupt requests. the interrupt caused by intr 0 has the highest priority, and the interrupt caused by intr 3 has the lowest prior- ity. the interrupt requests are masked in prioritized or- der by the interrupt mask field in the current processor status register. io/mem input/output or memory access (bidirectional, synchronous) for a data access, this signal indicates whether the ac- cess is to the input/output (i/o) address space (high) or the instruction/data memory address space (low). lock lock (three-state output, synchronous) this output allows the implementation of various bus and device interlocks. it can be active only for the dura- tion of an access or for an extended period of time under control of the lock bit in the current processor status register. the processor does not relinquish the bus (in response to bgrt ) when lock is active. memclk memory clock (input/output) memclk is either a clock output or an input from an ex- ternal clock generator, as determined by the clkdrv pin. memclk is used as the frequency reference for the pro- cessor. note that memclk on the AM29040 micropro- cessor operates differently than memclk on the am29030 microprocessor. if the div2 pin is high, the processor frequency is the frequency of memclk. if div2 is low, the processor fre- quency is twice the frequency of memclk and is achieved by frequency doubling. mpgm1mpgm0 mmu programmable (bidirectional, synchronous) these outputs reflect the value of the two pgm bits in the translation look-aside buffer entry associated with the access. if no address translation is performed, these signals are both low. opt2opt0 option control (three-state outputs, synchronous) these outputs reflect the value of the opt field of load and store instructions. pgmode page-mode access (three-state output, synchronous) this indicates that the address for an access is in the same page-mode block as the address for the previous access. rdn read narrow (input, synchronous) this input indicates that the accessed memory is an 8- or 16-bit device attached to id31id24 or to id31id16, respectively. this signal can be asserted for any read accessethough it is probably most useful for rom ac- cesseseand causes the processor to perform addition- al read accesses to obtain the remainder of a word or half-word, if required. this signal is ignored on a write access. the rdn signal is sampled when reset is asserted. the level of rdn during the four cycles before the deassertion of reset determines whether a narrow ac- cess is 8 or 16 bits wide. if rdn is low in each of these cycles, a narrow access is 16 bits wide. if rdn is high, a narrow access is 8 bits wide. the width of the narrow ac- cess is undefined if rdn changes in the four cycles be- fore reset is deasserted. rdy ready (bidirectional, synchronous) for a read, this input indicates that a valid instruction or data word is on the instruction/data bus. for a write, it indicates that the write is complete and that the data no longer needs to be driven on the instruction/data bus. the processor ignores this signal for the first cycle of a
amd p r e l i m i n a r y 20 AM29040 microprocessor simple access and for the first cycle of a burst-mode access (all other burst-mode cycles are not subject to this restriction). req request (bidirectional, synchronous) this signal requests an access. when req is low, the address for the access appears on the address bus. this signal is precharged and then maintained by a weak internal pullup when the bus is granted to another master, to prevent spurious requests. reset reset (input, asynchronous) this input places the processor in the reset mode. r/w read/write (bidirectional, synchronous) this signal indicates whether data is being transferred from the processor to the external system (low), or from the external system to the processor (high). stat2stat0 cpu status (outputs, synchronous) these outputs indicate the state of the processor's execution stage on the previous cycle. sup/us supervisor/user mode (three-state output, synchronous) this output indicates the program mode for an access. if the access is performed under supervisor mode, sup/ us is high. if the access is performed under user mode, sup/us is low. test test mode (input, asynchronous) when this input is active, the processor is in test mode. all outputs and bidirectional lines are forced to the high- impedance state. trap 1trap 0 trap requests (inputs, asynchronous) these inputs generate prioritized trap requests. the trap caused by trap 0 has the highest priority. warn warn (input, asynchronous, edge-sensitive) a high-to-low transition on this input causes a non- maskable warn trap to occur. this trap bypasses the normal trap vector fetch sequence and is useful in situa- tions where the vector fetch might not work (e.g., when data memory is faulty) . wbc write broadcast (bidirectional, synchronous) this output is asserted by a bus master to indicate a write broadcast. a write broadcast is performed to notify other agents of a modification to a shared cache block. the write need not be performed in the main memory. jtag interface pins the following pins are included as part of the ieee 1149.11990 compliant standard test access port. tck test clock input (input, asynchronous) this input clocks the test access port. tdi test data input (input, synchronous to tck) this signal supplies data to the test logic from an exter- nal source. it is sampled on the rising edge of tck. tdo test data output (three-state output, synchronous to tck) this output supplies data from the test logic to an exter- nal destination. it changes on the falling edge of tck. tms test mode select (input, synchronous to tck) this input controls the operation of the test access port. trst test reset input (input, asynchronous) this input asynchronously resets the test access port. the reset places the test logic in a state such that it does not cause an output driver to be enabled. the trst in- put must be asserted in conjunction with the reset in- put for correct processor initialization. special pins emacc emulator access (output, synchronous) the emacc pin is defined for use with hardware devel- opment systems (emulators). this pin does not exist on any package, and this definition is provided solely for the purposes of standardizing its location. the emacc output indicates the current access is gen- erated by an emulator. if emacc is low, the access is emulator specific and the external system must not re- spond to the access. if emacc is high, the access is di- rected to the external system.
amd p r e l i m i n a r y 21 AM29040 microprocessor absolute maximum ratings storage temperature 65 c to +150 c . . . . . . . . . . . . voltage on any pin with respect to gnd 0.5 to 5.5 v . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices case temperature (t c )0 c to +85 c . . . . . . . . . . . . . . supply voltage (v cc ) +3.0 to +3.6 v . . . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating range p a r a m e t e r pdii t c di i preliminary parameter symbol parameter description test conditions min max unit v il input low voltage 0.5 0.8 v v ih input high voltage 2.0 5.5 v v ilinclk inclk input low voltage 0.5 0.8 v v ihinclk inclk input high voltage 2.0 5.5 v v ilmemclk memclk input low voltage 0.5 0.8 v v ihmemclk memclk input high voltage v cc 0.8 5.5 v v ol output low voltage for all outputs except memclk i ol = 3.2 ma 0.45 v v oh output high voltage for all outputs except memclk i oh = 400 m a 2.4 v i li input leakage current 0.45 v v in v cc 0.45 v 10 m a i lo output leakage current 0.45 v v out v cc 0.4 v 10 m a i ccop operating power supply current outputs floating; holding reset active with exter- nally supplied memclk. v cc = 3.3 v 10 ma/mhz v olc memclk output low voltage i olc = 20 ma 0.6 v v ohc memclk output high voltage i ohc = 20 ma v cc 0.6 v i osgnd memclk gnd short circuit current v cc = 3.3 v 60 ma i osvcc memclk v cc short circuit current v cc = 3.3 v 60 ma i ccstb standby power supply current snooze mode sleep mode 20 5 ma capacitance p a r a m e t e r pdii t c di i preliminary parameter symbol parameter description test conditions min max unit c in input capacitance 15 pf c inclk inclk input capacitance 20 pf c memclk memclk capacitance fc = 10 mhz 20 pf c out output capacitance 20 pf c i/o i/o pin capacitance 20 pf note: limits guaranteed by characterization.
amd p r e l i m i n a r y 22 AM29040 microprocessor switching characteristics over commercial operating range n pdii t preliminary n pdii test conditions 50mhz 2 40 mhz 2 33 mhz 2 no. parameter description conditions (note 1) min max min max min max unit 1 inclk period (t) (normal operation) notes 2, 7 20 50 25 50 15 25 ns 2 inclk high time (maximum frequency) 7 13 9 16 5 10 ns 3 inclk low time (maximum frequency) 7 13 9 16 5 10 ns 4 inclk rise time 0 3 0 4 0 6 ns 5 inclk fall time 0 3 0 4 0 6 ns 6 memclk delay from inclk notes 3, 4 0 6 0 7 0 6 ns 7 synchronous output valid delay note 6 1 12 1 14 1 12 ns 7a synchronous output valid delay for id31id0 note 6 1 16 1 18 1 16 ns 8 synchronous output invalid delay 1 12 1 14 1 12 ns 8a synchronous output invalid delay for id31id0 1 16 1 18 1 16 ns 9 synchronous input setup time 12 14 12 ns 9a synchronous input setup time for id31id0 6 8 6 ns 9b synchronous input setup time for rdy , err , and rdn 16 16 16 ns 10 synchronous input hold time 0 0 0 ns 11 setup time for synchronous reset deassertion 2 2 2 ns 12 hold time for synchronous reset deassertion 5 5 5 ns 13 warn high time note 5 4t 4t 4t ns 14 asynchronous input pulse width note 5 t + 10 t + 10 t + 10 ns 15 memclk high time (note 5) memclk input memclk output 14 t/2 3 26 t/2 + 3 18 t/2 3 32 t/2 + 3 11 t/2 3 19 t/2 + 3 ns 16 memclk low time (note 5) memclk input memclk output 14 t/2 3 26 t/2 + 3 18 t/2 3 32 t/2 + 3 11 t/2 3 19 t/2 + 3 ns 17 memclk rise time memclk input memclk output 0 0 5 5 0 0 5 5 0 0 5 5 ns 18 memclk fall time memclk input memclk output 0 0 5 5 0 0 5 5 0 0 5 5 ns notes: 1. test conditions: all inputs/outputs are ttl compatible for v ih , v il , v oh , and v ol unless otherwise noted. all output timing speci- fications are for 80 pf of loading. all setup, hold, and delay times are measured relative to memclk unless otherwise noted. all input low levels must be driven to 0.45 v and all input high levels must be driven to 2.4 v except inclk. 2. maximum bus frequency is 25 mhz for a 50-mhz processor (t=40 ns), 20 mhz for a 40-mhz processor (t=50 ns), and 33 mhz for a 33-mhz processor (t=30 ns). 3. memclk as an input is always at cmos levels. 4. memclk can drive an external load of 100 pf. 5. the parameter t is the actual period of memclk, regardless of the processor frequency rating. 6. all output valid delays are measured with v ol =1.0 v and v oh =2.0 v. 7. does not apply to snooze or sleep modes.
amd p r e l i m i n a r y 23 AM29040 microprocessor switching waveforms 9b inclk memclk 1 4 3 0.8 v 1.5 v 2.0 v 5 17 16 15 0.8 v 1.5 v 2.0 v 18 6 synchronous outputs synchronous inputs asynchronous inputs reset warn 7a 7 8a 8 10 9 9a 11 12 13 14 2
amd p r e l i m i n a r y 24 AM29040 microprocessor switching test circuit v l i ol = 3.2 ma v ref = 1.5 v i oh = 400 m a c l v h v AM29040 cpu pin under test note: c l is guaranteed to 80 pf.
amd p r e l i m i n a r y 25 AM29040 microprocessor thermal characteristics the AM29040 microprocessor is specified for operation with case temperature ranges for a commercial tempera- ture device. case temperature is measured at the top center of the package as shown in figure 2. the various temperatures and thermal resistances can be determined using the equations shown in figure 3 along with information given in table 1. (the variable p is power in watts.) allowable ambient temperature curves for various air- flows are given in figure 4 through figure 6. these graphs assume a maximum v cc and a maximum power supply current equal to i ccop . all calculations made us- ing this information should guarantee that the operating case temperature does not exceed the maximum case temperature. since p is a function of operating frequen- cy, calculations can also be made to determine the am- bient temperature at various operating speeds. q ja q ca q jc q ja = q jc + q ca figure 1. pga package thermal resistance e c/watt q ja q ca q jc t c q ja = q jc + q ca figure 2. pqfp package thermal resistance e c/watt q ja = q jc + q ca p=i ccop ? freq ? v cc t j =t c +p ? q jc t j =t a +p ? q ja t c =t j p ? q jc t c =t a +p ? q ca t a =t j p ? q ja t a =t c p ? q ca figure 3. thermal characteristics equations
amd p r e l i m i n a r y 26 AM29040 microprocessor table 1. thermal characteristics ( c/watt) surface mounted airfloweft./min. (m/s) pga package 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) q ja junction-to-ambient 24 20 15 13 11 q jc1 junction-to-case 2 2 2 2 2 q ca case-to-ambient 22 18 13 11 9 pqfp package q ja junction-to-ambient 36 28 25 23 21 q jc junction-to-case 6.5 6.5 6.5 6.5 6.5 q ca case-to-ambient 29.5 21.5 18.5 16.5 14.5 30 40 50 60 70 80 0 200 400 600 800 30 40 50 60 70 80 0 200 400 600 800 t c at 85 c t c at 85 c maximum ambient ( c) air flow (ft./min.) 50 mhz 40 mhz air flow (ft./min.) 30 40 50 60 70 80 0 200 400 600 800 t c at 85 c maximum ambient ( c) 33 mhz air flow (ft./min.) figure 4. pga packageemaximum allowable ambient temperature (data sheet limit, i ccopmax , v cc =+3.6 v, average thermal impedance)
amd p r e l i m i n a r y 27 AM29040 microprocessor 30 40 50 60 70 80 0 200 400 600 800 30 40 50 60 70 80 0 200 400 600 800 t c at 85 c t c at 85 c maximum ambient ( c) air flow (ft./min.) 50 mhz 40 mhz air flow (ft./min.) 30 40 50 60 70 80 0 200 400 600 800 t c at 85 c maximum ambient ( c) 33 mhz air flow (ft./min.) figure 5. pqfp packageemaximum allowable ambient temperature (data sheet limit, i ccopmax , v cc =+3.6 v, average thermal impedance) 0 5 10 15 20 25 30 35 40 0 200 400 600 800 air flow (ft./min.) thermal resistance [ q ja ( c/w)] 0 5 10 15 20 25 30 35 40 0 200 400 600 800 air flow (ft./min.) pqfp package pga package figure 6. thermal impedance
amd p r e l i m i n a r y 28 AM29040 microprocessor physical dimensions cgm 145 pin grid array 1.540 1.580 1.400 bsc lid outline cavity-down pga index corner 1.540 1.580 1.400 bsc 0.003 min (4x) bottom view b a 0.080 max cgm145 53095 notes: all dimensions are in inches unless otherwise noted. bsc is an ansi standard for basic space centering. not to scale. for reference only.
amd p r e l i m i n a r y 29 AM29040 microprocessor cgm 145 (continued) lid 0.105 0.125 0.105 0.195 0.080 0.140 base plane 0.025 0.055 side view c seating plane 0.100 0.016 0.020 0.045 0.055 cgm145 53095 notes: all dimensions are in inches unless otherwise noted. bsc is an ansi standard for basic space centering. not to scale. for reference only.
amd p r e l i m i n a r y 30 AM29040 microprocessor pdr 144, trimmed and formed plastic quad flat pack 31.00 31.40 27.90 28.10 22.75 ref pin 108 pin 144 pin 36 pin 72 pin one i.d. 22.75 ref 27.90 28.10 31.00 31.40 see detail x seating plane 0.65 basic 0.25 min 3.20 3.60 3.95 max s s top view side view pqr144 41594 a b d a c notes: all measurements are in millimeters unless otherwise noted. not to scale. for reference only.
amd p r e l i m i n a r y 31 AM29040 microprocessor pdr 144 (continued) 0.20 min. flat shoulder 7 typ. 0 min. 0.30 0.05 r gage plane 0.25 0.73 1.03 0 7 7 typ. detail x 0.22 0.38 0.13 0.23 3.95 max section ss 0.22 0.38 0.13 0.23 pqr144 41594 notes: not to scale. for reference only. trademarks amd, the amd logo, am29000, minimon29k, and fusion29k are registered trademarks; and am29005, am29030, am29035, AM29040, am29050, am29200, am29202, am29205, am29240, am29243, am29245, 29k, xray29k, traceable cache, and scalable clocking are trade- marks of advanced micro devices, inc. high c is a registered trademark of metaware, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. copyright ? 1995 advanced micro devices, inc. all rights reserved.

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