1/6 december 2001 dsm2150f5v dsm (digital signal processor system memory) for analog devices general purpose dsps features summary n glueless connection to dsp C 512k x 8 or 256k x 16 (8 or 16 bit operation) C easily add memory, logic, and i/o to the exter- nal memory interface (emi) of analog devices' general purpose dsp families n dual flash memories C 512k x 8 main flash memory divided into eight, 64 kbyte sectors. C 32k x 8 secondary flash memory divided into four, 8 kbyte sectors. C small sector size ideal for storing small data sets, and calibration or configuration constants. C concatenate secondary flash with main flash for total of 544 kbytes. C each flash sector can be write protected. C built-in programmable address decoding logic allows mapping individual flash sectors to any address boundary. n up to 40 multifunction i/o pins C increase total dsp system i/o capability C i/o controlled by dsp software or pld logic n general purpose pld C over 3,000 gates of pld with 16 macrocells C use for peripheral glue logic to keypads, control panel, displays, lcds, and other devices. C eliminate plds and external logic devices C create state machines, chip selects, simple shifters and counters, clock dividers, delays C simple psdsoft express software ...free n in-system programming (isp) with jtag C program entire chip in 20-35 seconds with no in- volvement of the dsp C links with jtag debug port on dsp C eliminate sockets for pre-programmed memory and logic devices C isp allows efficient manufacturing and product testing supporting just-in-time inventory C use low-cost flashlink? jtag programmer with pc figure 1. packages n content security C programmable security bit blocks access of de- vice programmers and readers n operating range Cv cc : 3.3v10% C temperature: C40 o c to +85 o c n zero-power technology C 100 m a standby current (typical) n packaging C 80-pin tqfp n flash memory speed, endurance, retention C 120 ns, 100k cycles, 15 year retention tqfp80 (t)
dsm2150f5v 2/6 summary description the dsm2150f5 provides a turn-key system memory solution for the analog devices general purpose dsp families. with dual in- system pro- grammable (isp) flash memories, parameter storage, programmable logic, and additional i/o, the combination of the dsm2150f5 with the dsp results in a simple and flexible two-chip dsp sys- tem. on-chip memory decode logic simplifies mapping the dual banks of flash memory to the dsp for boot loading, code execution, data record- ing, code swapping, and pa-rameter storage. an on-chip jtag isp port allows blank dsm devices to be programmed on the circuit board, thus reduc- ing development time, simplifying manufacturing flow, lowering the cost of field upgrades, and elim- inating the need for sockets and pre-programmed memory and logic devices. the dsms jtag inter- face may also be chained with the dsps jtag debug interface for quick code iterations on the bench. jtag isp is accomplished via the flashlink jtag programmer which plugs into any pc or laptop parallel port. in addition to isp flash memory, dsm devices add programmable logic (pld) and up to 16 con- figurable i/o pins to the dsp system. pld and i/o configuration are programmable by jtag isp, just like the flash memory. the pld consists of more than 3000 gates and has 16 macrocell registers. common uses for the pld include chip selects for external devices, state-machines, simple shifters and counters, key-pad and control panel interfac- es, clock dividers, handshake delay, muxes, etc. the on-chip pld eliminates the need for small ex- ternal plds and logic devices. configuration of pld, i/o, and flash memory mapping are easily entered in a point-and-click environment using the software development tool, psdsoft express. the software is available to download from www.st.com/psd. the two-chip combination of a dsp and a dsm device is ideal for systems which have limitations on size, emi levels, and power consumption. dsm memory and logic are zero-power, meaning they automatically go to standby between memory ac- cesses or logic input changes, producing low ac- tive and standby current consumption, making them ideal for battery powered products. figure 2. system block diagram, two chip solution ai05732 addr & decode logic primary flash memory 512k bytes 16 macrocell pld i/o control power management content security jtag isp to all areas i/o bus address 8or16data control dsm2150f5v dsp system memory analog devices dsp adsp-218x adsp-219x adsp-2153x adsp-2106x adsp-2116x adsp-ts101s jtag isp jtag debug (all but adsp-218x family) secondary flash memory 32k bytes i/o flags sdram host mcu serial device serial device 16 i/o ports with pld i/o, pld, chip selects 8to16 i/o ports general purpose i/o
3/6 dsm2150f5v figure 3. tqfp connections 60 cntl1 59 cntl0 58 pa7 57 pa6 56 pa5 55 pa4 54 pa3 53 pa2 52 pa1 51 pa0 50 gnd 49 gnd 48 pc7 47 pc6 46 pc5 45 pc4 44 pc3 43 pc2 42 pc1 41 pc0 pd2 pd3 ad0 ad1 ad2 ad3 ad4 gnd v cc ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pd1 pd0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 gnd v cc pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 v cc gnd pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 reset cntl2 ai04943
dsm2150f5v 4/6 table 1. pin assignments C tqfp80 pin no. pin assign ments pin no. pin assign ments pin no. pin assign ments pin no. pin assign ments 1 pd2 21 pg0 41 pc0 61 pb0 2 pd3 22 pg1 42 pc1 62 pb1 3 ad0 23 pg2 43 pc2 63 pb2 4 ad1 24 pg3 44 pc3 64 pb3 5 ad2 25 pg4 45 pc4 65 pb4 6 ad3 26 pg5 46 pc5 66 pb5 7 ad4 27 pg6 47 pc6 67 pb6 8 gnd 28 pg7 48 pc7 68 pb7 9 v cc 29 v cc 49 gnd 69 v cc 10 ad5 30 gnd 50 gnd 70 gnd 11 ad6 31 pf0 51 pa0 71 pe0 12 ad7 32 pf1 52 pa1 72 pe1 13 ad8 33 pf2 53 pa2 73 pe2 14 ad9 34 pf3 54 pa3 74 pe3 15 ad10 35 pf4 55 pa4 75 pe4 16 ad11 36 pf5 56 pa5 76 pe5 17 ad12 37 pf6 57 pa6 77 pe6 18 ad13 38 pf7 58 pa7 78 pe7 19 ad14 39 reset 59 cntl0 79 pd0 20 ad15 40 cntl2 60 cntl1 80 pd1
5/6 dsm2150f5v table 2. ordering information scheme example: dsm2150 f5 v C12t 6 t device type dsm21 = dsp system memory for adsp-21xxx family dsm configuration 50 = dual flash memory arrays, 32 i/o pins main flash memory f5 = 4 mbit operating voltage v = v cc = 3.0 to 3.6v speed 12 = 120 ns package t = 80 pin tqfp temperature range 6 = C40 to 85 c option t = tape & reel packing
dsm2150f5v 6/6 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies austalia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com
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