1 idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger industrial temperature range january 2002 idt74fct16260at/ct/et industrial temperature range fast cmos 12-bit tri-port bus exchanger description: the fct16260t tri-port bus exchangers are high-speed 12-bit latched bus multiplexers/transceivers for use in high-speed microprocessor applica- tions. these bus exchangers support memory interleaving with latched outputs on the b ports and address multiplexing with latched inputs on the b ports. the tri-port bus exchanger has three 12-bit ports. data may be transferred between the a port and either/both of the b ports. the latch enable (le1b, le2b, lea1b and lea2b) inputs control data storage. when a latch-enable input is high, the latch is transparent. when a latch-enable input is low, the data at the input is latched and remains latched until the latch enable input is returned high. independent output enables ( oe1b and oe2b ) allow reading from one port while writing to the other port. the fct16260t is ideally suited for driving high capacitance loads and low impedance backplanes. the output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. a-1b latch lea1b le1b le2b 12 m u x 12 oe1b 12 a 1:12 1b-a latch 1b 1:12 12 12 12 2b-a latch 12 12 a-2b latch lea2b 12 2b 1:12 oe2b oea sel 1 0 29 30 2 28 1 27 55 56 the idt logo is a registered trademark of integrated device technology, inc. ? 2002 integrated device technology, inc. dsc-5431/2 features: ? 0.5 micron cmos technology ? high-speed, low-power cmos replacement for abt functions ? typical t sk(o) (output skew) < 250ps ? low input and output leakage 1a (max.) ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 5v 10% ? high drive outputs (C32ma i oh , 64ma i ol ) ? power off disable outputs permit live insertion ? typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25c ? power off disable outputs permit live insertion ? available in ssop and tssop packages functional block diagram
2 industrial temperature range idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger ssop/ tssop top view pin configuration oea le1b gnd 2b 2 v cc a 3 a 6 a 7 gnd a 12 2b 3 2b 1 a 1 a 2 gnd a 4 a 5 a 8 a 9 a 10 v cc 1b 1 a 11 1b 2 lea2b 2b 4 gnd 2b 5 2b 6 v cc 2b 7 2b 8 gnd 2b 10 2b 11 2b 12 1b 11 1b 10 gnd 1b 9 v cc 1b 6 1b 8 2b 9 1b 12 1b 7 1b 5 oe2b 39 29 30 31 32 33 34 35 36 37 38 25 26 27 28 48 47 41 42 43 44 45 46 40 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 21 22 23 24 le2b gnd sel 1b 3 oe1b gnd 1b 4 lea1b 49 56 55 50 51 52 53 54 symbol description max unit v term (2) terminal voltage with respect to gnd C0.5 to 7 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 v t stg storage temperature C65 to +150 c i out dc output current C60 to +120 ma absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all device terminals except fct162xxx output and i/o terminals. 3. output and i/o terminals for fct162xxx. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6 pf c out output capacitance v out = 0v 3.5 8 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested.
3 idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger industrial temperature range signal i/o description a (1:12) i/o bidirectional data port a. usually connected to the cpu's address/data bus. 1b (1:12) i/o bidirectional data port 1b. connected to the even path or even bank of memory. 2b (1:12) i/o bidirectional data port 2b. connected to the odd path or odd bank of memory. lea1b i latch enable input for a-1b latch. the latch is open when lea1b is high. data from the a-port is latched on the high to low transition of lea1b. lea2b i latch enable input for a-2b latch. the latch is open when lea2b is high. data from the a-port is latched on the high to low transition of lea2b. le1b i latch enable input for the 1b-a latch. the latch is open when le1b is high. data from the 1b port is latched on the high to low transition of le1b. le2b i latch enable input for the 2b-a latch. the latch is open when le2b is high. data from the 2b port is latched on the high to low transition of le2b. sel i 1b or 2b path selection. when high, sel enables data transfer from 1b port to a port. when low, sel enables data transfer from 2b port to a port. oea i output enable for a port (active low) oe1b i output enable for 1b port (active low) oe2b i output enable for 2b port (active low) pin description inputs output 1b 2b sel le1b le2b oea a hxhhxl h lxhhxl l xxhlxl a (1) xh l xh l h xllxhl l xxlxll a (1) xxxxxh z inputs outputs a lea1b lea2b oe1b oe2b 1b 2b hh h l l h h lh h l l l l hh l l l h b (1) lh l l l l b (1) hl hll b (1) h ll hll b (1) l xl lll b (1) b (1) xx xhh z z x x x l h active z x x x h l z active x x x l l active active notes: 1. output level before the indicated steady-state input conditions were established. 2. h = high voltage level l = low voltage level x = don't care z = high-impedance function tables (1)
4 industrial temperature range idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 v v il input low level guaranteed logic low level 0.8 v i ih input high current (input pins) (5) v cc = max. v i = v cc 1a input high current (i/o pins) (5) 1 i il input low current (input pins) (5) v i = gnd 1 input low current (i/o pins) (5) 1 i ozh high impedance output current v cc = max. v o = 2.7v 1a i ozl (3-state output pins) (5) v o = 0.5v 1 v ik clamp diode voltage v cc = min., i in = C18ma C0.7 C1.2 v i os short circuit current v cc = max., v o = gnd (3) C80 C140 C250 ma v h input hysteresis 100 mv i ccl quiescent power supply current v cc = max. 5 500 a i cch v in = gnd or v cc i ccz dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = C40c to +85c, v cc = 5.0v 10% output drive characteristics notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. duration of the condition can not exceed one second. 5. the test limit for this parameter is 5a at ta = C55c. symbol parameter test conditions (1) min. typ. (2) max. unit i o output drive current v cc = max., v o = 2.5v (3) C50 C180 ma v oh output high voltage v cc = min. i oh = C3ma 2.5 3.5 v in = v ih or v il i oh = C15ma 2.4 3.5 v i oh = C32ma (4) 23 v ol output low voltage v cc = min. i ol = 64ma 0.2 0.55 v v in = v ih or v il i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v 1 a
5 idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger industrial temperature range symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current v cc = max. 0.5 1.5 ma ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max. v in = v cc 60 100 a / current (4) outputs open v in = gnd mhz one output port enabled lexx = v cc one input bit togging one output bit toggling 50% duty cycle i c total power supply current (6) v cc = max. v in = v cc 0.6 1.5 ma outputs open v in = gnd f i = 10mhz 50% duty cycle v in = 3.4v 0.9 2.3 one output port enabled v in = gnd lexx = v cc one input bit toggling one output bit toggling v cc = max. v in = v cc 1.8 3.5 (5) outputs open v in = gnd f i = 2.5mhz 50% duty cycle v in = 3.4v 4.8 12.5 (5) one output port enabled v in = gnd lexx = v cc twelve input bits toggling twelve output bits toggling power supply characteristics notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp n cp /2 + fini) i cc = quiescent current (i ccl , i cch and i ccz ) d i cc = power supply current for a ttl high input (v in = 3.4v). d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp fi = input frequency ni = number of inputs at fi
6 industrial temperature range idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger fct16260at fct16260ct fct16260et symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. unit t plh propagation delay c l = 50pf 1.5 5.2 1.5 4.7 1.5 3.6 ns t phl ax to 1bx or ax to 2bx r l = 500 w t plh propagation delay 1.5 5.6 1.5 5 1.5 3.6 ns t phl 1bx to ax or 2bx to ax t plh propagation delay 1.5 5.2 1.5 4.7 1.5 4 ns t phl lexb to ax t plh propagation delay 1.5 4.7 1.5 4.4 1.5 4 ns t phl lea1b to 1bx or lea2b to 2bx t plh propagation delay 1.5 5.2 1.5 4.7 1.5 4 ns t phl sel to ax t pzh output enable time 1.5 5.7 1.5 5.1 1.5 4.4 ns t pzl oea to ax, oe1b to 1bx, or oe2b to 2bx t phz output disable time 1.5 4.4 1.5 4 1.5 4 ns t plz oea to ax, oe1b to 1bx, or oe2b to 2bx t su set-up time high or low data to latch 1.5 1 1 ns t h hold time, latch to data 1 1 1 ns t w pulse width, latch high (4) 3 3 3ns t sk(o) output skew (3) 0.5 0.5 0.5 ns switching characteristics over operating range notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. 4. this parameter is guaranteed but not tested.
7 idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger industrial temperature range pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h preset clear clock enable etc. high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh test circuits and waveforms test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. test circuits for all outputs set-up, hold, and release times propagation delay pulse width enable and disable times notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns.
8 industrial temperature range idt74fct16260at/ct/et fast cmos 12-bit tri-port bus exchanger ordering information idt xx temp. range xxxx device type xx package pv pa shrink small outline package thin shrink small outline package 12-bit tri-port bus exchanger 74 C 40c to +85c 16 double-density, 5 volt, balanced drive fct xxx family 206at 206ct 206et corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com data sheet document history 1/21/2002 removed military temp grade
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