View 24LC21ISN_2556668.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2001 microchip technology inc. ds21095h-page 1 features ? single supply with operation down to 2.5v completely implements ddc1 ? /ddc2 ? inter- face for monitor identification low power cmos technology - 1 ma active current typical -10 a standby current typical at 5.5v 2-wire serial interface bus, i 2 c ? compatible self-timed write cycle (including auto-erase) page-write buffer for up to 8 bytes 100 khz (2.5v) and 400 khz (5v) compatibility factory programming (qtp) available 1,000,000 erase/write cycles ensured data retention > 200 years 8-pin pdip and soic package available for extended temperature ranges description the microchip technology inc. 24lc21 is a 128 x 8 bit electrically erasable prom. this device is designed for use in applications requiring storage and serial transmission of configuration and control information. two modes of operation have been implemented: transmit only mode and bi-directional mode. upon power-up, the device will be in the transmit only mode, sending a serial bit stream of the entire memory array contents, clocked by the v clk pin. a valid high to low transition on the scl pin will cause the device to enter the bi-directional mode, with byte selectable read/write capability of the memory array. the 24lc21 is available in a standard 8-pin pdip and soic package in both commercial and industrial temperature ranges. - commercial (c): 0c to +70c - industrial (i): -40c to +85c package types block diagram 24lc21 nc nc nc v ss 1 2 3 4 8 7 6 5 v cc v clk scl sda 24lc21 nc nc nc v ss 1 2 3 4 8 7 5 5 v cc v clk scl sda pdip soic hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic v clk sda scl v cc v ss 24lc21 1k 2.5v dual mode i 2 c ? serial eeprom ddc is a trademark of the video electronics standards association. i 2 c is a trademark of philips corporation.
24lc21 ds21095h-page 2 ? 2001 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.6v to v cc +1.0v storage temperature ..................................... -65 c to +150 c ambient temp. with power applied ................-65 c to +125 c soldering temperature of leads (10 seconds) ............. +300 c esd protection on all pins .................................................. 4 kv *notice: stresses above those listed under ? maximum ratings ? may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function v ss ground sda serial address/data i/o scl serial clock (bi-directional mode) v clk serial clock (transmit-only mode) v cc +2.5v to 5.5v power supply nc no connection table 1-2: dc characteristics v cc = +2.5v to 5.5v commercial (c): t amb = 0c to +70c industrial (i): t amb = -40c to +85c parameter symbol min max units conditions scl and sda pins: high level input voltage low level input voltage v ih v il .7 v cc ? ? .3 v cc v v ? ? input levels on v clk pin: high level input voltage low level input voltage v ih v il 2.0 ? .8 .2 v cc v v v cc 2.7v (note 1) v cc < 2.7v (note 1) hysteresis of schmitt trigger inputs v hys .05 v cc ? v (note 1) low level output voltage v ol 1 ? .4 v i ol = 3 ma, v cc = 2.5v (note 1) low level output voltage v ol 2 ? .6 v i ol = 6 ma, v cc = 2.5v input leakage current i li -10 10 av in = .1v to v cc output leakage current i lo -10 10 av out = .1v to v cc pin capacitance (all inputs/outputs) c in , c out ? 10 pf v cc = 5.0v (note1), t amb = 25 c, f clk = 1 mhz operating current i cc write i cc read ? ? 3 1 ma ma v cc = 5.5v, scl = 400 khz standby current i ccs ? ? 30 100 a a v cc = 3.0v, sda = scl = v cc v cc = 5.5v, sda = scl = v cc (note 2) note 1: this parameter is periodically sampled and not 100% tested. 2: v lck must be grounded.
? 2001 microchip technology inc. ds21095h-page 3 24lc21 table 1-3: ac characteristics parameter symbol standard mode vcc= 4.5 - 5.5v fast mode units remarks min max min max clock frequency f clk ? 100 ? 400 khz ? clock high time t high 4000 ? 600 ? ns ? clock low time t low 4700 ? 1300 ? ns ? sda and scl rise time t r ? 1000 ? 300 ns (note 1) sda and scl fall time t f ? 300 ? 300 ns (note 1) start condition hold time t hd : sta 4000 ? 600 ? ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 ? 600 ? ns only relevant for repeated start condition data input hold time t hd : dat 0 ? 0 ? ns (note 2) data input setup time t su : dat 250 ? 100 ? ns ? stop condition setup time t su : sto 4000 ? 600 ? ns ? output valid from clock t aa ? 3500 ? 900 ns (note 2) bus free time t buf 4700 ? 1300 ? ns time the bus must be free before a new transmission can start output fall time from v ih min to v il max t of ? 250 20 + .1 c b 250 ns (note 1), c b 100 pf input filter spike suppres- sion (sda and scl pins) t sp ? 50 ? 50 ns (note 3) write cycle time t wr ? 10 ? 10 ms byte or page mode transmit-only mode parameters output valid from v clk t vaa ? 2000 ? 1000 ns ? v clk high time t vhigh 4000 ? 600 ? ns ? v clk low time t vlow 4700 ? 1300 ? ns ? mode transition time t vhz ? 500 ? 500 ns ? transmit-only power up time t vpu 0 ? 0 ? ns ? endurance ? 1m ? 1m ? cycles 25 c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise and spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific applica- tion, please consult the total endurance model which can be obtained on our website: www.microchip.com
24lc21 ds21095h-page 4 ? 2001 microchip technology inc. 2.0 functional description the 24lc21 operates in two modes, the transmit-only mode and the bi-directional mode. there is a separate two wire protocol to support each mode, each having a separate clock input and sharing a common data line (sda). the device enters the transmit-only mode upon power-up. in this mode, the device transmits data bits on the sda pin in response to a clock signal on the v clk pin. the device will remain in this mode until a valid high to low transition is placed on the scl input. when a valid transition on scl is recognized, the device will switch into the bi-directional mode. the only way to switch the device back to the transmit-only mode is to remove power from the device. 2.1 transmit-only mode the device will power up in the transmit-only mode. this mode supports a unidirectional two wire protocol for transmission of the contents of the memory array. this device requires that it be initialized prior to valid data being sent in the transmit-only mode (see initial- ization procedure, below). in this mode, data is trans- mitted on the sda pin in 8 bit bytes, each followed by a ninth, null bit (see figure 2-1). the clock source for the transmit-only mode is provided on the v clk pin, and a data bit is output on the rising edge on this pin. the eight bits in each byte are transmitted most significant bit first. each byte within the memory array will be out- put in sequence. when the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. the bi-directional mode clock (scl) pin must be held high for the device to remain in the transmit-only mode. 2.2 initialization procedure after v cc has stabilized, the device will be in the trans- mit-only mode. nine clock cycles on the v clk pin must be given to the device for it to perform internal synchro- nization. during this period, the sda pin will be in a high impedance state. on the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. the device will power up at an indeterminate byte address. (figure 2-2). figure 2-1: transmit only mode figure 2-2: device initialization scl sda vclk t vaa t vaa b it 1 (lsb) n ull b it b it 1 (msb) b it 7 t vlow t vhigh t vaa t vaa b it 8b it 7 h igh i mpedance for 9 clock cycles t vpu 12 891011 scl sda vclk v cc
? 2001 microchip technology inc. ds21095h-page 5 24lc21 3.0 bi-directional mode the 24lc21 can be switched into the bi-directional mode (see figure 3-1) by applying a valid high to low transition on the bi-directional mode clock (scl). when the device has been switched into the bi-direc- tional mode, the v clk input is disregarded, with the exception that a logic high level is required to enable write capability. this mode supports a two wire bi-direc- tional data transmission protocol. in this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. the bus must be con- trolled by a master device that generates the bi-direc- tional mode clock (scl), controls access to the bus and generates the start and stop conditions, while the 24lc21 acts as the slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.1 bi-directional mode bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (see figure 3-2). 3.1.1 bus not busy (a) both data and clock lines remain high. 3.1.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.1.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. figure 3-1: mode transition figure 3-2: data transfer sequence on the serial bus scl sda vclk bi-directional mode t vhz transmit only mode (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition scl sda
24lc21 ds21095h-page 6 ? 2001 microchip technology inc. 3.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. when an overwrite does occur it will replace data in a first in first out fashion. 3.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. note: the 24lc21 does not generate any acknowledge bits if an internal pro- gramming cycle is in progress. figure 3-3: bus timing start/stop figure 3-4: bus timing data t su : sta t hd : sta v hys t su : sto start stop scl sda t su : sta t f t low t high t r t hd : dat t su : dat t su : sto t hd : sta t buf t aa t aa t sp t hd : sta scl sda in sda out
24lc21 ds21095h-page 7 ? 2001 microchip technology inc. 3.1.6 slave address after generating a start condition, the bus master transmits the slave address consisting of a 7-bit device code ( 1010 ) for the 24lc21, followed by three don ? t care bits. the eighth bit of slave address determines if the master device wants to read or write to the 24lc21 (figure 3-5). the 24lc21 monitors the bus for its corresponding slave address all the time. it generates an acknowl- edge bit if the slave address was true and it is not in a programming mode. figure 3-5: control byte allocation 4.0 write operation 4.1 byte write following the start signal from the master, the slave address (4 bits), the don ? t care bits (3 bits) and the r/w bit which is a logic low is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will fol- low after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmit- ted by the master is the word address and will be writ- ten into the address pointer of the 24lc21. after receiving another acknowledge signal from the 24lc21 the master device will transmit the data word to be writ- ten into the addressed memory location. the 24lc21 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and dur- ing this time the 24lc21 will not generate acknowledge signals (figure 4-1). it is required that v clk be held at a logic high level in order to program the device. this applies to byte write and page write operation. note that v clk can go low while the device is in its self-timed program operation and not affect programming. 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24lc21 in the same way as in a byte write. but instead of generating a stop condi- tion the master transmits up to eight data bytes to the 24lc21 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order five bits of the word address remains con- stant. if the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (figure 4-3). it is required that v clk be held at a logic high level in order to program the device. this applies to byte write and page write operation. note that v clk can go low while the device is in its self-timed program operation and not affect programming. operation control code chip select r/w read 1010 xxx 1 write 1010 xxx 0 slave address 1010 xx x r/w a start read/write note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ? page size ? ) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data pre- viously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
24lc21 ds21095h-page 8 ? 2001 microchip technology inc. figure 4-1: byte write figure 4-2: byte write figure 4-3: page write s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k vclk s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k vclk s p bus activity master sda line bus activity s t a r t control byte word address data (n) data (n + 15) s t o p a c k a c k a c k a c k a c k data (n + 1) vclk
24lc21 ds21095h-page 9 ? 2001 microchip technology inc. 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for the flow diagram. figure 5-1: acknowledge polling flow 6.0 write protection when using the 24lc21 in the bi-directional mode, the v clk pin operates as the write protect control pin. set- ting v clk high allows normal write operations, while setting v clk low prevents writing to any location in the array. connecting the v clk pin to v ss would allow the 24lc21 to operate as a serial rom, although this con- figuration would prevent using the device in the trans- mit-only mode. 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to ? 1 ? . there are three basic types of read operations: current address read, random read and sequential read. 7.1 current address read the 24lc21 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to ? 1 ? , the 24lc21 issues an acknowl- edge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lc21 discontinues transmis- sion (figure 7-1). 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24lc21 as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a ? 1 ? . the 24lc21 will then issue an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24lc21 discontinues transmission (figure 7-2). 7.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24lc21 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lc21 to transmit the next sequentially addressed 8-bit word (see figure 7-3). to provide sequential reads the 24lc21 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 noise protection the 24lc21 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
? 2001 microchip technology inc. ds21095h-page 10 24lc21 figure 7-1: current address read figure 7-2: random read figure 7-3: sequential read sp bus activity master sda line bus activity s t a r t control byte data (n) a c k n o a c k s t o p s p s bus activity master sda line bus activity s t a r t s t o p control byte word address data (n) a c k a c k n o a c k control byte a c k s t a r t p bus activity master sda line bus activity s t o p control byte a c k n o a c k data (n) data (n + 1) data (n + 2) data (n + x) a c k a c k a c k 8.0 pin descriptions 8.1 sda this pin is used to transfer addresses and data into and out of the device, when the device is in the bi-direc- tional mode. in the transmit-only mode, which only allows data to be read from the device, data is also transferred on the sda pin. this pin is an open drain terminal, therefore the sda bus requires a pullup resis- tor to v cc (typical 10k ? for 100 khz, 2k ? for 400 khz). for normal data transfer in the bi-directional mode, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 8.2 scl this pin is the clock input for the bi-directional mode, and is used to synchronize data transfer to and from the device. it is also used as the signaling input to switch the device from the transmit only mode to the bi-direc- tional mode. it must remain high for the chip to continue operation in the transmit only mode. 8.3 v clk this pin is the clock input for the transmit only mode. in the transmit only mode, each bit is clocked out on the rising edge of this signal. in the bi-directional mode, a high logic level is required on this pin to enable write capability.
24lc21 ? 2001 microchip technology inc. ds21095h-page 11 24lc21 product identification system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory o r the listed sales offices. sales and support package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead temperature blank = 0 c to +70 c range: i =-40 c to +85 c device: 24lc21 dual mode i 2 c serial eeprom 24lc21t dual mode i 2 c serial eeprom (tape and reel) 24lc21 -/p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide web site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
? 2001 microchip technology inc. ds21095h-page 12 24lc21 notes:
24lc21 ds21095h-page 13 ? 2001 microchip technology inc. notes:
? 2001 microchip technology inc. ds21095h-page 14 24lc21 notes:
24lc21 ds21095h-page 15 ? 2001 microchip technology inc. ? all rights reserved. copyright ? 2001, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. ? trademarks the microchip name, logo, pic, picmicro, picmaster, picstart, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filterlab, mxdev, microid, flexrom, fuzzylab, mpasm, mplink, mplib, picdem, icepic, migratable memory, fansense, economonitor, selectmode and microport are trademarks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds21095h-page 16 ? 2001 microchip technology inc. all rights reserved. ? 2001 microchip technology incorporated. printed in the usa. 3/01 printed on recycled paper. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 austin analog product sales 8303 mopac expressway north suite a-201 austin, tx 78759 tel: 512-345-2030 fax: 512-345-6085 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 boston analog product sales unit a-8-1 millbrook tarry condominium 97 lowell road concord, ma 01742 tel: 978-371-6400 fax: 978-371-0050 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 dayton two prestige place, suite 130 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 mountain view analog product sales 1300 terra bella avenue mountain view, ca 94043-1836 tel: 650-968-9241 fax: 650-967-1590 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology beijing office unit 915 new china hong kong manhattan bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - shanghai microchip technology shanghai office room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 hong kong microchip asia pacific rm 2101, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o ? shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 asia/pacific (continued) korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d ? activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 germany analog product sales lochhamer strasse 13 d-82152 martinsried, germany tel: 49-89-895650-0 fax: 49-89-895650-22 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 01/30/01 w orldwide s ales and s ervice

▲Up To Search▲

Price & Availability of 24LC21ISN

	To Download 24LC21ISN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .