three-pll clock generator cy2081a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 november 16, 2000 features ? factory-eprom configurable for quick availability and prototyping. general purpose clock synthesizer for all applications such as: modems, disk drives, cd-rom drives, video cd players, games, set-top boxes, data/telecommuni- cations, etc. three independent configurable clock outputs outputs ranging from 500 khz to 100 mhz (5v) and up to 80 mhz for 3.3v operation configurable output control pin (pin 8) can be used as an output enable, power-down, suspend or select line. phase-locked loop oscillator input derived from exter- nal crystal (10 mhz to 25 mhz) or external reference clock (1 mhz to 30 mhz) 3.3v or 5v operation (factory configured) 8-pin 150-mil packaging achieves minimum footprint for space-critical applications sophisticated internal loop filter requires no external components or manufacturing tweaks as commonly re- quired with external filters functional description the cy2081a is a general-purpose clock synthesizer de- signed for use in applications such as modems, disk drives, cd-rom drives, video cd players, games, set-top boxes and data/telecommunications. this devices offers three config- urable clock outputs in an 8-pin 150-mil soic package and can be configured to operate off either a 3.3v or 5v power supply. the on-chip reference oscillator is desi gned for 10 mhz to 25 mhz crystals. alternatively, a reference clock between 1 mhz and 30 mhz can be used. the cy2081a also features an output control pin (pin 8) which can be configured as an output enable, power down, frequen- cy select, or suspend input. this gives the user the ability to three-state the output, power down the device, change the clka output frequency during operation, or suspend any of the outputs. asserting the pd input will result in all the plls and the outputs being shut down. the plls will have to re-lock when the pd input is deasserted. the cy2081a outputs three clocks: clka, clkb, and clkc, whose frequencies can possess any value within the specified range. additionally, the reference frequency can be obtained on any output. custom configurations with user-defined fea- tures and frequencies can be obtained by f illing out the custom configuration form located at the back of this data sheet and contacting your local cypress representative. the cy2081a can replace multiple metal can oscillators (mco) in a synchronous system, providing cost and board space savings to manufacturers. hence, this device is ideally suited for applications that require multiple, accurate, and sta- ble clocks synthesized from low-cost generators in small pack- ages. a hard disk drive is an example of such an application. in this case, clka drives the pll in the read controller, while clkb and clkc drive the mcu and associated sequencers. consider using the cy2291, cy2292, or cy2907 for applica- tions that require more than three output clo cks. pin configuration 2081?1 1 2 3 4 5 8 7 6 clka gnd xtalin xtalout v dd clkc clkb soic top view logic block diagram xtalout xtalin reference oscillator pll 1 clka 2081?2 clkb clkc eprom- configurable multiplexer and divide logic pll 2 pll 3 oe/pd /fs/suspend oe/pd /fs/suspend
cy2081a 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage ............................................... ? 0.5v to +7.0v dc input voltage ...................................... ? 0.5v to v dd +0.5v storage temperature ................................. ? 65 c to +150 c max. soldering temperature (10 sec.) .........................260 c junction temperature ...................................................150 c static discharge voltage ........................................... >2000v (per mil-std-883, method 3015) pin summary name number description clka 1 configurable clock output gnd 2 ground xtalin [1] 3 reference crystal input or external reference clock input xtalout [1, 2] 4 reference crystal feedback clkb 5 configurable clock output clkc 6 configurable clock output v dd 7 voltage supply oe / pd / fs / suspend 8 output control pin; either active-high output enable, active-low power down, clka frequency select, or active-low suspend input operating conditions [3] parameter description min. max. unit v dd supply voltage 4.5 (3.0) 5.5 (3.6) v t a operating temperature, ambient 0 70 c c l max. load capacitance per output 25 (15) pf f ref external reference crystal 10.0 25.0 mhz f ref external reference clock [4, 5] 1.0 30.0 mhz electrical characteristics v dd = 5v (3.3v) 10%, t a = 0 c to +70 c parameter description conditions min. typ. max. unit v oh high-level output voltage i oh = ? 4.0 ma 2.4 v v ol low-level output voltage i ol = 4.0 ma 0.4 v v ih high-level input voltage [6] except crystal pins 2.0 v v il low-level output voltage [6] except crystal pins 0.8 v i ih input high current v in = v dd ? 0.5v <100 150 a i il input low current v in = 0.5v <100 150 a i oz output leakage current three state outputs 250 a i dd v dd supply current [7] v dd = v dd max. 5v (3.3v) operation, c l = 25 pf (15 pf) 40 (24) 60 (40) ma i dds v dd power supply current in powerdown mode powerdown active, 5v operation 100 200 a notes: 1. for best accuracy, use a parallel-resonant crystal, c l =17 pf. 2. float xtalout pin if xtalin is driven by reference clock (as opposed to an external crystal). 3. electrical parameters are guaranteed with these operating conditions. values for 3.3v operation are shown in parentheses. 4. external input reference clock must have a duty cycle between 40% and 60%, measured at v dd /2. 5. please refer to application note ? crystal oscillator topics ? for information on ac-coupling the external input reference clock. 6. xtal inputs have cmos thresholds. 7. load = max, typical configuration, f ref = 14.318 mhz. specific configurations may vary.
cy2081a 3 switching characteristics [8] parameter name description min. typ. max. unit t 1 output period clock output range, 5v operation 10 [100 mhz] 2000 [500 khz] ns t 1 output period clock output range, 3.3v operation 12.5 [80 mhz] 2000 [500 khz] ns t 1a clock jitter [9] peak-to-peak period jitter, % of clock period (f out 4 mhz) <0.5 1 % t 1b clock jitter [9] peak-to-peak period jitter (4 mhz f out 16 mhz) <0.7 1 ns t 1c clock jitter [9] peak-to-peak period jitter (16 mhz < f out 50 mhz) <400 500 ps t 1d clock jitter [9] peak-to-peak period jitter (f out > 50 mhz) <250 350 ps output duty cycle [10] duty cycle for outputs, defined as t 2 t 1 [11] f out > 66.67 mhz 40% 50% 60% duty cycle for outputs, defined as t 2 t 1 [11] f out 66.67 mhz 45% 50% 55% t 3 rise time output clock rise time [12] at c l =25 pf (15 pf at 3.3v operation) 3 5 ns t 4 fall time output clock fall time [12] at c l =25 pf (15 pf at 3.3v operation) 2.5 4 ns t 5 frequency slew rate rate of change of frequency of clka 1 5 40 mhz/ ms t 6 power up stabiliza- tion time output clock stable time after power up < 25 50 ms switching waveforms notes: 8. guaranteed by design, not 100% tested. 9. jitter varies with configuration. all standard configurations sample tested at the factory conform to this limit. for more information on jitter, please refer to the application note: ? jitter in pll-based systems. ? 10. reference output duty cycle depends on xtalin duty cycle. 11. measured at 1.4v. 12. measured between 0.4v and 2.4v. all outputs duty cycle and rise/fall time 2081 ? 3 output t 3 t 4 t 2 t 1 2.4v 0.4v 0.4v 2.4v 3.3v 0v
cy2081a 4 document #: 38 ? 01038 ? ** test circuit 0.1 f v dd clk output c load gnd 2081 ? 4 7 2 outputs ordering information ordering code package name package type operating range cy2081asc ? xxx s8 8-pin (150-mil) soic 5.0v, commercial [13] cy2081asl ? xxx s8 8-pin (150-mil) soic 3.3v, commercial [13] note: 13. 0 c to +70 c
cy2081a ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams 8-lead (150-mil) soic s8
cy2081a 6 notes: if pin 8 is oe, pd or suspend , fill in only one value for clka buffered reference clock is available on all outputs. cy2081a configuration request form 1. operating voltage(circle one) 2. input reference frequency (circle one) 3.3v 5.0v default reference = 14.318 mhz. if a different reference is desired, specify the frequency in the box to the right (must be between 10 mhz and 25 mhz for crystal, 1 mhz and 30 mhz for external clock): 4. output configuration clkb clkc fill in the desired frequencies, specifying khz or mhz, for each output. please adhere to the notes at the right. contact your local cypress representative for assistance. after configuration, please fax the form to your local cypress crystal external clock 5. for cypress use only customer engineer fae/sales phone # fax # date 3. output control pin (pin 8) configuration (circle one) clka (fs=0) clka (fs=1) oe (default) pd fs suspend if the suspend option is desired, please circle what outputs must be suspended clka clkb clkc representative. customer configuration marking date quantity clka, clkb and clkc , outputs can range from 500 khz to 100 mhz (80 mhz at 3.3v)
|
