one-pll general purpose clock generator cy26111 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07095 rev. ** revised august 7, 2001 features benefits ? integrated phase-locked loop internal pll with up to 333 mhz internal operation low skew, low jitter, high-accuracy outputs meets critical timing requirements in complex system designs 3.3v operation with 2.5v output option enables application compatibility 16-tssop industry standard package saves on board space part number outputs input frequency output frequency range cy26111 4 25 mhz 3 x 25 mhz, 1 x 125 mhz output pin default frequency unit lclk1 7 25 mhz lclk2 8 25 mhz lclk3 9 25 mhz clk4 15 125 mhz logic block diagram xin xout lclk1 25 mhz output multiplexer and dividers pll osc. lclk3 25 mhz q p vco vddl avss avdd vss oe lclk2 25 mhz clk4 125 mhz vssl vdd 16-pin tssop cy26111 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl nc lclk1 xin xout vdd oe avss lclk3 lclk2 clk4 nc avdd vddl n/c pin configurations
cy26111 document #: 38-07095 rev. ** page 2 of 5 absolute maximum conditions recommended operating conditions summary name pin number description xin 1 reference input vdd 2 voltage supply avdd 3 analog voltage supply oe 4 output enable, oe = 0 three-state; oe = 1 active avss 5 analog ground vssl 6 lclk ground lclk 1 7 clock output 1 ? 25 mhz at v ddl level lclk 2 8 clock output 2 ? 25 mhz at v ddl level lclk 3 9 clock output 3 ? 25 mhz at v ddl level nc 10 no connect - reserved vddl 11 lclk voltage supply (2.5v or 3.3v) nc 12 no connect - reserved vss 13 ground nc 14 no connect - reserved clk 4 15 clock output 4 - 125 mhz xout [1] 16 reference output parameter description min. max. unit v dd supply voltage ? 0.5 7.0 v v ddl i/o supply voltage 7.0 v t j junction temperature 125 c digital inputs av ss ? 0.3v av dd + 0.3v v digital outputs referred to v dd v ss ? 0.3v v dd + 0.3v v digital outputs referred to v ddl v ss ? 0.3v v ddl +0.3v v electro-static discharge 2 kv parameter description min. typ. max. unit v dd operating voltage 3.0 3.3 3.6 v v ddl operating voltage 2.375 2.5 2.625 v t a ambient temperature 0 70 c c load max. load capacitance 15 pf f ref driven reference frequency 25 mhz note: 1. float xout if xin is externally driven.
cy26111 document #: 38-07095 rev. ** page 3 of 5 dc electrical characteristics ac electrical characteristics parame- ter [1] name description min. typ. max. unit i oh output high current v oh = v dd ? 0.5, v dd /v ddl = 3.3v 12 24 ma i ol output low current v ol = 0.5, v dd /v ddl = 3.3v 12 24 ma i oh output high current v oh = v ddl ? 0.5, v ddl = 2.5v 8 16 ma i ol output low current v ol = 0.5, v ddl = 2.5v 8 16 ma v ih input high voltage cmos levels, 70% of v dd 0.7 v dd v il input low voltage cmos levels, 30% of v dd 0.3 v dd c in input capacitance oe pin 7 pf i iz input leakage current oe pin 5 a i vdd supply current av dd /v dd current 30 ma i vddl supply current v ddl current (v ddl =3.6v) 10 ma i vddl supply current v ddl current (v ddl = 2.625v) 8 ma parameter [1] name description min. typ. max. unit dc duty cycle is defined in figure 1; t1/t2, 50% of v dd 40 50 60 % t 3 rising edge slew rate output clock rise time, 20% ? 80% of v dd /v ddl = 3.3v 0.8 1.4 v/ns t 3 rising edge slew rate output clock rise time, 20% ? 80% of v ddl = 2.5v 0.6 1.2 v/ns t 4 falling edge slew rate output clock fall time, 80% ? 20% of v dd /v ddl = 3.3v 0.8 1.4 v/ns t 4 falling edge slew rate output clock fall time, 80% ? 20% of v ddl = 2.5v 0.6 1.2 v/ns t5 skew delay between related outputs at rising edge 200 ps t9 clock jitter peak to peak period jitter 250 ps t10 pll lock time 3ms note: 2. not 100% tested. figure 1. duty cycle definition; dc = t2/t1. figure 2. rise and fall time definitions. t1 t2 clk 50% 50% t3 clk 80% 20% t4
cy26111 document #: 38-07095 rev. ** page 4 of 5 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. ordering information ordering code package name package type operating range operating voltage CY26111ZC z16 16-pin tssop commercial 3.3v test circuit 0.1 f v dd 0.1 f av dd clk out c load gnd outputs
cy26111 document #: 38-07095 rev. ** page 5 of 5 document title: cy26111 one-pll general purpose clock generator document number: 38-07095 rev. ecn no. issue date orig. of change description of change ** 107330 08/28/01 ckn new data sheet
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