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ht27lc020 otp cmos 256k 8-bit eprom block diagram 1 7th may 99 features operating voltage: +3.3v programming voltage C v pp =12.5v 0.2v C v cc =6.0v 0.2v high-reliability cmos technology latch-up immunity to 100ma from -1.0v to v cc +1.0v cmos and ttl compatible i/o low power consumption C active: 15ma max. C standby: 1 a typ. 256k 8-bit organization fast read access time: -120ns fast programming algorithm programming time 75 s typ. commercial and industrial temperature range two line controls (oe and ce ) standard product identification code package type C 32-pin dip/sop C 32-pin plcc commercial temperature ranges (0 cto+70 c) general description the ht27lc020 chip family is a low-power, 2048k (2,097,152) bit, +3.3v electrically one-time programmable (otp) read-only mem - ories (eprom). organized into 256k words with 8 bits per word, it features a fast single ad - dress location programming, typically at 75 m s per byte. any byte can be accessed in less than 120ns with respect to spec. this eliminates the need for wait states in high-performance mi - croprocessor systems. the ht27lc020 has separate output enable (oe ) and chip enable (ce ) controls which eliminate bus contention issues.

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pin assignment pin description pin name i/o/c/p description a0~a17 i address inputs dq0~dq7 i/o data inputs/outputs ce c chip enable oe c output enable pgm c program strobe nc no connection vpp p program voltage supply ht27lc020 2 7th may 99 ,- ,. ,( -/ -0 -* -1 -2 -3 -, -- -. -( ./ .0 .* . - , 3 2 1 * 0 / .( .. .- ., .3 .2 .1
& .* .3 ., 0 / .. .( '* '1 '2 '3 ', & .1 .2 .- * 1 2 3 , - . ( '( '. '- + 2 1 * 0 / .( .. .- ., ,. ,- . - , 3 -/ -* -1 -2 -3 -, -- -. ,( -0 .* .3 .2 .1 .0 ./ -( * 1 2 3 , - . ( '( .3 0 / .. .( '* ., ', '. '- + '3 '2 '1 & & .1 .2 .- .*
absolute maximum rating operation temperature commercial .................................................................................0 cto+70 c storage temperature....................................................................................................... 65 cto125 c applied vcc voltage with respect to gnd..................................................................... 0.6v to 7.0v applied voltage on input pin with respect to gnd ....................................................... 0.6v to 7.0v applied voltage on output pin with respect to gnd ............................................ 0.6v to v cc +0.5v applied voltage on a9 pin with respect to gnd .......................................................... 0.6v to 13.5v applied vpp voltage with respect to gnd .................................................................... 0.6v to 13.5v applied read voltage (functionality is guaranteed between these limits)................+3.0v to +3.6v note: these are stress ratings only. stresses exceeding the range specified under absolute maxi - mum ratings may cause substantial damage to the device. functional operation of this de - vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics read operation symbol parameter test conditions min. typ. max. unit v cc conditions v oh output high level 3.3v i oh = - 0.4ma 2.4 v v ol output low level 3.3v i ol =2.0ma 0.45 v v ih input high level 3.3v 2.0 v cc +0.5 v v il input low level 3.3v 0.3 0.8 v i li input leakage current 3.3v v in =0 to 3.6v 5 5 a i lo output leakage current 3.3v v out =0 to 3.6v 10 10 a i cc vcc active current 3.3v ce =v il , f=5mhz, i out =0ma 15 ma i sb1 standby current (cmos) 3.3v ce =v cc 0.3v 10 a i sb2 standby current (ttl) 3.3v ce =v ih 0.6 ma i pp vpp read/standby current 3.3v ce =oe =v il ,v pp =v cc 100 a ht27lc020 3 7th may 99
programming operation symbol parameter test conditions min. typ. max. unit v cc conditions v oh output high level 6v i oh = 0.4ma 2.4 v v ol output low level 6v i ol =2.0ma 0.45 v v ih input high level 6v 0.7v cc v cc +0.5 v v il input low level 6v - 0.5 0.8 v i li input load current 6v v in =v il ,v ih ? 5.0 a v h a9 product id voltage 6v 11.5 12.5 v i cc vcc supply current 6v 40 ma i pp vpp supply current 6v ce =v il 10 ma capacitance symbol parameter test conditions min. typ. max. unit v cc conditions c in input capacitance 3.3v v in =0v 812pf c out output capacitance 3.3v v out =0v 812pf c vpp vpp capacitance 3.3v v pp =0v 18 25 pf a.c. characteristics read operation symbol parameter test conditions 120 unit v cc conditions min. max. t acc address to output delay 3.3v ce =oe =v il 120 ns t ce chip enable to output delay 3.3v oe =v il 120 ns t oe output enable to output delay 3.3v ce =v il 45 ns t df ce or oe high to output float, whichever occurred first 3.3v 40 ns t oh output hold from address, ce or oe , whichever occurred first 3.3v 0 ns ht27lc020 4 7th may 99
programming operation ta=+25 c 5 c symbol parameter test conditions min. typ. max. unit v cc conditions t as address setup time 6v 2 s t oes oe setup time 6v 2 s t ds data setup time 6v 2 s t ah address hold time 6v 0 s t dh data hold time 6v 2 s t dfp output enable to output float delay 6v 0 130 ns t vps vpp setup time 6v 2 s t pw pgm program pulse width 6v 30 75 105 s t vcs vcc setup time 6v 2 s t ces ce setup time 6v 2 ns t oe data valid from oe 6v 150 s t prt vpp pulse rise time during programming 6v 2 s test waveforms and measurements utput test load ht27lc020 5 7th may 99 .4,& 5.+ /.36 ,4,7 2.4v 0.45v ac measurement level ac driving levels 2.0v 0.8v tr, tf<20ns (10% to 90%) note: c l =100pf including jig capacitance.
product identification code code pins hex data a0 a1 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 manufacturer 01000111001c device type 110000001002 continuation 00011111117f 10011111117f ht27lc020 6 7th may 99 functional description operation mode all the operation modes are shown in the table following. mode ce oe pgm a0 a1 a9 vpp output read v il v il x (2) x x x v cc dout output disable v il v ih xxx xv cc high z standby (ttl) v ih xxxx xv cc high z standby (cmos) v cc 0.3v xxxx x v cc high z program v il v ih v il xxxv pp d in program verify v il v il v ih xxxv pp d out product inhibit v ih xxxx xv pp high z manufacturer code (3) v il v il xv il v ih v h (1) v cc 1c device code (3) v il v il xv ih v ih v h (1) v cc 02 notes: (1) v h = 12.0v 0.5v (2) x=either v ih or v il (3) for manufacturer code and device code, a1=v ih , when a1=v il , both codes will read 7f
ht27lc020 7 7th may 99 programming of the ht27lc020 when the ht27lc020 is delivered, the chip has all 2048k bits in the one 2 , or high state. zeros are loaded into the ht27lc020 through programming. the programming mode is entered when 12.5 0.2v is applied to the vpp pin, oe is at v ih , and ce and pgm are v il . for programming, the data to be programmed is applied with 8 bits in parallel to the data pins. the programming flowchart in figure 3 shows the fast interactive programming algo - rithm. the interactive algorithm reduces pro - gramming time by using 30 sto105 s programming pulses and giving each address only as many pulses as is necessary in order to reliably program the data. after each pulse is applied to a given address, the data in that ad - dress is verified. if the data is not verified, ad - ditional pulses are given until it is verified or until the maximum number of pulses is reached while sequencing through each ad - dress of the ht27lc020. this process is re - peated while sequencing through each address of the ht27lc020. this part of the program - ming algorithm is done at v cc =6.0v to assure that each eprom bit is programmed to a suffi- ciently high threshold voltage. this ensures that all bits have sufficient margin. after the final address is completed, the entire eprom memory is read at v cc =v pp =5.25 0.25v to ver- ify the entire memory. program inhibit mode programming of multiple ht27lc020 in parallel with different data is also easily accomplished by using the program inhibit mode. except for ce , all like inputs of the parallel ht27lc020 may be common. a ttl low-level program pulse applied to an ht27lc020 ce input with vpp=12.5 0.2v, pgm low, and oe high will program that ht27lc020. a high-level ce input inhibits the ht27lc020 from being programmed. program verify mode verification should be performed on the pro - grammed bits to determine whether they were correctly programmed. the verification should be performed with oe and ce at v il , pgm at v ih , and vpp at its programming voltage. auto product identification the auto product identification mode allows the reading out of a binary code from an eprom that will identify its manufacturer and the type. this mode is intended for pro - gramming to automatically match the device to be programmed with its corresponding pro - gramming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when programming the ht27lc020. to activate this mode, the programming equip - ment must force 12.0 0.5v on the address line a9 of the ht27lc020. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from v il to v ih , when a1=v ih . all other address lines must be held at v ih during auto product identification mode. byte 0 (a0=v il ) represents the manufacturer code, and byte 1 (a0=v ih ), the device code. for ht27lc020, these two identifier bytes are given in the mode select table. all identifiers for the manufacturer and device codes will possess odd parity, with the msb (dq7) defined as the parity bit. when a1=v il , the ht27lc020 will read out the binary code of 7f, continuation code, to sig- nify the unavailability of manufacturer id codes. read mode the ht27lc020 has two control functions, both of which must be logically satisfied in or- der to obtain data at outputs. chip enable (ce ) is the power control and should be used for de - vice selection. output enable (oe ) is the out - put control and should be used to gate data to the output pins, independent of device selec - tion. assuming that addresses are stable, ad - dress access time (t acc ) is equal to the delay from ce to output (t ce ). data is available at the outputs (t oe ) after the falling edge of oe ,as - suming the ce has been low and addresses have been stable for at least t acc t oe .
ht27lc020 8 7th may 99 standby mode the ht27lc020 has cmos standby mode which reduces the maximum vcc current to 10 m a. it is placed in cmos standby when ce is at v cc 0.3v. the ht27lc020 also has a ttl-standby mode which reduces the maxi - mum vcc current to 0.6ma. it is placed in ttl-standby when ce is at v ih . when in standby mode, the outputs are in a high-impedance state, independent of the oe input. two-line output control function to accommodate multiple memory connections, a two-line control function is provided to allow for: low memory power dissipation assurance that output bus contention will not occur it is recommended that ce be decoded and used as the primary device-selection function, while oe be made a common connection to the read line from the system control bus. this assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. system considerations during the switch between active and standby conditions, transient current peaks are pro - duced on the rising and falling edges of chip enable. the magnitude of these transient cur - rent peaks is dependent on the output capaci - tance loading of the device. at a minimum, a 0.1 f ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and vpp to minimize tran - sient effects. in addition, to overcome the volt - age drop caused by the inductive effects of the printed circuit board traces on eprom arrays, a 4.7 f bulk electrolytic capacitor should be used between vcc and vpp for each eight de - vices. the location of the capacitor should be close to where the power supply is connected to the array.
ht27lc020 9 7th may 99 ## ##& 898: & 8 ; figure 1. a.c. waveforms for read operation ## 9
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ht27lc020 10 7th may 99
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ht27lc020 11 7th may 99 copyright
1999 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holtek semiconductor (shanghai) ltd. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 holmate technology corp. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885

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