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pcm3002 pcm3003 pcm3002 pcm3003 features l monolithic 20-bit ds adc and dac l 16-/20-bit input/output data l software control: pcm3002 l hardware control: pcm3003 l stereo adc: single-ended voltage input 64 x oversampling high performance thd+n: C86db snr: 90db dynamic range: 90db l stereo dac: single-ended voltage output analog low pass filter 8x oversampling digital filter high performance thd+n: C86db snr: 94db dynamic range: 94db l special features digital de-emphasis digital attenuation (256 steps) soft mute digital loop back power down: adc/dac independent l sampling rate: up to 48khz l system clock: 256f s , 384f s , 512f s l single +3v power supply l small package: 24-lead ssop international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 ? twx: 910-952-1111 internet: http://www.burr-brown.com/ ? faxline: (800) 548-6133 (us/canada only) ? cable: bbrcorp ? telex: 066-6491 ? fa x: (520) 889-1510 ? immediate product info: (800) 548-6132 16-/20-bit single-ended analog input/output stereo audio codecs tm description the pcm3002 and pcm3003 are low cost single chip stereo audio codecs (analog-to-digital and digital-to- analog converters) with single-ended analog voltage input and output. the adcs and dacs employ delta-sigma modulation with 64x oversampling. the adcs include a digital decimation filter, and the dacs include an 8x oversampling digital interpolation filter. the dacs also include digital attenuation, de-emphasis, infinite zero detection and soft mute to form a complete subsystem. pcm3002 and pcm3003 operate with left-justified, right-justified, or i 2 s data formats. pcm3002 and pcm3003 provide a power-down mode that operates on the adcs and dacs independently. fabricated on a highly advanced 0.6 m s cmos pro- cess, pcm3002 and pcm3003 are suitable for a wide variety of cost-sensitive consumer applications where good performance is required. pcm3002s multi-functions are controlled by soft- ware and the pcm3003s functions include de-empha- sis, power down, and audio data format selections, which are controlled by hardware. ? 1997 burr-brown corporation pds-1414b printed in u.s.a. august, 1998 lch in rch in analog front-end delta-sigma modulator decimation digital filter serial interface and mode control digital out digital in serial mode control system clock lch out rch out low pass filter and output buffer multi-level delta-sigma modulator oversampling interpolation digital filter
pcm3002/3003 2 specifications all specifications at +25 c, v dd = v cc = 3.0v, f s = 44.1khz, sysclk = 384f s , and 16-bit data, unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. price s and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. pcm3002e/3003e parameter conditions min typ max units digital input/output input logic input logic level: v ih (1, 2, 3) 0.7 x v dd vdc v il (1, 2, 3) 0.3 x v dd vdc input logic current: i in (2) 1 m a input logic current: i in (1) 100 m a output logic output logic level: v oh (5) i out = C1ma v dd C0.3 vdc v ol (5) i out = +1ma 0.3 vdc output logic level: v ol (4) i out = +1ma 0.3 vdc clock frequency sampling frequency (f s ) 32 44.1 48 khz system clock frequency 256f s 8.1920 11.2896 12.2880 mhz 384f s 12.2880 16.9344 18.4320 mhz 512f s 16.3840 22.5792 24.5760 mhz adc characteristics resolution 20 bits dc accuracy gain mismatch channel-to-channel 1.0 3.0 % of fsr gain error 2.0 5.0 % of fsr gain drift 20 ppm of fsr/ c bipolar zero error high-pass filter disabled (6) 1.7 % of fsr bipolar zero drift high-pass filter disabled (6) 20 ppm of fsr/ c dynamic performance (7) thd+n: v in = C0.5db C86 C80 db v in = C60db C28 db dynamic range a-weighted 86 90 db signal-to-noise ratio a-weighted 86 90 db channel separation 84 88 db digital filter performance passband 0.454f s hz stopband 0.583f s hz passband ripple 0.05 db stopband attenuation C65 db delay time 17.4/f s sec hpf frequency response C3db 0.019f s mhz analog input voltage range 0.60 v cc vp-p center voltage 0.50 v cc v input impedance 30 k w anti-aliasing filter frequency response C3db 150 khz
3 pcm3002/3003 specifications all specifications at +25 c, v dd = v cc = 3.0v, f s = 44.1khz, sysclk = 384f s , clkio input, 18-bit data, unless otherwise noted. pcm3002e/3003e parameter conditions min typ max units supply voltage +v dd , +v cc 1, +v cc 2 ...................................................................... +6.5v supply voltage differences ............................................................... 0.1v gnd voltage differences .................................................................. 0.1v digital input voltage ...................................................... C0.3 to v dd + 0.3v analog input voltage ......................................... C0.3 to v cc 1, v cc 2 + 0.3v power dissipation .......................................................................... 300mw input current ................................................................................... 10ma operating temperature range ......................................... C25 c to +85 c storage temperature ...................................................... C55 c to +125 c lead temperature (soldering, 5s) .................................................. +260 c (reflow, 10s) ..................................................... +235 c absolute maximum ratings package information package drawing product package number (1) pcm3002e/3003e 24-lead ssop 338 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. notes: (1) pins 7, 8, 17 and 18: rst, ml, md, mc for the pcm3002; pdad, pdda, dem1, dem0 for pcm3003 (schmitt-trigger input wit h 100k w typical internal pull-down resistor). (2) pins 9, 10, 11, 15: sysclk, lrcin, bckin, din (schmitt trigger input). (3) pin16: 20bit for pcm3003 (s chmitt-trigger input, 100k w typical internal pull-down resistor). (4) pin 12: dout. (5) pin 16: zflg (open drain output). (6) high pass filter for offset c ancel. (7) f in = 1khz, using audio precision system ii, rms mode with 20khz lpf, 400hz hpf used for performance calculation. (8) f out = 1khz, using audio precision system ii, rms mode with 20khz lpf, 400hz hpf used for performance calculation. (9) applies for voltages between 2.4v to 2.7v for 0 c to +70 c and 256f s /512f s operation (384f s not available). (10) sysclk, bckin, and lrcin are stopped. dac characteristics resolution 20 bits dc accuracy gain mismatch channel-to-channel 1.0 3 % of fsr gain error 1.0 5 % of fsr gain drift 20 ppm of fsr/ c bipolar zero error 1.0 % of fsr bipolar zero drift 20 ppm of fsr/ c dynamic performance (8) thd+n: v out = 0db (full scale) C86 C80 db v out = C60db C28 db dynamic range eiaj, a-weighted 88 94 db signal-to-noise ratio eiaj, a-weighted 88 94 db channel separation 86 91 db digital filter performance passband 0.445f s hz stopband 0.555f s hz passband ripple 0.17 db stopband attenuation C35 db delay time 11.1/f s sec analog output voltage range 0.60 x v cc vp-p center voltage 0.5 x v cc vdc load impedance ac-coupling 10 k w lpf frequency response f = 20khz C0.16 db power supply requirements voltage range: v cc , v dd C25 c to +85 c 2.7 3.0 3.6 vdc 0 c to +70 c (9) 2.4 3.0 3.6 vdc supply current: operation v cc = v dd = 3.0v 18 24 ma power-down v cc = v dd = 3.0v 50 m a power dissipation: operation v cc = v dd = 3.0v 54 72 mw power-down (10) v cc = v dd = 3.0v 150 m w temperature range operation C25 +85 c storage C55 +125 c thermal resistance, q ja 100 c/w
pcm3002/3003 4 v cc 1 v cc 1 v in r v ref l v ref r v in l pdad pdda sysclk lrcin bckin dout v cc 2 agnd1 agnd2 v com v out r v out l dem0 dem1 20bit din v dd dgnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pcm3003 v cc 1 v cc 1 v in r v ref l v ref r v in l rst ml sysclk lrcin bckin dout v cc 2 agnd1 agnd2 v com v out r v out l mc md zflg din v dd dgnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pcm3002 pin configurationpcm3002 pin configurationpcm3003 top view ssop top view ssop pin name i/o description 1v cc 1 adc analog power supply 2v cc 1 adc analog power supply 3v in r in adc analog input, rch 4v ref l adc reference, lch 5v ref r adc reference, rch 6v in l in adc analog input, lch 7 rst in reset, active low (1, 2) 8 ml in strobe pulse for mode control (1, 2) 9 sysclk in system clock input (2) 10 lrcin in sample rate clock input (f s ) (2) 11 bckin in bit clock input (2) 12 dout out data output 13 dgnd digital ground 14 v dd digital power supply 15 din in data input (2) 16 zflg out zero flag output, active low (3) 17 md in serial data for mode control (1, 2) 18 mc in bit clock for mode control (1, 2) 19 v out l out dac analog output, lch 20 v out r out dac analog output, rch 21 v com adc/dac common 22 agnd2 dac analog ground 23 agnd1 adc analog ground 24 v cc 2 dac analog power supply notes: (1) with 100k w typical internal pull-down resistor. (2) schmitt-trigger input. (3) open drain output. pin assignmentspcm3002 pin name i/o description 1v cc 1 adc analog power supply 2v cc 1 adc analog power supply 3v in r in adc analog input, rch 4v ref l adc reference, lch 5v ref r adc reference, rch 6v in l in adc analog input, lch 7 pdad in adc power down, active low (1, 2) 8 pdda in dac power down, active low (1, 2) 9 sysclk in system clock input (2) 10 lrcin in sample rate clock input (f s ) (2) 11 bckin in bit clock input (2) 12 dout out data output 13 dgnd digital ground 14 v dd digital power supply 15 din in data input 16 20bit in 20-bit format select (1, 2) 17 dem1 in de-emphasis control (1, 2) 18 dem0 in de-emphasis control 0 (1, 2) 19 v out l out dac analog output, lch 20 v out r out dac analog output, rch 21 v com adc/dac common 22 agnd2 dac analog ground 23 agnd1 adc analog ground 24 v cc 2 dac analog power supply note: (1) with 100k w typical internal pull-down resistor. (2) schmitt-trigger input. pin assignmentspcm3003
5 pcm3002/3003 typical performance curves adc section at t a = +25 c, v cc = v dd = 3.0v, f s = 44.1khz, f sysclk = 384f s , and f signal = 1khz, unless otherwise noted. thd+n vs temperature temperature (?) thd+n at ?.5db (%) 0.010 0.008 0.006 0.004 0.002 ?5 0 25 50 75 85 100 thd+n at ?0db (%) 5.0 4.0 2.0 3.0 1.0 ?0db 0.5db dynamic range and snr vs temperature temperature (?) dynamic range (db) 94 92 90 88 86 ?5 0 25 50 75 85 100 snr (db) 5.0 4.0 2.0 3.0 1.0 snr dynamic range dynamic range and snr vs supply voltage supply voltage (v) dynamic range (db) 94 92 90 88 86 2.4 2.7 3.0 3.3 3.6 snr (db) 94 92 90 88 86 dynamic range snr thd+n vs supply voltage supply voltage (v) thd+n at ?.50db (%) 0.010 0.008 0.006 0.004 0.002 2.4 2.7 3.0 3.3 3.6 thd+n at ?0db (%) 5.0 4.0 3.0 2.0 1.0 ?0db ?.5db thd+n vs sampling frequency f s (khz) thd+n at ?.5db (%) 0.010 0.008 0.006 0.004 0.002 32 44.1 48 thd+n at ?0db (%) 5.0 4.0 3.0 2.0 1.0 ?0db ?.5db dynamic range and snr vs sampling frequency f s (khz) dynamic range (db) 94 92 90 88 86 32 44.1 48 snr (db) 94 92 90 88 86
pcm3002/3003 6 typical performance curves dac section at t a = +25 c, v cc = v dd = 3.0v, f s = 44.1khz, f sysclk = 384f s , and f signal = 1khz, unless otherwise noted. thd+n vs temperature temperature (?) thd+n at fs (%) 0.010 0.008 0.006 0.004 0.002 ?5 0 25 50 75 85 100 thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 fs ?0db dynamic range and snr vs temperature temperature (?) dynamic range (db) 98 96 94 92 90 ?5 0 25 50 75 85 100 snr (db) 98 96 94 92 90 snr dynamic range thd+n vs supply voltage supply voltage (v) thd+n at fs (%) 0.010 0.008 0.006 0.004 0.002 2.4 2.7 3.0 3.3 3.6 thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 ?0db fs dynamic range and snr vs supply voltage supply voltage (v) dynamic range (db) 98 96 94 92 90 2.4 2.7 3.0 3.3 3.6 snr (db) 98 96 94 92 90 snr dynamic range thd+n vs sampling frequency and system clock f s (khz) thd+n at fs (%) 0.010 0.008 0.006 0.004 0.002 32 44.1 48 thd+n at ?0db (%) 4.0 3.0 2.0 1.0 0 ?0db 384f s 256f s , 512f s 384f s 256f s , 512f s fs dynamic range and snr vs sampling frequency and system clock f s (khz) dynamic range (db) 98 96 94 92 90 32 44.1 48 snr (db) 98 96 94 92 90 snr dynamic range 384f s 256f s , 512f s
7 pcm3002/3003 output spectrum (fs, n = 8192) frequency (khz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 51015 25 22 20 0 output spectrum (?0db, n = 8192) frequency (khz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 51015 25 20 22 0 output spectrum (fs, n = 8192) frequency (khz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 51015 25 20 22 0 output spectrum (fs, n = 8192) frequency (khz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 51015 25 22 20 0 typical performance curves output spectrum at t a = +25 c, v cc = v dd = 3.0v, f s = 44.1khz, f sysclk = 384f s , and f signal = 1khz, unless otherwise noted. dacs adcs thd+n vs signal level signal level (db) thd+n (%) 100 10 1 0.1 0.001 0.001 ?2 ?4 ?6 ?0 ?8 ?6 ?2 ?4 0 thd+n vs signal level signal level (db) thd+n (%) 100 10 1 0.1 0.001 0.001 ?2 ?4 ?6 ?0 ?8 ?6 ?2 ?4 0
pcm3002/3003 8 i cc + i dd vs sampling frequency f s (khz) i cc + i dd (ma) 20 19 18 17 16 15 32 44.1 48 adc & dac 512f s 256f s typical performance curves supply current at t a = +25 c, v cc = v dd = 3.0v, f s = 44.1khz, f sysclk = 384f s , din = bpz, and v in = bpz, unless otherwise noted. i cc + i dd vs temperature temperature (?) i cc + i dd (ma) i cc + i dd: power down and off (ma) 25 20 15 10 5 0 2.5 2.0 1.5 1.0 0.5 0 ?5 ?0 ? 25 50 75 100 adc dac power down & off adc & dac i cc + i dd vs supply voltage supply voltage (v) i cc + i dd (ma) i cc + i dd: power down and off (ma) 25 20 15 10 5 0 2.5 2.0 1.5 1.0 0.5 0 2.4 2.7 3.0 3.3 3.6 power down & off adc & dac adc dac
9 pcm3002/3003 typical performance curves at t a = +25 c, v cc = v dd = 3.0v, f s = 44.1khz, and f sysclk = 384f s , unless otherwise noted. adc digital filter overall characteristics normalized frequency (x f s hz) amplitude (db) 0 ?0 ?00 ?50 ?00 8162432 0 stopband attenuation characteristics normalized frequency (x f s hz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 0.2 0.4 0.6 0.8 1.0 0 passband ripple characteristics normalized frequency (x f s hz) amplitude (db) 0.2 0.0 ?.2 ?.4 ?.6 ?.8 ?.0 0.1 0.2 0.3 0.4 0.5 0 transient band characteristics normalized frequency (x f s hz) amplitude (db) 0 ? ? ? ? ? ? ? ? ? ?0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 ?.13db at 0.5 x f s high pass filter response normalized frequency (x f s /1000 hz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 0.1 0.2 0.3 0.4 0.5 0 high pass filter response normalized frequency (x f s /1000 hz) amplitude (db) 0.2 0.0 ?.2 ?.4 ?.6 ?.8 ?.0 1234 0
pcm3002/3003 10 typical performance curves at t a = +25 c, v cc = v dd = 3.0v, f s = 44.1khz, and f sysclk = 384f s , unless otherwise noted. anti-aliasing filter anti-aliasing filter overall frequency response frequency (hz) amplitude (db) 0 ?0 ?0 ?0 ?0 ?0 10 100 1k 10k 100k 1m 10m 0 anti-aliasing filter passband frequency response frequency (hz) amplitude (db) 0.2 0.0 ?.2 ?.4 ?.6 ?.8 ?.0 10 100 1k 10k 100k 0
11 pcm3002/3003 de-emphasis error (32khz) 0 3628 7256 10884 14512 0 4999.8375 9999.675 14999.5125 19999.35 0 5442 10884 16326 21768 frequency (hz) 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 de-emphasis error (44.1khz) frequency (hz) de-emphasis error (48khz) frequency (hz) error (db) error (db) error (db) de-emphasis frequency response (32khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 de-emphasis frequency response (44.1khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 de-emphasis frequency response (48khz) 0 5k 10k 15k 20k 25k frequency (hz) 0 ? ? ? ? ?0 ?2 level (db) level (db) level (db) typical performance curves at t a = +25 c, v cc = v dd = 3.0v, f s = 44.1khz, and f sysclk = 384f s , unless otherwise noted. dac digital filter 20 0 ?0 ?0 ?0 ?0 ?00 10 100 1k 10k 100k 1m 10m frequency (hz) level (db) internal analog filter frequency response (10hz~10mhz) 0 50k 100k 150k 0 ?0 ?0 ?0 ?0 ?00 level (db) overall frequency characteristics (f s = 44.1khz) frequency (hz) passband ripple characteristics (f s = 44.1khz) 0 ?.2 ?.4 ?.6 ?.8 ?.0 0 5k 10k 15k 20k level (db) frequency (hz) 0.15 0.10 0.05 0 ?.05 ?.10 ?.15 level (db) 1 frequency (hz) 10 100 1k 10k 100k internal analog filter frequency response (1hz~20khz)
pcm3002/3003 12 block diagram figure 1. analog front-end (single-channel). 30k w v in r 1 21 4 5 v com v ref l v ref r delta-sigma modulator (+) (? v ref + + 1.0? 4.7? + 4.7? + 4.7? interpolation filter 8x oversampling interpolation filter 8x oversampling multi-level delta-sigma modulator multi-level delta-sigma modulator clock reset and power down zero detect (1) rst (1) /pdad (2) sysclk zflg (1) agnd2 v cc 2 agnd1 v cc 1 pdda (1) reference mode control interface ml (1 ) 20bit (2 ) mc (1 ) /dem0 (2) md (1 ) /dem1 (2) serial data interface dout bckin lrcin din v in l v ref l v com v ref r v in r v out l v com v out r power supply dgnd v dd analog low-pass filter analog low-pass filter decimation and high pass filter delta-sigma modulator (? (+) analog front-end circuit decimation and high pass filter delta-sigma modulator adc dac (+) (? analog front-end circuit notes: (1) mc, md, ml, rst, and zflg are for pcm3002 only. (2) dem0, dem1, 20bit, pdad, and pdda are for pcm3003 only.
13 pcm3002/3003 pcm audio interface the four-wire digital audio interface for pcm3002/3003 is comprised of: lrcin (pin 10), bckin (pin 11), din (pin 15), and dout (pin 12). pcm3002/3003 can operate with four different data formats. the pcm3002 may be used with any of the four input/output data formats (formats 0 - 3), while the pcm3003 may only be used with selected input/ output formats (formats 0 - 1). for pcm3002, these formats are selected through program register 3 in the soft- ware mode. for the pcm3003, data formats are selected by 20bit (pin 16). figures 2, 3 and 4 illustrate audio data input/output format and timing. pcm3002/3003 can accept 32-, 48-, or 64-bit clocks (bckin) in one clock of lrcin. only 16-bit data formats can be selected when 32-bit clocks/lrcin are applied. figure 2. audio data input/output format. msb l?h r?h l?h r?h lsb lrcin bckin format 0: pcm3002/3003 din msb lsb dac: 16-bit, msb-first, right-justified adc: 16-bit, msb-first, left-justified 1 16 2 3 14 15 16 123 14 15 16 msb lsb lrcin bckin dout msb lsb 123 14 15 16 123 14 15 16 1 msb l?h r?h l?h r?h lsb lrcin bcin format 2: pcm3002 only din msb lsb dac: 20-bit, msb-first, left-justified adc: 20-bit, msb-first, left-justified 123 18 19 20 123 18 19 20 msb lsb lrcin bcin dout msb lsb 123 18 19 20 123 18 19 20 msb l?h r?h l?h r?h lsb lrcin bckin format 1: pcm3002/3003 din msb lsb dac: 20-bit, msb-first, right-justified adc: 20-bit, msb-first, left-justified 1 20 2 3 18 19 20 123 18 19 20 msb lsb lrcin bckin dout msb lsb 123 18 19 20 123 18 19 20 1 1 1
pcm3002/3003 14 figure 3. audio data input/output format. figure 4. audio data input/output timing. bckin pulse cycle time t bcy 300ns (min) bckin pulse width high t bch 120ns (min) bckin pulse width low t bcl 120ns (min) bckin rising edge to lrcin edge t bl 40ns (min) lrcin edge to bckin rising edge t lb 40ns (min) lrcin pulse width t lrp t bcy (min) din set-up time t dis 40ns (min) din hold time t dih 40ns (min) dout delay time to bckin falling edge t bdo 40ns (max) dout delay time to lrcin edge t ldo 40ns (max) rising time of all signals t rise 20ns (max) falling time of all signals t fall 20ns (max) t bch t bcy t bcl t lb t dih t dis t lrp t bl t ldo t bdo bckin lrcin din dout 0.5v dd 0.5v dd 0.5v dd 0.5v dd msb l-ch r-ch l-ch r-ch lsb lrcin bckin format 3: pcm3002 only din msb lsb dac: 20-bit, msb-first, i 2 s adc: 18-bit, msb-first, i 2 s 123 18 19 20 123 18 19 20 msb lsb lrcin bckin dout msb lsb 123 18 19 20 123 18 19 20
15 pcm3002/3003 system clock the system clock for pcm3002/3003 must be either 256f s , 384f s or 512f s , where f s is the audio sampling frequency. the system clock should be provided to sysclk (pin 9). pcm3002/3003 also has a system clock detection circuit which automatically senses if the system clock is operating at 256f s , 384f s , or 512f s . when 384f s or 512f s system clock is used, the clock is divded into 256f s automatically. the 256f s clock is used to operate the digital filter and the delta-sigma modulator. table i lists the relationship of typical sampling frequencies and system clock frequencies and figure 5 illustrates the system clock timing. reset pcm3002/3003 has an internal power-on reset circuit, as well as an external forced reset. the internal power-on reset initializes (resets) when the supply voltage v dd >2.0v (typ). external forced reset occurs when rst = low for pcm3002, or both, pdad = low and pdda = low for pcm3003. during v cc < 2.2v and/or internal initialize state (1024 system clocks count after v cc >2.2v) for power-on reset or during reset signal is forced to device or internal initialize state (1024 system clocks count after pdad = high or pdda = high) for external reset, the outputs of the dac are invalid and forced to gnd. the analog outputs are then forced to 0.5v cc during t dacdly1 (16384/f s ) after reset removal. the outputs of adc are also invalid, the digital outputs are forced to all zero during t adcdly1 (18432/f s ) after reset removal. figures 6 and 7 illustrate the power-on reset timing, external reset timing and adc, dac output response for reset and power-down on/off. sampling rate frequency system clock frequency (khz) (mhz) 256f s 384f s 512f s 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9340 22.5792 48 12.2880 18.4320 24.5760 table i. system clock frequencies. system clock pulse width high t sckh 12ns (min) system clock pulse width low t sckl 12ns (min) t sckh t sckl 1/256f s ,1/384f s ,or 1/512f s 0.7v "h" sysclk "l" 0.3v dd figure 5. system clock timing. 1024 system clock periods reset reset removal 4.4v 4.0v 3.6v v dd internal reset system clock figure 6. internal power-on reset timing. 1024 system clock periods reset reset removal system clock internal reset rstb-pin t rst t rst = 40ns minimum figure 7. external forced reset timing.
pcm3002/3003 16 synchronous asynchronous synchronization lost resynchronization within 1/f s synchronous normal normal t adcdly2 (32/f s ) t dacdly2 (32/f s ) undefined data v com (= 1/2 x v cc ) undefined data state of synchronization dac v out normal normal (1 ) zero adc dout notes: (1) the hpf transient response (exponentially attenuated signal from ?.2% dc of fsr with 200ms time constant) appears initially. reset power down gnd v com (0.5v cc ) ready/operation internal reset or power down adc dout dac v out zero zero normal data (1) t adcdly1 (18436/f s ) t dacdly1 (16384/f s ) reset removal or power down off note: (1) the hpf transient response (exponentially attenuated signal from ?.2% dc of fsr with 200ms time constant) appears initially. synchronization with the digital audio system pcm3002/3003 operates with lrcin synchronized to the system clock. pcm3002/3003 does not require any specific phase relationship between lrcin and the system clock, but there must be synchronization. if the synchronization be- tween the system clock and lrcin changes more than 6 bit clocks (bckin) during one sample (lrcin) period because of phase jitter on lrcin, internal operation of the dac will stop within 1/f s , and the analog output will be forced to bipolar zero (0.5v cc ) until the system clock is re-synchro- nized to lrcin followed by t dacdly2 delay time. internal operation of the adc will also stop within 1/f s , and the digital output codes will be set to bipolar zero until re- synchronization occurs followed by t adcdly2 delay time. if lrcin is synchronized with 5 or less bit clocks to the system clock, operation will be normal. figures 8 and 9 illustrate the effects on the output when synchronization is lost. before the outputs are forced to bipolar zero (<1/f s seconds), the outputs are not defined and some noise may occur. during the transitions between normal data and undefined states, the output has discontinuities, which will cause output noise. zero flag output: pcm3002 only pin 16 is an open-drain output for infinite zero detection flag on the pcm3002 only. when input data is continuously zero for 65,536 bckin cycles, zflg is low, otherwise, zflg is in a high-impedance state. figure 8. dac output and adc output for reset and power down. figure 9. dac output and adc output for loss of synchronization.
17 pcm3002/3003 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ml mc md figure 10. control data input format. mc pulse cycle time t mcy 100ns (min) mc pulse width low t mcl 40ns (min) mc pulse width high t mch 40ns (min) md setup time t mds 40ns (min) md hold time t mdh 40ns (min) ml low level time t mll 40ns + 1sysclk (min) ml high level time t mlh 40ns + 1sysclk (min) ml setup time t mls 40ns (min) ml hold time t mlh 40ns (min) sysclk: 1/256f s or 1/384f s ml mc md t mll t mlh t mch t mcl t mds t mcy t mls t mlh t mdh lsb figure 11. control data input timing. function adc/dac pcm3002 pcm3002 audio data format adc/dac 4 selectable formats 2 selectable formats lrcin polarity adc/dac o x loop-back control adc/dac o x left channel attenuation dac o x right channel attenuation dac o x attenuation control dac o x infinite zero detection dac o x dac output control dac o x soft mute control dac o x de-emphasis (off, 32khz, 44.1khz, 48khz) dac o o adc power-down control adc o o dac power-down control dac o o high pass filter operation adc o x table ii. selectable functions. operational control pcm3002 can be controlled in a software mode with a three-wire serial interface on mc (pin 18), md (pin 19), and ml (pin 8). table ii indicates selectable functions, and figure 10 illustrates control data input format and timing. pcm3003 only allows for control of 16-/20-bit data format, digital de-emphasis, and power-down control by hardware pins.
pcm3002/3003 18 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 register 0 res res res res res a1 a0 ldl al7 al6 al5 al4 al3 al2 al1 al0 register 1 res res res res res a1 a0 ldr ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 register 2 res res res res res a1 a0 pdad byps pdda atc izd out dem1 dem0 mut register 3 res res res res res a1 a0 res res res lop res fmt1 fmt0 lrp res mapping of program registers software control (pcm3002) pcm3002s special functions are controlled using four pro- gram registers which are 16 bits long. there are four distinct registers, with bits 9 and 10 determining which register is in use. table iii describes the functions of the four registers. register bit name name description register 0 a (1:0) register address 00 res reserved, should be set to 0 ldl dac attenuation data load control for lch al (7:0) attenuation data for lch register 1 a (1:0) register address 01 res reserved, should be set to 0 ldr dac attenuation data load control for rch ar (7:0) dac attenuation for rch register 2 a (1:0) register address 10 res reserved, should be set to 0 pdad adc power-down control pdda dac power-down control byps adc high-pass filter operation control atc dac attenuation data mode control izd dac infinite zero detection circuit control out dac output enable control dem (1:0) dac de-emphasis control mut lch and rch soft mute control register 3 a (1:0) register address 11 res reserved, should be set to 0 lop adc/dac analog loop-back control fmt (1:0) adc/dac audio data format selection lrp adc/dac polarity of lr-clock selection table iii. functions of the registers. program register 0 a (1:0): bit 10, 9 register address these bits define the address for register 0: a1 a0 0 0 register 0 res: bit 11 : 15 reserved these bits are reserved and should be set to 0. ldl: bit 8 dac attenuation data load control for left channel this bit is used to simultaneously set analog outputs of the left and right channels. the output level is controlled by al (7:0) attenuation data when this bit is set to 1. when set to 0, the new attenuation data will be ignored, and the output level will remain at the previous attenua- tion level. the ldr bit in register 1 has the equivalent function as ldl. when either ldl or ldr is set to 1, the output level of the left and right channels are simultaneously controlled. al (7:0): bit 7:0 dac attenuation data for left channel al7 and al0 are msb and lsb, respectively. the attenuation level (att) is given by: att = 20 x log 10 (att data/255) (db) al (7:0) attenuation level 00h C db (mute) 01h C48.16db :: feh C0.07db ffh 0db program register 1 a (1:0): register address these bits define the address for register 1: a1 a0 0 1 register 1 res: bit 15:11 reserved these bits are reserved and should be set to 0 ldr: bit 8 dac attenuation data load control for right channel this bit is used to simultaneously set analog outputs of the left and right channels. the output level is controlled by al (7:0) attenuation data when this bit is set to 1. when set to 0, the new attenuation data will be ignored, and the output level will remain at the previous attenua- tion level. the ldl bit in register 0 has the equivalent function as ldr. when either ldl or ldr is set to 1, the output level of the left and right channels are simultaneously controlled. ar (7:0): bit 7:0 dac attenuation data for left channel ar7 and ar0 are msb and lsb respectively. see register 0 for the attenuation formula.
19 pcm3002/3003 izd: bit 4 dac infinite zero detection circuit control this bit enables the infinite zero detection circuit in pcm3002. when enabled, this circuit will dis- connect the analog output amplifier from the delta- sigma dac when the input is continuously zero for 65,536 consecutive cycles of bckin. izd 0 infinite zero detection disabled 1 infinite zero detection enabled out: bit 3 dac output enable control when set to 1, the outputs are forced to v cc /2 (bipolar zero). in this case, all registers in pcm3002 hold the present data. therefore, when set to 0, the outputs return to the previous programmed state. out 0 dac outputs enabled (normal operation) 1 dac outputs disabled (forced to bpz) dem (1:0):bit 2,1 dac de-emphasis control these bits select the de-emphasis mode as shown below: dem1 dem0 0 0 de-emphasis 44.1khz on 0 1 de-emphasis off 1 0 de-emphasis 48khz on 1 1 de-emphasis 32khz on mut: bit 0 dac soft mute control when set to 1, both left and right-channel dac outputs are muted at the same time. this muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on. mut 0 mute disable 1 mute enable program register 3 a (1:0): bit 10:9 register address these bits define the address for register 3: a1 a0 1 1 register 3 res: bit 15:11, 8:6, 4:0 reserved these bits are reserved, and should be set to 0. program register 2 a (1:0): bit 10, 9 register address these bits define the address for register 2: a1 a0 1 0 register 2 res: bit 15:11, 6 reserved these bits are reserved and should be set to 0. pdad: bit 8 adc power-down control this bit places the adc section in the lowest power consumption mode. the adc operation is stopped by cutting the supply current to the adc section, and dout is fixed to zero during adc power-down mode enable. figure 8 illustrates the adc dout response for adc power-down on/ off. this does not affect the dac operation. pdad dac power-down 0 power down mode disabled 1 power down mode enabled byps: bit 7 adc high-pass filter bypass control this bit determines enables or disables the high- pass filter for the adc. byps 0 high-pass filter enabled 1 high-pass filter disabled (bypassed) pdda: bit 6 dac power-down control this bit places the dac section in the lowest power consumption mode. the dac operation is stopped by cutting the supply current to the dac section and v out is fixed to gnd during dac power- down mode enable. figure 8 illustrates the dac v out response for dac power-down on/off. this does not affect the adc operation. pdda 0 power-down mode disabled 1 power-down mode enabled atc: bit 5 dac attenuation channel control when set to 1, the register 0 attenuation data can be used for both dac channels. in this case, the register 1 attenuation data is ig- nored. atc 0 individual channel attenuation data control 1 common channel attenuation data control
pcm3002/3003 20 lop: bit 5 adc to dac loop-back control when this bit is set to 1, the adcs audio data is sent directly to the dac. the data format will default to i 2 s. in format 3 (i 2 s frame), loop- back is not supported. lop 0 loop-back disable 1 loop-back enable fmt (1,0) bit 3:2 audio data format select these bits determine the input and output audio data formats. fmt1 fmt0 dac adc data format data format name 0 0 16-bit, msb-first, 16-bit, msb-first, format 0 right-justified left-justified 0 1 20-bit, msb-first, 20-bit, msb-first, format 1 right-justified left-justified 1 0 20-bit, msb-first, 20-bit, msb-first, format 2 left-justified left-justified 1 1 20-bit, msb-first, 20-bit, msb-first, format 3 i 2 si 2 s lrp: bit 1 adc and dac polarity of lr-clock selection. applies only to formats 0 through 2. lrp 0 left-channel is h, right-channel is l. 1 left-channel is l, right-channel is h. figure 12. typical connection diagram for pcm3002/3003. 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 + 4.7 f (2) 4.7 f (2) + + + + 1 f 1 f control interface audio interface +3v analog v cc rch in lch in sysclk l/r clk bit clk data out data in 0.1 f and 10 f (1) 0.1 f and 10 f (1) 0.1 f and 10 f (1) 4.7 f (4) + 4.7 f (4) rch out lch out mc (6) /dem0 (7) md (6) /dem1 (7) rst (6) /pdad (7) ml (6) /pdda (7) zflg (6) /20bit (7) + + 4.7 f (4) + r pcm3002/3003 v cc 1 v cc 1 v in r v ref l v ref r v in l rst/pdad ml/pdda sysclk lrcin bckin dout v cc 2 agnd1 agnd2 v com v out r v out l mc/dem0 md/dem1 zflg/20bit din v dd dgnd notes: (1) 0.1 f ceramic and 10 f tantalum, typical, depending on power supply quality and pattern layout. (2) 4.7 f typical, gives settling time with 30ms (4.7 f x 6.4k w ) time constant in power on and power-down off period. (3) 1 f typical, gives 5.3hz cut-off frequency of input hpf in normal operation and gives settling time with 30ms (1 f x 30k w ) time constant in power on and power -down off period. (4) 4.7 f typical, gives 3.4hz cut-off frequency of output hpf in normal operation and gives settling time with 47ms (4.7 f x 10k w ) time constant in power on and power-down off period. (5) post low pass filter with r in >10k w , depending on requirement of system performance. (6) mc, md, ml, zflg, rst and 10k w pull-up resistor are for the pcm3002. (7) dem0, dem1, 20bit, pdad, pdda are for the pcm3003.
21 pcm3002/3003 pcm3003 data format control pcm3003 has hardwire functional control using pdad (pin 7) and pdda (pin 8) for power-down control, dem0 (pin 18) and dem1 (pin 17) for de-emphasis and 20bit (pin 16) for 16-/20-bit format selection. power-down control (pin 7 and pin 8) both the adcs and dacs power-down control pins place the adc or dac section in the lowest power con- sumption mode. the adc/dac operation is stopped by cutting the supply current to the adc/dac section. dout is fixed to zero during adc power-down mode enable and v out is fixed to gnd during dac power-down mode enable. figure 7 illustrates the adc and dac output re- sponse for power-down on/off. this does not affect the adc or dac operation. pdad pdda power down low low reset (adc/dac power-down enable) low high adc power-down/dac operate high low adc operate/dac power-down high high adc and dac normal operation de-emphasis control (pin 17 and pin 18) dem0 (pin 18) and dem1 (pin 17) are used as de-emphasis control pins. dem1 dem0 de-emphasis low low de-emphasis enable at 44.1khz low high de-emphasis disable high low de-emphasis enable at 48khz high high de-emphasis enable at 32khz 20bit audio data selection (pin 16) 20bit format low adc: 16-bit msb-first, left-justified dac: 16-bit msb-first, right-justified high adc: 20-bit msb-first, left-justified dac: 20-bit msb-first, right-justified application and layout considerations power supply bypassing the digital and analog power supply lines to pcm3002/ 3003 should be bypassed to the corresponding ground pins with both 0.1 m f ceramic and 10 m f tantalum capacitors as close to the device pins as possible. although pcm3002/ 3003 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power supply sequencing problems. if separate power supplies are used, back-to-back diodes are recom- mended to avoid latch-up problems. grounding in order to optimize the dynamic performance of pcm3002/ 3003, the analog and digital grounds are not connected internally. the pcm3002/3003 performance is optimized with a single ground plane for all returns. it is recommended to tie all pcm3002/3003 ground pins with low impedance connections to the analog ground plane. pcm3002/3003 should reside entirely over this plane to avoid coupling high frequency digital switching noise into the analog ground plane. voltage input pins a tantalum capacitor, between 1 m f and 10 m f, is recom- mended as an ac-coupling capacitor at the inputs. combined with the 30k w characteristic input impedance, a 1.0 m f cou- pling capacitor will establish a 5.3hz cut-off frequency for blocking dc. the input voltage range can be increased by adding a series resistor on the analog input line. this series resistor, when combined with the 30k w input impedance, creates a voltage divider and enables larger input ranges. v ref inputs a 4.7 m f to 10 m f tantalum capacitor is recommended be- tween v ref l, v ref r, and agnd1 to ensure low source impedance for the adcs references. these capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the adc reference. v com inputs a 4.7 m f to 10 m f tantalum capacitor is recommended be- tween v com and agnd1 to ensure low source impedance of the adc and dac common voltage. this capacitor should be located as close as possible to the v com pin to reduce dynamic errors on the dac common. system clock the quality of the system clock can influence dynamic performance of both the adc and dac in the pcm3002/ 3003. the duty cycle and jitter at the system clock input pin must be carefully managed. when power is supplied to the part, the system clock, bit clock (bckin) and a word clock (lcrin) should also be supplied simultaneously. failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipa- tion limit is exceeded. rst control if the capacitance between v ref and v com exceeds 2.2 m f, an external reset control delay time circuit must be used.
pcm3002/3003 22 external mute control for power-down on/off control without click noise which is generated by dac output dc level change, the external mute control is general required. the control sequence, which is external mute on, codec power-down on, sysclk stop and resume if necessary, codec power- down off, and external mute off is recommended. note that if sysclk is stopped when power-down condition for the pcm3002, all internal mode is initialized and need to re- write mode register value. theory of operation adc section the pcm3002/3003 adc consists of two reference circuits, a stereo single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (includ- ing digital high pass), and a serial interface circuit. the block diagram in this data sheet illustrates the architecture of the adc section, figure 1 shows the single-to-differential converter, and figure 14 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. an internal reference circuit with three external capacitors provides all reference voltages which are required by the adc, which defines the full scale range for the converter. the internal single-to-differential voltage converter saves the design, space and extra parts needed for external cir- cuitry required by many delta-sigma converters. the internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. the input signal is sampled at 64x oversampling rate, eliminating the need for a sample-and- hold circuit, and simplifying anti-alias filtering require- ments. the 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit dac. the delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. the high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. the 64f s one-bit data stream from the modulator is con- verted to 1f s 18-bit data words by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. the dc components are removed by a high pass filter function contained within the decimation filter. theory of operation dac section the delta-sigma dac section of pcm3002/3003 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. this section converts the oversampled input data to 5-level delta-sigma format. a block diagram of the 5-level delta- sigma modulator is shown in figure 14. this 5-level delta- sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. the combined oversampling rate of the delta- sigma modulator and the internal 8x interpolation filter is 64f s for a 256f s system clock. the theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in figure 15. + + + + + 5th sw-cap integrator 4th sw-cap integrator 3rd sw-cap integrator 2nd sw-cap integrator 1st sw-cap integrator + + + + + + 1-bit dac h(z) qn(z) analog in x(z) digital out y(z) y(z) = stf(z) ?x(z) + ntf(z) ?qn(z) signal transfer function noise transfer function stf(z) = h(z) / [1 + h(z)] ntf(z) = 1/ [1 + h(z)] comparator figure 13. simplified 5th-order delta-sigma modulator.
23 pcm3002/3003 out 64f s (256f s ) in 8f s 18-bit + + + 4 3 2 1 0 5-level quantizer + + z ? + + z ? + + z ? figure 14. 5-level delta-sigma modulator block diagram. 3rd order ds modulator frequency (khz) gain (?b) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 ?50 0 5 10 15 20 25 30 figure 15. quantization noise spectrum.

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