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| rev. 4153e?aero?06/02 1 features superscalar ieee floating-point-processor off-chip harvard architecture maximizes signal processing performance 50 ns, 20 mips instruction rate, single cycle execution 60 mflops peak, 40 mflops sustained performance 1024-point complex fft benchmark: 0.975 ms divide (y/x): 300 ns inverse square root (1/ /x): 450 ns 32-bit single-precision and 40-bit extended-precision ieee floating-point data formats 32-bit fixed-point formats, integer and fractional, with 80-bit accumulators ieee exception handling with interrupt on exception three independent computation units: multiplier, alu, and barrel shifter dual data address generators with indirect, immediate, modulo, and bit reverse addressing modes two off-chip memory transfers in parallel with instruction fetch and single-cycle multiply and alu operations multiply with add and subtract for fft butterfly computation efficient program sequencing with zero overhead looping: single-cycle loop setup single-cycle register file context switch 23ns external ram access time for zero-wait-state, 40 ns instruction execution ieee jtag standard 1149.1 test access port and on-chip emulation circuitry 223 cpga package for breadboarding 256 multi-layer quad flat pack, flat leads, for flight models fully compatible with analog devices adsp-21020 latch-up immune total dose better than 100 krad (si) seu immunity better than 50 mev/mg/cm 2 for 25 mhz specification (1) note: 1. contact atmel for availability. introduction atmel is manufacturing a radiation tolerant version of the analog devices adsp- 21020 32/40-bit floating-point dsp. the product is pin and code compatible with adi product, making system develop- ment straight forward and cost effective, using existing development tools and algorithms. notes: 1. design using patent from inpg-cnrs denis bessot/raoul velazco 2. product licensed from analog devices inc. rad. tolerant 32/40-bit ieee floating point dsp tsc21020f
2 tsc21020f 4153e?aero?06/02 functional block diagram 3 tsc21020f 4153e?aero?06/02 general description the tsc21020f is single-chip ieee floating-point processor optimized for digital signal processing applications (1) . its architecture is similar to that of analog devices' adsp- 2100 family of fixed-point dsp processors. fabricated in a high-speed, low-power and radiation tolerant cmos process, the tsc21020f has a 50ns instruction cycle time. with a high-performance on-chip instruc- tion cache, the tsc21020f can execute every instruction in a single cycle. the tsc21020f features: independent parallel computation units the arithmetic/logic unit (alu), multiplier and shifter perform single-cycle instructions. the units are architecturally arranged in parallel, maximizing computational throughput. a single multifunction instruction executes parallel alu and multiplier operations. these computation units support ieee 32-bit single-precision floating-point, extended preci- sion 40-bit floating-point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is used for transferring data between the computa- tion units and the data buses, and for storing intermediate results. this 10-port (16- register) register file, combined with the tsc21020f's harvard architecture, allows unconstrained data flow between computation units and off-chip memory. single-cycle fetch of instruction and two operands the tsc21020f uses a modified harvard architecture in which data memory stores data and program memory stores both instructions and data. because of its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch an operand from data memory, an operand from program memory, and an instruction from the cache, all in a single cycle. memory interface addressing of external memory devices by the tsc21020f is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. separate control lines are also generated for simplified addressing of page-mode dram. the tsc21020f provides programmable memory wait states, and external memory acknowledge controls allow interfacing to peripheral devices with variable access times. instruction cache the tsc21020f includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. the cache is selective-only the instructions whose fetches conflict with program memory data accesses are cached. this allows full-speed execution of core, looped operations such as digital filter multiply- accumulates and fft butterfly processing. hardware circular buffers the tsc21020f provides hardware to implement circular buffers in memory, which are common in digital filters and fourier transform implementations. it handles address pointer wraparound, reducing overhead (thereby increasing performance) and simplify- ing implementation. circular buffers can start and end at any location. flexible instruction set the tsc21020f's 48-bit instruction word accommodates a variety of parallel opera- tions, for concise programming. for example, the tsc21020f can conditionally execute a multiply, an add, a subtract and a branch in a single instruction. note: 1. it is fully compatible with analog devices adsp-21020 4 tsc21020f 4153e?aero?06/02 development system the tsc21020f is supported with a complete set of software and hardware develop- ment tools from analog devices. the adsp-21000 family development system from analog devices includes development software, an evaluation board and an in-circuit emulator. assembler creates relocatable, coff (common object file format) object files from adsp-21xxx assembly source code. it accepts standard c preprocessor directives for conditional assembly and macro processing. the algebraic syntax of the adsp-21xxx assembly language facilitates coding and debugging of dsp algorithms. linker/librarian the linker processes separately assembled object files and library files to create a sin- gle executable program. it assigns memory locations to code and to data in accordance with a user-defined architecture file that describes the memory and i/o configuration of the target system. the librarian allows you to group frequently used object files into a single library file that can be linked with your main program. simulator the simulator performs interactive, instruction-level simulation of adsp-21xxx code within the hardware configuration described by a system architecture file. it flags illegal operations and supports full symbolic disassembly. it provides an easy-to-use, window oriented, graphical user interface that is identical to the one used by the adsp- 21020 ez-ice emulator. commands are accessed from pull-down menus with a mouse. prom splitter formats an executable file into files that can be used with an industry-standard prom programmer. c compiler and runtime library the c compiler complies with ansi specifications. it takes advantage of the tsc21020f's high-level language architectural features and incorporates optimizing algorithms to speed up the execution of code. it includes an extensive runtime library with over 100 standard and dsp-specific functions. c source level debugger a full-featured c source level debugger that works with the simulator or ez-ice emula- tor to allow debugging of assembler source, c source, or mixed assembler and c. numerical c compiler supports ansi standard (x3j11.1) numerical c as defined by the numeric c exten- sions group. the compiler accepts c source input containing numerical c extensions for array selection, vector math operations, complex data types, circular pointers, and variably dimensioned arrays, and outputs adsp-21xxx assembly language source code. adsp- 21020 ez-lab ? evaluation board the ez-lab evaluation board is a general-purpose, standalone tsc21020f system that includes 32k words of program memory and 32k words of data memory as well as analog i/o. a pc rs-232 download path enables the user to download and run pro- grams directly on the ez-lab. in addition, it may be used in conjunction with the ez-ice emulator to provide a powerful software debug environment. adsp- 21020 ez-ice ? emulator this in-circuit emulator provides the system designer with a pc-based development environment that allows non-intrusive access to the tsc21020f's internal registers through the processor's 5-pin jtag test access port. this use of on-chip emulation circuitry enables reliable, full-speed performance in any target. the emulator uses the same graphical user interface as the adsp- 21020 simulator, allowing an easy transi- 5 tsc21020f 4153e?aero?06/02 tion from software to hardware debug. (see "target system requirements for use of ez-ice emulator" on page 27.) ? ez-lab and ez-ice are registered trademarks of analog devices, inc. additional information this data sheet provides a general overview of tsc21020f functionality. for additional information on the architecture and instruction set of the processor, refer to the adsp- 21020 user's manual. for development system and programming reference informa- tion, refer to the adsp-21000 family development software manuals and the adsp- 21020 programmer's quick reference. 6 tsc21020f 4153e?aero?06/02 architecture overview figure 1 shows a block diagram of the tsc21020f. the processor features: three computation units (alu, multiplier, and shifter) with a shared data register file two data address generators (dag 1, dag 2) program sequencer with instruction cache 32-bit timer memory buses and interface jtag test access port and on-chip emulation support computation units the tsc21020f contains three independent computation units: an alu, a multiplier with fixed-point accumulator, and a shifter. in order to meet a wide variety of processing needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit floating-point and 40-bit floating-point. the floating-point operations are single-precision ieee-compatible (ieee sta ndard 754/854). the 32-bit floating-point format is the stan- dard ieee format, whereas the 40-bit ieee extended- precision format has eight additional lsbs of mantissa for greater accuracy. the multiplier performs floating-point and fixed-point multiplication as well as fixed-point multiply/add and multiply/subtract operations. integer products are 64 bits wide, and the accumulator is 80 bits wide. the alu performs 45 standard arithmetic and logic opera- tions, supporting both fixed-point and floating-point formats. the shifter performs 19 different operations on 32-bit operands. these operations include logical and arithmetic shifts, bit manipulation, field deposit, and extract and derive exponent operations. the computation units perform single-cycle operations; there is no computation pipeline. the three units are connected in parallel rather than serially, via multiple-bus connec- tions with the 10-port data register file. the output of any computation unit may be used as the input of any unit on the next cycle. in a multifunction computation, the alu and multiplier perform independent, simultaneous operations. data register file the tsc21020f's general-purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. the register file has two sets (primary and alternate) of sixteen 40-bit registers each, for fast context switching. 7 tsc21020f 4153e?aero?06/02 figure 1. tsc21020f block diagram with a large number of buses connecting the registers to the computation units, data flow between computation units and from/to off-chip memory is unconstrained and free from bottlenecks. the 10-port register file and harvard architecture of the tsc21020f allow the following nine data transfers to be performed every cycle: off-chip read/write of two operands to or from the register file two operands supplied to the alu two operands supplied to the multiplier two results received from the alu and multiplier (three, if the alu operation is a combined addition/subtraction). the processor's 48-bit orthogonal instruction word supports fully parallel data transfer and arithmetic operations in the same instruction. address generators and program sequencer two dedicated address generators and a program sequencer supply addresses for memory accesses. because of this, the computation units need never be used to calcu- late addresses. because of its instruction cache, the tsc21020f can simultaneously fetch an instruction and data values from both off-chip program memory and off-chip data memory in a single cycle. the data address generators (dags) provide memory addresses when external mem- ory data is transferred over the parallel memory ports to or from internal registers. dual data address generators enable the processor to output two simultaneous addresses for dual operand reads and writes. dag 1 supplies 32-bit addresses to data memory. dag 2 supplies 24-bit addresses to program memory for program memory data accesses. each dag keeps track of up to eight address pointers, eight modifiers, eight buffer length values and eight base values. a pointer used for indirect addressing can be mod- ified by a value in a specified register, either before (premodify) or after (post-modify) 8 tsc21020f 4153e?aero?06/02 the access. to implement automatic modulo addressing for circular buffers, the tsc21020f provides buffer length registers that can be associated with each pointer. base values for pointers allow circular buffers to be placed at arbitrary locations. each dag register has an alternate register that can be activated for fast context switching. the program sequencer supplies instruction addresses to program memory. it controls loop iterations and evaluates conditional instructions. to execute looped code with zero overhead, the tsc21020f maintains an internal loop counter and loop stack. no explicit jump or decrement instructions are required to maintain the loop. the tsc21020f derives its high clock rate from pipelined fetch, decode and execute cycles. approximately 70% of the machine cycle is available for memory accesses; con- sequently, tsc21020f systems can be built using slower and therefore less expensive memory chips. instruction cache the program sequencer includes a high performance, selective instruction cache that enables three-bus operation for fetching an instruction and two data values. this two- way, set-associative cache holds 32 instructions. the cache is selective (only the instructions whose fetches conflict with program memory data accesses are cached), so the tsc21020f can perform a program memory data access and can execute the cor- responding instruction in the same cycle. the program sequencer fetches the instruction from the cache instead of from program memory, enabling the tsc21020f to simulta- neously access data in both program memory and data memory. context switching many of the tsc21020f's registers have alternate register sets that can be activated during interrupt servicing to facilitate a fast context switch. the data registers in the reg- ister file, dag registers and the multiplier result register all have alternate sets. registers active at reset are called primary registers; the others are called alternate reg- isters. bits in the mode1 control register determine which registers are active at any particular time. the primary/alternate select bits for each half of the register file (top eight or bottom eight registers) are independent. likewise, the top four and bottom four register sets in each dag have independent primary/alternate select bits. this scheme allows passing of data between contexts. interrupts the tsc21020f has four external hardware interrupts, nine internally generated inter- rupts, and eight software interrupts. for the external interrupts and the internal timer interrupt, the tsc21020f automatically stacks the arithmetic status and mode (mode1) registers when servicing the interrupt, allowing five nesting levels of fast service for these interrupts. an interrupt can occur at any time while the tsc21020f is executing a program. inter- nal events that generate interrupts include arithmetic exceptions, which allow for fast trap handling and recovery. timer the programmable interval timer provides periodic interrupt generation. when enabled, the timer decrements a 32-bit count register every cycle. when this count register reaches zero, the tsc21020f generates an interrupt and asserts its timexp output. the count register is automatically reloaded from a 32-bit period register and the count resumes immediately. 9 tsc21020f 4153e?aero?06/02 system interface figure 2 shows an tsc21020f basic system configuration. the external memory interface supports memory- mapped peripherals and slower mem- ory with a user-defined combination of programmable wait states and hardware acknowledge signals. both the program memory and data memory interfaces support addressing of page-mode drams. the tsc21020f's internal functions are supported by four internal buses: the program memory address (pma) and data memory address (dma) buses are used for addresses associated with program and data memory. the program memory data (pmd) and data memory data (dmd) buses are used for data associated with the two memory spaces. these buses are extended off chip. four data memory select (dms) signals select one of four user-configurable banks of data memory. similarly, two pro- gram memory select (pms) signals select between two user-configurable banks of program memory. all banks are independently programmable for 0-7 wait states. the px registers permit passing data between program memory and data memory spaces. they provide a bridge between the 48-bit pmd bus and the 40-bit dmd bus or between the 40-bit register file and the pmd bus. the pma bus is 24 bits wide allowing direct access of up to 16m words of mixed instruc- tion code and data. the pmd is 48 bits wide to accommodate the 48-bit instruction width. for access of 40-bit data the lower 8 bits are unused. for access of 32-bit data the lower 16 bits are ignored. the dma bus is 32 bits wide allowing direct access of up to 4 gigawords of data. the dmd bus is 40 bits wide. for 32-bit data, the lower 8 bits are unused. the dmd bus pro- vides a path for the contents of any register in the processor to be transferred to any other register or to any external data memory location in a single cycle. the data mem- ory address comes from one of two sources: an absolute value specified in the instruction code (direct addressing) or the output of a data address generator (indirect addressing). figure 2. basic system configuration external devices can gain control of the processor's memory buses from the tsc21020f by means of the bus request/grant signals (br and bg). to grant its buses in response to a bus request, the tsc21020f halts internal operations and places its 10 tsc21020f 4153e?aero?06/02 program and data memory interfaces in a high impedance state. in addition, three-state controls (dtms and pmts) allow an external device to place either the program or data memory interface in a high impedance state without affecting the other interface and without halting the tsc21020f unless it requires a memory access from the affected interface. the three-state controls make it easy for an external cache controller to hold the tsc21020f off the bus while it updates an external cache memory. jtag test and emulation support the tsc21020f implements the boundary scan testing provisions specified by ieee standard 1149.1 of the joint testing action group (jtag). the tsc21020f's test access port and on-chip jtag circuitry is fully compliant with the ieee 1149.1 specifi- cation. the test access port enables boundary scan testing of circuitry connected to the tsc21020f's i/o pins. the tsc21020f also implements on-chip emulation through the jtag test access port. the processor's eight sets of breakpoint range registers enable program execution at full speed until reaching a desired breakpoint address range. the processor can then halt and allow reading/writing of all the processor's internal registers and external mem- ories through the jtag port. 11 tsc21020f 4153e?aero?06/02 pin descriptions this section describes the pins of the tsc21020f. when groups of pins are identified with subscripts, e.g. pmd 47-0 , the highest numbered pin is the msb (in this case, pmd 47 ). inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi, and trst). those that are asynchronous (a) can be asserted asynchronously to clkin. note: o = output; i = input; s = synchronous; a = asynchronous; p = power supply; g = ground. pin name type function pma 23-0 o program memory address. the tsc21020f outputs an address in program memory on these pins. pmd 47-0 i/o program memory data. the tsc21020f inputs and outputs data and instructions on these pins. 32-bit fixed-point data and 32-bit single- precision floating-point data is transferred over bits 47-16 of the pmd bus. pms 1-0 o program memory select lines. these pins are asserted as chip selects for the corresponding banks of program memory. memory banks must be defined in the memory control registers. these pins are decoded program memory address lines and provide an early indication of a possible bus cycle. pmrd o program memory read strobe. this pin is asserted when the tsc21020f reads from program memory. pmwr o program memory write strobe. this pin is asserted when the tsc21020f writes to program memory. pmack i/s program memory acknowledge. an external device de-asserts this input to add wait states to a memory access. pmpage o program memory page boundary. the tsc21020f asserts this pin to signal that a program memory page boundary has been crossed. memory pages must be defined in the memory control registers. pmts i/s program memory three-state control. pmts places the program memory address, data, selects, and strobes in a high-impedance state. if pmts is asserted while a pm access is occurring, the processor will halt and the memory access will not be completed. pmack must be asserted for at least one cycle when pmts is de-asserted to allow any pending memory access to complete properly. pmts should only be asserted (low) during an active memory access cycle. dma 31-0 o data memory address. the tsc21020f outputs an address in data memory on these pins. dmd 39-0 i/o data memory data. the tsc21020f inputs and outputs data on these pins. 32-bit fixed-point data and 32-bit single-precision floating-point data is transferred over bits 39-8 of the dmd bus. dms 3-0 o data memory select lines. these pins are asserted as chip selects for the corresponding banks of data memory. memory banks must be defined in the memory control registers. these pins are decoded data memory address lines and provide an early indication of a possible bus cycle. 12 tsc21020f 4153e?aero?06/02 dmrd o data memory read strobe. this pin is asserted when the tsc21020f reads from data memory. dmwr o data memory write strobe. this pin is asserted when the tsc21020f writes to data memory. dmack i/s data memory acknowledge. an external device de-asserts this input to add wait states to a memory access. dmpage o data memory page boundary. the tsc21020f asserts this pin to signal that a data memory page boundary has been crossed. memory pages must be defined in the memory control registers. dmts i/s data memory three-state control. dmts places the data memory address, data, selects, and strobes in a high-impedance state. if dmts is asserted while dm access is occurring, the processor will halt and the memory access will not be completed. dmack must be asserted for at least one cycle when dmts is de-asserted to allow any pending memory access to complete properly. dmts should only be asserted (low) during an active memory access cycle. clkin i external clock input to the tsc21020f. the instruction cycle rate is equal to clkin. clkin may not be halted, changed, or operated below the specified frequency. reset i/a sets the tsc21020f to a known state and begins execution at the program memory location specified by the hardware reset vector (address). this input must be asserted (low) at power-up. irq 3-0 i/a interrupt request lines; may be either edge-riggered or level-sensitive. flag 3-0 i/o/a external flags. each is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. br i/a bus request. used by an external device to request control of the memory interface. when br is asserted, the processor halts execution after completion of the current cycle, places all memory data, addresses, selects, and strobes in a high-impedance state, and asserts bg. the processor continues normal operation when br is released. bg o bus grant. acknowledges a bus request (br), indicating that the external device may take control of the memory interface. bg is asserted (held low) until br is released. timexp o timer expired. asserted for four cycles when the value of tcount is decremented to zero. rcomp not available can be set to any voltage level. evdd p power supply (for output drivers), nominally + 5v dc (10 pins). egnd g power supply return (for output drivers); (16 pins). ivdd p power supply (for internal circuitry), nominally + 5v dc (4 pins). ignd g power supply return (for internal circuitry); (7 pins). pin name type function 13 tsc21020f 4153e?aero?06/02 tck i test clock. provides an asynchronous clock for jtag boundary scan. tms i/s test mode select. used to control the test state machine. tms has a 20 k ? internal pull-up resistor. tdi i/s test data input. provides serial data for the boundary scan logic. tdi hasa20k ? internal pull-up resistor. tdo o test data output. serial scan output of the boundary scan path. trst i/a test reset. resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the tsc21020f. trst has a 20 k ? internal pull-up resistor. nc no connect. no connects are reserved pins that must be left open and unconnected. table 1. pga pin configuration pga location pin name pga location pin name pga location pin name pga location pin name g16 dma0 b5 dmd25 k1 pmd9 l16 timexp g17 dma1 b6 dmd26 l3 pmd10 u12 rcomp f18 dma2 d6 dmd27 l2 pmd11 t11 clkin f17 dma3 c6 dmd28 m1 pmd12 t14 trst f16 dma4 a8 dmd29 m2 pmd13 r12 td0 f15 dma5 c7 dmd30 m3 pmd14 s13 tdi e18 dma6 d7 dmd31 m4 pmd15 u16 tms e17 dma7 b7 dmd32 n2 pmd16 u14 tck e16 dma8 b8 dmd33 n3 pmd17 h18 egnd d18 dma9 a10 dmd34 p1 pmd18 a3 egnd e15 dma10 c8 dmd35 p2 pmd19 a7 egnd d17 dma11 d8 dmd36 n4 pmd20 a11 egnd d16 dma12 b9 dmd37 s1 pmd21 a15 egnd c18 dma13 c9 dmd38 p3 pmd22 e1 egnd c17 dma14 b10 dmd39 r2 pmd23 g1 egnd d15 dma15 d10 dms0 p4 pmd24 l1 egnd b18 dma16 c11 dms1 r3 pmd25 l18 egnd b17 dma17 a12 dms2 s2 pmd26 r1 egnd c16 dma18 b11 dms3 t1 pmd27 r18 egnd d14 dma19 t13 dmwr s3 pmd28 t18 egnd c15 dma20 s11 dmrd r4 pmd29 u5 egnd b16 dma21 b12 dmpage t2 pmd30 u7 egnd pin name type function 14 tsc21020f 4153e?aero?06/02 a16 dma22 s12 dmts u1 pmd31 u11 egnd d13 dma23 t12 dmack t3 pmd32 u15 egnd c14 dma24 l17 pma0 r5 pmd33 d11 ignd b15 dma25 m18 pma1 s4 pmd34 g4 ignd b14 dma26 m15 pma2 u2 pmd35 g15 ignd d12 dma27 m16 pma3 s5 pmd36 l4 ignd c13 dma28 m17 pma4 t4 pmd37 l15 ignd a14 dma29 n17 pma5 r6 pmd38 r7 ignd b13 dma30 n16 pma6 u3 pmd39 r11 ignd c12 dma31 n15 pma7 u4 pmd40 a5 evdd h3 dmd0 p18 pma8 s6 pmd41 a9 evdd h4 dmd1 p17 pma9 t6 pmd42 a13 evdd e2 dmd2 r17 pma10 s7 pmd43 j1 evdd g3 dmd3 s18 pma11 u6 pmd44 j18 evdd d1 dmd4 p15 pma12 t7 pmd45 n1 evdd d2 dmd5 p16 pma13 r8 pmd46 n18 evdd f3 dmd6 s17 pma14 s8 pmd47 u9 evdd c1 dmd7 r16 pma15 r13 pms0 u13 evdd c2 dmd8 r15 pma16 t15 pms1 k18 evdd f4 dmd9 u18 pma17 u8 pmwr d9 ivdd e3 dmd10 s16 pma18 s9 pmrd j4 ivdd d3 dmd11 t17 pma19 s14 pmpage j15 ivdd b1 dmd12 u17 pma20 t8 pmts r9 ivdd e4 dmd13 r14 pma21 u10 pmack c10 nc b2 dmd14 s15 pma22 a17 bg s10 nc c3 dmd15 t16 pma23 a18 br t10 nc a2 dmd16 f2 pmd0 h16 flag0 t9 nc d4 dmd17 f1 pmd1 h15 flag1 k17 nc b3 dmd18 j3 pmd2 h17 flag2 t5 nc a4 dmd19 h2 pmd3 g18 flag3 g2 nc c4 dmd20 h1 pmd4 j17 irq0 b4 dmd21 j2 pmd5 j16 irq1 d5 dmd22 k4 pmd6 k16 irq2 a6 dmd23 k3 pmd7 k15 irq3 c5 dmd24 k2 pmd8 r10 reset table 1. pga pin configuration (continued) pga location pin name pga location pin name pga location pin name pga location pin name 15 tsc21020f 4153e?aero?06/02 table 2. mqfp pin configuration mqfp_f location pin name mqfp_f location pin name mqfp_f location pin name mqfp_f location pin name 1 ignd 65 ignd 129 ignd 193 ignd 2 ivdd 66 ivdd 130 ivdd 194 ivdd 3 dmd19 67 pmd25 131 pma19 195 dma15 4 dmd18 68 pmd26 132 pma18 196 egnd 5 dmd17 69 pmd27 133 pma17 197 dma16 6 dmd16 70 evdd 134 pma16 198 dma17 7 egnd 71 pmd28 135 egnd 199 dma18 8 dmd15 72 pmd29 136 pma15 200 dma19 9 dmd14 73 pmd30 137 pma14 201 evdd 10 dmd13 74 pmd31 138 pma13 202 dma20 11 dmd12 75 egnd 139 pma12 203 dma21 12 evdd 76 pmd32 140 evdd 204 dma22 13 dmd11 77 pmd33 141 pma11 205 dma23 14 dmd10 78 pmd34 142 pma10 206 egnd 15 dmd9 79 pmd35 143 pma9 207 dma24 16 dmd8 80 evdd 144 pma8 208 dma25 17 ignd 81 ignd 145 ignd 209 ignd 18 ivdd 82 ivdd 146 ivdd 210 ivdd 19 egnd 83 pmd36 147 egnd 211 dma26 20 dmd7 84 pmd37 148 pma7 212 dma27 21 dmd6 85 pmd38 149 pma6 213 evdd 22 dmd5 86 pmd39 150 pma5 214 dma28 23 dmd4 87 egnd 151 pma4 215 dma29 24 evdd 88 pmd40 152 evdd 216 dma30 25 dmd3 89 pmd41 153 pma3 217 dma31 26 dmd2 90 pmd42 154 pma2 218 egnd 27 dmd1 91 pmd43 155 pma1 219 dmpage 28 dmd0 92 evdd 156 pma0 220 br 29 egnd 93 pmd44 157 egnd 221 bg 30 pmd0 94 pmd45 158 timexp 222 dms0 31 pmd1 95 pmd46 159 evdd 223 dms1 32 pmd2 96 pmd47 160 egnd 224 evdd 33 ignd 97 ignd 161 ignd 225 ignd 34 ivdd 98 ivdd 162 ivdd 226 ivdd 35 pmd3 99 egnd 163 irq3 227 dms2 16 tsc21020f 4153e?aero?06/02 instruction set summary the tsc21020f instruction set provides a wide variety of programming capabilities. every instruction assembles into a single word and can execute in a single processor cycle. multifunction instructions enable simultaneous multiplier and alu operations, as well as computations executed in parallel with data transfers. the addressing power of the tsc21020f gives flexibility in moving data both internally and externally. the tsc21020f assembly language uses an algebraic syntax for ease of coding and readability. 36 evdd 100 pmts 164 irq2 228 dms3 37 pmd4 101 pmwr 165 irq1 229 dmd39 38 pmd5 102 pmack 166 irq0 230 dmd38 39 pmd6 103 pmrd 167 evdd 231 egnd 40 pmd7 104 rcmp 168 flag0 232 dmd37 41 egnd 105 evdd 169 flag1 233 dmd36 42 pmd8 106 reset 170 flag2 234 dmd35 43 pmd9 107 clkin 171 flag3 235 dmd34 44 pmd10 108 dmrd 172 egnd 236 evdd 45 pmd11 109 dmack 173 dma0 237 dmd33 46 evdd 110 dmwr 174 dma1 238 dmd32 47 pmd12 111 evdd 175 dma2 239 dmd31 48 pmd13 112 dmts 176 dma3 240 dmd30 49 ignd 113 ignd 177 ignd 241 ignd 50 ivdd 114 ivdd 178 ivdd 242 ivdd 51 pmd14 115 tck 179 evdd 243 egnd 52 pmd15 116 tms 180 dma4 244 dmd29 53 egnd 117 tdi 181 dma5 245 dmd28 54 pmd16 118 tdo 182 dma6 246 dmd27 55 pmd17 119 trst 183 dma7 247 dmd26 56 pmd18 120 pmpage 184 egnd 248 evdd 57 pmd19 121 pms0 185 dma8 249 dmd25 58 evdd 122 pms1 186 dma9 250 dmd24 59 pmd20 123 egnd 187 dma10 251 dmd23 60 pmd21 124 pma23 188 dma11 252 egnd 61 pmd22 125 pma22 189 evdd 253 dmd22 62 pmd23 126 pma21 190 dma12 254 dmd21 63 egnd 127 pma20 191 dma13 255 dmd20 64 pmd24 128 evdd 192 dma14 256 evdd table 2. mqfp pin configuration (continued) mqfp_f location pin name mqfp_f location pin name mqfp_f location pin name mqfp_f location pin name 17 tsc21020f 4153e?aero?06/02 the instruction types are grouped into four categories: compute and move or modify program flow control immediate move miscellaneous the instruction types are numbered; there are 22 types. some instructions have more than one syntactical form; for example, instruction 4 has four distinct forms. the instruc- tion number itself has no bearing on programming, but corresponds to the opcode recognized by the tsc21020f device. because of the width and orthogonality of the instruction word, there are many possible instructions. for example, the alu supports 21 fixed-point operations and 24 floating- point operations; each of these operations can be the compute portion of an instruction. the following pages provide an overview and summary of the tsc21020f instruction set. for complete information, see the adsp-21020 user's manual from analog devices. for additional reference information, see the adsp- 21020 programmer's quick reference from analog devices. this section also contains several reference tables for using the instruction set. table 3 describes the notation and abbreviations used. table 4 lists all condition and termination code mnemonics. table 5 lists all register mnemonics. table 6 through 9 list the syntax for all compute (alu, multiplier, shifter or multifunction) operations. table 10 lists interrupts and their vector addresses. 18 tsc21020f 4153e?aero?06/02 compute and move or modify instructions 1. compute, | dm(ia, mb) = dreg1 || pm(ic, md) = dreg2 | | dreg1= dm(ia, mb) || dreg2 =pm5ic, md) | 2. if condition compute ; 3a. if condition compute, | dm(mb, ia) | = ureg ; | pm(ic, md) | 3b. if condition compute, | dm(mb, ia) | = ureg ; | pm(md, ic) | 3c. if condition compute, ureg = | dm(ia, mb) | ; | pm(ic, md) | 3d. if condition compute, ureg = | dm(mb, ia) | ; | pm(md, ic) | 4a. if condition compute, | dm(ia, < data6 >) | = dreg ; | pm(ic, < data6 >) | 4b. if condition compute, | dm(ia, < data6 >,ia) | = dreg ; | pm(ic, < data6 >,ic) | 4c. if condition compute, dreg = | dm(mb, ia) | | pm(md, ic) | 4d. if condition compute, dreg = | dm(ia, < data6 >,ia) | ; | pm(ic, < data6 >,ic) | 5. if condition compute, ureg1 = ureg2; 6a. if condition shiftimm , | dm(ia, mb) | = dreg ; | pm(ic, md) | 6b. if condition shiftimm , | dm(ia, mb) | = dreg ; | pm(ic, md) | 7. if condition compute, modify | dm(ia, mb) | ; | pm(ic, md) | program flow control instructions 8. if condition | jump || < addr24 > | ( | db | ); | call || (pc, < reladdr24 >) || la | | db,la | 9. if condition | jump || < md, ic > | ( | db | ); | call || (pc, < reladdr6 >) || la | | db, la | 11. if condition | rts | ( | db | ), compute ; | rti || la | | db,la | 12. lcntr = | < data16 > | ,do | < addr24 > | until lce; | ureg || (pc, < reladdr24 >) | 13. do | < addr24 > | until termination; | (pc, < reladdr24 >) | note: db = delayed branch la = loop abort (pop loop pc stacks on branch) immediate move instructions 14a. | dm < addr32 > | = ureg ; | pm < addr24 > | 14b. ureg = | dm < addr32 > | ; | pm < addr24 > | 15a. | dm (< data32 >, ia) | = ureg ; | pm (< data24 >, ic) | 15b. ureg = | dm < data32 >, ia | ; | pm < data24 >, ic | 16. | dm(ia,mb) | = < data32 >; | pm(ic,md) | 17. ureg = < data32 >; 19 tsc21020f 4153e?aero?06/02 miscellaneous instructions 18. bit | set | sreg < data32 > : | clr | | tgl | | tst | | xor | 19a. modify | (ia, < data32 > |; | ic < data32 > | 19b. bitrev (ia, < data32 >) ; 20. | push | loop, | push | sts ; | pop || pop | 21. nop; 22. idle; table 3. syntax notation conventions notation meaning uppercase explicit syntax - assembler keyword (notation only; assembler is not case- sensitive and lowercase is the preferred programming convention) ; instruction terminator , separates parallel operations in an instruction italics optional part of instruction | between lines | list of options (choose one) 20 tsc21020f 4153e?aero?06/02 table 4. condition and termination codes name description eq alu equal to zero ne alu not equal to zero ge alu greater than or equal to zero lt alu less than zero le alu less than or equal to zero gt alu greater than zero ac alu carry not ac not alu carry av alu overflow not av not alu overflow mv multiplier overflow not mv not multiplier overflow ms multiplier sign not ms not multiplier sign sv shifter overflow not sv not shifter overflow sz shifter zero not sz not shifter zero flag0_in flag 0 not flag0_in not flag 0 flag1_in flag 1 not flag1_in not flag 1 flag2_in flag 2 not flag2_in not flag 2 flag3_in flag 3 not flag3_in not flag 3 tf bittestflag not tf not bit test flag lce loop counter expired (do until) not lce loop counter not expired (if) forever always false (do until) true always true (if) note: in a conditional instruction, the execution of the entire instruction is based on the speci- fied condition. 21 tsc21020f 4153e?aero?06/02 table 5. universal registers name function register file r15-r0 register file locations program sequencer pc (1) program counter; address of instruction currently executing pcstk top of pc stack pcstkp pc stack pointer faddr (1) fetch address daddr (1) decode address laddr loop termination address, code; top of loop address stack curlcntr current loop counter; top of loop count stack lcntr loop count for next nested counter-controlled loop data address generators i7-i0 dag1 index registers m7-m0 dag1 modify registers l7-l0 dag1 length registers b7-b0 dag1 base registers i15-i8 dag2 index registers m15-m8 dag2 modify registers l15-l8 dag2 length registers b15-b8 dag2 base registers bus exchange px1 pmd-dmd bus exchange 1 (16 bits) px2 pmd-dmd bus exchange 2 (32 bits) px 48-bit px1 and px2 combination timer tperiod timer period tcount timer counter memory interface dmwait wait state and page size control for data memory dmbank1 data memory bank 1 upper boundary dmbank2 data memory bank 2 upper boundary 22 tsc21020f 4153e?aero?06/02 dmbank3 data memory bank 3 upper boundary dmadr (1) copy of last data memory address pmwait wait state and page size control for program memory pmbank1 program memory bank 1 upper boundary pmadr (1) copy of last program memory address system register mode1 mode control bits for bit-reverse, alternate registers, interrupt nesting and enable, alu saturation, floating-point rounding mode and boundary mode2 mode control bits for interrupt sensitivity, cache disable and freeze, timer enable, and i/o flag configuration irptl interrupt latch imask interrupt mask imaskp interrupt mask pointer (for nesting) astat arithmetic status flags, bit test, i/o flag values, and compare accumulator stky sticky arithmetic status flags, circular buffer overflow flags, stack status flags (not sticky) ustat1 user status register 1 ustat2 user status register 2 note: 1. read-only refer to user's manual for bit-level definitions of each register. table 6. alu compute operations fixed-point floating-point rn = rx + ry fn = fx + fy rn = rx - ry fn = fx - fy rn = rx + ry, rm = rx - ry fn = fx + fy, fm = fx - fy rn = rx + ry + ci fn = abs (fx + fy) rn = rx - ry + ci - 1 fn = abs (fx - fy) rn=(rx+ry)/2 fn=(fx+fy)/2 comp(rx, ry) comp(fx, fy) rn = -rx fn = -fx rn = abs rx fn = abs fx rn = pass rx fn = pass fx rn = min(rx, ry) fn = min(fx, fy) rn = max(rx, ry) fn = max(fx, fy) table 5. universal registers (continued) name function 23 tsc21020f 4153e?aero?06/02 rn = clip rx by ry fn = clip fx by fy rn = rx + ci fn = rnd fx rn = rx + ci - 1 fn = scalb fx by ry rn = rx + 1 rn = mant fx rn = rx - 1 rn = logb fx rn = rx and ry rn = fix fx by ry rn = rx or ry rn = fix fx rn = rx xor ry fn = float rx by ry rn = not rx fn = float rx fn = recips fx fn = rsqrts fx fn = fx copysign fy note: rn, rx, ry r15-r0; register file location, fixed-point fn, fx, fy f15-f0; register file location, floating point table 6. alu compute operations (continued) fixed-point floating-point 24 tsc21020f 4153e?aero?06/02 multiplier compute operations rn, rx, ry r15-r0; register file location, fixed-point fn, fx, fy f15-f0; register file location, floating-point mrxf mr2f, mr1f, mr0f; multiplier result accumulators, foreground mrxb mr2b, mr1b, mr0b; multiplier result accumulators, background ( | x-input || y-input || data format | ) | rounding | s signed input u unsigned input i integer input(s) f fractional input(s) fr fractional inputs, rounded output (sf) default format for 1-input operations (ssf) default format for 2-input operations rn mrf mrb = rx * ry( s u s u f i fr ) fn = fx * fy rn rn mrf mrb = = = = mr f mr b mr f mr b + rx * ry s u s u f i fr ) rn rn mr f mrb = = = = mr f mr b mr f mr b rx * ry ( s u s u f i fr rn rn mrf mrb = = = = sat m rf sat m rb sat m rf sat m rb ( si ) ( ui) ( sf) ( uf ) rn rn mr f mrb rn d mrf rnd mrb rn d mrf rnd mrb ( sf) ( uf ) mrf mrb = 0 mrxf mrxb = rn rn = xf mr mrxb 25 tsc21020f 4153e?aero?06/02 table 7. shifter and shifter immediate compute operations shifter shifter immediate rn = lshift rx by ry rn = rn or lshift rx by ry rn = ashift rx by ry rn=rnorashiftrxbyry rn = rot rx by ry rn = bclr rx by ry rn = bset rx by ry rn = btgl rx by ry btst rx by ry rn = fdep rx by ry rn = rn or fdep rx by ry rn = fdep rx by ry (se) rn = rn or fdep rx by ry (se) rn = fext rx by ry rn = fext rx by ry (se) rn = exp rx rn = exp rx (ex) rn = leftz rx rn = lefto rx rn = lshift rx by 26 tsc21020f 4153e?aero?06/02 table 9. multifunction compute operations floating-point fm = f3-0 (1) f7-4, fa = f11-8 + f15-12 fm = f3-0 (1) f7-4, fa = f11-8 - f15-12 fm = f3-0 (1) f7-4, fa = float r11-8 by r15-12 fm = f3-0 (1) f7-4, fa = fix r11-8 by r15-12 fm = f3-0 (1) f7-4, fa = (f11-8 + f15-12)/2 fm = f3-0 (1) f7-4, fa = abs f11-8 fm = f3-0 (1) f7-4, fa = max (f11-8, f15-12) fm = f3-0 (1) f7-4, fa = min (f11-8 + f15-12) fm = f3-0 (1) f7-4, fa = f11-8 + f15-12, fs = f11-8 - f15-12 ra, rm any register file location (fixed-point) r3-0 r3, r2, r1, r0 r7-4 r7, r6, r5, r4 r11-8 r11,r10,r9,r8 r15-12 r15, r14, r13, 12 fa, fm any register file location (floating-point) f3-0 f3, f2, f1, f0 f7-4 f7, f6, f5, f4 f11-8 f11, f10, f9, f8 f15-12 f15, f14, f13, f12 (ssf) x-input signed, y-input signed, fractional inputs (ssfr) x-input signed, y-input signed, fractional inputs, rounded output table 10. interrupt vector addresses and priorities no vector address (hex) function 0 0x00 reserved 1 (1) 0x08 reset 2 0x10 reserved 3 0x18 status stack or loop stack overflow or pc stack full 4 0x20 timer = 0 (high priority option) 50x28 irq3asserted 60x30 irq2asserted 70x38 irq1asserted 80x40 irq0asserted 9 0x48 reserved 10 0x50 reserved 11 0x58 dag 1 circular buffer 7 overflow 12 0x60 dag 2 circular buffer 15 overflow 27 tsc21020f 4153e?aero?06/02 13 0x68 reserved 14 0x70 timer = 0 (low priority option) 15 0x78 fixed-point overflow 16 0x80 floating-point overflow 17 0x88 floating-point underflow 18 0x90 floating-point invalid operation 19-23 0x98-0xb8 reserved 24-31 0xc0-oxf8 user software interrupts note: 1. nonmaskable table 10. interrupt vector addresses and priorities (continued) no vector address (hex) function 28 tsc21020f 4153e?aero?06/02 electrical characteristics absolute maximum ratings recommended operating conditions esd sensitivity the tsc21020f features proprietary input protection circuitry to dissipate high-energy discharges (human body model). per method 3015 of mil-std-883, the tsc21020f has been classified as a class 2 devices, with the ability to withstand up to 2000v esd. prosper esd precautions are strongly recommended to avoid functional damage or per- formance degradation. charges readily accumulate on the human body and test equipment and discharge without detection. unused devices must be stored in conduc- tive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. dc parameters supply voltage .....................................................-0.5v to + 7v input voltage............................................ -0.5v to vdd + 0.5v output voltage swing .............................. -0.5v to vdd + 0.5v load capacitance ..........................................................200 pf operating temperature range (ambient)..... -55 cto+125 c storage temperature range ........................ -65 cto+150 c *note: stresses above those listed under "absolute maximum ratings" may cause permanent dam- age to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter mil range unit min max v dd supply voltage 4.50 5.50 v t amb ambient operating temperature -55 +125 c parameter test conditions min max unit v ih hi-level input voltage 1 v dd = max 2.0 v v ihcr hi-level input voltage 2, 12 v dd = max 3.0 v v il lo-level input voltage 1, 12 v dd =min 0.8 v v ilc lo-level input voltage 2 v dd =min 0.6 v v oh hi-level output voltage 3, 11 v dd =min,i oh =-1.0ma 2.4 v v ol lo-level output voltage 3, 11 v dd =min,i ol =4.0ma 0.4 v i ih hi-level input current 4, 5 v dd =max,v in =v dd max 10 a i il lo-level input current 4 v dd =max,v in =0v 10 a i ilt lo-level input current 5 v dd =max,v in = 0v 350 a i ozl tristate leakage current 6 v dd =max,v in =0v 10 a i ddin supply current (internal) 7 t ck =50ns,v dd =max,v ihcr =3.0v, v ih =2.4v,v il =v ilc =0.4v 430 ma 29 tsc21020f 4153e?aero?06/02 ac parameters see figure 15 for voltage reference levels. use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addi- tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add parameters to derive other specifications. i ddidle supply current (idle) 8 v dd =max,v in =0vorv dd max 150 ma c in input capacitance 9, 10 f in =1mhz,t case =25 5 c, v in =2.5v 10 pf notes: 1. applies to: pmd47-0, pmack, pmts, dmd39-0, dmack, dmts, irq3-0, flag3-0, br, tms, tdi. 2. applies to: clkin, tck. 3. applies to: pma23-0, pmd47-0, pms1-0, pmrd, pmwr, pmpage, dma31-0, dmd39-0, dms3-0, dmrd, dmwr, dmpage,flag3-0,timexp,bg. 4. applies to: pmack, pmts, dmack, dmts, irq3-0, br, clkin, reset, tck. 5. applies to: tms, tdi, trst. 6. applies to: pma23-0, pmd47-0, pms1-0, pmrd, pmwr, pmpage, dma31-0, dmd39-0, dms3-0, dmrd, dmwr, dmpage, flag3-0, tdo. 7. applies to ivdd pins. at t ck = 50ns, i ddin (typical) = 350 ma. see "power dissipation" for calculation of external (evdd) supply current for total supply current. 8. applies to ivdd pins. idle refers to tsc21020f state of operation during execution of the idle instruction. 9. guaranteed but not tested. 10. applies to all signal pins. 11. although specified for ttl outputs, all tsc21020f outputs are cmos-compatible and will drive to v dd and gnd assuming no dc loads. 12. applies to reset, trst. parameter test conditions min max unit 30 tsc21020f 4153e?aero?06/02 clock signal figure 3. clock reset parameter 20 mhz unit min max t ck clkin period 50 150 ns t ckh clkin width high 10 ns t ckl clkin width low 10 ns parameter 20 mhz frequency dependency (1) unit min max min max t wrst (2) reset width low 200 4t ck ns t srst (3) reset setup before clkin high 29 50 29 + dt/2 30 ns notes: 1. dt = t ck -50ns 2. applies after the power-up sequence is complete. at power up, the internal phase locked loop requires no more than 1000clkin cycles while reset is low, assum- ing stable v dd and clkin (not including clock oscillator start-up time). 3. specification only applies in cases where multiple tsc21020f processors are required to execute in program counter lock-step (all processors start execution at location 8 in the same cycle). see the hardware configuration chapter of the adsp-21020 user's manual from analog devices for reset sequence information. 31 tsc21020f 4153e?aero?06/02 figure 4. reset interrupts figure 5. interrupts timer figure 6. timexp parameter 20 mhz frequency dependency (1) unit min t sir irq3-0 setup before clkin high 38 38 + 3dt/4 ns t hir irq3-0 hold after clkin high 0 ns t ipw irq3-0 pulse width 55 t ck +5 ns note: 1. dt=t ck -50ns meeting setup and hold guarantees interrupts will be latched in that cycle. meeting the pulse width is not necessary if the setup and hold is met. likewise, meeting the setup and hold is not necessary if the pulse width is met. see the hardware config- uration chapter of the adsp-21020 user's manual from analog devices for interrupt servicing information. parameter 20 mhz frequency dependency (1) unit max min max t dtex clkin high to timexp 24 ns note: 1. dt=t ck -50ns 32 tsc21020f 4153e?aero?06/02 flags figure 7. flags parameter 20 mhz frequency dependency (1) unit min max min max t sfi (2) flag3-0 in setup before clkin high 19 19 + 5dt/16 ns t hfi (2) flag3-0 in hold after clkin high 012+ 7dt/16 ns t dwrfi (2) flag3-0 in delay from xrd, xwr low 12 ns t hfiwr (2) flag3-0 in hold after xrd, xwr deasserted 0ns t dfo flag3-0 out delay from clkin high 24 ns t hfo flag3-0 out hold after clkin high 5 ns t dfoe clkinhightoflag3-0 out enable (3) 1ns t dfod clkinhightoflag3-0 out disable 24 ns notes: 1. dt = t ck -50ns 2. flag inputs meeting these setup and hold times will affect conditional operations in the next instruction cycle. see the hardware configuration chapter of the adsp- 21020 user's manual from analog devices for additional flag servicing information. 3. guaranteed by design. 33 tsc21020f 4153e?aero?06/02 bus request/bus grant figure 8. bus request/bus grant parameter 20 mhz frequency dependency (1) unit min max min max t hbr br hold after clkin high 0 ns t sbr br setup before clkin high 18 18+5dt/16 ns t dmdbgl memory interface disable to bg low (2) -2 ns t dme clkin high to memory interface enable 25 25 + dt/2 ns t dbgl clkinhightobg low 22 ns t dbgh clkinhightobg high 22 ns notes: 1. dt = t ck -50ns memory interface = pma23-0, pmd47-0, pms1-0, pmrd, pmwr, pmpage, dma31-0, dmd39-0, dms3-0, dmrd, dmwr, dmpage. buses are not granted until completion of current memory access. see the memory interface chapter of the adsp-21020 user's manual from analog devices for bg, br cycle relationships. 2. guaranteed by design. 34 tsc21020f 4153e?aero?06/02 external memory three-state control figure 9. external memory three-state control parameter 20 mhz frequency dependency (1) unit min max min max t sts xts , setup before clkin high 14 50 14 + dt/4 t ck ns t dadts xts delay after address, select 28 28 + 7dt/8 ns t dsts xts , delay after xrd, xwr low 16 16 + dt/2 ns t dtsd memory interface disable before clkin high 0dt/4ns t dtsae xts high to address, select enable 0ns notes: 1. dt = t ck -50ns xts should only be asserted (low) during an active memory access cycle. memory interface = pma23-0, pmd47-0, pms1-0 ,pmrd ,pmwr , pmpage, dma31-0, dmd39-0, dms3-0 ,dmrd ,dmwr , dmpage. address = pma23-0, dma31-0, select = pms1-0 ,dms3-0 x=pmordm. 35 tsc21020f 4153e?aero?06/02 memory read parameter 20 mhz frequency dependency (1) unit min max min max t dad address, select to data valid 37 37 + dt ns t drld xrd low to data valid 24 24 + 5dt/8 ns t hda data hold from address, select 0ns t hdrh data hold from xrd high -1 ns t daak xack delay from address 27 27 + 7dt/8 ns t drak xack delay from xrd low 15 15 + dt/2 ns t sak xack setup before clkin high 14 14 + dt/4 ns t hak xack hold after clkin high 0 ns t darl address, select to xrd low 8 8 + 3dt/8 ns t dap xpage delay from address, select 1ns t dckrl clkinhightoxrd low 16 26 16 + dt/4 26 + dt/4 ns t rw xrd pulse width 26 26 + 5dt/8 ns t rwr xrd high to xrd ,xwr low 17 17 + 3dt/8 ns notes: 1. dt = t ck -50ns 2. x = pm or dm; address = pma23-0, dma31-0; data = pmd47-0, dmd39-0; select = pms1-0 ,dms3-0 . 36 tsc21020f 4153e?aero?06/02 figure 10. memory read memory write parameter 20 mhz frequency dependency (1) unit min max min max t daak xack delay from address, select 27 27 + 7dt/8 ns t dwak xack delay from xwr low 15 15 + dt/2 ns t sak xack setup before clkin high 14 14 + dt/4 ns t hak xack hold after clkin high 0ns t dawh address, select to xwr deasserted 37 37 + 15dt/16 ns t dawl address, select to xwr low 11 11 + 3d t/8 ns t ww xwr pulse width 26 26 + 9dt/16 ns t ddwh data setup before xwr high 23 23 + dt/2 ns 37 tsc21020f 4153e?aero?06/02 figure 11. memory write t dwha address, select hold after xwr deasserted (2) 1 1 + dt/16 ns t hdwh data hold after xwr deasserted (2) 0 dt/16 ns t dap xpage delay from address, select 1ns t dckwl clkinhightoxwr low 16 26 16 + dt/4 26 + dt/4 ns t wwr xwr high to xwr or xrd low 17 17 + 7dt/16 ns t ddwr data disable before xwr or xrd low 13 13 + 3dt/8 ns t wde xwr low to data enabled 0 dt/16 ns notes: 1. dt = t c -50ns 2. see "system hold time calculation" in "test conditions" section for calculating hold times given capacitive and dc loads. x = pm or dm; address = pma23-0, dma31-0; data = pmd47-0, dmd39-0; select =pms1-0 ,dms3-0 ; guaranteed by design. parameter 20 mhz frequency dependency (1) unit min max min max 38 tsc21020f 4153e?aero?06/02 ieee 1149.1 test access port figure 12. ieee 1149.1 test access port parameter 20 mhz frequency dependency (1) unit min max min max t tck tck period 50 t ck ns t stap tdi, tms setup before tck high 5ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck high 7ns t hsys system inputs hold after tck high 9ns t trstw trst pulse width 200 ns t dtdo tdo delay from tck low 15 ns t dsys system outputs delay from tck low 26 ns note: 1. dt=t ck -50ns system inputs = pmd47-0, pmack, pmts , dmd39-0, dmack, dmts ,clkin, irq3-0 , reset ,flag3-0,br . system outputs = pma23-0, pms1-0 ,pmrd ,pmwr , pmd47-0, pmpage, dma31-0, dms3-0 ,dmrd ,dmwr , dmpage, flag3-0, bg , timexp. see the ieee 1149.1 test access port chapter of the adsp-21020 user's manual from analog devices for further detail. 39 tsc21020f 4153e?aero?06/02 figure 13. output enable/disable test conditions output disable time output pins are considered to be disable when they stop driving, go into a high-imped- ance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l , and the load current, i l . it can be approximated by the following equation: the output disable time (t dis ) is the difference between t measured and t decay as shown in figure 13. the time t measured is the interval from when the reference signal switches to when the output voltage decays ? v from the measured output high or output low volt- age. t decay is calculated with ? v equal to 0.5v, and test loads c l and i l . output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena )isthe interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable /disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. t decay c l v ? i l -------------- - = 40 tsc21020f 4153e?aero?06/02 figure 14. equivalent device loading for ac measurements (includes all fixtures) example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the above equation. choose ? v to be the difference between the tsc21020f's output voltage and the input threshold for the device requiring the hold time. a typical ? vwillbe 0.4v. c l is the total bus capacitance (per data line), and i l is the total leakage or three- state current (per data line). the hold time will be t decay plus the minimum disable time (i.e. t hdwd for the write cycle). figure 15. voltage reference levels for ac measurements (except output enable/disable) capacitive loading output delays are based on standard capacitive loads: 100 pf on address, select, page and strobe pins, and 50 pf on all others (see figure 14). for different loads, these tim- ing parameters should be derated. see the hardware configuration chapter of the adsp-21020 user's manual from analog devices for further information on derating of timing specifications. figures 16 and 17 show how the output rise time varies with capacitance. figures 18 and 19 show how output delays vary with capacitance. note that the graphs may not be linear outside the ranges shown. 41 tsc21020f 4153e?aero?06/02 figure 16. typical output rise time vs. load capacitance (at maximum case temperature) figure 17. typical output rise time vs. load capacitance (at maximum case temperature) 0 1 2 3 4 5 6 7 8 9 10 25 50 75 100 125 150 175 200 rise time ? ns (0.8v ? 2.0v) load capacitance ?pf note: (1) output pins bg , timexp, pmd47?0, dmd39?0, flag3?0 9.9 (1) 1.6 0 1 2 3 4 5 25 50 75 100 125 150 175 200 rise time ? ns (0.8v ? 2.0v) load capacitance ? pf note: (1) output pins pma23 ? 0, pms1 ? 0 , pmpage, dma31 ? 0, dms3 ? 0 , dmpage, tdo, pmrd , pmwr , dmrd , dmwr 4.8 (1) 1 42 tsc21020f 4153e?aero?06/02 figure 18. typical output delay or hold vs. load capacitance (at maximum case temperature) figure 19. typical output delay or hold vs. load capacitance (at maximum case temperature) environmental conditions the tsc21020f is available in a ceramic pin grid array (cpga) and in a multi-layer quad flat package with flat leads (mqfpf). the cpga package uses a cavity-down configuration which gives it favorable thermal characteristics. the top surface of the package contains a raised copper slug from which much of the die heat is dissipated. the slug provides a surface for mounting a heat sink (if required). the military range tsc21020f is specified for operation at t amb of -55 cto+125 c. maximum t case (case temperature) can be calculated from the following equation: t case =t amb +(pdx ca ) ?2 0 2 4 6 8 10 12 25 50 75 100 125 150 175 200 output delay or hold ? ns load capacitance ? pf note: (1) output pins bg , timexp , flag3 ? 0, pmd47 ? 0, dmd39 ? 0 (1) 8.3 ? 1.7 ? 3 ? 2 ? 1 0 1 2 3 4 25 50 75 100 125 150 175 200 output delay or hold ? ns load capacitance ? pf note: (1) output pins pma ? 23, pms1 ? 0 , pmpage, dma31 ? 0, dms3 ? 0 , dmpage, tdo, pmrd , pmwr , dmrd , dmwr ? 2.2 (1) 2.8 43 tsc21020f 4153e?aero?06/02 where pd is power dissipation and ca is the case-to-ambient thermal resistance. the value of pd depends on your application; the method for calculating pd is shown under "power dissipation" below. ca varies with airflow. table 9 shows a range of ca values. the tsc21020f is also available in a 256-pin mqfpf package (ceramic). the pack- age uses a cavity-up configuration. table 11. maximum ca for various airflow values power dissipation total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data values involved. internal power dissipa- tion is calculated in the following way: p int = i ddin xv dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: 1) the number of output pins that switch during each cycle(o), 2) the maximum frequency at which they can switch (f), 3) their load capacitance (c), and 4) their voltage swing (v dd ). it is calculated by: p ext = oxcxv dd 2 xf the load capacitance should include the processor's package capacitance (c in ). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1/(2t ck ). the write strobes can switch every cycle at a frequency of 1/tck. select pins switch at 1/(2t ck ), but 2 dm and 2 pm selects can switch on each cycle. if only one bank is accessed, no select line will switch. example: estimate p ext with the following assumptions: a system with one ram bank each of pm (48 bits) and dm (32 bits). 32 k x 8 ram chips are used, each with a load of 10 pf. single-precision mode is enabled so that only 32 data pins can switch at once. pm and dm writes occur every other cycle, with 50% of the pins switching. the instruction cycle rate is 20 mhz (t ck =50ns)andv dd =5.0v. airflow (m/s) 0 0.5 1 1.5 mqfpf 31.5 c/w 25 c/w 21.5 c/w 19 c/w cpga 14.5 c/w 11.2 c/w 8.8 c/w 7.8 c/w note: jc is 1 c/w for cpga. jc is 0.3 c/w for mqfpf. maximum recommended t j is 130 c. as per method 1012 mil-std-883. ambient temperature: 25 c. power: 3.5w. 44 tsc21020f 4153e?aero?06/02 the p ext equation is calculated for each class of pins that can drive: a typical power consumption can now be calculated for this situation by adding a typical internal power dissipation: p total =p ext +(5vxi ddin (typ)) = 0.210 + 1.15 = 1.36w note that the conditions causing a worst case p ext are different from those causing a worst case p int . maximum p int cannot occur while 100% of the output pins are switch- ing from all ones to all zeros. also note that it is not common for a program to have 100% or even 50% of the outputs switching simultaneously. power and ground guidelines to achieve its fast cycle time, including instruction fetch, data access, and execution, the tsc21020f is designed with high speed drivers on all output pins. large peak cur- rents may pass through a circuit board's ground and power lines, especially when many output drivers are simultaneously charging or discharging their load capacitances. these transient currents can cause disturbances on the power and ground lines. to minimize these effects, the tsc21020f provides separate supply pins for its internal logic (ignd and ivdd) and for its external drivers (egnd and evdd). all gnd pins should have a low impedance path to ground. a ground plane is required in tsc21020f systems to reduce this impedance, minimizing noise. the evdd and ivdd pins should be bypassed to the ground plane using approximately 14 high-frequency capacitors (0.1 f ceramic). keep each capacitor's lead and trace length to the pins as short as possible. this low inductive path provides the tsc21020f with the peak currents required when its output drivers switch. the capacitors' ground leads should also be short and connect directly to the ground plane. this provides a low impedance return path for the load capacitance of the tsc21020f's output drivers. if a v dd plane is not used, the following recommendations apply. traces from the + 5v supply to the 10 evdd pins should be designed to satisfy the minimum v dd specifica- tion while carrying average dc currents of [i ddex /10 x (number of evdd pins per trace)]. i ddex is the calculated external supply current. a similar calculation should be made for the four ivdd pins using the i ddin specification. the traces connecting +5v to the ivdd pins should be separate from those connecting to the evdd pins. a low frequency bypass capacitor (20 f tantalum) located near the junction of the ivdd and evdd traces is also recommended. pin type # pins % switch xc xf xv dd 2 p ext pma pms pmwr pmd dma dms dmwr dmd 15 2 1 32 15 2 1 32 50 0 - 50 50 0 - 50 68 pf 68 pf 68 pf 18 pf 48 pf 48 pf 48 pf 18 pf 5mhz 5mhz 10 mhz 5mhz 5mhz 5mhz 10 mhz 5mhz 25v 25v 25v 25v 25v 25v 25v 25v 0.064w 0.000w 0.017w 0.036w 0.045w 0.000w 0.012w 0.036w p ext = 0.210w 45 tsc21020f 4153e?aero?06/02 target system requirements for use of ez-ice emulator the adsp-21020 ez-ice uses the ieee 1149.1 jtag test access port of the tsc21020f to monitor and control the target board processor during emulation. the ez-ice probe requires that clkin, tms, tck, trst, tdi, tdo, and gnd be made accessible on the target system via a 12-pin connector (pin strip header) such as that shown in figure 20. the ez-ice probe plugs directly onto this connector for chip-on- board emulation; you must add this connector to your target board design if you intend to use the adsp-21020 ez-ice. figure 21 shows the dimensions of the ez-ice probe; be sure to allow enough space in your system to fit the probe onto the 12-pin connector. figure 20. target board connector for ez-ice emulator (jumpers in place) figure 21. ez-ice probe the 12-pin, 2-row pin strip header is keyed at the pin 1 location - you must clip pin 1 off of the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing is 0.1 x 0.1 inches. the tip of the pins must be at least 0.10 inch higher than the tallest component under the probe to allow clearance for the bottom of the probe. pin strip headers are available from vendors such as 3m, mckenzie, and samtec. 46 tsc21020f 4153e?aero?06/02 the length of the traces between the ez-ice probe connector and the tsc21020f test access port pins should be less than 1 inch. note that the ez-ice probe adds two ttl loads to the clkin pin of the tsc21020f. the bmts, btck, btrst, and btdi signals are provided so that the test access port can also be used for board-level testing. when the connector is not being used for emu- lation, place jumpers between the bxxx pins and the xxx pins as shown in figure 20. if you are not going to use the test access port for board test, tie btrst to gnd and tie or pull up btck to vdd. the trst pin must be asserted (pulsed low) after power up (through btrst on the connector) or held low for proper operation of the tsc21020f. 47 tsc21020f 4153e?aero?06/02 ordering information part number temperature range speed package quality flow tsc21020f-20ma-e 25 c 20 mhz pga223 engineering samples tsc21020f-20mb-e 25 c 20 mhz mqfp-f256 engineering samples tsc21020f-20mb -55 to +125 c 20 mhz mqfp-f256 mil std. 5962-9953901vxc -55 to +125 c 20 mhz mqfp-f256 qml-q tsc21020f-20mb/883 -55 to +125 c 20 mhz mqfp-f256 mil 883 level b 5962-9953901vxc -55 to +125 c 20 mhz mqfp-f256 qml-v TSC21020F-20SBSB -55 to +125 c 20 mhz mqfp-f256 scc sb tsc21020f-20mc-e 25 c 20 mhz die engineering samples 5962-9953901q9a -55 to +125 c 20 mhz die qml-q 5962-9953901v9a -55 to +125 c 20 mhz die qml-v 48 tsc21020f 4153e?aero?06/02 package drawings 223-pin ceramic pin grid array bottom view symbol mm inches min. max min. max a2.54 3.30 .100.130 c 2.54 bsc .100 bsc d 46.74 47.75 1.840 1.880 e 46.74 47.75 1.840 1.880 h 0.41 0.51 0.16 0.20 l3.05 3.56 .120.140 q 1.14 1.40 0.45 .055 49 tsc21020f 4153e?aero?06/02 package drawings 256-pin mqfp-f package symbol mils mm min. max min. max a 0.095 0.125 2.41 3.18 c 0.004 0.008 0.10 0.20 d 2.095 2.195 53.23 55.74 d 1 1.450 1.470 36.83 37.34 e 2.095 2.195 53.23 55.74 e 1 1.450 1.470 36.83 37.34 e 0.020 bsc 0.508 bsc f 0.006 0.010 0.15 0.25 a 1 0.081 0.101 2.06 2.56 a 2 0.002 0.014 0.05 0.36 l 0.323 0.362 8.20 9.20 n 1 64 64 n 2 64 64 50 tsc21020f 4153e?aero?06/02 printedonrecycledpaper. atmel ? is a registered trademark of atmel. ez-lab and ez-ice is a registered trademark of analog devices, incorporated. other terms and product names may be the trademarks of others. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf data- com avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4153e?aero?06/02 /xm |
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