ht23c256 cmos 32k 8-bit mask rom block diagram features operating voltage 2.7v~5.5v low power consumption C operation: 25ma max. (v cc =5v) 10ma max. (v cc =3v) C standby: 30 m a max. (v cc =5v) 10 m a max. (v cc =3v) access time:150ns max. (v cc =5v) 250ns max. (v cc =3v) 32768 8 bits of mask rom mask options: chip enable ce/ ce/oe1/ oe1 and output enable oe/ oe/nc ttl compatible inputs and outputs tristate outputs fully static operation package type: 28-pin dip/sop general description the ht23c256 is a read-only memory with high performance cmos storage device whose 256k of memory is arranged into 32768 words by 8 bits. for application flexibility, the chip enable and output enable control pins can be selected as active high or active low. this flexibility not only allows easy interface with most microproc- essors, but also eliminates bus contention in multiple bus microprocessor systems. an addi- tional feature of the ht23c256 is its ability to enter the standby mode whenever the chip en- able (ce/ ce) is inactive, thus reducing current consumption to below 30 m a. the combination of these functions makes the chip suitable for high density low power memory applications. 1 24th aug 98
pin assignment pin description pin name i/o description a0~a14 i address inputs d0~d7 o data outputs ce/ ce/oe1/ oe1 i chip enable/output enable input oe/ oe/nc i output enable input vss i negative power supply vcc i positive power supply nc no connection operation truth table mode ce/ ce oe/ oe a0~a14 d0~d7 read h/l h/l valid data out deselect h/l l/h x high z standby l/h x x high z note: h=v ih , l=v il , x=v ih or v il ht23c256 2 24th aug 98
absolute maximum ratings* supply voltage ................................ C0.3v to 6v storage temperature ................ C50 c to 125 c input voltage ....................... C0.3v to v cc +0.3v operating temperature .............. C40 c to 85 c *note: these are stress ratings only. stresses exceeding the range specified under absolute maxi- mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics supply voltage: 2.7v~3.6v ta=C40 c to 85 c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 2.7 3.6 v i cc operating current 3v o/p unload, f= 5mhz 10ma v il input low voltage 3v v ss 0.4 v v ih input high voltage 3v 2.0 v cc v v ol output low voltage 3v i ol = 2.1ma 0.4 v v oh output high voltage 3v i oh = C0.4ma 2.4 v cc v i li input leakage current 3v v in = 0 to v cc 10 m a i lo output leakage current 3v v out = 0 to v cc 10 m a i stb1 standby current 3v ce=v il ce=v ih 500 m a i stb2 standby current 3v ce 0.2v ce 3 v cc -0.2v 10 m a c in input capacitance (see note) f= 1mhz 10 pf c out output capacitance (see note) f= 1mhz 10 pf note: these parameters are periodically sampled but not 100% tested. ht23c256 3 24th aug 98
supply voltage: 4.5v~5.5v ta=C40 c to 85 c symbol parameter test conditions min. typ. max. unit v cc conditions v cc operating voltage 4.5 5.5 v i cc operating current 5v o/p unload, f=5mhz 25ma v il input low voltage 5v v ss 0.8 v v ih input high voltage 5v 2.2 v cc v v ol output low voltage 5v i ol =3.2ma 0.4 v v oh output high voltage 5v i oh =C1ma 2.4 v cc v i li input leakage current 5v v in =0 to v cc 10 m a i lo output leakage current 5v v out =0 to v cc 10 m a i stb1 standby current 5v ce=v il ce=v ih 1.5 ma i stb2 standby current 5v ce 0.2v ce 3 v cc C0.2v 30 m a c in input capacitance (see note) f=1mhz 10 pf c out output capacitance (see note) f=1mhz 10 pf note: these parameters are periodically sampled but not 100% tested. a.c. characteristics ta=C40 c to 85 c symbol parameter v cc =2.7v~3.6v v cc =4.5v~5.5v unit min. max. min. max. t cyc cycle time 250 150 ns t aa address access time 250 150 ns t ace chip enable access time 250 150 ns t aoe output enable access time 150 80 ns t oh output hold time 10 ns t od output disable time (see note) 70 ns t oe output enable time (see note) 10 ns note: these parameters are periodically sampled but not 100% tested. ht23c256 4 24th aug 98
a.c. test conditions output load: see figure right input rise and fall time: 10ns input pulse levels: 0.4v to 2.4v input and output timing reference levels: 0.8v and 2.0v (v cc =5v), 1.5v (v cc =3v) timing diagrams propagation delay due to address (ce/ ce/oe1/ oe1 and oe/ oe are active) propagation delay due to chip enable and output enable (address valid) functional description the ht23c256 has two modes, namely data read mode and standby mode, controlled by ce/ ce/oe1/ oe1 and oe/oe/nc inputs. standby mode the ht23c256 has lower current consumption, controlled by the chip enable input (ce/ ce). when a low/high level is applied to the ce/ ce input regardless of the output enable (oe/ oe/nc) states the chip will enter the standby mode. data read mode when both the chip enable (ce/ ce/oe/ oe1) and the output enable (oe/ oe/nc) are active, the chip is in data read mode. otherwise, active ce/ ce and inactive oe/ oe/nc result in deselect mode. the output will remain in hi-z state. output load circuit ht23c256 5 24th aug 98
characteristic curves ht23c256 6 24th aug 98
ht23c256 7 24th aug 98
ht23c256 mask rom ordering sheet custom: input medium: eprom disk file (mail address: romfile@holtek.com.tw) other user no. type/ref. name qty check sum memory address start end control pin and package form option: (a) 28 pin type pin 20: (1) ce (2) ce (3) oe1 (4) oe1 pin 22: (1) oe (2) oe (3) nc (b) package form: (1) chip form (2) 28 dip (3) 28 sop companion user no. package marking : delivery date : qty: custom confirmed by: (name, date, position & co. chop) holtek confirmed by: (sales) (sales manager) ht23c256 8 24th aug 98
ht23c256 9 24th aug '98 copyright 1998 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holtek semiconductor (shanghai) ltd. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 holmate technology corp. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885
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