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843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 1 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer g eneral d escription the ics843002 is a 2 output lvpecl synthesizer optimized to generate fibre channel reference clock frequencies and is a member of the hiperclocks tm family of high performance clock solutions from ics. using a 26.5625mhz, 18pf parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (f_sel[1:0]): 212.5mhz, 187.5mhz, 159.375mhz, 106.25mhz, and 53.125mhz. the ics843002 uses ics? 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting fibre channel jitter requirements. the ics843002 is packaged in a small 20-pin tssop package. f eatures ? two 3.3v lvpecl outputs ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? supports the following output frequencies: 212.5mhz, 187.5mhz, 159.375mhz, 106.25mhz and 53.125mhz ? vco range: 560mhz - 680mhz ? rms phase jitter (637khz - 10mhz): 0.72ps (typical) ? typical phase noise at 212.5mhz phase noise: offset noise p o w er 100hz ............... -87.7 dbc/hz 1khz .............. -111.6 dbc/hz 10khz .............. -124.3 dbc/hz 100khz .............. -124.3 dbc/hz ? full 3.3v supply mode ? lead-free package rohs compliant ? -30c to 85c ambient operating temperature hiperclocks? ics p in a ssignment 11 0 1 0 phase detector vco 637.5mhz (w/26.5625mhz reference) osc m = 24 (fixed) f_sel[1:0] 0 0 3 0 1 4 1 0 6 1 1 12 2 ics843002 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view b lock d iagram f requency s elect f unction t able f_sel[1:0] npll_sel test_clk xtal_in xtal_out nxtal_sel mr q0 nq0 q1 nq1 pulldown pulldown 26.5625mhz nc v cco q0 nq0 mr npll_sel nc v cca f_sel0 v cc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cco q1 nq1 v ee v cc nxtal_sel test_clk xtal_in xtal_out f_sel1 pulldown pulldown pulldown s t u p n i t u p t u o y c n e u q e r f ) z h m ( t u p n i y c n e u q e r f ) z h m ( 1 l e s _ f0 l e s _ f r e d i v i d m e u l a v r e d i v i d n e u l a v n / m e u l a v r e d i v i d 5 2 6 5 . 6 2004 23 8 5 . 2 1 2 5 2 6 5 . 6 2014 24 6 5 7 3 . 9 5 1 5 2 6 5 . 6 2104 26 4 5 2 . 6 0 1 5 2 6 5 . 6 2114 22 12 5 2 1 . 3 5 5 7 3 4 . 3 2004 23 8 5 . 7 8 1
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 2 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 7 , 1c nd e s u n u. t c e n n o c o n 0 2 , 2v o c c r e w o p. s n i p y l p p u s t u p t u o 4 , 30 q n , 0 qt u p u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a x q n s t u p t u o d e t r e v n i e h t d n a w o l o g o t x q s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e 6l e s _ l l p nt u p n in w o d l l u p n e h w . s r e d i v i d e h t o t t u p n i s a k l c _ t s e t d n a l l p e h t n e e w t e b s t c e l e s k c o l c e c n e r e f e r e h t s t c e l e s e d , h g i h n e h w . ) e l b a n e l l p ( l l p s t c e l e s , w o l . s l e v e l e c a f r e t n i l t t v l / s o m c v l . ) s s a p y b l l p ( 8v a c c r e w o p. n i p y l p p u s g o l a n a 1 1 , 9 , 0 l e s _ f 1 l e s _ f t u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s y c n e u q e r f 6 1 , 0 1v c c r e w o p. n i p y l p p u s e r o c 3 1 , 2 1 , t u o _ l a t x n i _ l a t x t u p n i , t u p t u o e h t s i t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i n i _ l a t x 4 1k l c _ t s e tt u p n in w o d l l u p. t u p n i k c o l c l t t v l / s o m c v l 5 1l e s _ l a t x nt u p n in w o d l l u p e c n e r e f e r l l p e h t e h t s a s t u p n i k l c _ t s e t r o l a t s y r c n e e w t e b s t c e l e s . h g i h n e h w k l c _ t s e t s t c e l e s . w o l n e h w s t u p n i l a t x s t c e l e s . e c r u o s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 1v e e r e w o p. s n i p y l p p u s e v i t a g e n 9 1 , 8 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 3 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer t able 3a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v10%, ta = -30c to 85c t able 3b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v10%, ta = -30c to 85c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 73.2c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i t u p n i e g a t l o v w o l , l e s _ l a t x n , l e s _ l l p n r m , 1 l e s _ f , 0 l e s _ f 3 . 0 -8 . 0v k l c _ t s e t3 . 0 -0 . 1v i h i t u p n i t n e r r u c h g i h , r m , k l c _ t s e t , 1 l e s _ f , 0 l e s _ f , l e s _ l a t x n , l e s _ l l p n v c c v = n i v 3 6 . 3 =0 5 1a i l i t u p n i t n e r r u c w o l , r m , k l c _ t s e t , 1 l e s _ f , 0 l e s _ f , l e s _ l a t x n , l e s _ l l p n v c c v , v 3 6 . 3 = n i v 0 =0 5 1 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 7 9 . 23 . 33 6 . 3v v a c c e g a t l o v y l p p u s g o l a n a 7 9 . 23 . 33 6 . 3v v o c c e g a t l o v y l p p u s t u p t u o 7 9 . 23 . 33 6 . 3v i e e t n e r r u c y l p p u s r e w o p 5 3 1a m i c c t n e r r u c y l p p u s e r o c 0 0 1a m i a c c t n e r r u c y l p p u s g o l a n a 5 1a m i o c c t n e r r u c y l p p u s t u p t u o 1 3a m t able 3c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v10%, ta = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . v 2 -
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 4 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer t able 5. ac c haracteristics , v cc = v cca = v cco = 3.3v10%, ta = -30c to 85c t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 3 3 . 3 25 2 6 5 . 6 23 3 . 8 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 = ] 0 : 1 [ l e s _ f7 6 . 6 8 17 6 . 6 2 2z h m 1 0 = ] 0 : 1 [ l e s _ f0 4 10 7 1z h m 0 1 = ] 0 : 1 [ l e s _ f3 3 . 3 93 3 . 3 1 1z h m 1 1 = ] 0 : 1 [ l e s _ f7 6 . 6 47 6 . 6 5z h m t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o 0 2s p t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 3 e t o n ) z h m 0 1 - z h k 7 3 6 ( , z h m 5 . 2 1 22 7 . 0s p ) z h m 0 1 - z h k 7 3 6 ( , z h m 5 7 3 . 9 5 16 7 . 0s p ) z h m 0 1 - z h k 7 3 6 ( , z h m 5 2 . 6 0 14 8 . 0s p ) z h m 0 1 - z h k 7 3 6 ( , z h m 5 2 1 . 3 57 9 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 6s p c d oe l c y c y t u d t u p t u o 0 0 = ] 0 : 1 [ l e s _ f6 44 5% ] 0 : 1 [ l e s _ f 0 09 41 5% . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n v t a d e r u s a e m o c c . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 2 e t o n . t o l p e s i o n e s a h p e e s : 3 e t o n
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 5 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer 106.25mhz rms phase jitter (random) 637khz to 10mhz = 0.84ps (typical) o ffset f requency (h z ) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1m 10m 100m fibre channel jitter filter ? phase noise result by adding fibre channel filter to raw data ? raw phase noise data ? dbc hz n oise p ower t ypical p hase n oise at 106.25mh z t ypical p hase n oise at 53.125mh z 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 53.125mhz rms phase jitter (random) 637khz to 10mhz = 0.97ps (typical) o ffset f requency (h z ) 10 100 1k 10k 100k 1m 10m 100m fibre channel jitter filter ? phase noise result by adding fibre channel filter to raw data ? raw phase noise data ? dbc hz n oise p ower
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 6 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer t ypical p hase n oise at 212.5mh z 212.5mhz rms phase jitter (random) 637khz to 10mhz = 0.72ps (typical) o ffset f requency (h z ) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1m 10m 100m fibre channel jitter filter ? phase noise result by adding fibre channel filter to raw data ? raw phase noise data ? dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1m 10m 100m 159.375mhz rms phase jitter (random) 637khz to 10mhz = 0.76ps (typical) o ffset f requency (h z ) dbc hz fibre channel jitter filter ? phase noise result by adding fibre channel filter to raw data ? raw phase noise data ? n oise p ower t ypical p hase n oise at 159.375mh z
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 7 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer p arameter m easurement i nformation t pw t period t pw t period odc = x 100% q0, q1 rms p hase j itter o utput s kew 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.33v o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v swing v cc , v cca , v cco v ee nq0, nq1 o utput d uty c ycle /p ulse w idth /p eriod t sk(o) qy qx nqy nqx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 8 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843002 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10f and a .01 f bypass capacitor should be connected to each v cca . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc t ermination for 3.3v lvpecl o utput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 2b. lvpecl o utput t ermination f igure 2a. lvpecl o utput t ermination designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating frequency and minimize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed cir- cuit and clock component process variations.
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 9 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer c rystal i nput i nterface the ics843002 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 3 figure 3. c rystal i npu t i nterface below were determined using a 26.5625mhz 18pf parallel resonant crystal and were chosen to minimize the ppm error. ics843002 c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 10 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer l ayout g uideline figure 4a shows a schematic example of the ics843002. an example of lvepcl termination is shown in this schematic. additional lvpecl termination approaches are shown in the lvpecl termination application note. in this example, an 18 pf f igure 4a. ics843002 s chematic e xample parallel resonant 26.5625mhz crystal is used. the c1=27pf and c2=33pf are recommended for frequency accuracy. for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. f igure 4b. ics843002 pc b oard l ayout e xample c1 27pf vcc vcco zo = 50 ohm r6 50 c6 0.1u c4 0.01u vcc x1 26.5625 mhz vcc=3.3v 18pf to logic input pins c7 0.1u zo = 50 ohm ru1 1k to logic input pins c9 0.1u set logic input to '1' vcco=3.3v vcc vcc r5 50 u1 ics843002 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 vcco q0 nq0 mr npll_sel nc vcca f_sel0 vcc f_sel1 xtal_out xtal_in test_clk nxtal_sel vcc vee nq1 q1 vcco nc vcc vcco rd2 1k vcca r4 50 c3 10uf zo = 50 ohm rd1 not install r2 10 set logic input to '0' zo = 50 ohm + - c8 0.1u r7 50 logic control input examples r9 50 c2 33pf r8 50 + - ru2 not install pc b oard l ayout e xample figure 4b shows an example of ics843002 p.c. board layout. the crystal x1 footprint shown in this example allows installa- tion of either surface mount hc49s or through-hole hc49 pack- age. the footprints of other components in this example are listed in the table 6. there should be at least one decoupling capacitor per power pin. the decoupling capacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. t able 6. f ootprint t able e c n e r e f e re z i s 2 c , 1 c2 0 4 0 3 c5 0 8 0 8 c , 7 c , 6 c , 5 c , 4 c3 0 6 0 2 r3 0 6 0 s e z i s t n e n o p m o c s t s i l , 6 e l b a t : e t o n . e l p m a x e t u o y a l s i h t n i n w o h s
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 11 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843002. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843002 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 10% = 3.63v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.63v * 135ma = 490mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.63v, with all outputs switching) = 490mw + 60mw = 550mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.550w * 66.6c/w = 121.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7. t hermal r esistance ja for 20- pin tssop, f orced c onvection
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 12 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 5. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 13 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer r eliability i nformation t ransistor c ount the transistor count for ics843002 is: 2578 t able 8. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 1 14.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73. 2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 14 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer p ackage o utline - g s uffix for 20 l ead tssop t able 9. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m n i mx a m n0 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 4 . 60 6 . 6 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 15 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer t able 10. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requir ing e xtended temperature range, hi gh reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specif ications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 2 0 0 3 4 8 s c ig a 2 0 0 3 4 8 s c ip o s s t d a e l 0 2e b u tc 5 8 o t c 0 3 - t g a 2 0 0 3 4 8 s c ig a 2 0 0 3 4 8 s c ip o s s t d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - f l g a 2 0 0 3 4 8 s c if l a 2 0 0 3 4 8 s c ip o s s t " e e r f - d a e l " d a e l 0 2e b u tc 5 8 o t c 0 3 - t f l g a 2 0 0 3 4 8 s c if l a 2 0 0 3 4 8 s c ip o s s t " e e r f - d a e l " d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n the aforementioned trademark, hiperclocks? and f emto c locks ? is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries.
843002ag www.icst.com/products/hiperclocks.html rev. b may 6, 2005 16 integrated circuit systems, inc. ics843002 f emto c locks ? c rystal - to - 3.3v lvpecl f requency s ynthesizer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a1 . e l b a t n o i t c n u f n o i t c e l e s y c n e u q e r f e h t o t z h m 5 . 7 8 1 d e d d a 4 0 / 6 2 / 8 a0 1 t5 1. r e b m u n t r a p e e r f d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 0 3 / 9 a5 t4 f , o p y t d e t c e r r o c - e l b a t s c i t s i r e t c a r a h c c a t u o . n i m 7 6 . 6 8 1 o t . n i m 7 6 . 0 8 14 0 / 7 2 / 2 1 a 0 1 t 1 5 1 t u p t u o . . . s t r o p p u s " d a e r o t t e l l u b y c n e u q e r f d e t c e r r o c - n o i t c e s s e r u t a e f . " . . . s e i c n e u q e r f t u p n i . . . " m o r f " . . . s e i c n e u q e r f . e l b a t d e t a d p u - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 7 / 2 b5 t4 . y a l e d n o i t a g a p o r p d e t e l e d - e l b a t s c i t s i r e t c a r a h c c a 5 0 / 6 / 5

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