issi is62c256 integrated silicon solution, inc. 2-1 rev. d 0895 sr81995c256 issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1995, integrated silicon solution, inc. features ? access time: 45, 70, 100 ns ? low active power: 200 mw (typical) ? low standby power 250 m w (typical) cmos standby 28 mw (typical) ttl standby ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? single 5v power supply description the issi is62c256 is a low power, 32,768 word by 8-bit cmos static ram. it is fabricated using issi 's high- performance, low power cmos technology. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 m w (typical) at cmos input levels. easy memory expansion is provided by using an active low chip enable ( ce ) input and an active low output enable ( oe ) input. the active low write enable ( we ) controls both writing and reading of the memory. the is62c256 is pin compatible with other 32k x 8 srams in 600-mil pdip, 450-mil plastic sop, or tsop package. is62c256 32k x 8 low power cmos static ram issi functional block diagram a0-a14 ce oe we 256 x 1024 memory array decoder column i/o control circuit gnd vcc i/o data circuit i/o0-i/o7
issi is62c256 2-2 integrated silicon solution, inc. rev. d 0895 sr81995c256 pin configuration 28-pin dip and sop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd C0.5 to +7.0 v t bias temperature under bias C55 to +125 c t stg storage temperature C65 to +150 c p t power dissipation 0.5 w i out dc output current (low) 20 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 pin configuration 28-pin tsop pin descriptions a0-a14 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 input/output vcc power gnd ground truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation vcc current not selected x h x high-z i sb 1, i sb 2 (power-down) output disabled h l h high-z i cc 1, i cc 2 read h l l d out i cc 1, i cc 2 write l l x d in i cc 1, i cc 2
issi is62c256 integrated silicon solution, inc. 2-3 rev. d 0895 sr81995c256 operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial C40 c to +85 c 5v 10% capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 8 pf c out output capacitance v out = 0v 10 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 5.0v. power supply characteristics (1) (over operating range) -45 ns -70 ns -100 ns symbol parameter test conditions min. max. min. max. min. max. unit i cc 1 vcc operating v cc = max., ce = v il com. 60 60 60 ma supply current i out = 0 ma, f = 0 ind. 70 70 70 i cc 2 vcc dynamic operating v cc = max., ce = v il com. 70 65 65 ma supply current i out = 0 ma, f = f max ind. 80 75 75 i sb 1 ttl standby current v cc = max., com. 5 5 5 ma (ttl inputs) v in = v ih or v il ind. 10 10 10 ce 3 v ih , f = 0 i sb 2 cmos standby v cc = max., com. 0.5 0.5 0.5 ma current (cmos inputs) ce 3 v cc C 0.2v, ind. 1.0 1.0 1.0 v in 3 v cc C 0.2v, or v in 0.2v, f = 0 notes: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. dc electrical characteristics symbol parameter test conditions min. max. unit v oh output high voltage v cc = min., i oh = C1.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 2.1 ma 0.4 v v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v cc com. C2 2 m a ind. C10 10 i lo output leakage gnd v out v cc , com. C2 2 m a outputs disabled ind. C10 10 notes: 1. v il = C3.0v for pulse width less than 10 ns.
issi is62c256 2-4 integrated silicon solution, inc. rev. d 0895 sr81995c256 data retention characteristics symbol parameter test conditions min. max. units v dr v cc for retention of data 2.0 v i dr 1 data retention current v dr = 3.0v, t a = 0 c to +25 c 200 m a i dr 2 data retention current v dr = 3.0v, t a = 0 c to +70 c 200 m a figure 1a. figure 1b. 480 w 100 pf including jig and scope 255 w output 5v 480 w 5 pf including jig and scope 255 w output 5v ac test loads ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 3 ns input and output timing 1.5v and reference levels output load see figures 1a and 1b read cycle switching characteristics (1) (over operating range) -45 ns -70 ns -100 ns symbol parameter min. max. min. max. min. max. unit t rc read cycle time 45 70 100 ns t aa address access time 45 70 100 ns t oha output hold time 2 2 2 ns t ace ce access time 45 70 100 ns t doe oe access time 25 35 50 ns t lzoe (2) oe to low-z output 0 0 0 ns t hzoe (2) oe to high-z output 0 20 0 25 0 25 ns t lzce (2) ce to low-z output 3 3 3 ns t hzce (2) ce to high-z output 0 20 0 25 0 25 ns t pu (3) ce to power-up 0 0 0 ns t pd (3) ce to power-down 30 50 50 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
issi is62c256 integrated silicon solution, inc. 2-5 rev. d 0895 sr81995c256 data valid t aa t oha t oha t rc d out address read cycle no. 2 (1,3) ac waveforms read cycle no. 1 (1,2) 50% 50% t rc t oha t aa t doe t lzoe t ace t lzce t hzoe t pd high-z t pu data valid t hzce isb address oe ce d out supply current icc notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions.
issi is62c256 2-6 integrated silicon solution, inc. rev. d 0895 sr81995c256 write cycle switching characteristics (1,3) (over operating range) -45 ns -70ns -100 ns symbol parameter min. max. min. max. min. max. unit t wc write cycle time 45 70 100 ns t sce ce to write end 35 60 80 ns t aw address setup time to write end 25 60 80 ns t ha address hold from write end 0 0 0 ns t sa address setup time 0 0 0 ns t pwe (4) we pulse width 25 55 60 ns t sd data setup to write end 20 30 35 ns t hd data hold from write end 0 0 0 ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 4. tested with oe high. ac waveforms write cycle no. 1 ( we we we we we controlled) (1,2) data-in valid data undefined t wc t sce t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address ce we d out d in
issi is62c256 integrated silicon solution, inc. 2-7 rev. d 0895 sr81995c256 write cycle no. 2 ( ce ce ce ce ce controlled) (1,2) ordering information commerical range: 0 c to +70 c speed (ns) order part no. package 45 is62c256-45w 600-mil plastic dip 45 is62c256-45t tsop 45 is62c256-45u 450-mil plastic sop 70 is62c256-70w 600-mil plastic dip 70 is62c256-70t tsop 70 is62c256-70u 450-mil plastic sop 100 is62c256-100w 600-mil plastic dip 100 is62c256-100t tsop 100 is62c256-100u 450-mil plastic sop high-z data undefined data-in valid t wc t sce t sa t ha t pwe t aw t hzwe t sd t hd t lzwe address d in ce we d out ordering information industrial range: C40 c to +85 c speed (ns) order part no. package 45 is62c256-45wi 600-mil plastic dip 45 is62c256-45ti tsop 45 is62c256-45ui 450-mil plastic sop 70 is62c256-70wi 600-mil plastic dip 70 is62c256-70ti tsop 70 is62c256-70ui 450-mil plastic sop 100 is62c256-100wi 600-mil plastic dip 100 is62c256-100ti tsop 100 is62c256-100ui 450-mil plastic sop integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 800-379-4774 fax: 408-588-0806 e-mail: sales@issiusa.com web: www.issiusa.com issi notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe 3 v ih .
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