View MT28C128532W18_2667881.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80b10a55 mt28c128564w18d_b.fm - rev. b, pub 7/03 en 1 ?2003 micron technology, inc. 128mb multibank burst flash 32mb/64mb async/page cellularram combo advance ? flash and cellularram ? combo memory MT28C128532W18/w30d mt28c128564w18/w30d low voltage, wireless temperature features ? stacked die combo package includes two 64mb flash devices choice of either one 32mb or one 64mb cellularram device basic configuration flash flexible multibank architecture 4 meg x 16 async/page/burst interface support for true concurrent operations with no latency cellularram low-power, high-density design 2 meg x 16 or 4 meg x 16 configurations async/page f_v cc , v cc q, f_v pp , ps_v cc voltages 1.70v (min)/1.95v (max) f_v cc , ps_v cc 1.70v (min)/2.24v (max) v cc q (w18) 1.70v (min)/3.3v(max) v cc q (w30) 1.80v (typ) f_v pp (in-system program/erase) 12v 5% (hv) f_v pp (in-house programming and accelerated programming algorithm [apa] activation) asynchronous access time flash/cellularram access time: 60ns @ 1.70v v cc page mode read access (w18/w30) interpage read access: 60ns @ 1.70v f_v cc , ps_v cc (w18) intrapage read access: 20ns @ 1.70v f_v cc , ps_v cc (w18) interpage read access: 70ns @ 1.70v f_vcc , ps_vcc (w30) intrapage read access: 22ns @ 1.70v f_vcc, ps_vcc (w30) enhanced suspend options erase-suspend-to-read within same bank program-suspend-to-read within same bank erase-suspend-to-program within same bank read/write cellularram during program/erase of flash each flash contains two 64-bit chip protection registers for security purposes flash program/erase cycles 100,000 write/erase cycles per block cross-compatible command set support extended command set common flash interface (cfi) compliant manufacturer?s id (manid) micron ? (0x2ch) intel ? (0x89h) note: 1. contact factory for availability. part number example: mt28c128564w18dfw-705 bbwt o ptions m arking timing 60ns 70ns -60 -70 burst frequency 66 mhz 1 54 mhz 6 5 boot block configuration top /to p top /bo tt om bottom/top bottom/bottom tt tb bt bb i/o voltage range vccq 1.70v?1.95v vccq 1.70v?3.3v 18 30 manufacturer?s id (manid) micron (0x2ch) intel (0x89h) none k operating temperature range wireless temperature (-25c to +85c) wt package 77-ball fbga (8 x 10 grid) fw figure 1: 77-ball fbga a b c d e f g h j k 1 2 3 4 5 6 7 8 top view (ball down) ps_v ss ps_v ss f_v pp f_wp# f_rst# dq10 dq3 dq11 nc f_v cc a19 ps_ub# dq2 dq1 dq9 nc v cc q a4 a5 a3 a2 a1 a0 ps_oe# nc f_ce1# ps_v ss f_v cc clk ps_ce# a20 a8 dq13 dq14 dq6 f_v cc v ss q nc a9 a10 a14 wait# dq7 dq15 v cc q f_v ss a11 a12 a13 a15 a16 f_ce2# f_oe2# v cc q ps_zz# ps_v ss f_v cc nc ps_we# adv# f_we# dq5 dq12 dq4 ps_v cc ps_v ss a18 ps_lb# a17 a7 a6 dq8 dq0 f_oe1# nc v ss q a21
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 2 ?2003 micron technology. inc. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 flash configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 boot configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 multichip packaging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 unique ids, state machines, and registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 flash reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 flash electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 3 ?2003 micron technology. inc. list of figures figure 1: 77-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: flash memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: 77-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 4 ?2003 micron technology. inc. list of tables table 1: cross-reference for abbreviated device marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 2: valid part number combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 3: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: possible boot configurations for flash die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 5: truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 6: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 8: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 9: dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 10: cfi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 5 ?2003 micron technology. inc. general description the MT28C128532W18/w30d and mt28c128564w18/w30d combination flash and cel- lularram are high-performance, high-density, mem- ory solutions that can significantly improve system performance. the flash architecture features a multi- partition configuration that supports read-while- program/erase operations with no latency. a 4mb partition size enables optimal design flexibility. two flash devices are stacked to achieve the 128mb density. each flash die has a dedicated ce# and oe# control, enabling each flash to be independently select- able. the MT28C128532W18/w30d and mt28c128564w18/w30d stacked flash devices enable soft protection for blocks, as read only, by con- figuring soft protection registers with dedicated com- mand sequences. for security purposes, two user- programmable 64-bit chip protection registers are pro- vided for each flash device. the embedded word program and block erase functions are fully automated by an on-chip write state machine (wsm). an on-chip device status register can be used to monitor the wsm status and determine the progress of the program/erase tasks. each flash device has a read configuration register (rcr) that defines how the flash interacts with the mem- ory bus. for device specifications and additional docu- mentation concerning flash and cellularram features, please refer to the mt28f644w18/w30 data sheet at www.micron.com/flash and the mt45w2mw16pfa and mt45w4mw16pfa data sheets at http:// www.micron.com/cellularram . the cellularram architecture features high-speed cmos, dynamic random-access memories developed for low-power portable applications the cellularram device is available in either 32mb or 64mb densities. to operate seamlessly on a burst flash bus, cellular- ram products have incorporated a transparent self- refresh mechanism. the hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write per- formance. the refresh configuration register (cr) is used to con- trol how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up and can be updated any time during normal operation. special attention has been focused on standby current consumption during self-refresh. cellularram products include three system-acces- sible mechanisms used to minimize standby current. partial array refresh (par) limits refresh to the portion of the memory array being used. temperature com- pensated refresh (tcr) is used to adjust the refresh rate according to the ambient temperature. the refresh rate can be decreased at lower temperatures to minimize current consumption during standby. deep power down (dpd) halts the refresh operation alto- gether and is used when no vital information is stored in the device. these three refresh mechanisms are adjusted through the cr. please refer to micron?s web site www.micron.com/ flash for the latest mt28f644w18/w30 flash data sheet and http://www.micron.com/cellularram for the latest mt45w2mw16pfa and mt45w4mw16pfa cel- lularram data sheet. flash configurations each flash memory implements a multibank archi- tecture (16 banks of 4mb each) to allow concurrent operations. any address within a block address range selects that block for the required read, program, or erase operation. each flash memory features eight 4k-word sectors (8 x 65,536 bits), designated as parameter blocks, and the remaining part is organized in main blocks of 32k words each (524,288 bits). the parameter blocks are addressed either by the low order addresses (bottom boot) or by the higher order addresses (top boot). the two flash devices can be supplied with any combination of top or bottom boot (e.g., top/top, bot- tom/bottom, top/bottom, or bottom/top). please see figures 2 and 3 for more information.
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 6 ?2003 micron technology. inc. figure 2: flash memory map note: figure 2 shows a bt (bottom/top) dual flash configuration. parameter blocks ? top boot f_ce2#/f_oe2# controlled upper address space (64mb to 128mb) main main main parameter blocks ? bottom boot f_ce1#/f_oe1# controlled lower address space (0mb to 64mb) main main main
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 7 ?2003 micron technology. inc. figure 3: block diagram ps_oe# ps_zz# ps_ce# ps_we# dq0 ? dq15 a0 ? a21 f_we# f_oe2# f_ce2# clk f_ wp# wait # flash #1 cellularram f_rst# ps_ub# ps_lb# 4,096k x 16 2,048k x 16 4,096k x 16 bank 0 bank 15 ps_v cc f_oe1# f_ce1# adv# ps_v ss flash #2 4,096k x 16 bank 16 bank 31 v cc q v ss q f_v cc f_v ss f_v pp
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 8 ?2003 micron technology. inc. device marking due to the size of the package, the micron stan- dard part number is not printed on the top of each device. instead, an abbreviated device mark com- prised of a five-digit alphanumeric code is used. the abbreviated device marks are cross-referenced to the micron part numbers in table 1. table 1: cross-reference for abbreviated device marks product part number product marking sample marking mechanical marking MT28C128532W18dfw-606 btwt fw625 fx625 fy625 MT28C128532W18dfw-606 bbwt fw631 fx631 fy631 MT28C128532W18dfw-705 btwt fw632 fx632 fy632 MT28C128532W18dfw-705 ttwt fw626 fx626 fy626 mt28c128564w18dfw-606 btwt fw627 fx627 fy627 mt28c128564w18dfw-705 btwt fw637 fx637 fy637 MT28C128532W18dfw-606 tbwt fw639 fx639 fy639 MT28C128532W18dfw-606 bbwt fw642 fx642 fy642 MT28C128532W18dfw-705 bbwt fw638 fx638 fy638 MT28C128532W18dfw-705 ttwt fw643 fx643 fy643 mt28c128532w30dfw-606 bbwt fw649 fx649 fy649 mt28c128532w30dfw-705 tbwt fw651 fx651 fy651 mt28c128564w30dfw-606 btwt fw650 fx650 fy650 mt28c128564w30dfw-705 btwt fw640 fx640 fy640
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 9 ?2003 micron technology. inc. part numbering information micron?s low-power devices are available with sev- eral different combinations of features (see figure 4). valid combinations of features and their correspond- ing part numbers are listed in table 2. figure 4: part number chart mt 28c 1285 64 w18 d fw -70 5 bb wt es micron technology flash family 28c = dual-supply flash/cellularram combo density/organization/banks 128 = two 64mb (4,096k x 16) bank x = 5 multibank 32 banks (all banks have the same dimensions) access time -60 = 60ns -70 = 70ns cellularram density 64 = 64mb cellularram (4 meg x 16) 32 = 32mb cellularram (2 meg x 16) flash read mode operation w = flash async/page/burst read package code fw = 77-ball fbga (8 x 10 grid) operating temperature range wt = wireless (-25oc to +85oc) burst mode frequency 5 = 54 mhz 6 = 66 mhz boot block starting address bb = bottom boot/bottom boot bt = bottom boot/top boot tt = top boot/top boot tb = top boot/bottom boot operating voltage range 18 v cc = 1.70v?1.95v v cc v cc q = 1.70v?2.24v v cc 30 v cc = 1.70v?1.95v v cc v cc q = 1.70v?3.30v v cc ce select/special mark d = dual ce flash with aysnchronous psram production status blank = production es = engineering samples ms = mechanical samples manufacturer's id none = micron [2ch] k = intel [89h] table 2: valid part number combinations part number manid access time (ns) boot block starting address burst frequency (mhz) MT28C128532W18dfw-606 btwt micron -60 bottom/top 66 MT28C128532W18dfw-606 bbwt micron -60 bottom/bottom 66 MT28C128532W18dfw-705 btwt micron -70 bottom/top 54 MT28C128532W18dfw-705 ttwt micron -70 top/top 54 mt28c128564w18dfw-606 btwt micron -60 bottom/top 66 mt28c128564w18dfw-705 btwt micron -70 bottom/top 54 MT28C128532W18dfw-606 tbwt micron -60 top/bottom 66 MT28C128532W18dfw-606 bbwt micron -60 bottom/bottom 66 MT28C128532W18dfw-705 bbwt micron -70 bottom/bottom 54 MT28C128532W18dfw-705 ttwt micron -70 top/top 54 mt28c128532w30dfw-606 bbwt micron -60 bottom/bottom 66 mt28c128532w30dfw-705 tbwt micron -70 top/bottom 54 mt28c128564w30dfw-606 btwt micron -60 bottom/top 66 mt28c128564w30dfw-705 btwt micron -70 bottom/top 54
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 10 ?2003 micron technology. inc. table 3: ball descriptions 77-ball fbga numbers symbol ty p e descriptions f1, e1, d1, c1, a1, b1, e2, d2, e6, c7, d7, a8, b8, c8, e7, d8, e8, c2, a2, a3, d6, a7 a0?a21 input addresses: flash: a0?a21 (128mb ?d?) cellularram: a0?a20 (32mb) cellularram: a0?a21 (64mb) j1 f_ce1# input flash chip enable #1 f8 f_ce2# input flash chip enable #2 h2 f_oe1# input flash output enable #1 g8 f_oe2# input flash output enable #2 e5 f_we# input flash write enable d4 f_wp# input flash write protect b2 ps_lb# input cellularram lower byte control e3 ps_ub# input cellularram upper byte control c5 ps_we# input cellularram write enable g1 ps_oe# input cellularram output enable c6 ps_ce# input cellularram chip enable j8 ps_zz# input cellularram deep sleep mode and configuration mode d5 adv# input flash address valid (burst operation only) b6 clk input flash clock (burst operation only) e4 f_rst# input flash reset g2, g3, f3, g4, h5, f5, h6, g7, f2, h3, f4, h4, g5, f6, g6, h7 dq0?dq15 i/o flash/cellularram data input/output f7 wait# output flash wait# k7 f_v ss supply flash core ground c4 f_v pp supply flash v pp j6 f_v cc supply flash core power supply k5 ps_v ss supply cellularram core ground j5 ps_v cc supply cellularram core power supply j7 v cc q supply flash/cellularram i/o supply k6 v ss q supply flash/cellularram i/o ground b5, b7, h1, j2, j3, j4 nc ? no connect b3, c3, d3 ? ? ball not mounted
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 11 ?2003 micron technology. inc. boot configurations the possible configurations for flash die are shown in table 4 below. this table shows the possible config- urations of the two flash de vices for either top boot or bottom boot: f_ce1# and f_ce2# indicate to which flash die the configuration is referred. multichip packaging considerations multichip packaging presents unique chal- lenges when controlling complex memory devices. the MT28C128532W18/w30d and mt28c128564w18/w30d devices combine two micron flash devices with a single cellularram device. unique ids, stat e machines, and registers each flash device has a separate command state machine (csm) and status register (sr) and read con- figuration register (rcr). the rcr settings are sepa- rate and can be different for the upper and lower device. each flash device has its own otp, cfi, and device code. depending on the boot configuration of each flash device, the otp, cfi, and device code infor- mation may differ. both flash devices will share the same manid, either micron (0x2ch) or intel (0x89h), which is defined by the part number. (se figure 4 on page 9.) the cellularram has a configuration register (cr) that defines how the device performs self refresh. command codes all flash command codes are independent within each device. care must be taken when crossing the array boundary between the upper and lower flash and the cellularram to ensure that only one device is enabled at one time. in a two-cycle command sequence such as word program (0x40/data), it is required that both com- mands be issued to the same device. it is not recommended that read and erase operations occur simultaneously on two devices. read operation page and burst read modes are limited to the address boundaries of each device. a new page/ burst operation must be started when crossing a device boundary. flash reset the reset control is shared by both flash die. bringing rst# control low will reset both the upper and lower device. power consumption multiple chip packaging requires that power calculations consider the active operation of the upper and lower flash as well as that of the cellu- larram. total power consumed will be the sum of the currents associated with the state of each device. table 9 on page 14 shows the power con- sumption specifications. table 4: possible boot configurations for flash die configuration f_ce1# f_ce2# order code top/top top top tt bottom/top bottom top bt top/bottom top bottom tb bottom/bottom bottom bottom bb
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 12 ?2003, micron technology, inc. table 5: truth table modes flash signals shared signals cellularram signals memory output f_ce1# f_ce2# f_oe1# f_oe2# f_we# f_rp# adv# wait# ps_ce# ps_zz# ps_oe# ps_ ub/lb ps_we# memory bus control dq0? dq15 flash f_ce1# read lhl hhhlvalid cellularram must be in high-z flash d out write lhhhlhlvalid flashd in standby hxx xxhxx cellularram any mode allowable other high-z output disable lxhxhhxx otherhigh-z reset x x x x x l x x none high-z flash f_ce2# read hlh lhhlvalid cellularram must be in high-z flash d out write hlhhlhlvalid flashd in standby xhx xxhxx cellularram any mode allowable other high-z output disable xlxhhhxx otherhigh-z reset x x x x x l x x none high-z cellularram read flash must be in high-z xlvalidl h l l hpsramd out write xlvalidl h h l lpsramd in standby flash any mode allowable xx x h h x x x otherhigh-z output disable xx x l h h x x otherhigh-z deep sleep mode xx x h l x x x otherhigh-z
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 13 ?2003 micron technology. inc. flash electrical specifications note: 1. stresses greater than those listed in table 6 may cause perm anent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. maximum dc voltage on v pp may overshoot to +14v for periods <20ns. table 6: absolute maximum ratings note 1 parameters/conditions min max units notes voltage to any ball except v cc , v cc q, and v pp w18 w30 -0.5 -0.5 +2.45 +3.45 v v pp voltage -0.2 +14 v 2 v cc supply voltage w18 w30 -0.2 +2.45 +2.5 v v cc q supply voltage w18 w30 -0.2 +2.45 +3.3465 v output short circuit current 100 ma operating temperature range -25 +85 c storage temperature range -55 +125 c soldering cycle +260c for 10s table 7: recommended operating conditions parameter symbol min typ max units operating temperature t a -25 ? +85 c v cc supply voltage v cc 1.70 ? 1.95 v i/o supply voltage vccq (w18) 1.70 ? 2.24 v vccq (w30) 3.3 input/output capacitance: dqs c io ?4.06.5pf v pp voltage v pp 1 0.9 ? 1.95 v v pp in-factory programming voltage v pp 2 11.4 ? 12.6 v block erase cycling (v pp = v pp 1 ) ? ? 100,000 cycles block erase cycling (v pp = v pp 2 ) ??1,000cycles time for v pp at v pp 2 t pph ? ? 100 hours table 8: capacitance t a = +25 c; f = 1 mhz parameter/condition symbol ty p max units input capacitance c in tbd tbd pf output capacitance c out tbd tbd pf
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 14 ?2003 micron technology. inc. table 9: dc characteristics notes appear on following page; all currents are in rms unless otherwise noted parameter sym min w18/w30 units notes typ max input low voltage v il 00.4v1 input high voltage v ih v cc q ? 0.4 v cc qv 1 output low voltage i ol = 100a v ol 0.1 v output high voltage i oh = -100a v oh v cc q ? 0.1 v v pp lockout voltage f_v pplk 0.4 v v cc lock f_v lko 1.0 v vccq lock f_v ilkoq tbd v input load current f_i li 1 a output leakage current f_i lo 1 a v cc standby current with 32mb psram with 64mb psram i ccs 140 150 a asynchronous read current f_i ccr 2 4 ma page read current f_i ccr 3 6 ma vcc burst read current 4-word burst read current @ 54 mhz 4-word burst read current @ 66 mhz f_i ccr 3 3 5 5 ma 2, 3, 5 vcc burst read current 8-word burst read current @ 54 mhz 8-word burst read current @ 66 mhz f_i ccr 3 3 5 5 ma 2, 3, 5 vcc continuous burst read current continous burst read current @ 54 mhz continous burst read current @ 66 mhz f_i ccr 7 8 10 12 ma 2, 3, 5 f_v cc program current f_v pp = f_v pp 1 , program in progress f_v pp = f_v pp 2 , program in progress f_i ccw 18 8 25 15 ma f_v cc block erase current f_v pp = f_v pp 1 , block erase in progress f_v pp = f_v pp 2 , block erase in progress f_i cce 18 8 30 15 ma f_v cc program suspend current f_i ccws 725 a 4 f_v cc erase suspend current f_i cces 725 a 4 f_v cc automatic power save current f_i ccaps 725 a f_v pp standby current f_v pp program suspend current f_i pps f_i ppws 0.2 0.2 5 5 a f_v pp erase suspend current f_v pp read current f_i ppes f_i ppr 0.2 2 5 15 a
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 15 ?2003 micron technology. inc. note: 1. v il may decrease to -0.4v and v ih may increase to v cc q + 0.3v for durations not to exceed 20ns. 2. aps mode reduces i cc to approximately i ccs levels. 3. test conditions: v cc = v cc (max), ce# = v il , oe# = v ih . all other inputs = v ih or v il . 4. i cces and i ccws values are valid when the device is deselected. any read operation performed while in suspend mode will have an additional current draw of suspend current (i cces or i ccws ). 5. synchronous clock = 54 mhz/burst length = continuous is worst case for v cc burst read current. 6. this parameter is specified with the outputs disabled to avoid external loading effects. the user must add current required to drive output capacitance expected in the actual system. 7. this device assumes a standby mode if the chip is disabled (ce# high). it will also automatically go into a standby mode whenever all input signals are quiescent (not toggling) , regardless of the state of ce#, ub#, and lb#. in order to achieve low standby current all inputs must be either v cc or v ss . 8. v in = v cc or 0v chip enabled, i out = 0. 9. v in = v cc or 0v chip enabled, i out = 0. f_v pp program current f_v pp = f_v pp 1 , program in progress f_v pp = f_v pp 2 , program in progress f_i ppw 0.05 8 0.10 22 ma f_v pp erase current f_v pp = f_v pp 1 , erase in progress f_v pp = f_v pp 2 , erase in progress f_i ppe 0.05 8 0.10 22 ma read operating current asynchronous random read asynchronous page read initial access, burst read continuous burst read ps_i cc 1 (-60) 25 15 35 15 (-70) 21 13 21 11 ma 6, 7, 8 write operating current ps_i cc 2 (-60) (-70) 25 21 ma 6, 7, 9 table 9: dc characteristics (continued) notes appear on following page; all currents are in rms unless otherwise noted parameter sym min w18/w30 units notes typ max
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 16 ?2003 micron technology. inc. ta bl e 1 0 : cf i offset data description 00 2ch manufacturer?s identification code (manid) micron 89h intel 01 44c6h/8864h device id code (devid) top boot block device id code (micron / intel) 44c7h/8865h bottom boot block device id code (micron/intel) 02 ? 0f reserved reserved 10, 11 0051, 0052 ?qr? 12 0059 ?y? 13, 14 0003, 0000 primary oem command set 15, 16 0039, 0000 address for primary extended table 17, 18 0000, 0000 alternate oem command set 19, 1a 0000, 0000 address for oem extended table 1b 0017 v cc min for erase/write; bit 7?bit 4 volts in bcd; bit 3?bit 0 100mv in bcd 1c 0019 v cc max for erase/write; bit 7?bit 4 volts in bcd; bit 3?bit 0 100mv in bcd 1d 00b4 v pp min for erase/write; bit 7?bit 4 volts in hex; bit 3?bit 0 100mv in bcd 1e 00c6 v pp max for erase/write; bit 7?bit 4 volts in hex; bit 3?bit 0 100mv in bcd 1f 0004 typical timeout for single byte/word program, 2 n s, 0000 = not supported 20 0000 typical timeout for maximum size multiple byte/word program, 2 n s, 0000 = not supported 21 000a typical timeout for individual block erase, 2 n s, 0000 = not supported 22 0000 typical timeout for full chip erase, 2 n s, 0000 = not supported 23 0004 maximum timeout for single byte/word program, 2 n s, 0000 = not supported 24 0000 maximum timeout for maximum size multiple byte/word program, 2 n s, 0000 = not supported 25 0002 maximum timeout for individual block erase, 2 n s, 0000 = not supported 26 0000 maximum timeout for full chip erase, 2 n s, 0000 = not supported 27 0017 device size, 2 n bytes 28 0001 bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3 29 0000 flash device interface description 0000 = async 2a, 2b 0000, 0000 maximum number of bytes in multibyte program or page, 2 n 2c 0002 number of erase block regions within device (4k words and 32k words) 2d, 2e 007e, 0000 top boot block device erase block region information 1 0007, 0000 bottom boot block device erase block region information 1 2f, 30 0000, 0001 top boot block device erase block region information 1 0020, 0000 bottom boot block device erase block region information 1 31, 32 0007, 0000 top boot block device erase block region information 2 007e, 0000 bottom boot block device erase block region information 2 33, 34 0020, 0000 top boot block device erase block region information 2 0000, 0001 bottom boot block device erase block region information 2 35, 36 0000, 0000 reserved for future erase block region information 37, 38 0000, 0000 reserved for future erase block region information 39, 3a 0050, 0052 ?pr? 3b 0049 ?i? 3c 0031 major version number, ascii
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 17 ?2003 micron technology. inc. 3d 0033 minor version number, ascii 3e 3f 40 41 00e6 0003 0000 0000 optional feature and command support bit 0 chip erase supported no = 0 bit 1 suspend erase supported = yes = 1 bit 2 suspend program supported = yes = 1 bit 3 chip lock/unlock supported = no = 0 bit 4 queued erase supported = no = 0 bit 5 instant individual block locking supported = yes = 1 bit 6 protection bits supported = yes = 1 bit 7 page mode read supported = yes = 1 bit 8 synchronous read supported = no = 0 bit 9 simultaneous operat ion supported = yes = 1 42 0001 program supported after erase suspend = yes 43, 44 0003, 0000 bit 0 block lock status active = yes; bit 1 block lock down active = yes 45 0018 v cc supply optimum, 00 = not supported, bit 7?bit 4 volts in bcd; bit 3?bit 0 100mv in bcd 46 00c0 v pp supply optimum, 00 = not supported, bit 7?bit 4 volts in bcd; bit 3?bit 0 100mv in bcd 47 0001 number of protection register fields in jedec id space 48, 49 0080, 0000 lock bytes low address, lock bytes high address 4a, 4b 0003, 0003 2 n factory programmed bytes, 2 n user programmable bytes 4c 0004 page mode read capability 4d 0004 number of synchronous mode read configuration fields that follow 4e 0001 synchronous mode read capability configuration 1 4f 0002 synchronous mode read capability configuration 2 50 0007 synchronous mode read capability configuration 3 51 0000 synchronous mode read capability configuration 4 52 top: 0002 number of device hardware partition regions within the device bot :0002 53 top: 000f number of identical partitions within the partition region bot: 0001 54 top: 0000 number of identical partitions within the partition region bot: 0000 55 top: 0011 number of identical partitions within the partition region bot: 0011 56 top: 0000 simultaneous program/erase operations allowe d in other partitions while a partition in this region is in program mode bot: 0000 57 top: 0000 simultaneous program/erase operations allowe d in other partitions while a partition in this region is in erase mode bot: 0000 58 top: 0001 types of erase block regions in this partition region bot: 0002 59 top: 0007 partition region 1 erase block type 1 information bot: 0007 5a top: 0000 partition region 1 erase block type 1 information bot: 0000 5b top: 0000 partition region 1 erase block type 1 information bot: 0020 5c top: 0001 partition region 1 erase block type 1 information bot: 0000 table 10: cfi (continued) offset data description
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 18 ?2003 micron technology. inc. 5d top: 0064 partition 1 (erase block type 1) bot: 0064 5e top: 0000 partition 1 (erase block type 1) bot: 0000 5f top: 0001 partition 1 (erase block type 1) bits per cell; internal ecc bot: 0001 60 top: 0003 partition 1 (erase block type 1) page mode and synchronous mode capabilities bot: 0003 bot: 61 partition region 1 erase block type 2 information bot: 0006 bot: 62 partition region 1 erase block type 2 information bot: 0000 bot: 63 partition region 1 erase block type 2 information bot: 0000 bot: 64 partition region 1 erase block type 2 information bot: 0001 bot: 65 partition region 1 (erase block type 2) bot: 0064 bot: 66 partition region 1 (erase block type 2) bot: 0000 bot: 67 partition region 1 (erase block type 2) bits per cell bot: 0001 bot: 68 partition region 1 (erase block type 2) page mode and synchronous mode capabilities bot: 0003 top: 61 top: 0001 number of identical partitions within the partition region bot: 69 bot: 000f top: 62 top: 0000 number of identical partitions within the partition region bot: 6a bot: 0000 top: 63 top: 0011 number of program/erase operations allowed in a partition bot: 6b bot: 0011 top: 64 top: 0000 simultaneous program/erase operations allowe d in other partitions while a partition in this region is in program mode bot: 6c bot: 0000 top: 65 top: 0000 simultaneous program/erase operations allowe d in other partitions while a partition in this region is in erase mode bot: 6d bot: 0000 top: 66 top: 0002 types of erase block regions in this partition region bot: 6e bot: 0001 top: 67 top: 0006 partition region 2 erase block type 1 information bot: 6f bot: 0007 top: 68 top: 0000 partition region 2 erase block type 1 information bot: 70 bot: 0000 top: 69 top: 0000 partition region 2 erase block type 1 information bot: 71 bot: 0000 top: 6a top: 0001 partition region 2 erase block type 1 information bot: 72 bot: 0001 table 10: cfi (continued) offset data description
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 19 ?2003 micron technology. inc. top: 6b top: 0064 partition 2 (erase block type 1) bot: 73 bot: 0064 top: 6c top: 0000 partition 2 (erase block type 1) bot: 74 bot: 0000 top: 6d top: 0001 partition 2 (erase block type 1) bits per cell bot: 75 bot: 0001 top: 6e top: 0003 partition 2 (erase block type 1) page mode and synchronous mode capabilities bot: 76 bot: 0003 top: 6f top: 0007 partition region 2 erase block type 2 information top: 70 top: 0000 partition region 2 erase block type 2 information top: 71 top: 0020 partition region 2 erase block type 2 information top: 72 top: 0000 partition region 2 erase block type 2 information top: 73 top: 0064 partition 2 (erase block type 2) top: 74 top: 0000 partition 2 (erase block type 2) top: 75 top: 0001 partition 2 (erase block type 2) bits per cell top: 76 top: 0003 partition 2 (erase block type 2) page mode and synchronous mode capabilities 77 reserved 78 32mb: 0020 psram density 64mb: 0040 79?7f reserved table 10: cfi (continued) offset data description
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micr on technology, inc., reserves the right to change products or specif ications without notice.. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 20 ?2003 micron technology, inc ? 8000 s. federal way , p. o . box 6, bo ise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micr on, the m logo, and the micr on logo are trademarks and/or service marks o f micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of infineon technologies outside the u.s . all oth er trad emarks are the property of their respective owners. figure 5: 77-ball fbga note: 1. all dimensions in millimeters. data sheet designation advance: this data sheet conta ins initial descri ptions of products still under development. f or additional documentation concerning flash and cell ularram features, functional descriptions, program- ming , and timing, please refer to the mt28f644w18/w30 data sheet at www.micron.com/flash and the mt45w2mw16pfa and mt45w4mw16pfa data sheets at http://www.micron.com/cellularram. ball a1 id 1.025 0.075 seating plane 0.10 c c 1.40 max ball a8 ball a1 id 0.80 typ 0.80 typ 2.80 0.05 5.60 ball a1 8.00 0.10 4.00 0.05 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.35mm on a 0.30mm smd ball pad. 77x ?
128mb multibank burst flash 32mb/64mb async/page cellularram combo advance 09005aef80b10a55 micron technology, inc., reserves the right to change products or specifications without notice. mt28c128564w18d_b.fm - rev. b, pub 7/03 en 21 ?2003 micron technology. inc. revision history rev b, advance................................................................................................................. ................................................7/03 included w30 specification added intel manid varient updated mechanical information table 10 (cfi) clarification original document, rev. a ...................................................................................................... ........................................5/03

▲Up To Search▲

Price & Availability of MT28C128532W18

	To Download MT28C128532W18 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .