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1/101 www.dynexsemi.com 54hsc/t series the cmos/sos hsc/t series offer the combined benefits of low power, high speed cmos with the inherent latch up immunity, single event upset (seu) immunity and the high level of radiation hardness of silicon on sapphire technology. the 54hsc/t series of circuits are pin for pin compatible with the 54ls series range. hsc and hst devices have cmos and ttl compatible inputs/outputs respectively. features radiation hard to 1mrad (si) high seu immunity, latch up free low power cmos/sos technology plug in replacement for 54/74ls, hc and hct dual in line or flatpack packages adders 54hsc/t283 4-bit binary full adders with fast carry counters 54hsc/t161 4-bit synchronous binary counter 54hsc/t163 synchronous 4-bit counter 54hsc/t191 synchronous 4-bit counter decoders/demultiplexers 54hsc/t138 3-line to 8-line decoder/multiplexer 54hsc/t139 dual 2 to 4 decoders/multiplexers 54hsc/t148 8-line to 3-line octal priority encoders 54hsc/t151 1 of 8 data selectors/multiplexers 54hsc/t154 4 to 16-line decoders/demultiplexers 54hsc/t157 quad 2-line to 1-line data selectors/multiplexers 54hsc/t238 3 to 8 decoder/demultiplexer 54hsc/t253 dual 4 to 1 data selectors/multiplexers registers 54hsc/t164 8-bit parallel output serial shift register 54hsc/t165 parallel load 8-bit shift register 54h5c/t166 8-bit shift register comparators 54hsc/t521 8-bit magnitude comparator line drivers 54hsc/t240 octal 3-state driver inverting 54hsc/t241 octal 3-state driver complementary enable 54hsc/t244 octal 3-state driver 54hsc/t540 octal 3-state driver/buffer inverting 54hsc/t541 octal 3-state driver/buffer transceivers 54hsc/t245 octai bus transceiver latches 54hsc/t373 octal transparent latch, 3-state outputs 54hsc/t573 octal transparent latch, 3-state outputs miscellaneous 54hsc/t670 4 x 4 register files with tri-state outputs gates and buffers 54hsc/t00 quadruple 2-input positive nand gates 54hsc/t02 quadruple 2-input positive nor gates 54hsc/to3 quadruple 2-input positive nand gates with open collector outputs 54hsc/t04 hex inverters 54hsc/t08 quadruple 2-input positive and gates 54hsc/t10 triple 3-input positive nand gates 54hsc14 hex schmitt-trigger inverters 54hsc/t21 dual 4-input positive and gates 54hsc/t27 triple 3-input positive nor gates 54hsc/t32 quadruple 2-input positive or gates 54hsc/t86 quadruple 2-input exclusive or gates 54hsc/t125 quadruple bus buffer gates with tri-state outputs (active low enable) 54hsc/t126 quadruple bus buffer gates wlth tri-state outputs (active high enable) flip-flops 54hsc/t74 dual d-type flip-flops wlth preset and clear 54hsc/t109 dual j-kb flip-flop with preset and clear 54hsc/t273 octal d-type flip-flops 54hsc/t374 octal d-type edge triggered flip-flops 54hsc/t574 octal d-type edge triggered flip-flops 54hsc/t series radiation hard high speed cmos/sos logic replaces may 1995 version, ds3594-3.3 ds3594-4.0 november 2002
2/101 www.dynexsemi.com 54hsc/t series total dose radiation not exceeding 3x10 5 rad(si) symbol parameter conditions min. typ. max. units v dd supply voltage - 4.5 5.0 5.5 v v ih1 hst input high voltage - 2.0 - - v v il1 hst input low voltage - - - 0.8 v v ih2 hsc input high voltage - 3.5 - - v v il2 hsc input low voltage - - - 1.5 v v oh output high voltage v in = v ih or v il i oh = -20 a* v dd -0.1 - - v i oh = 6ma* 3.7 - - v i oh = -11ma 2.5 - - v v ol output low voltage v in = v ih or v il i ol = -20 a* - - 0.1 v i ol = 6ma* - - 0.2 v i ol = 9ma - - 0.4 v i il input leakage current v in = v dd or v ss -15 a all inputs i ol output leakage current v out = v dd or v ss -2050 a outputs disabled i dd quiescent current v in = v dd - ?? a outputs unloaded v dd = 5v 10%, over full operating temperature range. * guaranteed but not tested. ? refer to individual device types (-55 c / +125 c). figure 2: electrical characteristics figure 1: absolute maximum ratings dc characteristics and ratings parameter min. max. units supply voltage -0.5 10 v input voltage -0.3 v dd +0.3 v current through any pin -25 +25 ma operating temperature -55 125 c storage temperature -65 150 c note: stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3/101 www.dynexsemi.com 54hsc/t series 54hsc/t00 : quadruple 2-input positive nand gates figure 2: logic diagram figure 3: pin out 14 vdd 13 4b 12 4a 11 4y 10 3b 9 3a 8 3y 1 1a 2 1b 3 1y 4 2a 5 2b 6 2y 7 vss top view +25 c-55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns the 54hsc/t00 is a quadruple 2-input positive nand gate. inputs outputs ab y ll h lh h hl h hh l h = high level, l = low level figure 1: function table figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
4/101 www.dynexsemi.com 54hsc/t series 54hsc/t02 : quadruple 2-input positive nor gates figure 2: logic diagram figure 3: pin out the 54hsc/t02 is a quadruple 2-input positive nor gate. inputs outputs ab y ll h lh l hl l hh l h = high level, l = low level figure 1: function table 14 vdd 13 4y 12 4b 11 4a 10 3y 9 3b 8 3a 1 1y 2 1a 3 1b 4 2y 5 2a 6 2b 7 vss top view +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
5/101 www.dynexsemi.com 54hsc/t series 54hsc/t03 : quadruple 2-input positive nand gates with open collector outputs figure 2: logic diagram figure 3: pin out 14 vdd 13 4b 12 4a 11 4y 10 3b 9 3a 8 3y 1 1a 2 1b 3 1y 4 2a 5 2b 6 2y 7 vss top view +25 c-55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns the 54hsc/t03 is a quadruple 2-input positive nand gate with open collector output. inputs outputs ab y ll h lh h hl h hh l h = high level, l = low level figure 1: function table figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 0.5 a
6/101 www.dynexsemi.com 54hsc/t series 54hsc/t04 : hex inverters figure 2: logic diagram figure 3: pin out the 54hsc/t04 consists of six hex inverters. 14 vdd 13 6a 12 6y 11 5a 10 5y 9 4a 8 4y 1 1a 2 1y 3 2a 4 2y 5 3a 6 3y 7 vss top view inputs outputs ay hl lh h = high level, l = low level figure 1: function table +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
7/101 www.dynexsemi.com 54hsc/t series 54hsc/t08 : quadruple 2-input positive and gates figure 2: logic diagram figure 3: pin out the 54hsc/t08 is a quadruple 2-input positive and gate. inputs outputs ab y ll l lh l hl l hh h h = high level, l = low level figure 1: function table 14 vdd 13 4b 12 4a 11 4y 10 3b 9 3a 8 3y 1 1a 2 1b 3 1y 4 2a 5 2b 6 2y 7 vss top view +25 c-55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
8/101 www.dynexsemi.com 54hsc/t series 54hsc/t10 : triple 3-input positive nand gates figure 2: logic diagram figure 3: pin out the 54hsc/t10 is a triple 3-input positive nand gate. inputs outputs abc y lxx h xlx h xxl h hhh l h = high level, l = low level, x = irrelevant figure 1: function table 14 vdd 13 1c 12 1y 11 3c 10 3b 9 3a 8 3y 1 1a 2 1b 3 2a 4 2b 5 2c 6 2y 7 vss top view +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
9/101 www.dynexsemi.com 54hsc/t series 54hsc14 : hex schmitt-trigger inverters figure 2: logic diagram figure 3: pin out the 54hsc/t14 consists of six hex schmitt-trigger inverters. 14 vdd 13 6a 12 6y 11 5a 10 5y 9 4a 8 4y 1 1a 2 1y 3 2a 4 2y 5 3a 6 3y 7 vss top view inputs outputs ay lh hl h = high level, l = low level figure 1: function table +25 c-55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
10/101 www.dynexsemi.com 54hsc/t series 54hsc/t21 : dual 4-input positive and gates figure 2: logic diagram figure 3: pin out the 54hsc/t21 is a dual 4-input positive and gate. inputs outputs abcd y llll l lllh l llhl l llhh l lhll l lhlh l lhhl l lhhh l hlll l hllh l hlhl l hlhh l hhl l l hhlh l hhhl l hhhh h h = high level, l = low level figure 1: function table 14 vdd 13 2d 12 2c 11 nc 10 2b 9 2a 8 2y 1 1a 2 1b 3 nc 4 1c 5 1d 6 1y 7 vss top view +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
11/101 www.dynexsemi.com 54hsc/t series 54hsc/t27 : triple 3-input positive nor gates figure 2: logic diagram figure 3: pin out the 54hsc/t27 is a triple 3-input positive nor gate. inputs outputs abc y lll h llh l lhl l lhh l hll l hlh l hhl l hhh l 14 vdd 13 1c 12 1y 11 3c 10 3b 9 3a 8 3y 1 1a 2 1b 3 2a 4 2b 5 2c 6 2y 7 vss top view h = high level, l = low level figure 1: function table +25 c-55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
12/101 www.dynexsemi.com 54hsc/t series 54hsc/t32 : quadruple 2-input positive or gates figure 2: logic diagram figure 3: pin out the 54hsc/t32 is a quadruple 2-input positive or gate. inputs outputs ab y ll l lh h hl h hh h h = high level, l = low level figure 1: function table 14 vdd 13 4b 12 4a 11 4y 10 3b 9 3a 8 3y 1 1a 2 1b 3 1y 4 2a 5 2b 6 2y 7 vss top view +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
13/101 www.dynexsemi.com 54hsc/t series 54hsc/t86 : quadruple 2-input exclusive or gates figure 2: logic diagram figure 3: pin out the 54hsc/t86 is a quadruple 2-input exclusive or gate. inputs outputs ab y ll l lh h hl h hh l h = high level, l = low level figure 1: function table 14 vdd 13 4b 12 4a 11 4y 10 3b 9 3a 8 3y 1 1a 2 1b 3 1y 4 2a 5 2b 6 2y 7 vss top view +25 c-55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay time, low to high level output 11 20 17 22 ns t phl propagation delay time, high to low level output 10 18 18 20 ns figure 4: switching characteristics figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 300 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
14/101 www.dynexsemi.com 54hsc/t series 54hsc/t125 : quadruple bus buffer gates with tri-state outputs (active low enable) the 54hsc/t125 is a quadruple bus buffer gate. when g is low the a input is transferred to the y output. when g is high the output is in a high impedance state. inputs outputs g ay ll l lh h hl z hh z h = high level, l = low level, z = high impedance figure 1: function table figure 2: logic diagram figure 3: pin out +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay a to y 15 18 18 28 ns t phl propagation delay a to y 15 20 18 28 ns t pzh propagation delay g to y 12 25 15 28 ns t pzl propagation delay g to y 12 25 15 28 ns t phz propagation delay y to tri-state 12 25 15 28 ns t plz propagation delay y to tri-state 12 25 15 28 ns 14 vdd 13 4g 3g 1g 2g figure 4: switching characteristics
15/101 www.dynexsemi.com 54hsc/t series figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a 54hsc/t125 : quadruple bus buffer gates with tri-state outputs (active low enable)
16/101 www.dynexsemi.com 54hsc/t series 54hsc/t126 : quadruple bus buffer gates with tri-state outputs (active high enable) the 54hsc/t126 is a quadruple bus buffer gate. when g is high the a input is transferred tp the y output. when g is low the output is in a high impedance state. inputs outputs ga y hl l hh h ll z lh z h = high level, l = low level, z = high impedance figure 1: function table figure 2: logic diagram figure 3: pin out +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay a to y 14 25 17 28 ns t phl propagation delay a to y 15 25 19 28 ns t pzh propagation delay g to y 15 25 18 28 ns t pzl propagation delay g to y 17 25 19 28 ns t phz propagation delay y to tri-state 17 25 20 28 ns t plz propagation delay y to tri-state 15 25 19 28 ns 14 vdd 13 4g 12 4a 11 4y 10 3g 9 3a 8 3y 1 1g 2 1a 3 1y 4 2g 5 2a 6 2y 7 vss top view figure 4: switching characteristics
17/101 www.dynexsemi.com 54hsc/t series figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a 54hsc/t126 : quadruple bus buffer gates with tri-state outputs (active high enable)
18/101 www.dynexsemi.com 54hsc/t series 54hsc/t74 : dual d-type flip-flops with preset and clear the 54hsc/t74 is a dual d-type flip-flop. the d inputs are transferred to the q outputs on the positive going edge of the clock pulse. the clear is active low. inputs output preset clear clock d q q lh xxhl hl xxlh l l x x h* h* h h l-h h h l h h l-h l l h hh lxq 0 q 0 h = high level, l = low level, x = irrelevant, * = unknown return state figure 1: function table figure 2: logic diagram figure 3: pin out 14 vdd 13 2clear 2pr 2q 1clear 1pr 1q +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. preset to q or q . 15201824ns t phl propagation delay. preset to q or q . 16201024ns t plh propagation delay. clear to q or q . 18201524ns t phl propagation delay. clear to q or q . 15201524ns t plh propagation delay. clock to q or q . 17251525ns t phl propagation delay. clock to q or q . 18251525ns figure 4: switching characteristics
19/101 www.dynexsemi.com 54hsc/t series 54hsc/t74 : dual d-type flip-flops with preset and clear figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
20/101 www.dynexsemi.com 54hsc/t series 54hsc/t109 : dual j-kb flip-flops with preset and clear inputs output preset clear clock j kb q q lh xxxhl hl xxxlh ll xxxh*h* hh lllh hh hl toggle toggle hh lhq 0 q 0 hh hhhl hh lxxq 0 q 0 h = high level, l = low level, x = irrelevant, * = unknown return state figure 2: function table figure 1: pin out figure 3: logic diagram +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. preset to q or q . 15191719ns t phl propagation delay. preset to q or q . 16251925ns t plh propagation delay. clear to q or q . 17252025ns t phl propagation delay. clear to q or q . 15251825ns t plh propagation delay. clock to q or q . 18252125ns t phl propagation delay. clock to q or q . 15251825ns 1clr 14 2j 13 2k 12 2ck 11 2pr 10 2q 9 2q 3 1k 4 1ck 5 1pr 6 1q 7 1q 8 vss top view 16 vdd 15 2clr 1 2 1j the 54hsc/t109 is a dual positive-edge-triggered j-kb flip-flop with preset and clear. figure 4: switching characteristics
21/101 www.dynexsemi.com 54hsc/t series 54hsc/t109 : dual j-kb flip-flops with preset and clear figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
22/101 www.dynexsemi.com 54hsc/t series 54hsc/t273 : octal d-type flip-flops the 54hsc/t273 is an octal d-type flip-flop with a direct active low clear. the d-inputs are transferred to the q-outputs on the positive going edge of the clock pulse. inputs outputs clear clock d q lxx l h l-h h h h l-h l l hlxq 0 q 0 = level of q before inputs were established h = high level, l = low level, x = irrelevant figure 2: pin out clear figure 1: function table figure 3: logic diagram +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. clear to q or q . 14251728ns t phl propagation delay. clear to q or q . 16251928ns t plh propagation delay. clock to q or q . 15251828ns t phl propagation delay. clock to q or q . 17252028ns figure 4: switching characteristics
23/101 www.dynexsemi.com 54hsc/t series 54hsc/t273 : octal d-type flip-flops figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
24/101 www.dynexsemi.com 54hsc/t series 54hsc/t374 : octal d-type edge-triggered flip-flops the 54hsc/t374 consists of 8 positive-edge triggered d- type flip-flops with tri-state output. figure 2: pin out inputs outputs oc clock d q l hh l ll llxq 0 hxx z h = high level, l = low level, x = irrelevant, z = high impedance figure 1: function table oc +25 c -55 c / +125 c symbol parameter min. typ. max. min. typ. max. units t plh propagation delay. low to high output. - 14 22 - 17 25 ns t phl propagation delay. high to low output. - 15 22 - 16 25 ns t pzl propagation delay. enable to low. - 13 20 - 16 25 ns t pzh propagation delay. enable to high. - 16 20 - 18 23 ns t plz propagation delay. disable from low. - 14 20 - 16 22 ns t phz propagation delay. disable from high. - 13 18 - 15 20 ns figure 3: switching characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 4: dc characteristics
25/101 www.dynexsemi.com 54hsc/t series 54hsc/t374 : octal d-type edge-triggered flip-flops figure 5: logic diagram
26/101 www.dynexsemi.com 54hsc/t series 54hsc/t574 : octal d-type edge-triggered flip-flops the 54hsc/t574 consists of 8 positive-edge triggered d- type flip-flops with tri-state output. figure 2: pin out inputs outputs oc clock d q l hh l ll llxq 0 hxx z h = high level, l = low level, x = irrelevant, z = high impedance figure 1: function table +25 c -55 c / +125 c symbol parameter min. typ. max. min. typ. max. units t plh propagation delay. low to high output. - 16 25 - 19 28 ns t phl propagation delay. high to low output. - 19 27 - 22 30 ns t pzl propagation delay. enable to low. - 13 21 - 16 24 ns t pzh propagation delay. enable to high. - 16 24 - 19 27 ns t plz propagation delay. disable from low. - 14 22 - 17 25 ns t phz propagation delay. disable from high. - 13 21 - 16 24 ns oc figure 3: switching characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 4: dc characteristics
27/101 www.dynexsemi.com 54hsc/t series 54hsc/t574 : octal d-type edge-triggered flip-flops figure 5: logic diagram
28/101 www.dynexsemi.com 54hsc/t series 54hsc/t283 : 4-bit binary full adders with fast carry the 54hsc/t283 are 4-bit binary full adders with fast carry. input output when co=l / when c2=l when co=h / when c2=h a1/a3 b1/b3 a2/a4 b2/b4 1/ 3 2/ 4 c2/c4 1/ 3 2/ 4 c2/c4 l llllllhll hlllhlllhl lhllhlllhl h hlllhlhhl l lhllhlhhl hlhlhhlllh lhhlhhlllh h hhlllhhlh l llhlhlhhl hllhhhlllh lhlhhhlllh hhlhllhhlh l lhhl lhhlh hlhhhlhlhh l hhhhlhlhh h hhhlhhhhh h = high level, l = low level figure 1: function table figure 2: pin out +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. c0 to any . 13251628ns t phl propagation delay. c0 to any . 12251528ns t plh propagation delay. ai or bi to i. 14 25 17 28 ns t phl propagation delay. ai or bi to i. 12 25 15 28 ns t plh propagation delay. c0 to c4. 11 25 14 28 ns t phl propagation delay. c0 to c4. 16 25 19 28 ns t plh propagation delay. ai or bi to c4. 15 25 19 28 ns t phl propagation delay. ai or bi to c4. 14 25 17 28 ns figure 3: switching characteristics
29/101 www.dynexsemi.com 54hsc/t series figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a 54hsc/t283 : 4-bit binary full adders with fast carry
30/101 www.dynexsemi.com 54hsc/t series 54hsc/t283 : 4-bit binary full adders with fast carry figure 5: logic diagram
31/101 www.dynexsemi.com 54hsc/t series 54hsc/t161 : 4-bit synchronous binary counter inputs output clear enable p enable t a d load clock q a q d lxxxxx0 h l x x h x inhibit h x l x h x inhibit hx xq n l q n hx x x x lq 0 hx x x x hq 0 hh h x h count carry = h when q a q d = h, q 0 = previous level of q h = high level, l = low level, x = irrelevant figure 1: function table the 54hsc/t161 is a synchronous 4-bit binary counter which features direct clear and an internal carry look-ahead. clear load figure 2: pin out +25 c -55 c / +125 c symbol from (input) to (output) typ. max. typ. max. units t plh clock ripple carry 20 25 23 28 ns t phl clock ripple carry 19 25 22 28 ns t plh clock (load input high) any q output 16 25 19 28 ns t phl clock (load input high) any q output 15 25 18 28 ns t plh clock (load input low) any q output 15 25 18 28 ns t phl clock (load input low) any q output 15 25 18 28 ns t plh enable ripple carry 14 25 17 28 ns t phl enable ripple carry 14 25 17 28 ns t phl clear any q output 18 25 21 28 ns figure 3: switching characteristics
32/101 www.dynexsemi.com 54hsc/t series 54hsc/t161 : 4-bit synchronous binary counter figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
33/101 www.dynexsemi.com 54hsc/t series 54hsc/t161 : 4-bit synchronous binary counter figure 5: logic diagram
34/101 www.dynexsemi.com 54hsc/t series 54hsc/t163 : synchronous 4-bit counter the 54hsc/t163 is a 4-bit counter with synchronous clear. inputs output clear enable p enable t a d load clock q a q d lxxxxx0 h l x x h x inhibit h x l x h x inhibit hx xq n l q n hx x x x lq 0 hx x x x hq 0 hh h x h count carry = h when q a q d = h, q 0 = previous level of q h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out clear load +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay clock to rco 12 20 15 22 ns t phl propagation delay clock to rco 14 20 17 22 ns t plh propagation delay clock to any q 15 20 18 22 ns t phl propagation delay clock to any q 13 20 16 22 ns t plh propagation delay ent to rco 9 15 12 17 ns t phl propagation delay ent to rco 10 15 13 17 ns figure 3: switching characteristics
35/101 www.dynexsemi.com 54hsc/t series 54hsc/t163 : synchronous 4-bit counter figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
36/101 www.dynexsemi.com 54hsc/t series figure 5: logic diagram 54hsc/t163 : synchronous 4-bit counter
37/101 www.dynexsemi.com 54hsc/t series 54hsc/t191 : synchronous 4-bit counter the 54hsc/t191 is a 4-bit synchronous counter with presettable up/down and asynchronous reset. inputs pl ce u /d cp function hl l count up hl h count down l x x x asyn. preset h h x x no change h = high level, l = low level, x = irrelevant, = low-to-high clock (cp) transition. note: u /d or ce should be changed only when clock (cp) is high. figure 2: pin out p1 14 cp 13 rc pl ce u +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay pl to qn - 29 - 33 ns t phl propagation delay pl to qn - 32 - 36 ns t plh propagation delay pn to qn - 27 - 31 ns t phl propagation delay pn to qn - 30 - 34 ns t plh propagation delay cp to qn - 26 - 30 ns t phl propagation delay cp to qn - 29 - 33 ns t plh propagation delay cp to rc -20-23ns t phl propagation delay cp to rc -32-34ns t plh propagation delay cp to tc - 29 - 33 ns t phl propagation delay cp to tc - 32 - 36 ns t plh propagation delay u /d to rc -27-31ns t phl propagation delay u /d to rc -30-34ns t plh propagation delay u /d to tc - 26 - 30 ns t phl propagation delay u /d to tc - 29 - 33 ns t plh propagation delay ce to rc -22-25ns t phl propagation delay ce to rc -35-38ns figure 3: switching characteristics figure 1: function table
38/101 www.dynexsemi.com 54hsc/t series 54hsc/t191 : synchronous 4-bit counter figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: logic diagram 14 cp 5 u/d 11 pl 4 ce p t cp pl ff0 q q p0 15 q0 3 p1 1 2 q1 ff1 p2 10 6 q2 ff2 p3 9 7 q3 ff3 rc 13 tc 12 p t cp pl q q p t cp pl q q p t cp pl q q
39/101 www.dynexsemi.com 54hsc/t series 54hsc/t138 : 3-line to 8-line decoder/multiplexer the 54hsc/t138 is a 3-line to 8-line decoder/multiplexer, with inverted outputs. enable inputs select inputs outputs g1 g 2a g 2bc b a y0y1y2y3y4y5y6y7 x hxxxxhhhhhhhh x xhxxxhhhhhhhh l xxxxxhhh hhhhh h l l l l l lhhhhhhh h l l l lhhlhhhhhh h l l lhlhhlhhhhh h l l lhhhhhlhhhh h l lhl lhhhhlhhh h l lhlhhhhhhlhh h l lhhlhhhhhhlh h l lhhhhhhhhhhl h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. address to output. 17 25 20 28 ns t phl propagation delay. address to output. 19 25 22 28 ns t plh propagation delay. g to output. 21 25 24 28 ns t phl propagation delay. g to output. 21 25 24 28 ns a 14 y1 13 y2 12 y3 11 y4 10 y5 9 y6 3 c 4 g g figure 3: switching characteristics
40/101 www.dynexsemi.com 54hsc/t series 54hsc/t138 : 3-line to 8-line decoder/multiplexer figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: logic diagram
41/101 www.dynexsemi.com 54hsc/t series 54hsc/t139 : dual 2 to 4 decoders/multiplexers the 54hsc/t139 consists of two independent 2 to 4 line decoder/multiplexers. inputs output enable select g b a y0 y1 y2 y3 hxxhhhh ll l lhhh llhhlhh lh l hh l h lhhhhhl h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out 1 g g +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. address to output. 16 28 22 34 ns t phl propagation delay. address to output. 17 28 20 34 ns t plh propagation delay. g to output. 16 22 19 25 ns t phl propagation delay. g to output. 17 22 20 25 ns figure 3: switching characteristics
42/101 www.dynexsemi.com 54hsc/t series 54hsc/t139 : dual 2 to 4 decoders/multiplexers figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 10 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: logic diagram
43/101 www.dynexsemi.com 54hsc/t series 54hsc/t148 : 8-line to 3-line octal priority encoders the 54hsc/t148 is an 8 to 3 line priority encoder. data inputs and outputs are active at the low logic level. data is accepted on the eight priority inputs (i0-i7). the binary code, corresponding to the highest priority input which is low, is generated on the address outputs (a0-a2) if the enable input is high. the group select (gs) is low when one or more priority inputs and the enable input (ei) are low. the enable output (eo) is low when all priority inputs are high and the enable is low. when the enable input is high all outputs are high. figure 1: pin out i4 14 gs 13 i3 12 i2 11 i1 10 i0 9 a0 3 i6 4 i7 5 ei 6 a2 7 a1 8 vss top view 16 vdd 15 eo 1 2 i5 inputs outputs ei i0 i1 i2 i3 i4 i5 i6 i7 a2 a1 a0 gs eo h xxxxxxxx hhhhh l hhhhhhhhhhhhl l xxxxxxxl l l l lh l xxxxxxlhl lhlh l xxxxxlhhlhl lh l xxxxlhhhlhhlh l xxx lhhhhhl l lh l xx lhhhhhhlhlh l x lhhhhhhhhl lh l lhhhhhhhhhhlh h = high level, l = low level, x = irrelevant figure 2: function table +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay ei to a 14 22 17 28 ns t phl propagation delay ei to a 15 22 18 28 ns t plh propagation delay ei to gs 15 22 18 28 ns t phl propagation delay ei to gs 15 22 18 28 ns t plh propagation delay ei to eo 14 22 17 28 ns t phl propagation delay ei to eo 15 22 18 28 ns t plh propagation delay i to a 12 22 15 28 ns t phl propagation delay i to a 14 22 17 28 ns figure 3: switching characteristics
44/101 www.dynexsemi.com 54hsc/t series 54hsc/t148 : 8-line to 3-line octal priority encoders figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
45/101 www.dynexsemi.com 54hsc/t series figure 5: logic diagram 54hsc/t148 : 8-line to 3-line octal priority encoders
46/101 www.dynexsemi.com 54hsc/t series 54hsc/t151 : 1 of 8 data selectors/multiplexers the 54hsc/t151 is a 1 of 8 data selector. when the strobe input is low the device is enabled. when high this forces the w-output high and the y- output low. inputs output select strobe cb a str yw xx x h l h ll l ld 0 d 0 llhld 1 d 1 lh l ld 2 d 2 lhh ld 3 d 3 hl l ld 4 d 4 hl h ld 5 d 5 hh l ld 6 d 6 hh h ld 7 d 7 h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out d3 14 d5 13 d6 12 d7 11 a 10 b 9 c 3 d1 4 d0 5 y 6 w 7 str +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay a b or c to y 15 22 18 25 ns t phl propagation delay a b or c to y 16 22 19 25 ns t plh propagation delay a b or c to w 14 22 17 25 ns t phl propagation delay a b or c to w 15 22 18 25 ns t plh propagation delay strobe to y 14 22 17 25 ns t phl propagation delay strobe to y 16 22 19 25 ns t plh propagation delay strobe to w 14 22 17 25 ns t phl propagation delay strobe to w 15 22 18 25 ns t plh propagation delay d 0 -d 7 to y 12221525ns t phl propagation delay d 0 -d 7 to y 14221725ns t plh propagation delay d 0 -d 7 to w 12221525ns t phl propagation delay d 0 -d 7 to w 14221725ns figure 3: switching characteristics
47/101 www.dynexsemi.com 54hsc/t series figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a 54hsc/t151 : 1 of 8 data selectors/multiplexers
48/101 www.dynexsemi.com 54hsc/t series figure 5: logic diagram 54hsc/t151 : 1 of 8 data selectors/multiplexers
49/101 www.dynexsemi.com 54hsc/t series 54hsc/t154 : 4 to 16 line decoders/demultiplexers the 54hsc/t154 consists of a 4 to 16 line decoder/demultiplexer. inputs outputs g1 g2 dcba 0123456789101112131415 lllllll hhhhhhhhhhhhhhh l l l l lhhlhhhhhhhhhhhhhh l l l lhlhhlhhhhhhhhhhhhh l l l lhhhhhlhhhhhhhhhhhh l l lhl lhhhhlhhhhhhhhhhh l l lhlhhhhhhlhhhhhhhhhh l l lhhlhhhhhhlhhhhhhhhh l l lhhhhhhhhhhlhhhhhhhh l lhl l lhhhhhhhhlhhhhhhh l lhl lhhhhhhhhhhlhhhhhh l lhlhlhhhhhhhhhhlhhhhh l lhlhhhhhhhhhhhhhlhhhh l lhhl lhhhhhhhhhhhhlhhh l lhhlhhhhhhhhhhhhhhlhh l lhhhlhhhhhhhhhhhhhhlh l lhhhhhhhhhhhhhhhhhhhl lhxxxx hhhhhhhhhhhhhhhh hlxxxx hhhhhhhhhhhhhhhh hhxxxx hhhhhhhhhhhhhhhh h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out 0 22 b 21 c 20 d 19 g2 g1
50/101 www.dynexsemi.com 54hsc/t series 54hsc/t154 : 4 to 16 line decoders/demultiplexers +25 c -55 c / +125 c sym parameter typ. max. typ. max. units t plh propagation delay low to high level 18 30 21 33 ns output for change in a b c or d input t phl propagation delay high to low level 21 30 24 33 ns output for change in a b c or d input t plh propagation delay low to high level 21 30 24 33 ns output for change in g1 or g2 t phl propagation delay high to low level 18 30 21 33 ns output for change in g1 or g2 figure 3: switching characteristics figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 100 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
51/101 www.dynexsemi.com 54hsc/t series 54hsc/t154 : 4 to 16 line decoders/demultiplexers figure 5: logic diagram
52/101 www.dynexsemi.com 54hsc/t series 54hsc/t157 : quad 2-line to 1-line data selectors/multiplexers the 54hsc/t157 is a quadruple 2-line to 1-line data selector with non-inverted output. the strobe must be low to enable the device. when select is low, a is selected. when select is high, b is selected. inputs outputs str select a b y hxx xl lll xl llhxh lhx ll lhx hh h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out sel 14 4a 13 4b 12 4y 11 3a 10 3b 9 3y 3 1b 4 1y 5 2a 6 2b 7 2y 8 vss top view 16 vdd 15 str +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay a or b to y 14 25 17 25 ns t phl propagation delay a or b to y 15 20 18 22 ns t pzh propagation delay strobe to y 14 22 17 24 ns t pzl propagation delay strobe to y 15 22 18 24 ns t phz propagation delay select to y 14 25 17 25 ns t plz propagation delay select to y 15 25 18 25 ns figure 3: switching characteristics figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
53/101 www.dynexsemi.com 54hsc/t series figure 5: logic diagram 54hsc/t157 : quad 2-line to 1-line data selectors/multiplexers
54/101 www.dynexsemi.com 54hsc/t series 54hsc/t238 : 3-line to 8-line decoder/demultiplexer the 54hsc/t238 is a 3-line to 8-line decoder/demultiplexer, with unlatched inputs and non-inverted outputs. enable inputs select inputs outputs e 3 e 2 / e 1 a 2 a 1 a 0 o 0 o 1 o 2 o 3 o 4 o 5 o 6 o 7 x h xxxllllllll l x xxxllllllll h l lllhlllllll h l llhlhllllll h l lhlllhlllll h l lhhlllhllll h l hllllllhlll h l hlhlllllhll h l hhlllllllhl h l hhhlllllllh h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay, address to output, low to high level output 16 24 19 27 ns t phl propagation delay, address to output, high to low level output 17 25 20 28 ns t plh propagation delay, enable to output, low to high level output 19 27 22 30 ns t phl propagation delay, enable to output, high to low level output 19 27 22 30 ns a 0 14 o 1 13 o 2 12 o 3 11 o 4 10 o 5 9 o 6 3 a 2 4 e e figure 3: switching characteristics
55/101 www.dynexsemi.com 54hsc/t series 54hsc/t238 : 3-line to 8-line decoder/demultiplexer figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: logic diagram
56/101 www.dynexsemi.com 54hsc/t series 54hsc/t253 : dual 4 to 1 data selectors/multiplexers the 54hsc/t253 is a dual 4-line to 1-line data selector/multiplexer with tri-state outputs. output select inputs data inputs control output b a c0 c1 c2 c3 g y xxx xxxhz lll xxxll llhxxxlh lhx lxxl l lhx hxxlh hlx xlxll hlx xhxlh hhx xx l l l hhx xxh lh h = high level, l = low level, x = irrelevant, z = high impedance figure 1: function table figure 2: pin out 1 g g +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay data to output 14 25 17 25 ns t phl propagation delay data to output 15 25 18 25 ns t plh propagation delay select to output 14 25 17 25 ns t phl propagation delay select to output 15 25 18 25 ns t pzl propagation delay tri-state to output low 12 25 15 25 ns t pzh propagation delay tri-state to output high 13 25 16 25 ns t plz propagation delay low to tri-state 12 25 15 25 ns t phz propagation delay high to tri-state 13 25 16 25 ns figure 3: switching characteristics
57/101 www.dynexsemi.com 54hsc/t series 54hsc/t253 : dual 4 to 1 data selectors/multiplexers limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 4: dc characteristics figure 5: logic diagram
58/101 www.dynexsemi.com 54hsc/t series 54hsc/t164 : 8-bit parallel output serial shift register the 54hsc/t164 is an 8-bit parallel output serial shift register with asynchronous clear. inputs outputs clear clock a b q a q b q h l xxxl l l hlxxq ao q bo q ho h hhhq an q gn h lxlq an q gn h xllq an q gn h = high level, l = low level, x = irrelevant, = transition from low to high level. q ao , q bo , q ho = the level of q a , q b or q h , respectively, before the indicated steady-state input conditions were set up. q an , q bn , q hn = the level of q a or q g before the latest transition of the clock. indicates a one bit shift. figure 2: pin out 14 v dd 13 q h 12 q g 11 q f 10 q e 9 clear +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. q output from clock input, low to high level output. 15 25 18 28 ns t phl propagation delay. q output from clock input, high to low level output. 15 25 18 28 ns t phl propagation delay. q output from clear input, high to low level output. 15 25 18 28 ns figure 1: function table figure 3: switching characteristics figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
59/101 www.dynexsemi.com 54hsc/t series 54hsc/t164 : 8-bit parallel output serial shift register figure 5: logic diagram
60/101 www.dynexsemi.com 54hsc/t series the 54hsc/t165 is an 8-bit serial shift register that shifts the data in the direction of q a to q h when clocked. 54hsc/t165 : parallel load 8-bit shift register inputs internal outputs output shift/ clock parallel load inhibit clock serial a...h q a q b q h l x x x a...h a b h hl l x xq ao q bo q ho hl hxhq an q gn hl lxlq an q gn hh x x xq ao q bo q ho h = high level, l = low level, x = irrelevant, = transition from low to high, a...h = the level of steady state inputs at inputs a through h. q o = level of q before the indicated steady state input conditions were set up. q n = level of q before the most recent active transition indicated by . figure 1: function table figure 2: pin out shift/ load q +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. load to any output. 18 25 21 28 ns t phl propagation delay. load to any output. 16 25 19 28 ns t plh propagation delay. clock to any output. 18 25 21 28 ns t phl propagation delay. clock to any output. 18 25 21 28 ns t plh propagation delay. h to q h . 18252128ns t phl propagation delay. h to q h . 18252128ns t plh propagation delay. h to qb h . 18252128ns t phl propagation delay. h to qb h . 18252128ns figure 3: switching characteristics
61/101 www.dynexsemi.com 54hsc/t series 54hsc/t165 : parallel load 8-bit shift register figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: logic diagram
62/101 www.dynexsemi.com 54hsc/t series the 54hsc/t166 is an 8-bit parallel in or serial in, serial out shift register with a gated clock input and an overriding clear input. 54hsc/t166 : 8-bit shift register inputs internal outputs output shift/ clock parallel clear load inhibit clock serial a...h q a q b q h lxxxxxlll hx l l x xq ao q bo q ho hl l x a...h a b h hh l hxhq an q gn hh l lxlq an q gn hx h xxq ao q bo q ho h = high level, l = low level, x = irrelevant, = transition from low to high, a...h = the level of steady state inputs at inputs a through h. q o = level of q before the indicated steady state input conditions were set up. q n = level of q before the most recent active transition indicated by . figure 1: function table figure 2: pin out serial input 14 h 13 q h 12 g 11 f 10 e 9 clear load +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t phl propagation delay. clear to q h . 15251828ns t phl propagation delay. clock to q h . 15251828ns t plh propagation delay. clock to q h . 15251828ns figure 3: switching characteristics
63/101 www.dynexsemi.com 54hsc/t series figure 4: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 400 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a 54hsc/t166 : 8-bit shift register
64/101 www.dynexsemi.com 54hsc/t series 54hsc/t166 : 8-bit shift register figure 5: logic diagram
65/101 www.dynexsemi.com 54hsc/t series 54hsc/t521 : 8-bit magnitude comparator the 54hsc/t521 is an 8-bit magnitude comparator. h = high level, l = low level, x = irrelevant inputs outputs data p,q enable g p = q p = q l l p > q l h p < q l h xhh figure 1: function table +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. p or q to pn = qn. 15 25 18 28 ns t phl propagation delay. p or q to pn = qn. 16 25 19 28 ns t plh propagation delay. gn to pn = qn. 14 25 17 28 ns t phl propagation delay. gn to pn = qn. 15 25 18 28 ns figure 3: logic diagram figure 2: pin out g p = q figure 4: switching characteristics
66/101 www.dynexsemi.com 54hsc/t series 54hsc/t521 : 8-bit magnitude comparator figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a
67/101 www.dynexsemi.com 54hsc/t series 54hsc/t240 : octal 3-state driver, inverting the 54hsc/t240 is an octal 3-state driver, inverting. inputs outputs e e e e e i 0-3 o 0-3 llh lhl hxz h = high level l = low level x = irrelevant z = high impedance figure 1: function table figure 2: pin out figure 3: logic diagram +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay, low to high level output. 12 20 15 23 ns t phl propagation delay, high to low level output. 14 22 17 25 ns t pzl propagation delay, enable to low level. 19 27 21 30 ns t pzh propagation delay, enable to high level. 14 22 17 25 ns t plz propagation delay, disable from low. 22 30 25 33 ns t phz propagation delay, disable from high. 21 30 24 33 ns e o o o o o o e o o figure 4: switching characteristics
68/101 www.dynexsemi.com 54hsc/t series 54hsc/t240 : octal 3-state driver, inverting limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: dc characteristics
69/101 www.dynexsemi.com 54hsc/t series 54hsc/t241 : octal 3-state driver, complementary enable the 54hsc/t241 is an octal 3-state driver, complementary enable. figure 3: logic diagram +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay, low to high level output. 11 19 14 22 ns t phl propagation delay, high to low level output. 13 21 16 24 ns t pzl propagation delay, enable to low level. 19 27 21 30 ns t pzh propagation delay, enable to high level. 19 27 21 30 ns t plz propagation delay, low to disable. 22 30 25 33 ns t phz propagation delay, high to disable. 21 30 24 33 ns inputs outputs e e e e e a e b i 0-3 o 0-3 lhlh lhhl hlxz figure 1: function table figure 2: pin out h = high level l = low level x = irrelevant z = high impedance e figure 4: switching characteristics
70/101 www.dynexsemi.com 54hsc/t series figure 5: dc characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a 54hsc/t241 : octal 3-state driver, complementary enable
71/101 www.dynexsemi.com 54hsc/t series 54hsc/t244 : octal 3-state driver the 54hsc/t244 is an octal 3-state driver. inputs outputs e e e e e i 0-3 o 0-3 llh lhl hxz h = high level l = low level x = irrelevant z = high impedance figure 1: function table figure 2: pin out figure 3: logic diagram e e +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay, low to high level output. 11 21 14 21 ns t phl propagation delay, high to low level output. 13 21 16 21 ns t pzl propagation delay, enable to low level. 19 25 21 25 ns t pzh propagation delay, enable to high level. 15 20 21 24 ns t plz propagation delay, low to disable. 19 25 22 25 ns t phz propagation delay, high to disable. 18 25 21 25 ns figure 4: switching characteristics
72/101 www.dynexsemi.com 54hsc/t series 54hsc/t244 : octal 3-state driver limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: dc characteristics
73/101 www.dynexsemi.com 54hsc/t series 54hsc/t540 : octal 3-state driver/buffer inverting the 54hsc/t540 is an octal 3-state driver/buffer inverting. inputs outputs e e e e e a e b i 0-7 o 0-7 lllh llhl hxx z xhx z figure 1: function table h = high level l = low level x = irrelevant z = high impedance figure 2: pin out e o o o o o o e o o figure 3: logic diagram +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay, low to high level output. 13 21 16 24 ns t phl propagation delay, high to low level output. 13 21 16 24 ns t pzl propagation delay, enable to low level. 21 29 24 32 ns t pzh propagation delay, enable to high level. 16 24 19 27 ns t plz propagation delay, low to disable. 24 32 27 35 ns t phz propagation delay, high to disable. 23 31 26 34 ns figure 4: switching characteristics
74/101 www.dynexsemi.com 54hsc/t series 54hsc/t540 : octal 3-state driver/buffer inverting limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: dc characteristics
75/101 www.dynexsemi.com 54hsc/t series 54hsc/t541 : octal 3-state driver/buffer the 54hsc/t541 is an octal 3-state driver/buffer. inputs outputs e e e e e a e b i 0-7 o 0-7 llll llhh hxx z xhx z figure 1: function table h = high level l = low level x = irrelevant z = high impedance figure 2: pin out figure 3: logic diagram +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay, low to high level output. 11 19 14 22 ns t phl propagation delay, high to low level output. 13 21 16 22 ns t pzl propagation delay, enable to low level. 17 21 20 35 ns t pzh propagation delay, enable to high level. 16 24 19 30 ns t plz propagation delay, low to disable. 24 21 27 25 ns t phz propagation delay, high to disable. 23 21 26 25 ns e e figure 4: switching characteristics
76/101 www.dynexsemi.com 54hsc/t series 54hsc/t541 : octal 3-state driver/buffer limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: dc characteristics
77/101 www.dynexsemi.com 54hsc/t series 54hsc/t245 : octal bus transceiver the 54hsc/t245 is an octal bus transceiver. inputs outputs e e e e e dir l l b data to bus a l h a data to bus b h x isolation h = high level, l = low level, x = irrelevant figure 1: function table figure 2: pin out dir 18 b 0 17 b 1 16 b 2 15 b 3 14 b 4 13 b 5 3 a 1 4 a 2 5 a 3 6 a 4 7 a 5 8 a 6 top view 20 v dd 19 e figure 3: logic diagram +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay, low to high level output. 10 19 13 23 ns t phl propagation delay, high to low level output. 11 19 14 23 ns t pzl propagation delay, enable to low level. 21 26 24 30 ns t pzh propagation delay, enable to high level. 16 25 19 28 ns t plz propagation delay, low to disable. 24 28 27 33 ns t phz propagation delay, high to disable. 24 28 27 33 ns figure 4: switching characteristics
78/101 www.dynexsemi.com 54hsc/t series 54hsc/t245 : octal bus transceiver limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: dc characteristics
79/101 www.dynexsemi.com 54hsc/t series 54hsc/t373 : octal transparent latch, 3-state outputs the 54hsc/t373 is an octal transparent latch with 3-state outputs. inputs outputs oc oc oc oc oc c dq lhhh lhl l llxq 0 hxx z figure 1: function table h = high level l = low level x = irrelevant z = high impedance figure 2: pin out oc +25 c -55 c / +125 c symbol parameter min. typ. max. min. typ. max. units t plh propagation delay. low to high output. - 15 20 - 20 24 ns t phl propagation delay. high to low output. - 14 20 - 21 24 ns t pzl propagation delay. enable to low. - 13 25 - 14 25 ns t pzh propagation delay. enable to high. - 16 20 - 18 24 ns t plz propagation delay. low to disable. - 14 25 - 18 25 ns t phz propagation delay. high to disable. - 13 25 - 19 25 ns figure 3: switching characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 4: dc characteristics
80/101 www.dynexsemi.com 54hsc/t series 54hsc/t373 : octal transparent latch, 3-state outputs figure 5: logic diagram
81/101 www.dynexsemi.com 54hsc/t series 54hsc/t573 : octal transparent latch, 3-state outputs the 54hsc/t573 is an octal transparent latch with 3-state outputs. inputs outputs oc oc oc oc oc c dq lhhh lhl l llxq 0 hxx z figure 1: function table h = high level l = low level x = irrelevant z = high impedance figure 2: pin out +25 c -55 c / +125 c symbol parameter min. typ. max. min. typ. max. units t plh propagation delay. low to high output. - 19 24 - 22 29 ns t phl propagation delay. high to low output. - 19 24 - 22 29 ns t pzl propagation delay. enable to low. - 13 21 - 16 24 ns t pzh propagation delay. enable to high. - 16 24 - 19 27 ns t plz propagation delay. low to disable. - 14 22 - 17 25 ns t phz propagation delay. high to disable. - 13 21 - 16 24 ns oc figure 3: switching characteristics limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 4: dc characteristics
82/101 www.dynexsemi.com 54hsc/t series figure 5: logic diagram 54hsc/t573 : octal transparent latch, 3-state outputs
83/101 www.dynexsemi.com 54hsc/t series 54hsc/t670 : 4 x 4 register files with tri-state outputs the 54hsc/t670 is a register storing 4 words of 4 bits each. separate on-chip decoding is provided for addressing the four word locations to either write or retrieve data. this allows simultaneous writing into one location and reading from another location. figure 1: pin out write inputs word wb wa g w1234 l l l q = d q0 q0 q0 l h l q0 q = d q0 q0 h l l q0 q0 q = d q0 h h l q0 q0 q0 q = d x x h q0q0q0q0 read inputs outputs wb wa g w1234 l l l w1d1 w1d2 w1d3 w1d4 l h l w2d1 w2d2 w2d3 w2d4 h l l w3d1 w3d2 w3d3 w3d4 h h l w4d1 w4d2 w4d3 w4d4 xxhzzzz h = high level, l = low level, x = irrelevant, z = high impedance figure 3: read function table q0 = level of q before inputs were established h = high level, l = low level, x = irrelevant figure 2: write function table d2 14 wa 13 wb 12 g w 11 g r 10 q1 9 q2 3 d4 4 rb 5 ra 6 q4 7 q3 8 vss top view 16 vdd 15 d1 1 2 d3 +25 c -55 c / +125 c symbol parameter typ. max. typ. max. units t plh propagation delay. read select to q. 25 30 28 33 ns t phl propagation delay. read select to q. 18 25 21 28 ns t plh propagation delay. write enable to q. 18 25 21 28 ns t phl propagation delay. write enable to q. 18 25 21 28 ns t plh propagation delay. data to q. 27 35 30 38 ns t phl propagation delay. data to q. 23 25 26 28 ns t pzh propagation delay. read enable to q. 18 25 21 28 ns t pzl propagation delay. read enable to q. 18 25 21 28 ns t phz propagation delay. read enable to q. 18 25 21 28 ns t plz propagation delay. read enable to q. 18 25 21 28 ns v cc = 5v, t max = +125 c, c l = 50pf figure 4: switching characteristics
84/101 www.dynexsemi.com 54hsc/t series 54hsc/t670 : 4 x 4 register files with tri-state outputs limits +25 c -55 c / +125 c symbol parameter test conditions min. max. min. max. units i dd quiescent current v in = 0v or v dd - 20 - 600 a v ol output voltage low level i ol = 9ma - 0.4 - 0.4 v v oh output voltage high level i oh = -11ma 2.5 - 2.5 - v v il1 voltage input low (cmos) - - 1.5 - 1.5 v v ih1 voltage input high (cmos) - 3.5 - 3.5 - v v il2 voltage input low (ttl) - - 0.8 - 0.8 v v ih2 voltage input high (ttl) - 2.0 - 2.0 - v i oz tri-state leakage v o = 0v or v dd - 1- 50 a i in input leakage current v in = v dd or v ss - 0.5 - 5.0 a figure 5: dc characteristics
85/101 www.dynexsemi.com 54hsc/t series 54hsc/t670 : 4 x 4 register files with tri-state outputs figure 6: logic diagram
86/101 www.dynexsemi.com 54hsc/t series pin count 14 14 14 14 14 14 14 14 14 14 14 14 16 14 14 16 16 16 14 16 characterisation data device base listing as below: ma9003 base 00 02 03 04 08 10 14 21 27 32 74 86 109 125 126 148 151 157 164 253 ma9007 base 154 161 163 165 166 191 273 283 670 bms011 base 138 139 238 240 241 244 245 373 374 521 540 541 573 574 pin count 16 16 16 20 20 20 20 20 20 20 20 20 20 20 pin count 24 16 16 16 16 16 20 16 16
87/101 www.dynexsemi.com 54hsc/t series package: li/as/4/in/02001 - 14 lead bottombraze flatpack (mil-std-38510h)
88/101 www.dynexsemi.com 54hsc/t series finished product outline: li/as/4/in/02001 - 14 lead bottombraze flatpack (mil-std-38510h)
89/101 www.dynexsemi.com 54hsc/t series finished product outline: li/as/4/in/02001 - 14 lead bottombraze flatpack (mil-std-38510h)
90/101 www.dynexsemi.com 54hsc/t series finished product outline: li/as/4/in/02001 - 14 lead bottombraze flatpack (mil-std-38510h)
91/101 www.dynexsemi.com 54hsc/t series package outline: xg 257 - 20 lead bottombraze flatpack (mil-std-38510h)
92/101 www.dynexsemi.com 54hsc/t series package outline: 16 lead bottombraze flatpack (mil-std-38510h)
93/101 www.dynexsemi.com 54hsc/t series finished product outline: 24 lead ceramic flatpack (mil-m-38510)
94/101 www.dynexsemi.com 54hsc/t series finished product outline: 16 lead flatpack (mil-m-38510h)
95/101 www.dynexsemi.com 54hsc/t series 0 100 200 300 rad levels (krads) 450 400 350 300 250 200 150 100 50 0 static idd (?) static idd vs radiation bms011 base 9007 base 9003 base bms011 base 9007 base 9003 base static idd vs temp. 250 200 150 100 50 0 idd (?) temperature (deg c) -100 -50 0 50 100 150 bms011 base 9007 base 9003 base iozh vs temp. 300 250 200 150 100 50 0 iozh (na) temperature (deg c) 40 80 120 0 20 60 100 140 bms011 base 9007 base 9003 base iil vs temp. iil (-na) temperature (deg c) 350 300 250 200 150 100 50 0 40 80 120 0 20 60 100 140 1 10 100 frequency (mhz) 15 10 5 0 dynamic idd (ma) dynamic idd for octal device bases bms011 base 9007 base 9003 base bms011 base 9007 base 9003 base iozl vs temp. 40 80 120 temperature (deg c) 20 60 100 140 30 25 20 15 10 5 0 iozl (- a) 0
96/101 www.dynexsemi.com 54hsc/t series bms011 base 9007 base 9003 base iih vs temp. 500 400 300 200 100 0 iih (na) temperature (deg c) 40 80 120 0 20 60 100 140 vol vs temp. bms011 base 9007 base 9003 base -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) 0.22 0.2 0.18 0.16 0.14 0.12 0.1 0.08 vol (v) voh vs temp. bms011 base 9007 base 9003 base -60 -40 -20 0 20 40 60 80 100 120 140 temperature (deg c) 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 voh (v) 0 2 4 6 8 10 12 14 16 iol (ma) 0.4 0.3 0.2 0.1 0 vol (v) vol vs iol ma9003 base room temp. hot (125) cold (-55) vdd = 5.5v 0 2 4 6 8 10 12 14 16 iol (ma) 0.4 0.3 0.2 0.1 0 vol (v) vol vs iol ma9007 base room temp. hot (125) cold (-55) vdd = 5.5v 0 2 4 6 8 10 12 14 16 iol (ma) 0.4 0.3 0.2 0.1 0 vol (v) vol vs iol bms011 base room temp. hot (125) cold (-55) vdd = 5.5v
97/101 www.dynexsemi.com 54hsc/t series 0 2 4 6 8 10 12 14 16 iol (-ma) 4.5 4.3 4.1 3.9 3.7 3.5 3.3 voh (v) voh vs ioh ma9003 base room temp. hot (125) cold (-55) vdd = 4.5v 0 2 4 6 8 10 12 14 16 iol (-ma) 4.5 4.3 4.1 3.9 3.7 3.5 3.3 voh (v) voh vs ioh bms011 base room temp. hot (125) cold (-55) vdd = 4.5v 0 2 4 6 8 10 12 14 16 iol (-ma) 4.5 4.3 4.1 3.9 3.7 3.5 3.3 voh (v) voh vs ioh ma9007 base room temp. hot (125) cold (-55) vdd = 4.5v
98/101 www.dynexsemi.com 54hsc/t series 54 hsc 14 schmitt i/p hysteresis 1 i/p voltage 6 5 4 3 2 1 0 o/p voltage 2 3 45 cold at -55? i/p decreasing i/p increasing test at +25? i/p decreasing i/p increasing hot at +125? i/p decreasing i/p increasing 0 i/p pin 3 54 hsc 14 schmitt i/p hysteresis 1 i/p voltage 6 5 4 3 2 1 0 o/p voltage 2 3 45 0 i/p pin 9 pre rad i/p decreasing i/p increasing post rad (100krad) i/p decreasing i/p increasing
99/101 www.dynexsemi.com 54hsc/t series
100/101 www.dynexsemi.com 54hsc/t series total dose (function to specification)* 3x10 5 rad(si) transient upset (stored data loss) 1x10 11 rad(si)/sec transient upset (survivability) >1x10 12 rad(si)/sec neutron hardness (function to specification) >1x10 15 n/cm 2 single event upset** <1x10 -10 errors/bit day latch up not possible * other total dose radiation levels available on request ** worst case galactic cosmic ray upset - interplanetary/high altitude orbit radiation tolerance figure 5: radiation hardness parameters ordering information unique circuit designator ?lank s r q h no tolerance implied radiation hard processing 100 krads (si) guaranteed 300 krads (si) guaranteed 1000 krads (si) guaranteed* radiation tolerance c f l n ceramic dil (solder seal) flatpack (solder seal) leadless chip carrier naked die package type qa/qci process (see section 9 part 4) test process (see section 9 part 3) assembly process (see section 9 part 2) l c d e b s rel 0 rel 1 rel 2 rel 3/4/5/stack class b class s reliability level 54xhsc139xxxxx 54xhst139xxxxx * hsc only for details of reliability, qa/qc, test and assembly options, see ?anufacturing capability and quality assurance standards?section 9.
www.dynexsemi.com customer service tel: +44 (0)1522 502753 / 502901. fax: +44 (0)1522 500020 sales office tel: +44 (0)1522 500500. fax: +44 (0)1522 502777 these offices are supported by representatives and distributors in many countries world-wide. ?dynex semiconductor 2002 technical documentation ?not for resale. produced in united kingdom headquarters operations dynex semiconductor ltd doddington road, lincoln. lincolnshire. ln6 3lf. united kingdom. tel: +44-(0)1522-500500 fax: +44-(0)1522-500550 this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design or price of any product or service. information con cerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully deter mine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any me dical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. all brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respec tive owners. http://www.dynexsemi.com e-mail: space_comms@dynexsemi.com datasheet annotations: dynex semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. the annota tions are as follows:- target information: this is the most tentative form of information and represents a very preliminary specification. no actual design work on the product has been started. preliminary information: the product is in design and development. the datasheet represents the product as it is understood but details may change. advance information: the product design is complete and final characterisation for volume production is well in hand. no annotation: the product parameters are fixed and the product is available to datasheet specification.

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