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eol product document no. e0206h30 (ver. 3.0) date published september 2002 (k) japan url: http://www.elpida.com ? elpida memory, inc. 2001-2002 elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. data sheet 256mb, 512mb registered ddr sdram dimm hb54a2569f1u (32m words 72 bits, 1 bank) hb54a5129f2u (64m words 72 bits, 2 banks) description the hb54a2569f1u, hb54a5129f2u are double data rate (ddr) sdram module, mounted 256m bits ddr sdram (hm5425801btt) sealed in tsop package, and 1 piece of serial eeprom (2k bits eeprom) for presence detect (pd). the hb54a2569f1u is organized as 32m 72 1 bank mounted 9 pieces of 256m bits ddr sdram. the hb54a5129f2u is organized as 32m 72 2 banks mounted 18 pieces of 256m bits ddr sdram. read and write operations are performed at the cross points of the ck and the /ck. this high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. data strobe (dqs) both for read and write are available for high speed and reliable data bus design. by setting extended mode register, the on-chip delay locked loop (dll) can be set enable or disable. an outline of the products is 184-pin socket type package (dual lead out). therefore, it makes high density mounting possible without surface mount technology. it provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the module board. features ? 184-pin socket type package (dual lead out) ? outline: 133.35mm (length) 30.48mm (height) 4.00mm (thickness) ? lead pitch: 1.27mm ? 2.5v power supply (vcc/vccq) ? sstl-2 interface for all inputs and outputs ? clock frequency: 143mhz/133mhz/125mhz (max.) ? data inputs, outputs and dm are synchronized with dqs ? 4 banks can operate simultaneously and independently (component) ? burst read/write operation ? programmable burst length: 2, 4, 8 ? burst read stop capability ? programmable burst sequence ? sequential ? interleave ? start addressing capability ? even and odd ? programmable /cas latency (cl): 3, 3.5 ? 8192 refresh cycles: 7.8 s (8192/64ms) ? 2 variations of refresh ? auto refresh ? self refresh
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 2 ordering information part number clock frequency mhz (max.) /cas latency package contact pad hb54a2569f1u-a75b* 1 hb54a2569f1u-b75b* 2 hb54a2569f1u-10b* 3 133 133 100 3.0 3.5 3.0 184-pin dual lead out socket type gold hb54a5129f2u-a75b* 1 hb54a5129f2u-b75b* 2 HB54A5129F2U-10B* 3 133 133 100 3.0 3.5 3.0 notes: 1. 143mhz operation at /cas latency = 3.5. 2. 100mhz operation at /cas latency = 3.0. 3. 125mhz operation at /cas latency = 3.5. pin configurations 1 pin front side back side 52 pin 53 pin 92 pin 93 pin 144 pin 145 pin 184 pin pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vref 47 dqs8 93 vss 139 vss 2 dq0 48 a0 94 dq4 140 dm8/dqs17 3 vss 49 cb2 95 dq5 141 a10 4 dq1 50 vss 96 vccq 142 cb6 5 dqs0 51 cb3 97 dm0/dqs9 143 vccq 6 dq2 52 ba1 98 dq6 144 cb7 7 vcc 53 dq32 99 dq7 145 vss 8 dq3 54 vccq 100 vss 146 dq36 9 nc 55 dq33 101 nc 147 dq37 10 /reset 56 dqs4 102 nc 148 vcc 11 vss 57 dq34 103 nc 149 dm4/dqs13 12 dq8 58 vss 104 vccq 150 dq38 13 dq9 59 ba0 105 dq12 151 dq39 14 dqs1 60 dq35 106 dq13 152 vss 15 vccq 61 dq40 107 dm1/dqs10 153 dq44 16 nc 62 vccq 108 vcc 154 /ras 17 nc 63 /we 109 dq14 155 dq45 18 vss 64 dq41 110 dq15 156 vccq 19 dq10 65 /cas 111 cke1 (nc)* 1 157 /s0 20 dq11 66 vss 112 vccq 158 /s1 (nc)* 1 21 cke0 67 dqs5 113 nc 159 dm5/dqs14 22 vccq 68 dq42 114 dq20 160 vss 23 dq16 69 dq43 115 a12 161 dq46 24 dq17 70 vcc 116 vss 162 dq47 25 dqs2 71 nc 117 dq21 163 nc 26 vss 72 dq48 118 a11 164 vccq
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 3 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 27 a9 73 dq49 119 dm2/dqs11 165 dq52 28 dq18 74 vss 120 vcc 166 dq53 29 a7 75 nc 121 dq22 167 nc 30 vccq 76 nc 122 a8 168 vcc 31 dq19 77 vccq 123 dq23 169 dm6/dqs15 32 a5 78 dqs6 124 vss 170 dq54 33 dq24 79 dq50 125 a6 171 dq55 34 vss 80 dq51 126 dq28 172 vccq 35 dq25 81 vss 127 dq29 173 nc 36 dqs3 82 vccid 128 vccq 174 dq60 37 a4 83 dq56 129 dm3/dqs12 175 dq61 38 vcc 84 dq57 130 a3 176 vss 39 dq26 85 vcc 131 dq30 177 dm7/dqs16 40 dq27 86 dqs7 132 vss 178 dq62 41 a2 87 dq58 133 dq31 179 dq63 42 vss 88 dq59 134 cb4 180 vccq 43 a1 89 vss 135 cb5 181 sa0 44 cb0 90 nc 136 vccq 182 sa1 45 cb1 91 sda 137 ck0 183 sa2 46 vcc 92 scl 138 /ck0 184 vccspd note: 1. the hb54a2569f1u assign ?nc?.
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 4 pin description pin name function a0 to a12 address input row address a0 to a12 column address a0 to a9 ba0, ba1 bank select address dq0 to dq63 data input/output cb0 to cb7 check bit (data input/output) /ras row address strobe command /cas column address strobe command /we write enable /s0, /s1 chip select cke0, cke1 clock enable ck0 clock input /ck0 differential clock input dqs0 to dqs8 input and output data strobe dm0 to dm8/dqs9 to dqs17 input mask scl clock input for serial pd sda data input/output for serial pd sa0 to sa2 serial address input vcc power for internal circuit vccq power for dq circuit vccspd power for serial eeprom vref input reference voltage vss ground vccid vcc identification flag /reset reset pin (forces register inputs low) nc no connection
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 5 serial pd matrix* 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes utilized by module manufacturer 1 0 0 0 0 0 0 0 80h 128 1 total number of bytes in serial pd device 0 0 0 0 1 0 0 0 08h 256 bytes 2 memory type 0 0 0 0 0 1 1 1 07h sdram ddr 3 number of row address 0 0 0 0 1 1 0 1 0dh 13 4 number of column address 0 0 0 0 1 0 1 0 0ah 10 5 number of dimm banks hb54a2569f1u 0 0 0 0 0 0 0 1 01h 1 hb54a5129f2u 0 0 0 0 0 0 1 0 02h 2 6 module data width 0 1 0 0 1 0 0 0 48h 72 bits 7 module data width continuation 0 0 0 0 0 0 0 0 00h 0 (+) 8 voltage interface level of this assembly 0 0 0 0 0 1 0 0 04h sstl 2.5v 9 ddr sdram cycle time, cl = x -a75b 0 1 1 1 0 0 0 0 70h cl = 2.5* 5 -b75b 0 1 1 1 0 1 0 1 75h -10b 1 0 0 0 0 0 0 0 80h 10 sdram access from clock (tac) -a75b, -b75b 0 1 1 1 0 1 0 1 75h 0.75ns* 5 -10b 1 0 0 0 0 0 0 0 80h 0.8ns* 5 11 dimm configuration type 0 0 0 0 0 0 1 0 02h ecc 12 refresh rate/type 1 0 0 0 0 0 1 0 82h 7.8 s self refresh 13 primary sdram width 0 0 0 0 1 0 0 0 08h 8 14 error checking sdram width 0 0 0 0 1 0 0 0 08h 8 15 sdram device attributes: minimum clock delay back-to-back column access 0 0 0 0 0 0 0 1 01h 1 clk 16 sdram device attributes: burst length supported 0 0 0 0 1 1 1 0 0eh 2, 4, 8 17 sdram device attributes: number of banks on sdram device 0 0 0 0 0 1 0 0 04h 4 18 sdram device attributes: /cas latency 0 0 0 0 1 1 0 0 0ch 2, 2.5 19 sdram device attributes: /cs latency 0 0 0 0 0 0 0 1 01h 0 20 sdram device attributes: /we latency 0 0 0 0 0 0 1 0 02h 1 21 sdram module attributes 0 0 1 0 0 1 1 0 26h registered 22 sdram device attributes: general 1 1 0 0 0 0 0 0 c0h 0.2v 23 minimum clock cycle time at clx - 0.5 -a75b 0 1 1 1 0 1 0 1 75h cl = 2* 5 -b75b/10b 1 0 1 0 0 0 0 0 a0h 24 maximum data access time (tac) from clock at clx - 0.5 -a75b, -b75b 0 1 1 1 0 1 0 1 75h 0.75ns* 5 -10b 1 0 0 0 0 0 0 0 80h 0.8ns* 5 25 minimum clock cycle time at clx - 1 0 0 0 0 0 0 0 0 00h 26 maximum data access time (tac) from clock at clx - 1 0 0 0 0 0 0 0 0 00h
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 27 minimum row precharge time (trp) 0 1 0 1 0 0 0 0 50h 20ns 28 minimum row active to row active delay (trrd) 0 0 1 1 1 1 0 0 3ch 15ns 29 minimum /ras to /cas delay (trcd) 0 1 0 1 0 0 0 0 50h 20ns 30 minimum active to precharge time (tras) -a75b, -b75b 0 0 1 0 1 1 0 1 2dh 45ns -10b 0 0 1 1 0 0 1 0 32h 50ns 31 module bank density 0 1 0 0 0 0 0 0 40h 256mb 32 address and command setup time before clock (tis) -a75b, -b75b 1 0 0 1 0 0 0 0 90h 0.9ns* 5 -10b 1 0 1 1 0 0 0 0 b0h 1.1ns* 5 33 address and command hold time after clock (tih) -a75b, -b75b 1 0 0 1 0 0 0 0 90h 0.9ns* 5 -10b 1 0 1 1 0 0 0 0 b0h 1.1ns* 5 34 data input setup time before clock (tds) -a75b, -b75b 0 1 0 1 0 0 0 0 50h 0.5ns* 5 -10b 0 1 1 0 0 0 0 0 60h 0.6ns* 5 35 data input hold time after clock (tdh) -a75b, -b75b 0 1 0 1 0 0 0 0 50h 0.5ns* 5 -10b 0 1 1 0 0 0 0 0 60h 0.6ns* 5 36 to 40 superset information 0 0 0 0 0 0 0 0 00h future use 41 active command period (trc) -a75b, -b75b 0 1 0 0 0 0 0 1 41h 65ns* 5 -10b 0 1 0 0 0 1 1 0 46h 70ns* 5 42 auto refresh to active/auto refresh command cycle (trfc) -a75b, -b75b 0 1 0 0 1 0 1 1 4bh 75ns* 5 -10b 0 1 0 1 0 0 0 0 50h 80ns* 5 43 sdram tck cycle max. (tck max.) 0 0 1 1 0 0 0 0 30h 12ns* 5 44 dout to dqs skew -a75b, -b75b 0 0 1 1 0 0 1 0 32h 500ps* 5 -10b 0 0 1 1 1 1 0 0 3ch 600ps* 5 45 data hold skew (tqhs) -a75b, -b75b 0 1 1 1 0 1 0 1 75h 750ps* 5 -10b 1 0 1 0 0 0 0 0 a0h 1000ps* 5 46 to 61 superset information 0 0 0 0 0 0 0 0 00h future use 62 spd revision 0 0 0 0 0 0 0 0 00h initial 63 checksum for bytes 0 to 62 hb54a2569f1u-a75b 1 1 0 0 1 0 1 0 cah 202 hb54a2569f1u-b75b 1 1 1 1 1 0 1 0 fah 250 hb54a2569f1u-10b 1 0 1 1 1 1 1 1 bfh 191 hb54a5129f2u-a75b 1 1 0 0 1 0 1 1 cbh 203 hb54a5129f2u-b75b 1 1 1 1 1 0 1 1 fbh 251 HB54A5129F2U-10B 1 1 0 0 0 0 0 0 c0h 192 64 manufacturer?s jedec id code 0 0 0 0 0 1 1 1 07h hitachi 65 to 71 manufacturer?s jedec id code 0 0 0 0 0 0 0 0 00h 72 manufacturing location * 2 (ascii-8bit code)
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 73 module part number 0 1 0 0 1 0 0 0 48h h 74 module part number 0 1 0 0 0 0 1 0 42h b 75 module part number 0 0 1 1 0 1 0 1 35h 5 76 module part number 0 0 1 1 0 1 0 0 34h 4 77 module part number 0 1 0 0 0 0 0 1 41h a 78 module part number hb54a2569f1u 0 0 1 1 0 0 1 0 32h 2 hb54a5129f2u 0 0 1 1 0 1 0 1 35h 5 79 module part number hb54a2569f1u 0 0 1 1 0 1 0 1 35h 5 hb54a5129f2u 0 0 1 1 0 0 0 1 31h 1 80 module part number hb54a2459f1u 0 0 1 1 0 1 1 0 36h 6 hb54a5129f2u 0 0 1 1 0 0 1 0 32h 2 81 module part number 0 0 1 1 1 0 0 1 39h 9 82 module part number 0 1 0 0 0 1 1 0 46h f 83 module part number hb54a2569f1u 0 0 1 1 0 0 0 1 31h 1 hb54a5129f2u 0 0 1 1 0 0 1 0 32h 2 84 module part number 0 1 0 1 0 1 0 1 55h u 85 module part number 0 0 1 0 1 1 0 1 2dh ? 86 module part number -a75b 0 1 0 0 0 0 0 1 41h a -b75b 0 1 0 0 0 0 1 0 42h b -10b 0 0 1 1 0 0 0 1 31h 1 87 module part number -a75b, -b75b 0 0 1 1 0 1 1 1 37h 7 -10b 0 0 1 1 0 0 0 0 30h 0 88 module part number -a75b, -b75b 0 0 1 1 0 1 0 1 35h 5 -10b 0 1 0 0 0 0 1 0 42h b 89 module part number -a75bb, -b75b 0 1 0 0 0 0 1 0 42h b -10b 0 0 1 0 0 0 0 0 20h (space) 90 module part number 0 0 1 0 0 0 0 0 20h (space) 91 revision code 0 0 1 1 0 0 0 0 30h initial 92 revision code 0 0 1 0 0 0 0 0 20h (space) 93 manufacturing date year code (bcd) 94 manufacturing date week code (bcd) 95 to 98 module serial number * 3 99 to 127 manufacturer specific data * 4 notes: 1. all serial pd data are not protected. 0: serial data, ?driven low?, 1: serial data, ?driven high? these spd are based on jedec committee ballot jc-42.5-99-129. 2. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows ?j? on ascii code.) 3. bytes 95 through 98 are assembly serial number. 4. all bits of 99 through 127 are not defined (?1? or ?0?). 5. these specifications are defined based on component specification, not module.
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 8 block diagram (hb54a2569f1u) dq dqs dm dq0 to dq7 8 dqs0 r s r s r s r s r s r s r s r s r s r s r s /cs d0 rs0 dq dq8 to dq15 8 dqs1 r s r s d1 dq dq16 to dq23 8 dqs2 r s r s d2 dq dq24 to dq31 8 dqs3 r s r s d3 dq dq32 to dq39 8 dqs4 r s r s d4 dq dq40 to dq47 8 dqs5 r s r s d5 dq dq48 to dq55 8 dqs6 r s r s d6 dq dq56 to dq63 8 dqs7 r s r s d7 dq cb0 to cb7 8 dqs8 r s r s d8 dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dm0/dqs9 dm1/dqs10 dm2/dqs11 dm3/dqs12 dm4/dqs13 dm5/dqs14 dm6/dqs15 dm7/dqs16 dm8/dqs17 * d0 to d8: hm5425801 u0: 2k-bits eeprom r s : 22 ?
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 9 block diagram (hb54a5129f2u) dq dqs dm dq0 to dq7 8 dqs0 dm0/dqs9 r s r s r s /cs d0 /rs0 /rs1 dq dq8 to dq15 8 dqs1 dm1/dqs10 r s r s r s d1 dq dq16 to dq23 8 dqs2 dm2/dqs11 r s r s r s d2 dq dq24 to dq31 8 dqs3 dm3/dqs12 r s r s r s d3 dq dq32 to dq39 8 dqs4 dm4/dqs13 r s r s r s d4 dq dq40 to dq47 8 dqs5 dm5/dqs14 r s r s r s d5 dq dq48 to dq55 8 dqs6 dm6/dqs15 r s r s r s d6 dq dq56 to dq63 8 dqs7 dm7/dqs16 r s r s r s d7 dq cb0 to cb7 8 dqs8 dm8/dqs17 r s r s r s d8 dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dq dqs dm /cs d9 dq d10 dq d11 dq d12 dq d13 dq d14 dq d15 dq d16 dq d17 dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs dqs dm /cs * d0 to d17: hm5425801 u0: 2k bits eeprom r s : 22 ?
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 10 differential clock net wiring (ck0, /ck0) 120 ? ? ? ? ?
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 11 pin functions (1) ck (clk), /ck (/clk) (input pin): the ck and the /ck are the master clock inputs. all inputs except dms, dqss and dqs are referred to the cross point of the ck rising edge and the vref level. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dms and dqs are referred to the cross point of the dqs and the vref level. dqss for write operation are referred to the cross point of the ck and the /ck. /s (/cs) (input pin): when /s is low, commands and data can be input. when /s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins): these pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. see "command operation". a0 to a12 (input pins): row address (ax0 to ax12) is determined by the a0 to the a12 level at the cross point of the ck rising edge and the vref level in a bank active command cycle. column address (ay0 to ay9) is loaded via the a0 to the a9, the a11 at the cross point of the ck rising edge and the vref level in a read or a write command cycle. this column address becomes the starting address of a burst operation. a10 (ap) (input pin): a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1, ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. ba0, ba1 (input pin): ba0/ba1 are bank select signals. the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if ba1 = low and ba0 = low, bank 0 is selected. if ba1 = high and ba0 = low, bank 1 is selected. if ba1 = low and ba0 = high, bank 2 is selected. if ba1 = high and ba0 = high, bank 3 is selected. cke (input pin): cke controls power down and self-refresh. the power down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. the cke level must be kept for 1 ck cycle (= lckepw) at least, that is, if cke changes at the cross point of the ck rising edge and the vref level with proper setup time tis, at the next ck rising edge cke level must be kept with proper hold time tih. pin functions (2) dm (input pins): dm is the reference signals of the data input mask function. dms are sampled at the cross point of dqs and vref. dq, cb (input and output pins): data are input to and output from these pins. dqs (input and output pin): dqs provide the read data strobes (as output) and the write data strobes (as input). vcc and vccq (power supply pins): 2.5v is applied. (vcc is for the internal circuit and vccq is for the output buffer.) vccspd (power supply pin): 2.5v is applied (for serial eeprom). vss (power supply pin): ground is connected. /reset (input pin): lvcmos reset input. when /reset is low, all registers are reset and all outputs are low.
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 12 detailed operation part, ac characteristics and timing waveforms refer to the hm5425161b/hm5425801b/hm5425401b series datasheet (e0086h10). dimm /cas latency = device cl + 1 for registered type. electrical specifications absolute maximum ratings parameter symbol value unit note voltage on any pin relative to vss vt ?1.0 to +4.6 v 1 supply voltage relative to vss vcc, vccq ?1.0 to +4.6 v 1 short circuit output current iout 50 ma power dissipation pt 9 w operating temperature topr 0 to +55 c storage temperature tstg ?50 to +100 c notes: 1. respect to vss. dc operating conditions (ta = 0 to +55c) parameter symbol min. typ max. unit notes supply voltage vcc, vccq 2.3 2.5 2.7 v 1, 2 vss 0 0 0 v input reference voltage vref 1.15 1.25 1.35 v 1 termination voltage vtt vref ? 0.04 vref vref + 0.04 v 1 dc input high voltage vih vref + 0.18 ? vccq + 0.3 v 1, 3 dc input low voltage vil ?0.3 ? vref ? 0.18 v 1, 4 dc input signal voltage vin (dc) ?0.3 ? vccq + 0.3 v 5 dc differential input voltage vswing (dc) 0.36 ? vccq + 0.6 v 6 notes: 1. all parameters are referred to vss, when measured. 2. vccq must be lower than or equal to vcc. 3. vih is allowed to exceed vcc up to 4.6v for the period shorter than or equal to 5ns. 4. vil is allowed to outreach below vss down to ?1.0v for the period shorter than or equal to 5ns. 5. vin (dc) specifies the allowable dc execution of each differential input. 6. vswing (dc) specifies the input differential voltage required for switching.
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 13 dc characteristics 1 (ta = 0 to 55c, vcc, vccq = 2.5v 0.2v, vss = 0v) hb54a2569f1u hb54a5129f2u parameter symbol grade max. max. unit test condition notes operating current (actv-pre) icc0 -a75b -b75b -10b 1294 1241 1099 1744 1646 1459 ma cke vih, trc = min. 1, 2, 5 operating current (actv-read-pre) icc1 -a75b -b75b -10b 1789 1691 1549 2239 2096 1909 ma cke vih, bl = 2, cl = 3.5, trc = min. 1, 2, 5 idle power down standby current icc2p -a75b -b75b -10b 556 521 487 718 656 595 ma cke vil 4 idle standby current icc2n -a75b -b75b -10b 754 701 649 1114 1016 919 ma cke vih, /cs vih 4 active power down standby current icc3p -a75b -b75b -10b 619 556 514 844 746 649 ma cke vil 3 active standby current icc3n -a75b -b75b -10b 844 791 739 1294 1196 1099 ma cke vih, /cs vih tras = max. 3 operating current (burst read operation) icc4r -a75b -b75b -10b 2419 2321 2224 2869 2726 2584 ma cke vih, bl = 2, cl = 3.5 1, 2, 5, 6 operating current (burst write operation) icc4w -a75b -b75b -10b 2239 2141 2044 2689 2546 2404 ma cke vih, bl = 2, cl = 3.5 1, 2, 5, 6 auto refresh current icc5 -a75b -b75b -10b 2239 2186 1999 2689 2591 2359 ma trfc = min., input vil or vih self refresh current icc6 -a75b -b75b -10b 421 413 406 448 440 433 ma input vcc ? 0.2v input 0.2v. notes. 1. these icc data are measured under condition that dq pins are not connected. 2. one bank operation. 3. one bank active. 4. all banks idle. 5. command/address transition once per one cycle. 6. data/data mask transition twice per one cycle. 7. the icc data on this table are measured with regard to tck = min. in general. dc characteristics 2 (ta = 0 to 55c, vcc, vccq = 2.5v 0.2v, vss = 0v) parameter symbol min. max. unit test condition notes input leakage current ili ?10 10 a vcc vin vss output leakage current ilo ?10 10 a vcc vout vss output high voltage voh vtt + 0.76 ? v ioh (max.) = ?15.2ma output low voltage vol ? vtt ? 0.76 v iol (min.) = 15.2ma
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 14 pin capacitance (ta = 25c, vcc, vccq = 2.5v 0.2v) [hb54a2569f1u] parameter symbol pins max. unit notes input capacitance ci1 address, /ras, /cas, /we, /s, cke 15 pf 1, 3 input capacitance ci2 ck, /ck 20 pf 1, 3 data and dqs input/output capacitance co dq, dqs, cb, dm 15 pf 1, 2, 3 [hb54a5129f2u] parameter symbol pins max. unit notes input capacitance ci1 address, /ras, /cas, /we, /s, cke 15 pf 1, 3 input capacitance ci2 ck, /ck 20 pf 1, 3 data and dqs input/output capacitance co dq, dqs, cb, dm 20 pf 1, 2, 3 notes: 1. these parameters are measured on conditions: f = 100mhz, vout = vccq/2, ? vout = 0.2v. 2. dout circuits are disabled. 3. this parameter is sampled and not 100% tested. timing parameter measured in clock cycle for registered dimm number of clock cycle parameter symbol min. max. write to pre-charge command delay (same bank) twpd 3 + bl/2 read to pre-charge command delay (same bank) trpd bl/2 write to read command delay (to input all data) twrd 2 + bl/2 burst stop command to write command delay (cl = 3) tbstw 2 (cl = 3.5) tbstw 3 burst stop command to dq high-z (cl = 3) tbstz 3 (cl = 3.5) tbstz 3.5 read command to write command delay (to output all data) (cl = 3) trwd 2 + bl/2 (cl = 3.5) trwd 3 + bl/2 pre-charge command to high-z (cl = 3) thzp 3 (cl = 3.5) thzp 3.5 write command to data in latency twcd 2 write recovery twr 1 register set command to active or register set command tmrd 2 self refresh exit to non-read command tsnr 10 self refresh exit to read command tsrd 200 power down entry tpden 1 power down exit to command input tpdex 1 cke minimum pulse width tckepw 1
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 15 physical outline detail a 0.20 0.15 2.50 0.20 1.27 typ 133.35 0.15 128.95 (datum -a-) 2.30 64.77 49.53 (64.48) a b 1 92 93 r 2.00 184 1.00 0.05 unit: mm note: tolerance on all dimensions 0.13 unless otherwise specified. 1.27 0.10 3.00 min 4.00 min 10.00 4.00 0.10 17.80 30.48 0.15 4.00 max 2 ?
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 16 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
eol product hb54a2569f1u, hb54a5129f2u data sheet e0206h30 (ver. 3.0) 17 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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