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data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 1 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| features ? meets jitter requirements for at&t tr62411 stratum 4 and stratum 4 enhanced for ds1 interfaces, and for etsi ets300 011 for e1 inter- faces provides c1.5, c3, c2, c4, c8 and c16 output clock signals provides 3 kinds of 8khz framing signals selectable 1.544mhz, 2.084mhz or 8khz input reference signals operates in either normal or free-run states enhanced in jitter and duty cycle comparing with pt7a4401b package: 28-pin plcc (PT7A4401Cj) applications synchronization and timing control for multitrunk t1 and e1 systems st-bus clock and frame pulse sources introduction PT7A4401C is functionally enhanced version of pt7a4401b. it has better jitter performance and c16 whose output duty cycle is independent of 20mhz master clock. the PT7A4401C employs a digital phase-locked loop (dpll) to provide timing and synchronizing signals for multitrunk t1 and e1 primary rate transmission links. it generates the st-bus clock and framing sig- nals that are phase-locked to input reference signals of either 2.048mhz, 1.544mhz or 8khz. the PT7A4401C is compliant with at&t tr62411 stratum 4 and stratum 4 enhanced, and etsi ets 300 011. it meets the requirements for jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, cap- ture range and phase slope, etc.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| features ............................................................................................................................... ................ 1 applications ............................................................................................................................... ......... 1 introduction ............................................................................................................................... .......... 1 block diagram .................................................................................................................. .................. 3 pin information ................................................................................................................ ................... 4 pin assignment ................................................................................................................. ......... 4 pin configuration .............................................................................................................. ........ 4 pin description ................................................................................................................ .......... 5 functional description ......................................................................................................... ............... 6 overall operation .............................................................................................................. ........ 6 states of operation ............................................................................................................ ........ 7 applications information ....................................................................................................... .... 8 detailed specifications ........................................................................................................ .............. 10 definition of critical performance specifications .................................................................... 10 absolute maximum ratings .................................................................................................... 11 recommended operating conditions ...................................................................................... 11 dc electrical and power supply characteristics ..................................................................... 12 ac electrical characteristics .................................................................................................. .13 mechanical specifications ...................................................................................................... .25 ordering information ........................................................................................................... ............. 26 notes .......................................................................................................................... ....................... 27 contents page contents
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 3 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| ref osci osco output circuit feedback frequency select mux phase detector limiter & loop filter dco1 dco2 input impairment monitor state machine master clock t1 divider e1 divider rst ms fs1 fs2 c1.5 c3 c2 c4 c8 c16 f0 f8 f16 v cc gnd block diagram figure 1. block digram
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 4 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| pin information pin assignment table 1. pin assignment s p u o r gs p u o r g s p u o r g s p u o r gs p u o r gs l o b m y ss l o b m y s s l o b m y s s l o b m y ss l o b m y ss n o i t c n u fs n o i t c n u f s n o i t c n u f s n o i t c n u fs n o i t c n u f k c o l c p i h co c s o , i c s ok c o l c d n u o r g & r e w o pv c c d n g ,r e w o p t u p t u o g n i m a r f d n a k c o l c , 0 f , 6 1 c , 8 c , 4 c , 2 c , 3 c , 5 . 1 c 6 1 f , 8 f s l a n g i s g n i m a r f d n a k c o l c s l a n g i s l o r t n o ct s r , 2 s f , 1 s f , s ml o r t n o c t u p n i e c n e r e f e rf e rk c o l c e c n e r e f e r pin configuration figure 2. pin configuration ref nu nu gnd rst fs1 fs2 nu nu ms nu nu nc nu 4 3 2 1 28 27 26 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 c3 c2 c4 gnd c8 c16 v c c v cc osco osci f16 f0 f8 c1.5 top view 28-pin plcc
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 5 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| pin description table 2. pin description n i pn i p n i p n i pn i pe m a ne m a n e m a n e m a ne m a ne p y te p y t e p y t e p y te p y tn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d 5 1 , 1d n gd n u o r g ) v 0 ( d n u o r g) v 0 ( d n u o r g ) v 0 ( d n u o r g ) v 0 ( d n u o r g) v 0 ( d n u o r g , 1 2 , 9 1 , 3 , 2 5 2 , 4 2 , 2 2 u ni d e s u t o nd e s u t o n d e s u t o n d e s u t o nd e s u t o n) d n u o r g o t d e t c e n n o c e b d l u o h s ( 4f e ri e l b i t a p m o c l t t ( t u p n i e c n e r e f e re l b i t a p m o c l t t ( t u p n i e c n e r e f e r e l b i t a p m o c l t t ( t u p n i e c n e r e f e r e l b i t a p m o c l t t ( t u p n i e c n e r e f e re l b i t a p m o c l t t ( t u p n i e c n e r e f e rs l a n g i s e c n e r e f e r t u p n i : ) 8 1 , 5v c c r e w o p ) v 5 + ( y l p p u s r e w o p) v 5 + ( y l p p u s r e w o p ) v 5 + ( y l p p u s r e w o p ) v 5 + ( y l p p u s r e w o p) v 5 + ( y l p p u s r e w o p 6o c s oo : ) s o m c ( t u p t u o k c o l c r e t s a m r o t a l l i c s o: ) s o m c ( t u p t u o k c o l c r e t s a m r o t a l l i c s o : ) s o m c ( t u p t u o k c o l c r e t s a m r o t a l l i c s o : ) s o m c ( t u p t u o k c o l c r e t s a m r o t a l l i c s o: ) s o m c ( t u p t u o k c o l c r e t s a m r o t a l l i c s ok c o l c r e t s a m z h m 0 2 f o t u p t u o 7i c s oi : ) s o m c ( t u p n i k c o l c r e t s a m r o t a l l i c s o: ) s o m c ( t u p n i k c o l c r e t s a m r o t a l l i c s o : ) s o m c ( t u p n i k c o l c r e t s a m r o t a l l i c s o : ) s o m c ( t u p n i k c o l c r e t s a m r o t a l l i c s o: ) s o m c ( t u p n i k c o l c r e t s a m r o t a l l i c s o e b n a c ( k c o l c r e t s a m z h m 0 2 f o t u p n i ) e c r u o s k c o l c a o t y l t c e r i d d e t c e n n o c 86 1 fo e l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r fe l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f e l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f e l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r fe l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f s e t a c i d n i t a h t e s l u p t u p t u o g n i m a r f z h k 8 : ) e h t f o d o i r e p e h t n o p u d e s a b s i h t d i w e s l u p e h t . e m a r f s u b - t s e h t f o t r a t s e h t . k c o l c n o i t a z i n o r h c n y s z h m 4 8 3 . 6 1 90 fo l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r fl b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r fl b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f s e t a c i d n i t a h t e s l u p g n i m a r f t u p t u o z h k 8 : ) e e h t f o d o i r e p e h t n o p u d e s a b s i h t d i w e s l u p e h t . e m a r f s u b - t s e v i t c a e h t f o t r a t s e h t . k c o l c n o i t a z i n o r h c n y s z h m 6 9 0 . 4 0 18 fo e l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r fe l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f e l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f e l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r fe l b i t a p m o c s o m c ( t u p t u o e s l u p e m a r f s e t a c i d n i t a h t e s l u p g n i m a r f t u p t u o z h k 8 : ) e h t f o d o i r e p e h t n o p u d e s a b s i h t d i w e s l u p e h t . e m a r f s u b - t s e v i t c a e h t f o t r a t s e h t . k c o l c n o i t a z i n o r h c n y s z h m 2 9 1 . 8 1 15 . 1 co ) e l b i t a p m o c s o m c ( k c o l c z h m 4 4 5 . 1) e l b i t a p m o c s o m c ( k c o l c z h m 4 4 5 . 1 ) e l b i t a p m o c s o m c ( k c o l c z h m 4 4 5 . 1 ) e l b i t a p m o c s o m c ( k c o l c z h m 4 4 5 . 1) e l b i t a p m o c s o m c ( k c o l c z h m 4 4 5 . 1 2 13 co ) e l b i t a p m o c s o m c ( k c o l c z h m 8 8 0 . 3) e l b i t a p m o c s o m c ( k c o l c z h m 8 8 0 . 3 ) e l b i t a p m o c s o m c ( k c o l c z h m 8 8 0 . 3 ) e l b i t a p m o c s o m c ( k c o l c z h m 8 8 0 . 3) e l b i t a p m o c s o m c ( k c o l c z h m 8 8 0 . 3 3 12 co ) e l b i t a p m o c s o m c ( k c o l c z h m 8 4 0 . 2) e l b i t a p m o c s o m c ( k c o l c z h m 8 4 0 . 2 ) e l b i t a p m o c s o m c ( k c o l c z h m 8 4 0 . 2 ) e l b i t a p m o c s o m c ( k c o l c z h m 8 4 0 . 2) e l b i t a p m o c s o m c ( k c o l c z h m 8 4 0 . 2 4 14 co ) e l b i t a p m o c s o m c ( k c o l c z h m 6 9 0 . 4) e l b i t a p m o c s o m c ( k c o l c z h m 6 9 0 . 4 ) e l b i t a p m o c s o m c ( k c o l c z h m 6 9 0 . 4 ) e l b i t a p m o c s o m c ( k c o l c z h m 6 9 0 . 4) e l b i t a p m o c s o m c ( k c o l c z h m 6 9 0 . 4 6 18 co ) e l b i t a p m o c s o m c ( k c o l c z h m 2 9 1 . 8) e l b i t a p m o c s o m c ( k c o l c z h m 2 9 1 . 8 ) e l b i t a p m o c s o m c ( k c o l c z h m 2 9 1 . 8 ) e l b i t a p m o c s o m c ( k c o l c z h m 2 9 1 . 8) e l b i t a p m o c s o m c ( k c o l c z h m 2 9 1 . 8 7 16 1 co ) e l b i t a p m o c s o m c ( k c o l c z h m 4 8 3 . 6 1) e l b i t a p m o c s o m c ( k c o l c z h m 4 8 3 . 6 1 ) e l b i t a p m o c s o m c ( k c o l c z h m 4 8 3 . 6 1 ) e l b i t a p m o c s o m c ( k c o l c z h m 4 8 3 . 6 1) e l b i t a p m o c s o m c ( k c o l c z h m 4 8 3 . 6 1 0 2c no : d e t c e n n o c t o n: d e t c e n n o c t o n : d e t c e n n o c t o n : d e t c e n n o c t o n: d e t c e n n o c t o n. n i p s i h t o t n o i t c e n n o c o n e k a m 3 2s mi : ) e l b i t a p m o c l t t ( t c e l e s e d o m: ) e l b i t a p m o c l t t ( t c e l e s e d o m : ) e l b i t a p m o c l t t ( t c e l e s e d o m : ) e l b i t a p m o c l t t ( t c e l e s e d o m: ) e l b i t a p m o c l t t ( t c e l e s e d o m , e c i v e d e h t f o e d o m n o i t a r e p o e h t s t c e l e s t u p n i s i h t . 4 e l b a t o t r e f e r . n u r e e r f r o l a m r o n , . e . i 6 22 s fi : ) e l b i t a p m o c l t t ( 2 t c e l e s y c n e u q e r f: ) e l b i t a p m o c l t t ( 2 t c e l e s y c n e u q e r f : ) e l b i t a p m o c l t t ( 2 t c e l e s y c n e u q e r f : ) e l b i t a p m o c l t t ( 2 t c e l e s y c n e u q e r f: ) e l b i t a p m o c l t t ( 2 t c e l e s y c n e u q e r f e h t s t c e l e s , 1 s f h t i w r e h t e g o t , t u p n i s i h t o t r e f e r . z h m 8 4 0 . 2 r o z h m 4 4 5 . 1 , z h k 8 r e h t i e , l a n g i s e c n e r e f e r t u p n i e h t f o y c n e u q e r f . 3 e l b a t 7 21 s fi : ) e l b i t a p m o c l t t ( 1 t c e l e s y c n e u q e r f: ) e l b i t a p m o c l t t ( 1 t c e l e s y c n e u q e r f : ) e l b i t a p m o c l t t ( 1 t c e l e s y c n e u q e r f : ) e l b i t a p m o c l t t ( 1 t c e l e s y c n e u q e r f: ) e l b i t a p m o c l t t ( 1 t c e l e s y c n e u q e r f. 2 s f f o n o i t p i r c s e d n i p e h t o t r e f e r 8 2t s ri : ) r e g g i r t t t i m h c s t u p n i s o m c ( t e s e r: ) r e g g i r t t t i m h c s t u p n i s o m c ( t e s e r : ) r e g g i r t t t i m h c s t u p n i s o m c ( t e s e r : ) r e g g i r t t t i m h c s t u p n i s o m c ( t e s e r: ) r e g g i r t t t i m h c s t u p n i s o m c ( t e s e r t e s e r e h t . l e v e l w o l t a n e h w e c i v e d e h t t e s e r r e p o r p e r u s n e o t e g n a h c t u p n i t c e l e s y c n e u q e r f n e h w r o p u - r e w o p n e h w d e d e e n s i e h t s e m i t e v i f f o . n i m a e b t s u m t i u c r i c t e s e r p u - r e w o p a r o f t n a t s n o c e m i t e h t . n o i t a r e p o a r o f w o l d l e h e b t s u m n i p t s r e h t , n o i t a r e p o l a m r o n n i . y l p p u s r e w o p e h t f o e m i t e s i r . h g i h t a d e x i f e r a s t u p t u o l l a , l e v e l w o l t a t s r n e h w . e c i v e d e h t t e s e r o t s n 0 0 3 f o . n i m
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 6 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| functional description overall operation the PT7A4401C is a multitrunk synchronizer that provides the clock and frame signals for t1 and e1 primary rate digital transmission links. it basically consists of the master clock circuit, digital phase- locked loop (dpll), input impairment monitor and output circuit. the dpll circuit is employed to provide synchronization of the output signals. referring to the block diagram on page 3, the detailed func- tions of the PT7A4401C are described as follows. master clock as its master clock, the PT7A4401C uses either an external clock source or an external crystal and a few discrete compo- nents with its internal oscillator. major digital phase-locked loop (dpll) block the major dpll blocks are the phase detector, limiter, loop filter, and digitally controlled oscillators (dco1 and dco2). the input signal is sent to the phase detector for comparison with the feedback signal from the feedback frequency select mux. an error signal corresponding to their instantaneous phase difference is produced and sent to the limiter. the limiter amplifies this error signal to ensure that the dpll responds to all input transient conditions with a maximum output phase slope of 5ns per 125 s. this performance easily meets the maximum phase slope of 7.6ns per 125 s or 81ns per 1.326ms specified by at&t tr62411. the loop filter is a 1.9hz low pass filter for all three reference frequency selections: 8khz, 1.544mhz and 2.048mhz. this filter ensures that the jitter transfer requirements in ets 300- 011 and at&t tr62411 are met. the error signal, after being limited and filtered, is sent to two digitally controlled variable frequency oscillators (dco1 and dco2). based upon the processed error value, the dcos will generate the corresponding digital output signals to the out- put circuit to produce 12.352mhz and 16.384mhz signals. the dco synchronization method depends upon the PT7A4401C operating state, as follows: in normal state, each dco generates an output signal which is frequency and phase locked to the input reference signal. in auto-holdover state, each dco generates an output signal whose frequency is equal to what it was for a 30ms period shortly before the end of the last normal state. in free-run state, the dcos are free running with an accuracy equal to the accuracy of the osci 20mhz source. output circuit signals from the two dcos are sent to the output circuit to generate two clock signals, 12.352mhz and 16.384mhz, which are divided in the t1 and e1 dividers respectively to provide needed clock and frame signals. the t1 divider uses the 12.352mhz signal to generate two clock signals, c1.5 and c3. they have a nominal 50% duty cycle. the e1 divider uses the 16.384mhz signal to generate four clock signals and three frame signals, i.e., c2, c4, c8, c16, f0, f8 and f16. the frame signals are generated directly from the c16 signal. the c2, c4 and c8 signals have a nominal 50% duty cycle, and c16 ? s duty cycle is about 50% if the master clock has a 50% duty cycle. all the frame and clock outputs are locked to each other for all operating states. they have limited driving capability and should be buffered when driving high capacitance loads. feedback frequency selection mux the feedback frequency is selected by fs1 and fs2 (as shown in table 3) to match the particular incoming reference fre- quency (1.544mhz, 2.048mhz or 8khz). a reset (rst) must be performed after every frequency select input change. input impairment monitor this circuit monitors the input signal to the dpll and auto- matically enables auto-holdover state when the incoming sig- nal is completely lost, or if its frequency is outside the auto- holdover capture range (either a small or large amount). when the incoming signal returns to normal, the dpll will be re- turned to normal state.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 7 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| 2 s f2 s f 2 s f 2 s f2 s f1 s f1 s f 1 s f 1 s f1 s fy c n e u q e r f t u p n iy c n e u q e r f t u p n i y c n e u q e r f t u p n i y c n e u q e r f t u p n iy c n e u q e r f t u p n i 00 d e v r e s e r 01 z h k 8 10 z h m 4 4 5 . 1 11 z h m 8 4 0 . 2 table 3. input frequency selection states of operation typically, the PT7A4401C operates in either the normal or free-run state. however, when the input signal is temporarily missing or its frequency is temporarily out of specification, it operates in auto-holdover state (refer to table 7). normal state in normal state, the output signals of the PT7A4401C are synchronized with the input reference signal by the dpll. free-run state typically, the free-run state is used immediately following system power-up before network synchronization is achieved, or when a master clock is otherwise required. in free-run state, the outputs of the PT7A4401C are uncorrelated with the input reference signal (and the stored information concerning the output reference signals). instead, these output signals are based solely on the master clock fre- quency (osci). auto-holdover state the auto-holdover state will be automatically initiated when incoming reference signal disappears or its frequency moves outside the auto-holdover capture range (table 7), by either a small or large amount. in auto-holdover state, the PT7A4401C output signals are not synchronized with the external input reference signal. in- stead, they are generated by using the information stored 30 ms to 60ms before the incoming reference signal became un- usable. while in normal state, a numerical value related to the output reference frequency is stored alternately in two memory loca- tions every 30ms. whenever the device is switched into auto- holdover state, the value in memory between 30ms and 60ms is used to set the output frequency of the device. state machine if the value of ms is 1, the ? free-run ? state of operation is forced. if the value of ms is 0, the state of operation is either ? normal ? or ? auto-holdover ? , depending upon the state of the input impairment monitor. see table 4. table 4. operation state selection s ms m s m s ms me t a t s n o i t a r e p oe t a t s n o i t a r e p o e t a t s n o i t a r e p o e t a t s n o i t a r e p oe t a t s n o i t a r e p o 0l a m r o n 1n u r e e r f
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 8 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| applications information master clock the PT7A4401C uses either an external clock source or an external crystal and a few passive components with its internal oscillator as the master timing source. in free-run state, the frequency tolerance of the PT7A4401C output clocks are equal to the frequency tolerance of the tim- ing source. in a given application, if an accurate free-run state is not required, the tolerance of the master timing source may be 100ppm. if required, the tolerance must be no worse than 32 ppm. the capture range of PT7A4401C must also be considered when deciding the accuracy of the master timing source. the sum of the accuracy of the master timing source and the cap- ture range of the PT7A4401C will always equal 230ppm. for example, if the master timing source is 100ppm, the capture range will be 130ppm. clock oscillator if using an external clock source, its output pin should be connected directly (not ac coupled) to the osci pin of the PT7A4401C, and the osco pin can be left open as shown in figure 3 or connected as an output pin. when selecting the clock oscillator, following specifications should be considered. they are - absolute frequency - frequency change over temperature - output rise and fall time - output level - duty cycle crystal oscillator if a crystal and passive components operating together with the PT7A4401C oscillator are selected as the master timing source, they should be connected as shown in figure 4. it should be possible to adjust the trimmer capacitor so that the frequency is well within the 32 ppm tolerance; however, only the proper specification of components will insure this toler- ance over the necessary temperature range. figure 4. crystal oscillator connection figure 3. clock oscillator connection +5v 20mhz out gnd PT7A4401C osci osco +5v no connection 0.1 f the crystal specification is as follows: - frequency: 20mhz - tolerance: as required - oscillation mode: fundamental - resonance mode: parallel - load capacitance: 32pf - maximum series resistance: 35 ? - pproximate drive level: 1mw PT7A4401C 56 p f 1m ? 20mhz 39pf 3-50 p f osci osco 100 ?
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 9 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| reset circuit a simple power-up reset circuit with about a 50 s reset active (low) time is shown in figure 5. resistor r p is used for protec- tion only. the reset time is not critical but should be greater than 300ns. figure 5. power-up reset circuit power supply decoupling the PT7A4401C has two v cc pins and two gnd pins. power decoupling capacitors should be included as shown in figure 6. + 1 5 15 18 c1 0.1 f c2 0.1 f PT7A4401C + figure 6. power supply decoupling PT7A4401C rst +5v r 10k ? r p 1k ? c 10nf
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 10 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| detailed specifications definitions of critical performance specifications intrinsic jitter: intrinsic jitter is the jitter produced by the synchronizing circuit. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. intrinsic jitter may also be measured when the device is in a non-synchronizing mode--such as free running or auto-holdover--by measuring the output jitter of the device. intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards. jitter tolerance: jitter tolerance is a measure of the ability of a pll to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is present on its reference. the appli- cable standard specifies how much jitter to apply to the refer- ence when testing for jitter tolerance. jitter transfer: jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device with respect to a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and frequencies, and output jit- ter is measured with various filters depending on the appli- cable standard. its 3 possible input frequencies and 9 outputs gives the PT7A4401C 27 possible jitter transfer combinations. how- ever, only three cases of the jitter transfer specifications are given in the ac electrical characteristics; as the remaining combinations can be derived from them. for the PT7A4401C, jitter attenuation is determined by the internal 1.9hz low pass loop filter and phase slope limiter. the phase slope limiter limits the output phase slope to 5ns/125 s. therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum out- put phase slope will be limited (i.e., attenuated) to 5ns/125 s. it should be noted that 1ui at 1.544mhz (644ns) is not equal to 1ui at 2.048mhz (488ns). a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. example - when the t1 input jitter is 20ui (t1 ui units) and the t1 to t1 jitter attenuation is 18db, the t1 and e1 output jitter can be calculated as follows: j t1o = j t1i x 10 = 20 x 10 = 2.5ui j e1o = j t1o x ( ) = j t1o x ( ) = 3.3ui 1uit1 1uie1 644ns 488ns ( ) ( ) -a 20 -18 20 using the above method, the jitter attenuation can be calcu- lated for all combinations of inputs and outputs based upon the three jitter transfer functions provided. note that the resulting jitter transfer functions for all combina- tions of inputs (8khz, 1.544mhz, 2.048mhz) and outputs (8khz, 1.544mhz, 2.048mhz, 4.096mhz, 8.192mhz, 16.384mhz) for a given input signal (jitter frequency and jit- ter amplitude) are the same. as intrinsic jitter is always present, jitter attenuation will ap- pear to be lower for small input jitter signals than for large ones. consequently, accurate jitter transfer function measure- ments are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). frequency accuracy: frequency accuracy is defined as the ab- solute tolerance of an output clock signal when it is operating in a free running mode (not locked to an external reference). for the PT7A4401C, free- run accuracy is equal to the master clock (osci) accuracy. auto-holdover accuracy: auto-holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. for the PT7A4401C the storage value is deter- mined while the device is in normal state and locked to an exter- nal reference signal. the absolute master clock (osci) accuracy of the PT7A4401C does not affect auto-holdover accuracy, but the change in osci accuracy while in auto-holdover state does. lock range: if the PT7A4401C dpll is already in a state of synchronization ( ? lock ? ) with the incoming reference signal, it is able to track this signal to maintain lock as its frequency varies over a certain range, called the lock range. the size of lock range is related to the range of the digitally controlled oscillators and is equal to 230ppm minus the accuracy of the master clock (osci). for example, a 32ppm master clock re- sults in a lock range of 198ppm. capture range: if the PT7A4401C dpll is not at present in a state of synchronization (lock) with the incoming reference signal, it is able to initiate (acquire) lock only if the signal ? s frequency is within a certain range, called the capture range. for any pll, no portion of the capture range can fall outside the lock range, and, in general, the capture range is more narrow than the lock range. however, owing to the design of its phase detector, the PT7A4401C ? s capture range is equal to its lock range. phase slope: phase slope is measured in seconds per second and is defined as the rate at which a given signal changes phase with respect to an ideal signal of constant frequency. the given signal is typically the output signal. the ideal sig- nal has a constant frequency that is nominally equal in value to that of the final output signal or final input signal.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 11 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| absolute maximum ratings recommended operating conditions table 5. recommended operating conditions m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u v c c e g a t l o v y l p p u s d e d n e m m o c e r r e v o s n o i t i d n o c g n i t a r e p o 5 . 40 . 55 . 5v t a e r u t a r e p m e t g n i t a r e p o0 4 -5 25 8 o c storage temperature ...................................................... -65 o c to +150 o c ambient temperature with power applied ...................... -40 o c to +85 o c supply voltage to ground potential (inputs & v cc only) ...... -0.3 to 7.0v supply voltage to ground potential (outputs & d/o only) .. -0.3 to 7.0v dc input voltage .................................................................. -0.3 to 7.0v dc output current ...................................................................... 120ma power dissipation ....................................................................... 900mw note: typical figures are at 25 o c and are for design aid only; not production tested. note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 12 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| dc electrical and power supply characteristics table 6. dc electrical and power supply characteristics note: 1. v cc = 5v, 2. ms = v cc (freerun), fs1 = v cc , fs2 = gnd, ref = gnd, other inputs connected to gnd. 3. all outputs are unloaded except for v oh and v ol measurement. m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u i o c c t n e r r u c y l p p u s r e w o p t n e c s e i u q2 e t o n , v 0 = i c s o0 0 5 a i c c t n e r r u c y l p p u s 0 5a m i c c 2 e t o n , l a t s y r c = i c s o0 6a m v h i s n i p l l a - e g a t l o v t u p n i h g i h l t t t s r , i c s o t p e c x e 0 . 2v v l i s n i p l l a - e g a t l o v t u p n i w o l l t t t s r , i c s o t p e c x e 8 . 0v v h i c - e g a t l o v t u p n i h g i h s o m c n i p i c s o v 7 . 0 c c v v l i c - e g a t l o v t u p n i w o l s o m c n i p i c s o v 3 . 0 c c v v h i s - e g a t l o v t u p n i h g i h t t i m h c s s n i p t s r 6 . 3v v l i s - e g a t l o v t u p n i w o l t t i m h c s s n i p t s r 5 . 1v v s y h - e g a t l o v s i s e r e t s y h t t i m h c s s n i p t s r 0 . 1v i l i t n e r r u c e g a k a e l t u p n iv i v = c c v 0 r o 0 1 a v h o e g a t l o v t u p t u o h g i hi h o a m 4 =4 . 2v v l o e g a t l o v t u p t u o w o li l o a m 4 =8 . 0v
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 13 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| ac electrical characteristics performance table 7. performance m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u m p p 0 3 00m p p m p p 2 3 : t a i c s o h t i w y c a r u c c a e t a t s n u r e e r f2 3 -2 3 +m p p m p p 0 0 10 0 1 -0 0 1 +m p p m p p 0 6 - 4 , 1 0 9 1 -0 3 2 +m p p m p p 2 3 : t a i c s o h t i w e g n a r e r u t p a c8 5 1 -8 9 1 +m p p m p p 0 0 10 9 -0 3 1 +m p p e m i t k c o l e s a h p2 1 - 4 , 10 3s e p o l s e s a h p t u p t u o5 2 , 2 1 - 15 4 s / s * refer to the test conditions on page 24 for details.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 14 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| voltage levels for timing parameter measurement table 8. voltage levels for timing parameter measurement m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d t t i m h c st t i m h c s t t i m h c s t t i m h c st t i m h c s ) t s r r o f ( l t tl t t l t t l t tl t t s o m cs o m c s o m c s o m cs o m c ) i c s o r o f ( s t i n us t i n u s t i n u s t i n us t i n u v t e g a t l o v d l o h s e r h t5 . 15 . 1v 5 . 0 c c v v m h h g i h e g a t l o v d l o h s e r h t g n i l l a f d n a g n i s i r4 . 20 . 2v 7 . 0 c c v v m l w o l e g a t l o v d l o h s e r h t g n i l l a f d n a g n i s i r8 . 08 . 0v 3 . 0 c c v figure 7. voltage levels for timing parameter measurement signal t if /t of t ir /t or timing reference points v hm v t v lm
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 15 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| timing characteristics table 9. timing characteristics * refer to the test conditions on page 24 for details. note: 1. typical figures are at 25 o c and are for design aid only; not production tested. 2. the maximum and minimum timing is measured under recommended temperature conditions and power supplies. 3. ttl voltage levels are used for timing parameter measurement. m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t w r r o h g i h h t d i w e s l u p t u p n i e c n e r e f e r w o l 7 3 , 9 - 4 , 1 0 0 1s n t r i t / f i g n i l l a f r o g n i s i r t u p n i e c n e r e f e r e m i t 0 1s n t d 8 r y a l e d 8 f o t t u p n i e c n e r e f e r z h k 8 6 3 , 1 2 , 9 1 , 2 1 - 4 , 1 8 2 -1 -s n t d 5 1 r 8 f o t t u p n i e c n e r e f e r z h m 4 4 5 . 1 y a l e d 7 3 33 6 3s n t d 2 r 8 f o t t u p n i e c n e r e f e r z h m 8 4 0 . 2 y a l e d 7 1 28 3 2s n t d 0 f y a l e d 0 f o t 8 f7 3 , 9 1 , 2 1 - 10 1 14 3 1s n t d 6 1 f y a l e d 6 1 f o t 8 f9 1 , 2 1 - 19 14 4s n t d 5 1 c y a l e d 5 . 1 c o t 8 f 7 3 , 9 1 , 2 1 - 1 5 4 -1 3 -s n t d 3 c y a l e d 3 c o t 8 f6 4 -1 3 -s n t d 2 c y a l e d 2 c o t 8 f0 1 -5s n t d 4 c y a l e d 4 c o t 8 f0 1 -5s n t d 8 c y a l e d 8 c o t 8 f0 1 -5s n t d 6 1 c y a l e d 6 1 c o t 8 f0 1 -5s n t w 5 1 c w o l r o h g i h h t d i w e s l u p 5 . 1 c9 0 39 3 3s n t w 3 c w o l r o h g i h h t d i w e s l u p 3 c9 4 15 7 1s n t w 2 c w o l r o h g i h h t d i w e s l u p 2 c0 3 28 5 2s n t w 4 c w o l r o h g i h h t d i w e s l u p 4 c1 1 13 3 1s n t w 8 c w o l r o h g i h h t d i w e s l u p 8 c2 50 7s n
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 16 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| table 9. timing characteristics (continued) * refer to the test conditions on page 24 for details. note: 1. typical figures are at 25 o c and are for design aid only; not production tested. 2. the maximum and minimum timing is measured under recommended temperature conditions and power supplies. 3. ttl voltage levels are used for timing parameter measurement. figure 8. setup and hold timing of input controls f8 ms v t v t t s t h m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t l w 6 1 c w o l h t d i w e s l u p 6 1 c9 1 , 2 1 - 16 27 3s n t l w 0 f w o l h t d i w e s l u p 0 f 7 3 , 9 1 , 2 1 - 1 0 3 28 5 2s n t h w 8 f h g i h h t d i w e s l u p 8 f1 1 13 3 1s n t l w 6 1 f w o l h t d i w e s l u p 6 1 f2 50 7s n t f r o g n i s i r e s l u p e m a r f d n a k c o l c t u p t u o e m i t g n i l l a f r o 9s n t s e m i t p u t e s s l o r t n o c t u p n i0 0 1s n t h e m i t d l o h s l o r t n o c t u p n i0 0 1s n
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 17 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 9. timing information for PT7A4401C ref 8khz ref 1.544mhz ref 2.048mhz f8 v t v t v t v t t r8d t rw t rw t rw t r15d t r2d note: input to output delay values are valid after a rst with no further state changes. t f16d f8 f0 f16 c16 c8 c4 c2 c3 c1.5 v t v t v t v t v t v t v t v t v t t f8w h t f0d t f0w l t f16w l t c16wl t c16d t c8w t c8w t c8d t c4w t c4w t c4d t c2w t c2d t c3w t c3w t c3d t c15w t c15d figure 10. output timing
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 18 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| intrinsic jitter unfiltered table 10. intrinsic jitter unfiltered m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u ) z h k 8 ( 0 f t a r e t t i j c i s n i r t s n i 3 3 , 6 2 , 2 2 - 9 1 , 2 1 - 1 1 0 0 0 . 02 0 0 0 . 0p p i u ) z h k 8 ( 8 f t a r e t t i j c i s n i r t s n i 1 0 0 0 . 02 0 0 0 . 0p p i u ) z h k 8 ( 6 1 f t a r e t t i j c i s n i r t s n i 1 0 0 0 . 02 0 0 0 . 0p p i u ) z h m 4 4 5 . 1 ( 5 . 1 c t a r e t t i j c i s n i r t s n i3 3 , 7 2 , 2 2 - 9 1 , 2 1 - 16 1 0 . 00 3 0 . 0p p i u ) z h m 8 4 0 . 2 ( 2 c t a r e t t i j c i s n i r t s n i3 3 , 8 2 , 2 2 - 9 1 , 2 1 - 10 2 0 . 00 4 0 . 0p p i u ) z h m 8 8 0 . 3 ( 3 c t a r e t t i j c i s n i r t s n i3 3 , 9 2 , 2 2 - 9 1 , 2 1 - 12 3 0 . 00 6 0 . 0p p i u ) z h m 6 9 0 . 4 ( 4 c t a r e t t i j c i s n i r t s n i3 3 , 0 3 , 2 2 - 9 1 , 2 1 - 17 4 0 . 00 8 0 . 0p p i u ) z h m 2 9 1 . 8 ( 8 c t a r e t t i j c i s n i r t s n i3 3 , 1 3 , 2 2 - 9 1 , 2 1 - 19 0 . 06 1 . 0p p i u ) z h m 4 8 3 . 6 1 ( 6 1 c t a r e t t i j c i s n i r t s n i3 3 , 2 3 , 2 2 - 9 1 , 2 1 - 18 1 . 02 3 . 0p p i u * refer to the test conditions on page 24 for details. c1.5 (1.544mhz) instrinsic jitter filtered table 11. c1.5 (1.544mhz) instrinsic jitter filtered m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u ) r e t l i f z h k 0 0 1 o t z h 4 ( r e t t i j c i s n i r t s n i 7 2 , 2 2 - 9 1 , 2 1 - 1 5 1 0 . 0p p i u ) r e t l i f z h k 0 4 o t z h 0 1 ( r e t t i j c i s n i r t s n i 0 1 0 . 0p p i u ) r e t l i f z h k 0 4 o t z h k 8 ( r e t t i j c i s n i r t s n i 0 1 0 . 0p p i u ) r e t l i f z h k 8 o t z h 0 1 ( r e t t i j c i s n i r t s n i 5 0 0 . 0p p i u * refer to the test conditions on page 24 for details.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 19 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| c2 (2.048mhz) instrinsic jitter filtered table 12. c2 (2.048mhz) instrinsic jitter filtered m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u ) r e t l i f z h k 0 0 1 o t z h 4 ( r e t t i j c i s n i r t s n i 8 2 , 2 2 - 9 1 , 2 1 - 1 5 1 0 . 0p p i u ) r e t l i f z h k 0 4 o t z h 0 1 ( r e t t i j c i s n i r t s n i 0 1 0 . 0p p i u ) r e t l i f z h k 0 4 o t z h k 8 ( r e t t i j c i s n i r t s n i 0 1 0 . 0p p i u ) r e t l i f z h k 8 o t z h 0 1 ( r e t t i j c i s n i r t s n i 5 0 0 . 0p p i u * refer to the test conditions on page 24 for details. 8khz input to 8khz output jitter transfer table 13. 8khz input to 8khz output jitter transfer m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u h t i w z h 1 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 1 0 . 0 , 6 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 4 , 1 3 3 06b d h t i w z h 1 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 4 5 . 0 66 1b d h t i w z h 0 1 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 0 1 . 0 2 12 2b d h t i w z h 0 6 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 0 1 . 0 8 28 3b d h t i w z h 0 0 3 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 0 1 . 0 2 4b d h t i w z h 0 0 6 3 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 5 0 0 . 0 5 4b d * refer to the test conditions on page 24 for details.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 20 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| 1.544mhz input to 1.544mhz output jitter transfer table 14. 1.544mhz input to 1.544mhz output jitter transfer m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u p p i u 0 2 h t i w z h 1 r o f n o i t a u n e t t a r e t t i j t u p n i , 7 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 5 , 1 3 3 06b d p p i u 4 0 1 h t i w z h 1 r o f n o i t a u n e t t a r e t t i j t u p n i 66 1b d p p i u 0 2 h t i w z h 0 1 r o f n o i t a u n e t t a r e t t i j t u p n i 2 12 2b d p p i u 0 2 h t i w z h 0 6 r o f n o i t a u n e t t a r e t t i j t u p n i 8 28 3b d h t i w z h 0 0 3 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 0 2 2 4b d h t i w z h k 0 1 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 3 . 0 5 4b d h t i w z h k 0 0 1 r o f n o i t a u n e t t a r e t t i j t u p n i p p i u 3 . 0 5 4b d * refer to the test conditions on page 24 for details.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 21 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| 2.048mhz input to 2.048mhz output jitter transfer table 15. 2.048mhz input to 2.048mhz output jitter transfer m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t u p n i p p i u 0 0 . 3 z h 1 r o f t u p t u o t a r e t t i j 3 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 19 . 2p p i u 4 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 19 0 . 0p p i u t u p n i p p i u 3 3 . 2 z h 3 r o f t u p t u o t a r e t t i j 3 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 13 . 1p p i u 4 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 10 1 . 0p p i u t u p n i p p i u 7 0 . 2 z h 5 r o f t u p t u o t a r e t t i j 3 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 10 8 . 0p p i u 4 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 10 1 . 0p p i u t u p n i p p i u 6 7 . 1 z h 0 1 r o f t u p t u o t a r e t t i j 3 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 10 4 . 0p p i u 4 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 10 1 . 0p p i u p p i u 0 5 . 1 z h 0 0 1 r o f t u p t u o t a r e t t i j t u p n i 3 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 16 0 . 0p p i u 4 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 15 0 . 0p p i u p p i u 0 5 . 1 z h 0 0 4 2 r o f t u p t u o t a r e t t i j t u p n i 3 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 14 0 . 0p p i u 4 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 13 0 . 0p p i u p p i u 0 2 . 0 z h k 0 0 1 r o f t u p t u o t a r e t t i j t u p n i 3 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 14 0 . 0p p i u 4 3 , 8 2 , 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 12 0 . 0p p i u * refer to the test conditions on page 24 for details.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 22 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t u p n i z h 1 r o f e c n a r e l o t r e t t i j , 4 2 - 2 2 , 0 2 , 9 1 , 2 1 - 7 , 4 , 1 6 2 0 8 . 0p p i u t u p n i z h 5 r o f e c n a r e l o t r e t t i j0 7 . 0p p i u t u p n i z h 0 2 r o f e c n a r e l o t r e t t i j0 6 . 0p p i u t u p n i z h 0 0 3 r o f e c n a r e l o t r e t t i j0 2 . 0p p i u t u p n i z h 0 0 4 r o f e c n a r e l o t r e t t i j5 1 . 0p p i u t u p n i z h 0 0 7 r o f e c n a r e l o t r e t t i j8 0 . 0p p i u t u p n i z h 0 0 4 2 r o f e c n a r e l o t r e t t i j2 0 . 0p p i u t u p n i z h 0 0 6 3 r o f e c n a r e l o t r e t t i j1 0 . 0p p i u 8khz input jitter tolerance table 16. 8khz input jitter tolerance * refer to the test conditions on page 24 for details. 1.544mhz input jitter tolerance table 17. 1.544mhz input jitter tolerance m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t u p n i z h 1 r o f e c n a r e l o t r e t t i j , 4 2 - 2 2 , 0 2 , 9 1 , 2 1 - 7 , 5 , 1 7 2 0 5 1p p i u t u p n i z h 5 r o f e c n a r e l o t r e t t i j0 4 1p p i u t u p n i z h 0 2 r o f e c n a r e l o t r e t t i j0 3 1p p i u t u p n i z h 0 0 3 r o f e c n a r e l o t r e t t i j5 3p p i u t u p n i z h 0 0 4 r o f e c n a r e l o t r e t t i j5 2p p i u t u p n i z h 0 0 7 r o f e c n a r e l o t r e t t i j5 1p p i u t u p n i z h 0 0 4 2 r o f e c n a r e l o t r e t t i j4p p i u t u p n i z h k 0 1 r o f e c n a r e l o t r e t t i j1p p i u t u p n i z h k 0 0 1 r o f e c n a r e l o t r e t t i j5 . 0p p i u * refer to the test conditions on page 24 for details.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 23 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| 2.048mhz input jitter tolerance table 18. 2.048mhz input jitter tolerance m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t u p n i z h 1 r o f e c n a r e l o t r e t t i j , 4 2 - 2 2 , 0 2 , 9 1 , 2 1 - 7 , 6 , 1 8 2 0 5 1p p i u t u p n i z h 5 r o f e c n a r e l o t r e t t i j0 4 1p p i u t u p n i z h 0 2 r o f e c n a r e l o t r e t t i j0 3 1p p i u t u p n i z h 0 0 3 r o f e c n a r e l o t r e t t i j0 5p p i u t u p n i z h 0 0 4 r o f e c n a r e l o t r e t t i j0 4p p i u t u p n i z h 0 0 7 r o f e c n a r e l o t r e t t i j0 2p p i u t u p n i z h 0 0 4 2 r o f e c n a r e l o t r e t t i j5p p i u t u p n i z h k 0 1 r o f e c n a r e l o t r e t t i j1p p i u t u p n i z h k 0 0 1 r o f e c n a r e l o t r e t t i j1p p i u * refer to the test conditions on page 24 for details. osci 20mhz master clock input table 19. osci 20mhz master clock input m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d* s n o i t i d n o c t s e t* s n o i t i d n o c t s e t * s n o i t i d n o c t s e t * s n o i t i d n o c t s e t* s n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u e c n a r e l o t 6 1 , 3 100m p p 7 1 , 4 12 3 -2 3 +m p p 8 1 , 5 10 0 1 -0 0 1 +m p p e l c y c y t u d0 40 6% e m i t e s i r0 1s n e m i t l l a f0 1s n * refer to the test conditions on page 24 for details.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 24 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| test conditions: 1. normal state selected. 2. auto-holdover state. 3. freerun state selected. 4. 8khz frequency source selected. 5. 1.544mhz frequency source selected. 6. 2.048mhz frequency source selected. 7. master clock input osci at 20mhz 0ppm. 8. master clock input osci at 20mhz 32ppm. 9. master clock input osci at 20mhz 100ppm. 10. reference input at 0ppm. 11. reference input at 32ppm. 12. reference input at 100ppm. 13. for freerun state of 0ppm. 14. for freerun state of 32ppm. 15. for freerun state of 100ppm. 16. for capture range of 230ppm. 17. for capture range of 198ppm. 18. for capture range of 130ppm. 19. 25pf capacitive load. 20. osci master clock jitter is less than 2ns p-p, or 0.04ui p-p where 1ui p-p = 1/20mhz. 21. jitter on reference input is less than 7ns p-p. 22. applied jitter is sinusoidal. 23. minimum applied input jitter magnitude to regain syn- chronization. 24. loss of synchronization is obtained at slightly higher in- put jitter amplitudes. 25. within 10 ms of the state or input change 26. 1uipp = 125 s for 8khz signals. 27. 1uipp = 648ns for 1.544mhz signals. 28. 1uipp = 488ns for 2.048mhz signals. 29. 1uipp = 323ns for 3.088mhz signals. 30. 1uipp = 244ns for 4.096mhz signals. 31. 1uipp = 122ns for 8.192mhz signals. 32. 1uipp = 61ns for 16.384mhz signals. 33. no filter. 34. 40hz to 100khz bandpass filter. 35. with respect to reference input signal frequency. 36. after a rst. 37. master clock duty cycle 40% to 60%. 38. prior to auto-holdover state, device was in normal state and phase-locked. notes: 1. voltages are with respect to ground (gnd) unless otherwise stated. 2. supply voltage and operation temperature are as per recommended operating conditions. 3. timing parameters are as per ac electrical characteristics - voltage levels for timing parameter measurement.
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 25 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| mechanical specifications figure 11. 28-pin plcc
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 26 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| r e b m u n t r a pr e b m u n t r a p r e b m u n t r a p r e b m u n t r a pr e b m u n t r a pe g a k c a pe g a k c a p e g a k c a p e g a k c a pe g a k c a p j c 1 0 4 4 a 7 t pc c l p n i p - 8 2 ordering information table 20. ordering information
data sheet PT7A4401C t1/e1 system synchronizer pt0108(09/02) ver:0 27 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| notes pericom technology inc. email: support@pti.com.cn web-site: www.pti.com.cn, www.pti-ic.com china : no. 20 building, 3/f, 481 guiping road, shanghai, 200233, china tel: (86)-21-6485 0576 fax: (86)-21-6485 2181 asia pacific : unit 1517, 15/f, chevalier commercial centre, 8 wang hoi rd, kowloon bay, hongkong tel: (852)-2243 3660 fax: (852)- 2243 3667 u.s.a. : 2380 bering drive, san jose, california 95131, usa tel: (1)-408-435 0800 fax: (1)-408-435 1100 pericom technology incorporation reserves the right to make changes to its products or specifications at any time, without noti ce, in order to improve design or performance and to supply the best possible product. pericom technology does not assume any responsibility fo r use of any circuitry described other than the circuitry embodied in pericom technology product. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom technology incorporation.

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