target specification this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. march 2010 doc id 17266 rev 1 1/10 10 STL60N32N3LL dual n-channel 30 v, 0.006 , 15 a powerflat?5x6 asymmetrical double island, stripfet? power mosfet features r ds(on) * q g industry benchmark extremely low on-resistance r ds(on) very low switching gate charge high avalanche ruggedness low gate drive power losses application switching applications description this product utilizes latest generations of design rules of st?s proprietary stripfet? v and stripfet? vi deepgate technology. the lowest available r ds(on) *q g , in this chip scale package, makes this device suitable for the most demanding dc-dc converter applications, where high power density is to be achieved. figure 1. internal schematic diagram type v dss r ds(on) i d STL60N32N3LL q 1 30 v < 0.012 12 a q 2 30 v < 0.008 15 a powerflat?5x6 asymmetrical double island ' $ $ $ ' 3 3 3 1 1 0 i n i n d i c a t o r ! - v table 1. device summary order code marking package packaging STL60N32N3LL 60n32n3ll powerflat?5x6 asymmetrical double island tape and reel www.st.com
contents STL60N32N3LL 2/10 doc id 17266 rev 1 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STL60N32N3LL electrical ratings doc id 17266 rev 1 3/10 1 electrical ratings table 2. absolute maximum ratings symbol parameter type value unit v ds drain-source voltage (v gs = 0) q 1 q 2 30 30 v v v gs gate- source voltage q 1 q 2 22 20 v v i d (1) 1. this value is accordingly r thj-c drain current (continuous) at t c = 25c q 1 q 2 32 60 a a i d (1) drain current (continuous) at t c = 100c q 1 q 2 20 37 a a i d (2) 2. this value is accordingly r thj-pcb drain current (continuous) at t c = 25c q 1 q 2 12 15 a a i d (2) drain current (continuous) at t c = 100c q 1 q 2 7.5 9 a a i dm (3) 3. pulse width limited by safe operating area drain current (pulsed) q 1 q 2 48 60 a a p tot (1) total dissipation at t c = 25c q 1 q 2 23 50 w w p tot (2) total dissipation at t c = 25c q 1 q 2 3.12 3.12 w w e as (4) 4. starting t j = 25 c, i d = 7.5 a single pulse avalanche energy tbd mj table 3. thermal data symbol parameter type value unit r thj-pcb (1) 1. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec thermal resistance junction-ambient max 40 c/w r thj-c thermal resistance junction-case q 1 q 2 5.5 2.5 c/w t j thermal operating junction-ambient 150 c t stg storage temperature -55 to 150 c
electrical characteristics STL60N32N3LL 4/10 doc id 17266 rev 1 2 electrical characteristics (t case =25c unless otherwise specified) table 4. on/off states symbol parameter test conditions type min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 q 1 q 2 30 30 v v i dss zero gate voltage drain current (v gs = 0) v ds = max rating q 1 q 2 1 1 a a i dss zero gate voltage drain current (v gs = 0) v ds =max rating @125c q 1 q 2 10 10 a a i gss gate-body leakage current (v ds = 0) v gs = 22 v q 1 q 2 100 100 na na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a q 1 q 2 1 1 v v r ds(on) static drain-source on resistance v gs = 10 v, i d = 6 a v gs = 10 v, i d = 7.5 a q 1 q 2 0.01 0.006 0.12 0.008 r ds(on) static drain-source on resistance v gs = 4.5 v, i d = 6 a v gs = 4.5 v, i d = 7.5 a q 1 q 2 0.0115 0.009 0.014 0.011 table 5. dynamic symbol parameter test conditions type min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 q 1 q 2 - 1020 1690 - pf pf c oss output capacitance q 1 q 2 - 200 291 - pf pf c rss reverse transfer capacitance q 1 q 2 - 26 176 - pf pf q g total gate charge v dd = 15 v, i d = 15 a, v gs = 4.5 v (see figure 3) q 1 q 2 - 7 17 - nc nc q gs gate-source charge q 1 q 2 - tbd tbd - nc nc q gd gate-drain charge q 1 q 2 - tbd tbd - nc nc
STL60N32N3LL electrical characteristics doc id 17266 rev 1 5/10 table 6. switching times symbol parameter test conditions type min. typ. max. unit t d(on) t r turn-on delay time rise time v dd =15 v, i d =7.5 a, r g =4.7 , v gs = 4.5 v (see figure 7) q 1 q 2 q 1 q 2 -tbd- ns ns ns ns t d(off) t f turn-off delay time fall time v dd =15 v, i d =7.5 a, r g =4.7 , v gs = 4.5v (see figure 7) q 1 q 2 q 1 q 2 -tbd- ns ns ns ns table 7. source drain diode symbol parameter test conditions type min. typ. max. unit i sd source-drain current v dd =15 v, i d =7.5 a r g =4.7 , v gs =4.5 v q 1 q 2 - 12 15 a a i sdm (1) 1. pulse width limited by safe operating area. source-drain current (pulsed) v dd =15 v, i d = 7.5 a r g =4.7 , v gs =4.5 v q 1 q 2 - 48 60 a a v sd (2) 2. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 15 a, v gs = 0 q 1 q 2 - 1.1 1.1 v v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 15 a, v dd = 15 v di/dt = 100 a/s, t j = 150c (see figure 7) q 1 q 2 q 1 q 2 q 1 q 2 - tbd tbd tbd tbd tbd tbd ns ns nc nc a a
test circuits STL60N32N3LL 6/10 doc id 17266 rev 1 3 test circuits figure 2. switching times test circuit for resistive load figure 3. gate charge test circuit figure 4. test circuit for inductive load switching and diode recovery times figure 5. unclamped inductive load test circuit figure 6. unclamped inductive wavefo rm figure 7. switching time waveform
STL60N32N3LL package mechanical data doc id 17266 rev 1 7/10 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 8. package drawing table 8. powerflat? 5x6 asymmetrical double island dimentions dim. mm min. typ. max. a 0.77 0.97 a1 0.03 b 0.42 0.52 d 4.90 5.00? 5.10 d2 2.40 2.60 e 5.90 6.00 6.10 e2 2.90 3.10 e1.27 l 0.40 0.60 ! - v
package mechanical data STL60N32N3LL 8/10 doc id 17266 rev 1 figure 9. recommended footprint (dimensions are in mm)
STL60N32N3LL revision history doc id 17266 rev 1 9/10 5 revision history table 9. document revision history date revision changes 15-mar-2010 1 first release
STL60N32N3LL 10/10 doc id 17266 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
|
