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1 5390a?bdc?06/04 features dual adc with 8-bit resolution 500 msps sampling rate per channe l, 1 gsps in interlaced mode single or 1:2 demultiplexed output lvds output format (100 ? ) 500 mvpp analog input (differential only) differential or single-ended 50 ? pecl/lvds compatible clock inputs power supply: 3.3v (analog), 3. 3v (digital), 2.25v (output) lqfp144 package temperature range: ? 0c < t a < 70c (commercial grade) ? -40c < t a < 85c (industrial grade) 3-wire serial interface ? 16-bit data, 3-bit address ? 1:2 or 1:1 output demultiplexer ratio selection ? full or partial standby mode ? analog gain (1.5 db) digital control ? input clock selection ? analog input switch selection ? binary or gray logical outputs ? synchronous data ready reset ? data ready delay adjust able on both channels ? interlacing functions: offset and gain (channel to channel) calibration digital fine sda (fine sampling delay adjust) on one channel ? internal static or dynamic built-in test (bit) performance low power consumption: 0.7w per channel power consumption in standby mode: 120 mw 1 ghz full power input bandwidth (-3 db) snr = 43 db typ (7.0 enob), thd = -53 dbc, sfdr = -55 dbc at fs = 500 msps fin = 250 mhz 2-tone imd3: -54 dbc (249 mhz, 251 mhz) at 500 msps dnl = 0.25 lsb, inl = 0.5 lsb channel to channel input offset erro r: 0.5 lsb max (after calibration) gain matching (channel to channel): 0.5 lsb max (after calibration) low bit error rate (10 -15 ) at 500 msps application instrumentation satellite receivers direct rf down conversion wlan dual 8-bit 500 msps adc at84ad004 smart adc
2 at84ad004 5390a?bdc?06/04 description the at84ad004 is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4w power consumption and excellent digitizing accuracy. it integrates dual on-chip track/holds that provide an enhanced dynamic performance with a sampling rate of up to 500 msps and an input frequency bandwidth of 1 ghz. the dual concept, the integrated demultiplexer and the easy interleaving mode make this device user-friendly for all dual channel applications, such as direct rf conversion or data acquisition. the smart func- tion of the 3-wire serial interface eliminates the need for external components, which are usually necessary for gain and offset tuning and setting of other parameters, leading to space and power r eduction as well as system flexibility. functional description the at84ad004 is a dual 8-bit 500 ms ps adc based on advanced high-speed bicmos technology. each adc includes a front-end analog multip lexer followed by a samp le and hold (s/h), and an 8-bit flash-like architecture core analog-to-digital converter. the output data is followed by a switchable 1:1 or 1:2 demultiplexer and lvds output buffers (100 ). two over-range bits are provided for adjustment of the external gain control on each channel. a 3-wire serial interface (3-bit address and 16-bit data) is included to provide several adjustments: analog input range adjustment (1.5 db) with 8-bit data control using a 3-wire bus interface (steps of 0.18 db) analog input switch: both adcs can convert the same analog input signal i or q gray or binary encoder output. output format: dmux 1:1 or 1:2 with control of the output frequency on the data ready output signal partial or full standby on channel i or channel q clock selection: ? two independent clocks: clki and clkq ? one master clock (clki) with the same phase for channel i and channel q ? one master clock but with two phases (clki for channel i and clkib for channel q) isa: internal settling adjustment on channel i and channel q fisda: fine sampling delay adjustment on channel q adjustable data ready output delay on both channels test mode: decimation mode (by 16), built-in test a calibration phase is provided to set the two dc offsets of channel i and channel q close to code 127.5 and calibrate the two gai ns to achieve a maximum difference of 0.5 lsb. the offset and gain error can also be set externally via the 3-wire serial interface. the at84ad004 operates in fully differential mo de from the analog inputs up to the dig- ital outputs. the at84ad004 features a full-power input bandwidth of 1 ghz.
3 at84ad004 5390a?bdc?06/04 figure 1. simplified block diagram doiri doirin doirq doirqn clki clock buffer divider 2 to16 drda i lvds clock buffer 2 clkio ddrb 16 doai doain 8bit adc i dmux 1:2 or 1:1 i lvds buffer i doiri input mux + vini s/h 16 dobi dobin vinib 8 - 2 gain control i calibration gain/offset isa i dmux control bit data clock ldn 3-wire serial interface 3wsi input switch gain control q calibration gain/offset isa q & fisda dmux control mode 2 doirq lvds buffe r q 8bit adc q dmux 1: 2 or 1: 1 q + vinq s/h 16 doaq doaqn vinqb - 8 16 dobq dobqn clkq clock buffer divider 2 to 16 drda q lvds clock buffer 2 clkqo ddrb
4 at84ad004 5390a?bdc?06/04 typical applications figure 2. satellite receiver application bandpass amplifier 11..12 ghz local oscillator bandpass amplifier 1..2 ghz low noise converter (connected to the dish) 0 90 local oscillator synthesizer 1.5 ? 2.5 ghz i q at84ad004 i q tunable band filter control functions: clock and carrier recovery... clock agc if band filter low pass filter satellite tuner demodulation dish satellite quadrature i q q
5 at84ad004 5390a?bdc?06/04 figure 3. dual channel digital oscilloscope application note: absolute maximum ratings are limiting values (referenced to gnd = 0v), to be applied individually, while other parameters are within specified operating conditions. long exposure to maximum ratings may affect device reliability. dac gain dac offset dac offset dac gain adc b adc a timing circuit fiso ram display analog switch channel mode selection p clock selection dacs dacs smart dual adc a a channel b channel a absolute maximum ratings parameter symbol value unit analog positive supply voltage v cca 3.6 v digital positive supply voltage v ccd 3.6 v output supply voltage v cco 3.6 v maximum difference between v cca and v ccd v cca to v ccd 0.8 v minimum v cco v cco 1.6 v analog input voltage v ini or v inib v inq or v inqb 1/-1 v digital input voltage v d -0.3 to v ccd + 0.3 v clock input voltage v clk or vc lkb -0.3 to v ccd + 0.3 v maximum difference between v clk and v clkb v clk - v clkb -2 to 2 v maximum junction temperature t j 125 c storage temperature t stg -65 to 150 c lead temperature (soldering 10s) t leads 300 c
6 at84ad004 5390a?bdc?06/04 electrical operating characteristics unless otherwise specified: v cca = 3.3v; v ccd = 3.3v; v cco = 2.25v v ini - v inb or v inq - v inqb = 500 mvpp full-scale differential input lvds digital outputs (100 ? ) t a (typical) = 25 c full temperature range: 0 c < t a < 70 c (commercial grade) or -40 c < t a < 85 c (industrial grade) recommended condi tions of use parameter symbol comments r ecommended value unit analog supply voltage v cca 3.3 v digital supply voltage v ccd 3.3 v output supply voltage v cco 2.25 v differential analog input voltage (full-scale) v ini -v inib or v inq -v inqb 500 mvpp differential clock input level vinclk 600 mvpp internal settling adjustment (isa) with a 3-wire serial interface for channel i and channel q isa -50 ps operating temperature range t ambient commercial grade industrial grade 0 < t a < 70 -40 < t a < 85 c table 1. electrical operating characteristics in nominal conditions parameter symbol min typ max unit resolution 8bits power requirements positive supply voltage - analog - digital output digital (lvds) and serial interface v cca v ccd v cco 3.15 3.15 2.0 3.3 3.3 2.25 3.45 3.45 2.5 v v v supply current (typical conditions) - analog - digital - output i cca i ccd i cco 150 230 100 180 275 120 ma ma ma supply current (1:2 dmux mode) - analog - digital - output i cca i ccd i cco 150 260 175 180 310 210 ma ma
7 at84ad004 5390a?bdc?06/04 supply current (2 input clocks, 1:2 dmux mode) - analog - digital - output i cca i ccd i cco 150 290 180 180 350 215 ma supply current (1 channel only, 1:1 dmux mode) - analog - digital - output i cca i ccd i cco 80 160 55 95 190 65 ma ma ma supply current (1 channel only, 1:2 dmux mode) - analog - digital - output i cca i ccd i cco 80 170 90 95 205 110 ma ma ma supply current (full standby mode) - analog - digital - output i cca i ccd i cco 12 24 3 17 34 5 ma ma ma nominal dissipation (1 clock, 1:1 dmux mode, 2 channels) p d 1.4 1.7 w nominal dissipation (full standby mode) stbpd 120 mw analog inputs full-scale differential analog input voltage v ini - v inib or v inq - v inqb 450 500 550 mv mv analog input capacitance i and q c in 2pf full power input bandwidth (-3 db) fpbw 1.0 ghz gain flatness (-0.5 db) 400 mhz clock input logic compatibility for clock inputs and ddrb reset (pins 124, 125,126,127,128,129) pecl/ecl/lvds pecl/lvds clock inputs voltages (v clki/in or v clkq/qn ) differential logical level v il - v ih 600 mv clock input power level -9 0 6 dbm clock input capacitance 2 pf digital outputs logic compatibility for digital outputs (depending on the value of v cco ) lv d s differential output voltage swings (assuming v cco = 2.25v) v od 220 270 350 mv table 1. electrical operating characteristics in nominal conditions (continued) parameter symbol min typ max unit
8 at84ad004 5390a?bdc?06/04 note: the gain setting is 0 db, one clock input, no stand by mode [full power mode], 1:1 dmux, calibration off. note: the gain setting is 0 db, two clock inputs, no st andby mode [full power mode], 1:2 dmux, calibration on. output levels (assuming v cco = 2.25v) 100 ? differentially terminated logic 0 voltage logic 1 voltage v ol v oh 1.0 1.25 1.1 1.35 1.2 1.45 v v output offset voltage (assuming v cco = 2.25v) 100 ? differentially terminated v os 1125 1250 1325 mv output impedance r o 50 w output current (shorted output) 12 ma output current (grounded output) 30 ma output level drift with temperature 1.3 mv/c digital input (serial interface) maximum clock frequency (input clk) fclk 50 mhz input logical level 0 (clk, mode, data, ldn) -0.4 0 0.4 v input logical level 1 (clk, mode, data, ldn) v cco - 0.4 v cco - 0.4 v cco + 0.4 v output logical level 0 (cal) -0.4 0 0.4 v output logical level 1 (cal) v cco - 0.4 v cco v cco + 0.4 v maximum output load (cal) 15 pf table 1. electrical operating characteristics in nominal conditions (continued) parameter symbol min typ max unit table 2. electrical operating characteristics parameter symbol min typ max unit dc accuracy no missing code guaranteed over specified temperature range differential non-linearity dnl 0.25 0.6 lsb integral non-linearity inl 0.5 1 lsb gain error (single channel i or q) with calibration -0.5 0 0.5 lsb input offset matching (single channel i or q) with calibration -0.5 0 0.5 lsb gain error drift against temperature gain error drift against v cca 0.062 0.064 lsb/c lsb/mv mean output offset code with calibration 127 127.5 128 lsb transient performance bit error rate fs = 1 gsps fin = 250 mhz ber 10 -15 10 -12 error/ sample adc settling time channel i or q (between 10% - 90% of output response) v ini -v inib = 500 mvpp ts 170 ps
9 at84ad004 5390a?bdc?06/04 notes: 1. differential input [-1 dbfs analog input level], gain setting is 0 db, two input clock signals, no standby mode, 1:1 dmux, isa = -50 ps. 2. measured on the at84ad004td-eb evaluation board. table 3. ac performances parameter symbol min typ max unit ac performance signal-to-noi se ratio fs = 500 msps fin = 20 mhz snr 42 44 dbc fs = 500 msps fin = 250 mhz 41 43 dbc fs = 500 msps fin = 500 mhz 42 dbc effective number of bits fs = 500 msps fin = 20 mhz enob 77.2 bits fs = 500 msps fin = 250 mhz 6.7 7.0 bits fs = 500 msps fin = 500 mhz 6.8 bits total harmonic distortion (first 9 harmonics) fs = 500 msps fin = 20 mhz |thd| 48 54 dbc fs = 500 msps fin = 250 mhz 47 53 dbc fs = 500 msps fin = 500 mhz 51 dbc spurious free dynamic range fs = 500 msps fin = 20 mhz |sfdr| 50 56 dbc fs = 500 msps fin = 250 mhz 49 55 dbc fs = 500 msps fin = 500 mhz 54 dbc two-tone inter-modulation distortion (single channel) f in1 = 249 mhz , f in2 = 251 mhz at fs = 500 msps imd -54 dbc phase matching using auto-calibration and fisda in interlace mode (channel i and q) fin = 250 mhz fs = 500 msps d ? -0.7 0 0.7 crosstalk channel i versus channel q fin = 250 mhz, fs = 500 msps (2) cr -55 db
10 at84ad004 5390a?bdc?06/04 note: one analog input on both cores, clock i samples the ana log input on the rising and falling edges. the calibration phase is necessary. the gain setting is 0 db, one input clock i, no standby mode, 1:1 dmux, fisda adjustment. table 4. ac performances in interlace mode parameter symbol min typ max unit interlace mode maximum equivalent clock frequency fint = 2 x fs where fs = external clock frequency f int 1gsps minimum clock frequency f int 20 msps differential non-linearity in interlace mode intdnl 0.25 lsb integral non-linearity in interlace mode intinl 0.5 lsb signal-to-n oise ratio in interlace mode fint = 1 gsps fin = 20 mhz isnr 42 dbc fint = 1 gsps fin = 250 mhz 40 dbc effective number of bits in interlace mode fint = 1 gsps fin = 20 mhz ienob 7.1 bits fint = 1 gsps fin = 250 mhz 6.8 bits total harmonic distorti on in interlace mode fint = 1 gsps fin = 20 mhz |ithd| 52 dbc fint = 1 gsps fin = 250 mhz 49 dbc spurious free dynamic range in interlace mode fint = 1 gsps fin = 20 mhz |isfdr| 54 dbc fint = 1 gsps fin = 250 mhz 52 dbc two-tone inter-modulation distortion (single channel) in interlace mode f in1 = 249 mhz , f in2 = 251 mhz at f int = 1 gsps iimd -54 dbc
11 at84ad004 5390a?bdc?06/04 table 5. switching performances parameter symbol min typ max unit switching performance and characteristics - see ?timing diagrams? on page 12. maximum operating clock frequency f s 500 msps minimum clock frequency (no transparent mode) f s 10 msps minimum clock frequency (with transparent mode) 1 ksps minimum clock pulse width [high] (no transparent mode) tc1 0.4 1 50 ns minimum clock pulse width [low] (no transparent mode) tc2 0.4 1 50 ns aperture delay: nominal mode with isa & fisda ta 1 ns aperture uncertainty jitter 0.4 ps (rms) data output delay between input clock and data tdo 3.8 ns data ready output delay tdr 3 ns data ready reset to data ready trdr 2 ns data output delay with data ready td2 1/2 fs +tdrda ps data ready (clko) delay adjust (140 ps steps) tdrda range -560 to 420 ps output skew 50 100 ps output rise/fall time for data (20% - 80%) tr/tf 300 350 500 ps output rise/fall time for data ready (20% - 80%) tr/tf 300 350 500 ps data pipeline delay (nominal mode) tpd 3 (port b) 3.5 (port a, 1:1 dmux mode) 4 (port a, 1:2 dmux mode) clock cycles data pipeline delay (nominal mode) in s/h transparent mode 2.5 (port b) 3 (port a, 1:1 dmux mode) 3.5 (port a, 1:2 dmux mode) ddrb recommended pulse width 1 ns
12 at84ad004 5390a?bdc?06/04 timing diagrams figure 4. timing diagram, adc i or adc q, 1:2 dmux mode, clock i for adc i, clock q for adc q figure 5. 1:1 dmux mode, clock i = adc i, clock q = adc q clkoi or clkoq (= clki/4) clki or clkq clkoi or clkoq (= clki/2) programmable delay vin ta n n + 1 n + 2 n + 3 pipeline delay = 4 clock cycles tdo td2 doia[0:7] or doqa[0:7] n - 2 n - 4 n doib[0:7] or doqb[0:7] pipeline delay = 3 clock cycles tdo n - 3 n - 1 n +1 address: d7 d6 d5 d4 d3 d2 d1 d0 1 1 x x 1 x 0 0 clki or clkq clkoi or clkoq vin ta n n + 1 n + 2 n + 3 pipeline delay = 3.5 clock cycles tdo doia[0:7] or doqa[0:7] n - 1 n - 3 n + 1 n - 2 n doib[0:7] and doqb[0:7] are high impedance address: d7 d6 d5 d4 d3 d2 d1 d0 1 1 x x 0 x 0 0
13 at84ad004 5390a?bdc?06/04 figure 6. 1:2 dmux mode, clock i = adc i, clock i = adc q clkoi (= clki/4) clki clkoi (= clki/2) vin ta n n + 1 n + 2 n + 3 pipeline delay = 4 clock cycles tdo td2 doia[0:7] ni - 2 ni - 4 ni doib[0:7] pipeline delay = 3 clock cycles tdo ni - 3 ni - 1 ni +1 address: d7 d6 d5 d4 d3 d2 d1 d0 1 0 x x 1 x 0 0 nq - 4 nq - 2 nq nq - 3 nq - 1 nq +1 doqa[0:7] doqb[0:7] clkoq is high impedance
14 at84ad004 5390a?bdc?06/04 figure 7. 1:1 dmux mode, clock i = adc i, clock i = adc q doib[0:7] and doqb[0:7] are high impedance clkoq is high impedance clki clkoi vin ta n n + 1 n + 2 n + 3 pipeline delay = 3.5 clock cycles tdo doia[0:7] doqa[0:7] n - 1 n - 3 n + 1 n - 2 n n - 1 n - 3 n + 1 n - 2 n address: d7 d6 d5 d4 d3 d2 d1 d0 1 0 x x 0 x 0 0
15 at84ad004 5390a?bdc?06/04 figure 8. 1:2 dmux mode, clock i = adc i, clock in = adc q clki clkoi (= clki/2) vin ta n n + 1 n + 4 n + 6 pipeline delay = 4 clock cycles tdo td2 doqa[0:7] n - 4 n - 8 n doqb[0:7] pipeline delay = 3 clock cycles tdo n - 6 n - 2 n + 2 address: d7 d6 d5 d4 d3 d2 d1 d0 0 x x x 1 x 0 0 n - 7 n - 3 n + 1 n - 5 n - 1 n + 3 doia[0:7] doib[0:7] clkoq is high impedance clkin pipeline delay = 3.5 clock cycles tdo n + 2 n + 3 n + 5 clkoi (= clki/4)
16 at84ad004 5390a?bdc?06/04 figure 9. 1:1 dmux mode, clock i = adc i, clock in = adc q figure 10. 1:1 dmux mode, decimation mode test (1:16 factor) notes: 1. frequency(clkoi) = frequency(data) = frequency(clki)/16. clki clkoi (= clki/2) vin ta n n + 1 n + 4 n + 6 pipeline delay = 3.5 clock cycles tdo doqa[0:7] address: d7 d6 d5 d4 d3 d2 d1 d0 0 x x x 0 x 0 0 doia[0:7] doib[0:7] and doqb[0:7] are high impedance clkoq is high impedance clkin n + 2 n + 3 n + 5 n - 2 n - 6 n + 2 n - 4 n n - 1 n - 5 n + 3 n - 3 n + 1 pipeline delay = 3 clock cycles tdo vin n - 16 n n + 16 n + 32 clki 16 clock cycles clkoi doia[0:7] n + 16 n + 32 n + 48 n - 16 n doqa[0:7] n + 16 n + 32 n + 48 n - 16 n address: d7 d6 d5 d4 d3 d2 d1 d0 1 0 x x 0 x 0 0 doib[0:7] and doqb[0:7] are high impedance clkoq is high impedance
17 at84ad004 5390a?bdc?06/04 figure 11. data ready reset figure 12. data ready reset 1:1 dmux mode note: the data ready reset is taken into account only 2 ns afte r it is asserted. the output clock first completes its cycle (if the reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) a nd then only, remains in reset state (frozen to a low level in 1:1 dmux mode). the next falling edge of the input clock after reset mak es the output clock return to normal mode (after tdr). ddrb clki or clkq 500 ps allowed allowed forbidden forbidden 1 ns min 500 ps 1 ns min clki or clkq clkoi or clkoq doia[0:7] or doqa[0:7] vin ta n n ddrb 2 ns tdr tdr pipeline delay + tdo clock in reset n + 1
18 at84ad004 5390a?bdc?06/04 figure 13. data ready reset 1:2 dmux mode notes: 1. in 1:2 dmux, fs/2 mode: the data ready reset is taken into account only 2 ns after it is asserted. the output clock fi rst completes its cycle (if the reset occurs when it is low, it goes high only when its half cycle is complete; if the re set occurs when it is high, it remains high) and then only, remains in reset state (frozen to a high le vel in 1:2 dmux fs/2 mode). t he next rising edge of the input clock after reset makes the output clock return to normal mode (after tdr). 2. in 1:2 dmux, fs/4 mode: the data ready reset is taken into account only 2 ns after it is asserted. the output clock fi rst completes its cycle (if the reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then only, remains in reset state (frozen to a low level in 1:2 dmux fs/4 mode). the next rising edge of the input clock after reset makes the output clock return to normal mode (after tdr). clki or clkq clkoi or clkoq (= clki/2) doia[0:7] or doqa[0:7] vin ta n n ddrb pipeline delay + tdo n + 1 2 ns doib[0:7] or doqb[0:7] n + 1 clkoi or clkoq (= clki/4) 1 ns min tdr tdr tdr + 2 cycles tdr + 2 cycles clock in reset
19 at84ad004 5390a?bdc?06/04 functions description table 6. description of functions name function v cca positive analog power supply v ccd positive digital power supply v cco positive output power supply gnda analog ground gndd digital ground gndo output ground v ini , v inib differential analog inputs i v inq , v inqb differential analog inputs q clkoi, clkoin, clkoq, clkoqn differential output data ready i and q clki, clkin, clkq, clkqn differential clock inputs i and q ddrb, ddrbn synchronous data ready reset i and q mode bit selection for 3-wire bus or nominal setting clk input clock for 3-wire bus interface data input data for 3-wire bus ldn beginning and end of register line for 3-wire bus interface differential output data port channel i differential output data port channel q doiri, doirin doirq, doirqn differential output in range data i and q vtestq test voltage output for adc q (to be left open) vtesti test voltage output for adc i (to be left open) cal output bit status internal calibration vdiode test diode voltage for t j measurement vini vinib clki clkib d0ai0 doai7 d0ai0n doai7n d0bi0 dobi7 d0bi0n dobi7n 32 gndd vcca = 3.3v at84ad004 gndo gnda vinq vinqb vccd = 3.3v vcco = 2.25v d0aq0 doaq7 d0aq0 doaq7 dobq0 doqbq7 dobq0n doqbq7n 32 doiri, doirin doirq, doirqn 4 clockoi, clockoib clockoq, clockoqb 4 clkq clkqb mode data clk ldn vtesti vtestq 2 vdiode
20 at84ad004 5390a?bdc?06/04 digital output coding (nominal settings) pin description table 7. digital output coding (nominal setting) differential analog input voltag e level digital output i or q (binary coding) out-of-range bit > 250 mv > positive full-scale + 1/2 lsb 1 1 1 1 1 1 1 1 1 250 mv 248 mv positive full-scale + 1/2 lsb positive full-scale - 1/2 lsb 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 mv -1 mv bipolar zero + 1/2 lsb bipolar zero - 1/2 lsb 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 -248 mv -250 mv negative full-scale + 1/2 lsb negative full-scale - 1/2 lsb 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 < -250 mv < negative full-scale - 1/2 lsb 0 0 0 0 0 0 0 0 1 table 8. at84ad004 lqfp 144 pin description symbol pin number function gnda, gndd, gndo 10, 12, 22, 24, 36, 38, 40, 42, 44, 46, 51, 54, 59, 61, 63, 65, 67, 69, 85, 87, 97, 99, 109, 111, 130, 142, 144 ground pins. to be connected to external ground plane v cca 41, 43, 45, 60, 62, 64 analog pos itive supply: 3.3v typical v ccd 9, 21, 37, 39, 66, 68, 88, 100, 112, 123, 141 3.3v digital supply v cco 11, 23, 86, 98, 110, 143 2.25v output and 3-wire serial interface supply v ini 57, 58 in-phase (+) analog input signal of the sample & hold differential preamplifier channel i v inib 55, 56 inverted phase (-) of analog input signal (v ini ) v inq 47, 48 in-phase (+) analog input signal of the sample & hold differential preamplifier channel q v inqb 49, 50 inverted phase (-) of analog input signal (v inq ) clki 124 in-phase (+) clock input signal clkin 125 inverted phase (-) clock input signal (clki) clkq 129 in-phase (+) clock input signal
21 at84ad004 5390a?bdc?06/04 clkqn 128 inverted phase (-) clock input signal (clkq) ddrb 126 synchronous data ready reset i and q ddrbn 127 inverted phase (-) of input signal (ddrb) doai0, doai1, doai2, doai3, doai4, doai5, doai6, doai7 117, 113, 105, 101, 93, 89, 81, 77 in-phase (+) digital outputs first phase demultiplexer (channel i) doai0 is the lsb. d0ai7 is the msb doai0n, doai1n, doai2n, doai3n, doai4n, doai5n, doai6n, doai7n, 118, 114, 106, 102, 94, 90, 82, 78 inverted phase (-) digital outputs first phase demultiplexer (channel i) doai0n is the lsb. d0ai7n is the msb dobi0, dobi1, dobi 2, dobi3, dobi4, dobi5, dobi6, dobi7 119, 115, 107, 103, 95, 91, 83, 79 in-phase (+) digital outputs second phase demultiplexer (channel i) dobi0 is the lsb. d0bi7 is the msb dobi0n, dobi1n, dobi2n, dobi3n, dobi4n, dobi5n, dobi6n, dobi7n 120, 116, 108, 104, 96, 92, 84, 80 inverted phase (-) digital outputs second phase demultiplexer (channel i) dobi0n is the lsb. d0bi7n is the msb doaq0, doaq1, doaq2, doaq3, doaq4, doaq5, doaq6, doaq7 136, 140, 4, 8, 16, 20, 28, 32 in-phase (+) digital outputs first phase demultiplexer (channel q) doai0 is the lsb. d0aq7 is the msb doaq0n, doaq1n, doaq2n, doaq3n, doaq4n, doaq5n, doaq6n, doaq7n 135, 139, 3, 7, 15, 19, 27, 31 inverted phase (-) digital outputs first phase demultiplexer (channel q) doai0n is the lsb. d0aq7n is the msb dobq0, dobq1, dobq2, dobq3, dobq4, dobq5, dobq6, dobq7 134, 138, 2, 6, 14, 18, 26, 30 in-phase (+) digital outputs second phase demultiplexer (channel q) dobq0 is the lsb. d0bq7 is the msb dobq0n, dobq1n, dobq2n, dobq3n, dobq4n, dobq5n, dobq6n, dobq7n 133, 137, 1 ,5, 13, 17, 25, 29 inverted phase (-) digital outputs second phase demultiplexer (channel q) dobq0n is the lsb. d0bq7n is the msb doiri 75 in-phase (+) out-of-range bit input (i phase) combined demultiplexer out-of-range is high on the leading edge of code 0 and code 256 doirin 76 inverted phase of output signal doiri doirq 34 in-phase (+) out-of-range bit input (q phase) combined demultiplexer out-of-range is high on the leading edge of code 0 and code 256 doirqn 33 inverted phase of output signal doirq mode 74 bit selection for 3-wire bus interface or nominal setting clk 73 input clock for 3-wire bus interface data 72 input data for 3-wire bus lnd 71 beginning and end of register line for 3- wire bus interface clkoi 121 output clock in-phase (+) channel i table 8. at84ad004 lqfp 144 pin description (continued) symbol pin number function
22 at84ad004 5390a?bdc?06/04 figure 14. at84ad004 pinout (top view) clkoin 122 inverted phase (-) output clock channel i clkoq 132 output clock in-phase (+) channel q, 1/2 input clock frequency clkoqn 131 inverted phase (-) output clock channel q vtestq, vtesti 52, 53 pins for in ternal test (to be left open) cal 70 calibration output bit status vdiode 35 positive node of diode used for die junction temperature measurements table 8. at84ad004 lqfp 144 pin description (continued) symbol pin number function lqfp 144 20 by 20 by 1.4 mm atmel - dual 8-bit
23 at84ad004 5390a?bdc?06/04 typical characterization results nominal conditions (unle ss otherwise specified): v cca = 3.3v; v ccd = 3.3v; v cco = 2.25v v ini - v inb or v inq to v inqb = 500 mvpp full-scale differential input lvds digital outputs (100 ) ta (typical) = 25 c full temperature range: 0 c < ta < 70 c (commercial grade) or -40 c < ta < 85 c (industrial grade) typical full power input bandwidth fs = 500 msps pclock = 0 dbm pin = -1 dbfs gain flatness (5 db) from dc to > 400 mhz full power input bandwidth at -3 db > 1 ghz figure 15. full power inpu t bandwidth -7 -6 -5 -4 -3 -2 -1 0 250 500 750 1000 1250 1500 fin (mhz) dbfs -3 db bandwidth gain flatness
24 at84ad004 5390a?bdc?06/04 typical crosstalk figure 16. crosstalk (fs = 500 msps) note: measured on the at84ad004td-eb evaluation board. typical dc, inl and dnl patterns 1:2 dmux mode, fs/4 dr type figure 17. typical inl (fs = 50 msps, fin = 1 mhz, saturated input) 0 10 20 30 40 50 60 70 80 0 100 200 300 400 500 600 700 800 900 1000 fin (mhz) dbc -0,6 -0,4 -0,2 0 0,2 0,4 0,6 1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256 codes inl (lsb)
25 at84ad004 5390a?bdc?06/04 figure 18. typical dnl (fs = 50 msps, fin = 1 mhz, saturated input) typical dynamic performances versus sampling frequency figure 19. enob versus sampling frequency in nyquist conditions (fin = fs/2) figure 20. sfdr versus sampling frequency in nyquist conditions (fin = fs/2) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 1 16 31 46 61 76 91 106 121 136 151 166 181 196 211 226 241 256 codes dnl (lsb) 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 50 100 150 200 250 300 350 400 450 500 550 fs (msps) enob (bit) -68 -65 -62 -59 -56 50 100 150 200 250 300 350 400 450 500 550 fs (msps) sfdr (dbc)
26 at84ad004 5390a?bdc?06/04 figure 21. thd versus sampling fr equency in nyquist conditions (fin = fs/2) figure 22. snr versus sampling frequency in nyquist conditions (fin = fs/2) typical dynamic performances versus input frequency figure 23. enob versus input frequency (fs = 500 msps) -60 -58 -56 -54 -52 -50 -48 50 100 150 200 250 300 350 400 450 500 550 fs (msps) thd (dbc) 40 41 42 43 44 45 50 100 150 200 250 300 350 400 450 500 550 fs (msps snr (dbc) 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 0 100 200 300 400 500 fin (mhz) enob (bit) channel i channel q
27 at84ad004 5390a?bdc?06/04 figure 24. sfdr versus input frequency (fs = 500 msps) figure 25. thd versus input frequency (fs = 500 msps) figure 26. snr versus input frequency (fs = 500 msps) -64 -62 -60 -58 -56 -54 -52 -50 -48 -46 0 100 200 300 400 500 fin (mhz) sfdr (dbc) channel i channel q -58 -57 -56 -55 -54 -53 -52 -51 -50 -49 -48 0 100 200 300 400 500 fin (mhz) thd (dbc) channel i channel q 40 41 42 43 44 45 0 100 200 300 400 500 fin (mhz) snr (dbc) channel i channel q
28 at84ad004 5390a?bdc?06/04 typical signal spectrum figure 27. fs = 500 msps and fin = 20 mhz (1:2 dmux, fs/4 dr type fisda = -35 ps, isa = -50 ps) figure 28. fs = 500 msps and fin = 250 mhz (1:2 dmux, fs/4 dr type fisda = -35 ps, isa = -50 ps) -120 -100 -80 -60 -40 -20 0 20 0 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234 fs (msps) dbc h2 h3 h4 fundamental: h1 sfdr = -60 dbc -120 -100 -80 -60 -40 -20 0 20 0 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234 fs (msps) dbc h2 h3 fundamental : h1 sfdr = -58 dbc
29 at84ad004 5390a?bdc?06/04 figure 29. fs = 500 msps and fin = 500 mhz (1:2 dmux, fs/4 dr type fisda = -35 ps, isa = -50 ps) note: the spectra are given with respect to the output clock frequency observed by the acquisi- tion system (figures 27 to 29). figure 30. fs = 500 msps and fin = 250 mhz (interleaving mode fint = 1 gsps 1:1 dmux, fisda = -35 ps, isa = -50 ps) -120 -100 -80 -60 -40 -20 0 20 0 16 31 47 63 78 94 109 125 141 156 172 188 203 219 234 fs (msps) dbc h3 h2 fundamental: h1 sfdr = -57 dbc -120 -100 -80 -60 -40 -20 0 20 0 62 125 187 249 311 374 436 498 fs (msps) dbc fs fundamental: h1 sfdr = -53 dbc
30 at84ad004 5390a?bdc?06/04 typical performance sensitivity versus power supplies and temperature figure 31. enob versus v cca (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) figure 32. sfdr versus v cca (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) 6.6 6.8 7.0 7.2 7.4 7.6 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 vcca (v) enob (bit) channel i channel q -62 -60 -58 -56 -54 -52 -50 -48 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 vcca (v) sfdr (dbc) channel i channel q
31 at84ad004 5390a?bdc?06/04 figure 33. thd versus v cca (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) figure 34. snr versus v cca (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) -58 -57 -56 -55 -54 -53 -52 -51 -50 -49 -48 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 vcca (v) thd (dbc) channel i channel q 41.0 42.0 43.0 44.0 45.0 46.0 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 vcca (v) snr (dbc) channel i channel q
32 at84ad004 5390a?bdc?06/04 figure 35. enob versus junction temperature (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) figure 36. sfdr versus junction temperatur e (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 -50 -25 0 25 50 75 100 tj (c) enob (bit) 500 msps 20 mhz 500 msps 250 mhz 500 msps 500 mhz -62 -60 -58 -56 -54 -52 -50 -48 -46 -50 -25 0 25 50 75 100 tj (c) sfdr (dbc) 500 msps 20 mhz 500 msps 250 mhz 500 msps 500 mhz
33 at84ad004 5390a?bdc?06/04 figure 37. thd versus junction temperature (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) figure 38. snr versus junction temperature (fs = 500 msps, fin = 250 mhz, 1:2 dmux, fs/4 dr type, isa = -50 ps) -58 -56 -54 -52 -50 -48 -46 -44 -50 -25 0 25 50 75 100 tj (c) thd (dbc) 500 msps 20 mhz 500 msps 250 mhz 500 ms p s 500 mhz 40 41 42 43 44 45 46 -50 -25 0 25 50 75 100 tj (c) snr (dbc) 500 msps 20 mhz 500 msps 250 mhz 500 msps 500 mhz
34 at84ad004 5390a?bdc?06/04 test and control features 3-wire serial interface control setting table 9. 3-wire serial interface control settings mode characteristics mode = 1 (2.25v) 3-wire serial bus interface activated mode = 0 (0v) 3-wire serial bus interface deactivated nominal setting: dual channel i and q activated one clock i 0 db gain dmux mode 1:1 drda i & q = 0 ps isa i & q = 0 ps fisda q = 0 ps binary output decimation test mode off calibration setting off data ready = fs /2
35 at84ad004 5390a?bdc?06/04 3-wire serial interface and data description the 3-wire bus is activated with the control bit mode set to 1. the length of the word is 19 bits: 16 for the data and 3 for the address. the maximum clock frequency is 50 mhz. table 10. 3-wire serial interface address setting description address setting 000 standby gray/binary mode 1:1 or 1:2 dmux mode analog input mux clock selection auto-calibration decimation test mode data ready delay adjust 001 analog gain adjustment data7 to data0: gain channel i data15 to data8: gain channel q code 00000000: -1.5 db code 10000000: 0 db code 11111111: 1.5 db steps: 0.011 db 010 offset compensation data7 to data0: offset channel i data15 to data8: offset channel q data7 and data15: sign bits code 11111111b: 31.75 lsb code 10000000b: 0 lsb code 00000000b: 0 lsb code 01111111b: -31.75 lsb steps: 0.25 lsb maximum correction: 31.75 lsb 011 gain compensation data6 to data0: channel i/q (q is matched to i) code 11111111b: -0.315 db code 10000000b: 0 db code 0000000b: 0 db code 0111111b: 0.315 db steps: 0.005 db data6: sign bit 100 internal settling adjustment (isa) data2 to data0: channel i data5 to data3: channel q data15 to data6: 1000010000
36 at84ad004 5390a?bdc?06/04 notes: 1. the internal settling adjustment could change independentl y of the two analog sampling times (ta channels i and q) of t he sample/hold (with a fixed digital sampling time) with steps of 50 ps: nominal mode will be given by data2?data0 = 100 or data5?data3 = 100. data5?data3 = 000 or data2?data0 = 000: sampling time is -200 ps compared to nominal. data2?data0 = 111 or data5?data3 = 111: sampling time is 150 ps compared to nominal. we recommend setting the isa to -50 ps to optimize the adc?s dynamic performances. 2. the fine sampling delay adjustment enables you to change the sampling time (steps of 5 ps) on channel q more pre- cisely, particularly in the interleaved mode. 3. the ?s/h transparent? mode (address 101, data4) enables by passing of the adc?s track/hold. this function optimizes the adc?s performances at very low input frequencies (fin < 50 mhz). 4. in the gray mode, when the input signal is overflow (that is , the differential analog input is greater than 250 mv), the outp ut data must be corrected using the output doir: if doir = 1: data7 unchanged data6 = 0, data5 = 0, dat a4 = 0, data3 = 0, data2 = 0, data1 = 0, data0 = 0. in 1:2 dmux mode, only one out-of-range bit is provided for both a and b ports. 101 testability data3 to data0 = 0000 mode s/h transparent off: data4 = 0 on: data4 = 1 data7 = 0 data8 = 0 110 built-in test (bit) data0 = 0 bit inactive data0 = 1 bit active data1 = 0 static bit data1 = 1 dynamic bit if data1 = 1, then ports bi & bq = rising ramp ports ai & aq = decreasing ramp if data1 = 0, then data2 to data9 = static data for bit ports bi & bq = data2 to data9 ports ai & aq = no t (data2 to data9) 111 data ready delay adjust (drda) data2 to data0: clock i data5 to data3: clock q steps: 140 ps 000: -560 ps 100: 0 ps 111: 420 ps fine sampling delay adjustment (fisda) on channel q data10 to data6: channel q steps: 5 ps data4: sign bit code 11111: -75 ps code 10000: 0 ps code 00000: 0 ps code 01111: 75 ps table 10. 3-wire serial interface address setting description (continued) address setting
37 at84ad004 5390a?bdc?06/04 table 11. 3-wire serial interface data setting description setting for address: 000 d15 d14 d13 d12 d11 d10 d9 (1) d8 d7 d6 d5 d4 d3 d2 d1 d0 full standby mode xxxxxx 0 xxxxxxx11 standby channel i (2) xxxxxx 0 xxxxxxx01 standby channel q (3) xxxxxx 0 xxxxxxx10 no standby mode xxxxxx 0 xxxxxxx00 binary output mode xxxxxx 0 xxxxxx1xx gray output mode xxxxxx 0 xxxxxx0xx dmux 1:2 mode xxxxxx 0 xxxxx1xxx dmux 1:1 mode xxxxxx 0 xxxxx0xxx analog selection mode input i adc i input q adc q xxxxxx 0 xxx11xxxx analog selection mode input i adc i input i adc q xxxxxx 0 xxx10xxxx analog selection mode input q adc i input q adc q xxxxxx 0 xxx0xxxxx clock selection mode clki adc i clkq adc q xxxxxx 0 x11xxxxxx clock selection mode clki adc i clki adc q xxxxxx 0 x10xxxxxx clock selection mode clki adc i clkin adc q xxxxxx 0 x0xxxxxxx decimation off modexxxxxx 0 0xxxxxxxx decimation on mode xxxxxx 0 1xxxxxxxx keep last calibration calculated value (4) no calibration phase xxxx0 1 0 xxxxxxxxx no calibration phase (5) no calibration value xxxx0 0 0 xxxxxxxxx start a new calibration phase xxxx1 1 0 xxxxxxxxx
38 at84ad004 5390a?bdc?06/04 notes: 1. d9 must be set to ?0? 2. mode standby channel i: use analog input i vini, vinib and clocki. 3. mode standby channel q: use analog input q vinq, vinqb and clockq. 4. keep last calibration calculated value - no calibration phase: d11 = 0 and d10 = 1. no new calibration is required. the val- ues taken into account for the gain and offset are either from the last calibration phase or ar e default values (reset values). 5. no calibration phase - no calibration value: d11 = 0 and d10 = 0. no new calibration phase is required. the gain and offset compensation functions can be accessed externally by writing in the registers at address 010 for the offset compensation and at address 011 for the gain compensation. 6. the control wait bit gives the possibility to change the internal setting for the auto-calibration phase: for high clock rates (= 500 msps) use a = b = 1. for clock rates > 250 msps and < 500 msps use a = 1 and b = 0. for clock rates > 125 msps and < 250 msps use a = 0 and b = 1. for low clock rates < 125 msps use a = 0 and b = 0. 3-wire serial interface timing description the 3-wire serial interface is a synchronous write-only serial interface made of three wires: sclk: serial clock input sldn: serial load enable input sdata: serial data input the 3-wire serial interface gives write-only ac cess to as many as 8 different internal reg- isters of up to 16 bits each. the input format is always fixed with 3 bits of register address followed by 16 bits of data. the data and address are entered with the most significant bit (msb) first. the write procedure is fully synchronous with the rising clock edge of ?sclk? and described in the write chronogram (figure 39 on page 39). ?sldn? and ?sdata? are sampled on each rising clock edge of ?sclk? (clock cycle). ?sldn? must be set to 1 when no write procedure is performed. a minimum of one rising clock edge (clock cycle) with ?sldn? at 1 is required for a correct start of the write procedure. a write starts on the first clock cycle with ?sldn? at 0. ?sldn? must stay at 0 during the complete write procedure. during the first 3 clock cycles with ?sldn? at 0, 3 bits of the register address from msb (a[2]) to lsb (a[0]) are entered. during the next 16 clock cycles with ?sldn? at 0, 16 bits of data from msb (d[15]) to lsb (d[0]) are entered. an additional clock cycle with ?sldn? at 0 is required for parallel transfer of the serial data d[15:0] into the addressed register with address a[2:0]. this yields 20 clock cycles with ?sldn? at 0 for a normal write procedure. control wait bit calibration (6) x x a b x x 0 xxxxxxxxx in 1:2 dmux fdataready i & q = fs/2 x 0 x x x x 0 xxxxxxxxx in 1:2 dmux fdataready i & q = fs/4 x 1 x x x x 0 xxxxxxxxx table 11. 3-wire serial interface data setting description (continued) setting for address: 000 d15 d14 d13 d12 d11 d10 d9 (1) d8 d7 d6 d5 d4 d3 d2 d1 d0
39 at84ad004 5390a?bdc?06/04 a minimum of one clock cycle with ?sldn? returned at 1 is requested to close the write procedure and make the interface ready for a new write procedure. any clock cycle where ?sldn? is at 1 before the write procedure is completed interrupts this procedure and no further data transfer to the internal registers is performed. additional clock cycles with ?sldn? at 0 after the parallel data transfer to the register (done at the 20th consecutive clock cycle with ?sldn? at 0) do not affect the write procedure and are ignored. it is possible to have only one clock cycle wi th ?sldn? at 1 between two following write procedures. 16 bits of data must always be entered even if the internal addressed register has less than 16 bits. unused bits (usually m sbs) are ignored. bit signification and bit positions for the internal registers are detailed in table 10 on page 35. to reset the registers, the pin mode can be used as a reset pin for chip initialization, even when the 3-wire serial interface is used. figure 39. write chronogram figure 40. timing definition reset write procedure a[2] a[1] a[0] d[15] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] 12 345 1314151617181920 reset setting mode sclk sldn sdata internal register value new d mode sclk sldn sdata twlmode tdmode tssldn tssdata thsldn thsdata tdmode twsclk tsclk
40 at84ad004 5390a?bdc?06/04 calibration description the at84ad004 offers the poss ibility of reducing of fset and gain matching between the two adc cores. an internal digital calibration may start right after the 3-wire serial inter - face has been loaded (using data d12 of the 3-wire serial interface with address 000). the beginning of calibration disables the two adcs and a standard data acquisition is performed. the output bit cal goes to a high level during the entire calibration phase. when this bit returns to a low level, the two adcs are calibrated with offset and gain and can be used again for a standard data acquisition. if only one channel is selected (i or q) the offset calibration duration is divided by two and no gain calibration between the two channels is necessary. figure 41. internal timing calibration the tcal duration is a multiple of the clock frequency clocki (master clock). even if a dual clock scheme is used during calibration, clockq will not be used. the control wait bits (d13 and d14) give the possibility of changing the calibration?s set - ting depending on the clock?s frequency: for high clock rates (= 500 msps) use a = b = 1, tcal = 10112 clock i periods. for clock rates > 250 msps and < 500 msps use a = 1, b = 0, tcal = 6016 clock i periods. for clock rates > 125 msps and < 250 msps use a = 0, b = 1 ,tcal = 3968 clock i periods. for low clock rates (< 125 msps) use a = 0, b = 0 , tcal = 2944 clock i periods. table 12. timing description name parameter value unit min typ max tsclk sclk period 20 ns twsclk high or low time of sclk 5 ns tssldn setup time of sldn before rising edge of sclk 4 ns thsldn hold time of sldn after rising edge of sclk 2 ns tssdata setup time of sdata before rising edge of sclk 4 ns thsdata hold time of sdata after rising edge of sclk 2 ns twlmode minimum low pulse width of mode 5 ns tdmode minimum delay between an edge of mode and the rising edge of sclk 10 ns 3-wire serial interface ldn cal tcal
41 at84ad004 5390a?bdc?06/04 the calibration phase is necessary when using the at84ad004 in interlace mode, where one analog input is sampled at both adc cores on the common input clock?s ris - ing and falling edges. this operation is equiv alent to converting the analog signal at twice the clock frequency during the adc?s auto-calibra tion phase, the dual adc is set with the following: decimation mode on 1:1 dmux mode binary mode any external action applied to any signal of the adc?s registers is inhibited during the calibration phase. gain and offset compensation functions it is also possible for the user to have exte rnal access to the adc?s gain and offset com- pensation functions: offset compensation between i and q channels (at address 010) gain compensation between i and q channels (at address 011) to obtain manual access to these two functions, which are used to set the offset to mid- dle code 127.5 and to match the gain of channel q with that of channel i (if only one channel is used, the gain compensation does not apply), it is necessary to set the adc to ?manual? mode by writing 0 at bits d11 and d10 of address 000. built-in test (bit) a built-in test (bit) function is available to allow rapid testing of the device?s i/o by either applying a defined static pattern to the adc or by generating a dynamic ramp at the adc?s output. this function is controlled via the 3-wire bus interface at address 101. the bit is active when data0 = 1 at address 110. the bit is inactive when data0 = 0 at address 110. the data1 bit allows choosing between static mode (data1 = 0) and dynamic mode (data1 = 1). when the static bit is selected (data1 = 0), it is possible to write any 8-bit pattern by defining the data9 to data2 bits. port b then outputs an 8-bit pattern equal to data9 ... data2, and port a outputs an 8-bit pattern equal to not (data9 ... data2) . table 13. matching between channels parameter value unit min typ max gain error (single channel i or q) without calibration 0 lsb gain error (single channel i or q) with calibration -0.5 0 0.5 lsb offset error (single channel i or q) without calibration 0 lsb offset error (single channel i or q) with calibration -0.5 0 0.5 lsb mean offset code without calibr ation (single channel i or q) 127.5 mean offset code with calibration (single channel i or q) 127 127.5 128
42 at84ad004 5390a?bdc?06/04 example: address = 110 data = one should then obtain 01010101 on port b and 10101010 on port a. when the dynamic mode is chosen (data1 = 1) port b outputs a rising ramp while port a outputs a decreasing one. note: in dynamic mode, use the drda function to align the edges of clko with the middle of the data. decimation mode the decimation mode is provided to enable rapid testing of the adc. in decimation mode, one data out of 16 is output, thus leading to a maximum output rate of 31.25 msps. note: frequency (clko) = frequency (data) = frequency (clki)/16. die junction temperature monitoring function a die junction temperature measurement setting is included on the board for junction temperature monitoring. the measurement method forces a 1 ma current into a diode-mounted transistor. caution should be given to respecting the polarity of the current. in any case, one should make sure the maximum voltage compliance of the current source is limited to a maximum of 1v or use a resistor serial-mounted with the current source to avoid damaging the transistor device (this may occur if the current source is reverse-connected). the measurement setup is illustrated in figure 42. figure 42. die junction temperature monitoring setup d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxx 0101010101 1 ma gndd (pin 36) vdiode (pin 35) protection diodes
43 at84ad004 5390a?bdc?06/04 the vbe diode?s forward voltage in relation to the junction temper ature (in steady-state conditions) is shown in figure 43. figure 43. diode characteristics versus t j vtesti, vtestq vtesti and vtestq pins are for internal test use only. these two signals must be left open. equivalent input/output schematics figure 44. simplified input clock model 620 640 660 680 700 720 740 760 780 800 820 840 860 -20-100 102030405060708090100110120 junction temperature (c) diode voltage ( mv) vccd/2 100 vccd gndd clk clkb 100 50 50
44 at84ad004 5390a?bdc?06/04 figure 45. simplified data read y reset buffer model figure 46. analog input model vccd/2 100 vccd gndd ddrb ddrbn 100 50 50 gnd gnd vcca gnd vcca sel input i gnd vini vinq sel input q vinq reverse termination 50 esd esd vinq double pad vini double pad dc coupling (common mode = ground = 0v) gnd ? 0.4v max 50 vinl reverse termination
45 at84ad004 5390a?bdc?06/04 figure 47. data output buffer model definitions of terms vcco gndo doaio, doai7 dobio, dobi7 doaion, doai7n dobion, dobi7n table 14. definitions of terms abbreviation definition description ber bit error rate the probability of exceeding a specified error threshold for a sample at a maximum specified sampling rate. an error code is a code that differs by more than 4 lsb from the correct code dnl differential non-linearity the differential non-linearity for an output c ode i is the difference between the measured step size of code i and the ideal lsb step size. dnl (i) is expressed in lsbs. dnl is the maximum value of all dnl (i). a dnl error sp ecification of less than 1 lsb guarantees that there are no missing output codes and th at the transfer function is monotonic enob effective number of bits where a is the actual input amplitude and fs is the full scale range of the adc under test fpbw full power input bandwidth the analog input frequency at which the fu ndamental component in the digitally reconstructed output waveform has fallen by 3 db with respect to its low frequency value (determined by fft analysis) for input at full-scale -1 db (-1 dbfs) imd inter-modulation distortion the two tones intermodulation distortion (imd) reje ction is the ratio of either of the two input tones to the worst third order intermodulation products inl integral non-linearity the integral non-linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. inl (i) is expressed in lsbs and is the maximum value of all |inl (i)| jitter aperture uncertainty the sample-to-sample variation in aperture delay. the voltage error due to jitters depends on the slew rate of the signal at the sampling point npr noise power ratio the npr is measured to characterize the adc?s performance in response to broad bandwidth signals. when applying a notch-filtered broadband white noise signal as the input to the adc under test, the noise power ratio is defined as the ratio of the average out-of- notch to the average in-notch power spectral density magnitudes for the fft spectrum of the adc output sample test enob sinad 1.76 ? 20 a fs /2 ----------- log + 6.02 ----------------------------------------------------------------------------- =
46 at84ad004 5390a?bdc?06/04 ort overvoltage recovery time the time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on the input is reduced to midscale psrr power supply rejection ratio the ratio of input offset variation to a change in power supply voltage sfdr spurious free dynamic range the ratio expressed in db of the rms signal amplitude, set at 1 db below full-scale, to the rms value of the highest spectral component (peak spurious spectral component). the peak spurious component may or may not be a harmonic. it may be reported in db (related to the converter -1 db full-scale) or in dbc (related to the input signal level) sinad signal to noise and distortion ratio the ratio expressed in db of the rms signal amplitude, set to 1 db below full-scale (-1 dbfs) to the rms sum of all other spectral co mponents including the harmonics, except dc snr signal to noise ratio the ratio expressed in db of the rms signal amplitude, set to 1 db below full-scale, to the rms sum of all other spectral com ponents excluding the first 9 harmonics ssbw small signal input bandwidth the analog input frequency at which the fu ndamental component in the digitally reconstructed output waveform has fallen by 3 db with respect to its low frequency value (determined by fft analysis) for input at full-scale -10 db (-10 dbfs) ta aperture delay the delay between the rising edge of the differential clock inputs (clk, clkb) [zero crossing point] and the time at which vin and vinb are sampled tc encoding clock period tc1 = minimum clock pulse width (high) tc = tc1 + tc2 tc2 = minimum clock pulse width (low) td1 time delay from data transition to data ready the general expression is td1 = tc1 + tdr - tdo with tc = tc1 + tc2 = 1 encoding clock period td2 time delay from data ready to data the general expression is td2 = tc2 + tdr - tdo with tc = tc1 + tc2 = 1 encoding clock period tdo digital data output delay the delay from the rising edge of the differential clock inputs (clk, clkb) [zero crossing point] to the next point of change in the di fferential output data (zero crossing) with a specified load tdr data ready output delay the delay from the falling edge of the differential clock inputs (clk, clkb) [zero crossing point] to the next point of change in the di fferential output data (zero crossing) with a specified load tf fall time the time delay for the output data signals to fall from 20% to 80% of delta between the low and high levels thd total harmonic distortion the ratio expressed in db of the rms sum of the first 9 harmonic components to the rms input signal amplitude, set at 1 db below full-scale. it may be reported in db (related to the converter -1 db full-scale) or in dbc (related to the input signal level ) tpd pipeline delay the number of clock cycles between the sampli ng edge of an i nput data and the associated output data made available (not taking into account the tdo) tr rise time the time delay for the output data signals to rise from 20% to 80% of delta between the low and high levels table 14. definitions of terms (continued) abbreviation definition description
47 at84ad004 5390a?bdc?06/04 trdr data ready reset delay the delay between the falling edge of the data ready output asynchronous reset signal (ddrb) and the reset to digital zero transition of the data ready output signal (dr) ts settling time the time delay to rise from 10% to 90% of the converter output when a full-scale step function is applied to the differential analog input vswr voltage standing wave ratio the vswr corresponds to the adc input insertion loss due to input power reflection. for example, a vswr of 1.2 corresponds to a 20 db return loss (99% power transmitted and 1% reflected) table 14. definitions of terms (continued) abbreviation definition description
48 at84ad004 5390a?bdc?06/04 using the at84ad004 dual 8-bit 500 msps adc decoupling, bypassing and grounding of power supplies the following figures show the re commended bypassing, decoupling and grounding schemes for the dual 8-bit 500 msps adc power supplies. figure 48. v ccd and v cca bypassing and grounding scheme figure 49. v cco bypassing and grounding scheme note: l and c values must be chosen in accordan ce with the operating frequency of the application. figure 50. power supplies decoupling scheme note: the bypassing capacitors (1 f and 100 pf) should be plac ed as close as possible to the board connectors, whereas the decoupling capacitors (100 pf and 10 nf) should be placed as close as possible to the device. 1 f l pc board 3.3v pc board gnd vccd l c c vcca 100 pf 1 f l pc board 2.25v pc board gnd vcco c 100 pf vcca gnda vcco gndo gnda gndd gndo vccd vcca vcco 100 pf 100 pf 10 nf 10 nf 100 pf 10 nf
49 at84ad004 5390a?bdc?06/04 analog input implementation the analog inputs of the dual adc have been designed with a double pad implementa- tion as illustrated in figure 51 . the reverse pad for each input should be ti ed to ground via a 50 resistor. the analog inputs must be used in differential mode only. figure 51. termination method for the adc analog inputs in dc coupling mode channel i channel q 50 source vini vinib vinq vinqb vini vinib vinq vinqb dual adc 50 50 50 50 gnd gnd 50 source gnd gnd
50 at84ad004 5390a?bdc?06/04 figure 52. termination method for the adc analog inputs in ac coupling mode clock implementation the adc features two different clocks (i or q) that must be implemented as shown in figure 53. each path must be ac coupled with a 100 nf capacitor. figure 53. differential termination method for clock i or clock q note: when only clock i is used, it is not necessary to add the capacitors on the clkq and clkqn signal paths; they may be left floating. channel i channel q 50 source vini vinib vinq vinqb vini vinib vinq vinqb dual adc 50 50 50 50 gnd gnd 50 source gnd gnd adc package vccd/2 50 50 100 nf 100 nf differential buffer clk clkb
51 at84ad004 5390a?bdc?06/04 figure 54. single-ended termination method for clock i or clock q output termination in 1:1 ratio when using the integrated dmux in 1:1 ratio, the valid port is port a. port b remains unused. port a functions in lvds mode and the corresponding outputs (doai or doaq) have to be 100 differentially terminated as shown in figure 55 on page 52. the pins corresponding to port b (dobi or dobq pins) must be left floating (in high impedance state). figure 55 on page 52 is an example of a 1:1 ratio of the integrated dmux for channel i (the same applies to channel q). clk clkb 50 50 vccd r1 r2 vccd/2 ac coupling capacitor ac coupling capacitor 50 source 50
52 at84ad004 5390a?bdc?06/04 figure 55. example of termination for channel i us ed in dmux 1:1 ratio (port b unused) note: if the outputs are to be used in single-ended mode, it is re commended that the true and fa lse signals be terminated with a 50 resistor. using the dual adc with and asic/fpga load figure 56 on page 53 illustrate s the configuration of the dual adc (1:2 dmux mode, independent i and q clocks) dr iving an lvds system (asic/fpga) with potential addi- tional dmuxes used to halve the speed of the dual adc outputs. port b dobi0 / dobi0n dobi1 / dobi1n dobi2 / dobi2n dobi3 / dobi3n dobi4 / dobi4n dobi5 / dobi5n dobi6 / dobi6n dobi7 / dobi7n floating (high z) port a doai0 / doai0n doai1 / doai1n doai2 / doai2n doai3 / doai3n doai4 / doai4n doai5 / doai5n doai6 / doai6n doai7 / doai7n vcco doai0 doai0n z0 = 50 z0 = 50 100 lvds in lvds in dual adc package
53 at84ad004 5390a?bdc?06/04 figure 56. dual adc and asic/fpga load block diagram note: the demultiplexers may be in ternal to the asic/fpga system. port a channel i port a channel q port b channel i port b channel q demux 8:16 dmux 8:16 dmux 8:16 dmux 8:16 clki/clkin @ fsi clkq/clkqn @ fsq data rate = fsq/2 data rate = fsi/2 data rate = fsq/4 asic / fpga dual 8-bit 1 gsps adc
54 at84ad004 5390a?bdc?06/04 thermal characteristics simplified thermal model for lqfp 144 20 x 20 x 1.4 mm the following model has been extracted from the ansys fem simulations. assumptions: no air, no convection and no board. figure 57. simplified thermal mo del for lqfp package note: the above are typical values with an assumption of uniform power dissipation over 2.5 x 2.5 mm 2 of the top surface of the die. thermal resistance from junction to bottom of leads assumptions: no air, no convection and no board. the thermal resistance from the junction to the bottom of the leads is 15.2 c/w typical. thermal resistance from junction to top of case assumptions: no air, no convection and no board. the thermal resistance from the junction to the top of the case is 8.3 c/w typical. thermal resistance from junction to bottom of case assumptions: no air, no convection and no board. the thermal resistance from the junction to the bottom of the case is 6.4 c/w typical. thermal resistance from junction to bottom of air gap the thermal resistance from the junction to the bottom of the air gap (bottom of pack- age) is 17.9 c/w typical. 355 m silicon die 25 mm = 0.95w/cm/c 40 m epoxy/ag glue = 0. 02 w/ cm/ c copper paddle = 2.5w/cm/c aluminium paddle = 0. 75w/ cm/ c copper alloy leadframe package top 5.5c/watt 0.1c/watt 11.4c/watt package bottom 4.3c/watt 1.5c/watt = 0.007w/cm/c silicon junction 0.6c/watt 8.3c/watt 1.4c/watt 0.1c/watt 6.1c/watt 1.5c/watt leads tip assumptions: die 5.0 x 5.0 = 25 mm 40 m thick epoxy/ag glue 2 top of user board package bottom connected to: (user dependent) resin bottom = 0.007w/cm/ c 2 aluminium paddle resin resin = 0.007w/cm/c = 25w/cm/c 100 m air gap = 0.00027w/cm/ c 100 m thermal grease gap diamater 12 mm = 0.01w/cm/ c
55 at84ad004 5390a?bdc?06/04 thermal resistance from junction to ambient the thermal resistance from the junction to ambient is 25.2 c/w typical. note: in order to keep the ambient temperature of the die within the sp ecified limits of the device grade (that is t a max = 70c in commercial grade and 85c in industrial grade) and the die junction temperature below the maximum allowed junction temperature of 105c, it is necessary to operate the dual adc in air flow conditions (1m/s recom- mended). in still air conditions, the junction temper ature is indeed greater than the maximum allowed t j . - t j = 25.2c/w x 1.4w + t a = 35.28 + 70 = 105.28c for commercial grade devices - t j = 25.2c/w x 1.4w + t a = 35.28 + 85 = 125.28c for industrial grade devices thermal resistance from junction to board the thermal resistance from the junction to the board is 13 c/w typical.
56 at84ad004 5390a?bdc?06/04 ordering information part number package temperature range screening comments at84xad004td lqfp 144 ambient prototype prototype version please contact your local atmel sales office at84ad004ctd lqfp 144 c grade 0c < ta < 70c standard AT84AD004VTD lqfp 144 v grade -40c < ta < 85c standard at84ad004td-eb lqfp 144 ambient prototype evaluation kit
57 at84ad004 5390a?bdc?06/04 packaging information figure 58. package type note: thermally enhanced package: lqfp 144, 20 x 20 x 1.4 mm. d a1 a2 a c c 0.25 0.17 max lead coplanarity seating plane stand off a 1 b l ccc c ddd e c a-b e d e 6 o + - 4 o 0 0.20 rad max. 0.20 rad nom. a e 12 o typ. 12 o typ. e1 n 1 e b d d1 a notes: 1. all dimensions are in millimeters 2. dimensions shown are nominal with tolerances as indicated 3. l/f: eftec 64t copper or equivalent 4. foot length: "l" is measured at gauge plane at 0.25 mm above the seating plane dims. tols. leads 144l a max. 1.60 a1 0.05 min./0.15 max. a2 +/- 0.05 1.40 d +/-0.20 22.00 d1 +/-0.10 20.00 e +/-0.20 22.00 e1 +/-0.10 20.00 l +0.15/-0.10 0.60 e basic 0.50 b +/-0.05 0.22 ddd 0.08 ccc max. 0.08 o 0 - 5 o o body +2.00 mm footprint
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