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ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 16 features ? 144-pin jedec standard, 8-byte small outline dual-in-line memory module ? 16mx64 synchronous dram so dimm ?low power ? performance: ? inputs and outputs are lvttl (3.3v) compatible ? single 3.3v 0.3v power supply ? single pulsed ras interface ? sdrams have 4 internal banks ? module has 2 physical banks ? fully synchronous to positive clock edge ? data mask for byte read/write control ? programmable operation: - cas latency: 2, 3 - burst type: sequential or interleave - burst length: 1, 2, 4, 8, full-page (full- page supports sequential burst only) - operation: burst read and write or multiple burst read with single write ? auto refresh (cbr) and self refresh ? automatic and controlled precharge commands ? suspend mode and power down mode ? 12/9/2 addressing (row/column/bank) ? 4096 refresh cycles distributed across 64ms ? serial presence detect ? card size: 2.66" x 1.15" x 0.149" ? gold contacts ? sdram s in tsop type ii package description ibm13t16644npa is a 144-pin synchronous dram small outline dual in-line memory module (so dimm) which is organized as a 16mx64 high-speed memory array and is configured as two 8mx64 phys- ical banks. the so dimm uses eight 8mx16 sdrams in 400mil tsop ii packages. the so dimm achieves high speed data transfer rates of up to 100mhz by employing a prefetch/pipeline hybrid architecture that supports the jedec 1n rule while allowing very low burst power. the so dimm is intended to comply with all jedec standards set for 144-pin sdram so dimms. all control, address, and data input/output circuits are synchronized with the positive edge of the exter- nally supplied clock inputs. all inputs are sampled at the positive edge of each externally supplied clock (ck0, ck1). internal oper- ating modes are defined by combinations of the ras, cas, we, s0, s1, dqmb, and cke0, cke1 signals. a command decoder initiates the necessary timings for each operation. a 12-bit address bus accepts address information in a row/column multi- plexing arrangement. prior to any access operation, the cas latency, burst type, burst length, and burst operation type must be programmed into the so dimm by address inputs a0-a9 during the mode register set cycle. the so dimm uses serial presence detects imple- mented via a serial eeprom using the two pin iic protocol. the first 128 bytes of serial pd data are used by the dimm manufacturer. the last 128 bytes are available to the customer. all ibm 144-pin so dimms provide a high perfor- mance, flexible 8-byte interface in a 2.66" long space-saving footprint. -10 units cas latency 3 f ck clock frequency 100 mhz t ck clock cycle 10 ns t ac clock access time 9 ns .
ibm13t16644npa 16m x 64 two bank sdram so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 16 06k2331.h00961 11/99 card outline pin description ck0, ck1 clock inputs dq0 - dq63 data input/output cke0, cke1 clock enable dqmb0 - dqmb7 data mask ras row address strobe v dd power (3.3v) cas column address strobe v ss ground we write enable nc no connect s0, s1 chip selects scl serial presence detect clock input a0 - a9, a11 address inputs sda serial presence detect data input/output a10/ap address input/auto-precharge sa0-2 serial presence detect address inputs ba0 - ba1 sdram bank address pinout pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side 1v ss 2v ss 37 dq8 38 dq40 71 s1 72 nc 107 v ss 108 v ss 3 dq0 4 dq32 39 dq9 40 dq41 73 du 74 ck1* 109 a9 110 ba1 5 dq1 6 dq33 41 dq10 42 dq42 75 v ss 76 v ss 111 a10/ap 112 a11 7 dq2 8 dq34 43 dq11 44 dq43 77 nc 78 nc 113 v dd 114 v dd 9 dq3 10 dq35 45 v dd 46 v dd 79 nc 80 nc 115 dqmb2 116 dqmb6 11 v dd 12 v dd 47 dq12 48 dq44 81 v dd 82 v dd 117 dqmb3 118 dqmb7 13 dq4 14 dq36 49 dq13 50 dq45 83 dq16 84 dq48 119 v ss 120 v ss 15 dq5 16 dq37 51 dq14 52 dq46 85 dq17 86 dq49 121 dq24 122 dq56 17 dq6 18 dq38 53 dq15 54 dq47 87 dq18 88 dq50 123 dq25 124 dq57 19 dq7 20 dq39 55 v ss 56 v ss 89 dq19 90 dq51 125 dq26 126 dq58 21 v ss 22 v ss 57 nc 58 nc 91 v ss 92 v ss 127 dq27 128 dq59 23 dqmb0 24 dqmb4 59 nc 60 nc 93 dq20 94 dq52 129 v dd 130 v dd 25 dqmb1 26 dqmb5 voltage key 95 dq21 96 dq53 131 dq28 132 dq60 27 v dd 28 v dd 61 ck0 62 cke0 97 dq22 98 dq54 133 dq29 134 dq61 29 a0 30 a3 63 v dd 64 v dd 99 dq23 100 dq55 135 dq30 136 dq62 31 a1 32 a4 65 ras 66 cas 101 v dd 102 v dd 137 dq31 138 dq63 33 a2 34 a5 67 we 68 cke1 103 a6 104 a7 139 v ss 140 v ss 35 v ss 36 v ss 69 s0 70 nc 105 a8 106 ba0 141 sda 142 scl 143 v dd 144 v dd ordering information part number organization clock cycle leads dimension power IBM13T16644NPA-10T 16mx64 10ns gold 2.66" x 1.15" x 0.149" 3.3v 1 143 (front) (back) 2 59 60 61 62 144
ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 16 block diagram we s0 cs we d5 s1 cs we d7 cs we d4 cs we d6 dq48 dq49 dq50 dq51 cs we d3 dqmb6 dq52 dq53 dq54 dq55 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmb7 dq56 dq32 dq33 dq34 dq35 cs we d2 dqmb4 dq36 dq37 dq38 dq39 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmb5 dq40 dq16 dq17 dq18 dq19 cs we d1 dqmb2 dq20 dq21 dq22 dq23 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmb3 dq24 dq0 dq1 dq2 dq3 cs we d0 dqmb0 dq4 dq5 dq6 dq7 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb1 dq8 v dd v ss d0-d7 d0-d7 a0 - a11 a0-a11: sdram s d0 - d7 ras ras: sdram s d0 - d7 cas cas: sdram s d0 - d7 cke0 cke: sdram s d0 - d3 * clock wiring *ck0 clock input sdram s *ck1 4 sdram s a0 serial pd a1 a2 scl sda cke1 cke: sdram s d4 - d7 4 sdram s ba0 ba0-ba1: sdrams d0 - d3
ibm13t16644npa 16m x 64 two bank sdram so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 16 06k2331.h00961 11/99 input/output functional description symbol type signal polarity function ck0, ck1 input pulse positive edge cke0, cke1 input level active high activates the ck0 and ck1 signals when high and deactivates them when low. by deactivating the clocks, cke0 low initiates the power down mode, suspend mode, or the self refresh mode. s0, s1 input pulse active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras, cas we input pulse active low when sampled at the positive rising edge of the clock, ras, cas, and we define the operation to be executed by the sdram. ba0, ba1 input level selects which sdram bank is to be active. a0 - a9, a11 a10/ap input level during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11), when sampled at the rising clock edge. during a read or write command cycle, a0-a8 defines the column address (ca0-ca8), when sampled at the rising clock edge. in addition to the column address, ap is used to invoke auto-precharge operation at the end of the burst read or write cycle. if ap is high, auto-precharge is selected and ba0 defines the bank to be precharged (low=bank a, high=bank b). if ap is low, auto-precharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0 to control which bank(s) to precharge. if ap is high, both bank a and bank b will be precharged regard- less of the state of ba0. if ap is low, then ba0 is used to define which bank to precharge. dq0 - dq63 input output level data input/output pins operate in the same manner as on conventional drams. dqmb0 - dqmb7 input pulse active high the data input/output mask places the dq buffers in a high impedance state when sam- pled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a byte mask by allowing input data to be written if it is low, but blocks the write operation if dqm is high. sda input output level serial data. bidirectional signal used to transfer data into and out of the serial presence detect eeprom. since the sda signal is open drain/open collector at the eeprom, a pull-up resistor is required on the system board. scl input pulse serial clock. used to clock all serial presence detect data into and out of the eeprom. since the scl signal is inactive in the high state, a pull-up resistor is recommended on the system board. v dd , v ss supply power and ground for the module.
ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 16 serial presence detect (part 1 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram 04 3 number of row addresses on assembly 12 0c 4 number of column addresses on assembly 9 09 5 number of dimm banks 2 02 6 - 7 data width of assembly x64 4000 8 voltage interface level of this assembly lvttl 01 9 sdram device cycle time at cl=3 10.0ns a0 10 sdram device access time from clock at cl=3 7.0ns 70 11 dimm configuration type non-parity 00 12 refresh rate/type sr/1x(15.625us) 80 13 primary sdram device width x16 10 14 error checking sdram device width n/a 00 15 sdram device attributes: min clk delay, random col access 1 clock 01 16 sdram device attributes: burst lengths supported 1, 2, 4, 8, full page 8f 17 sdram device attributes: number of device banks 4 04 18 sdram device attributes: cas latencies supported 2, 3 06 19 sdram device attributes: cs latency 0 01 20 sdram device attributes: we latency 0 01 21 sdram module attributes unbuffered 00 22 sdram device attributes: general wr-1/rd burst, precharge all, auto-precharge, v dd 10% 0e 23 minimum clock cycle at cl=2 15.0ns f0 24 maximum data access time (t ac ) from clock at cl=2 8.0ns 80 25 minimum clock cycle time at cl=1 n/a 00 26 maximum data access time (t ac ) from clock at cl=1 n/a 00 27 minimum row precharge time (t rp ) 30ns 1e 1. cc = checksum data byte, 00-ff (hex) 2. r = alphanumeric revision code, a-z, 0-9 3. rr = ascii coded revision code byte r 4. yy = binary coded decimal year code, 00-99 (decimal) 00-63 (hex) 5. ww = binary coded decimal week code, 01-52 (decimal) 01-34 (hex) 6. ss = serial number data byte, 00-ff (hex)
ibm13t16644npa 16m x 64 two bank sdram so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 16 06k2331.h00961 11/99 28 minimum row active to row active delay (t rrd ) 20ns 14 29 minimum ras to cas delay (t rcd ) 30ns 1e 30 minimum ras pulse width (t ras ) 60ns 3c 31 module bank density 64mb 10 32 address and command set-up time before clock 3.0ns 30 33 address and command hold time after clock 1.0ns 10 34 data input set-up time before clock 3.0ns 30 35 data input hold time after clock 1.0ns 10 36 - 61 reserved undefined 00 62 spd revision 2 02 63 checksum for bytes 0 - 62 checksum data cc 1 64 - 71 manufacturers jedec id code ibm a400000000000000 72 module manufacturing location toronto, canada 91 vimercate, italy 53 73 - 90 module part number ascii 13t16644npr-10t 31335431363634344e5 0 rr2d313054202020 2, 3 91 - 92 module revision code r plus ascii blank rr20 93 - 94 module manufacturing date year/week code yyww 4, 5 95 - 98 module serial number serial number ssssssss 6 99 - 125 reserved undefined 00 126 module supports this clock frequency 66mhz 66 127 attributes for clock frequency defined in byte 126 cl 2, 3 concurrent ap 07 128 - 255 available for customer use undefined 00 serial presence detect (part 2 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 1. cc = checksum data byte, 00-ff (hex) 2. r = alphanumeric revision code, a-z, 0-9 3. rr = ascii coded revision code byte r 4. yy = binary coded decimal year code, 00-99 (decimal) 00-63 (hex) 5. ww = binary coded decimal week code, 01-52 (decimal) 01-34 (hex) 6. ss = serial number data byte, 00-ff (hex)
ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 16 absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v 1 v in input voltage sdram devices -0.3 to +4.6 serial pd device -0.3 to +6.5 v out output voltage sdram devices -0.3 to +4.6 serial pd device -0.3 to +6.5 t opr operating temperature 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 16mx64 1.51 w 1, 2 i out short circuit output current 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. power is calculated using i dd1 @ 3.6volt. recommended dc operating conditions (t a = 0 to 70 c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v dd + 0.3 v 1 v il input low voltage -0.3 0.8 v 1 1. all voltages referenced to v ss . capacitance (t a = 25 c, f=1mhz, v dd = 3.3v 0.3v) symbol parameter max capacitance units c i1 input capacitance (a0 - a9, a10/ap, ba0, ras, cas, we) 58 pf c i2 input capacitance (cke, cke1) 28 pf c i3 input capacitance ( s0, s1) 28 pf c i4 input capacitance (ck0, ck1) 32 pf c i5 input capacitance (dqmb0 - dqmb7) 14 pf c i6 input capacitance (scl) 13 pf c input/output capacitance (dq0 - dq63) 17 pf c io2 input/output capacitance (sda) 15 pf
ibm13t16644npa 16m x 64 two bank sdram so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 16 06k2331.h00961 11/99 dc output load circuit output characteristics (t a = 0 to +70?c, v dd = 3.3v 0.3v) symbol parameter 16mx64 units notes min. max. i i(l) input leakage current, any input (0.0v v in v dd ), all other pins not under test = 0v ras, cas, we, cke0, ck0, a0-a9, a10/ap, a11, ba0, ba1 -8 +8 m a s0 -8 +8 s1 -4 +4 dqmb0-7 -2 +2 scl -2 +2 i o(l) output leakage current (d out is disabled, 0.0v v out v dd ) dq0 - 63, sda -2 +2 m a v oh output level (lvttl) output h level voltage (i out = -2.0ma) 2.4 v 1 v ol output level (lvttl) output l level voltage (i out = +2.0ma) 0.4 1. see dc output load circuit. output 1200 w 50pf 3.3v 870 w v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma
ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 16 operating, standby and refresh currents (t a = 0 to +70?c, v dd = 3.3v 0.3v) parameter symbol test condition 16mx64 units notes operating current t rc = t rc (min), t ck = min active-precharge command cycling without burst operation i dd1 1 bank operation 420 ma 1, 3, 4 precharge standby current in power down mode i dd2p cke v il (max), t ck = min, s0, s1 = v ih (min) 8.0 ma 2 i dd2ps cke v il (max), t ck = infinity, s0, s1 = v ih (min) 8.0 ma 2 precharge standby current in non-power down mode i dd2n cke 3 v ih (min), t ck = min, s0, s1 = v ih (min) 280 ma 2, 5 i dd2ns cke 3 v ih (min), t ck = infinity, s0, s1 = v ih (min) 80 ma 2 no operating current (active state: four-bank) i dd3n cke 3 v ih (min), t ck = min, s0, s1 = v ih (min) 320 ma 2, 5 i dd3p cke v il (max), t ck = min, s0, s1 = v ih (min) (power down mode) 80 ma 2 burst operating current i dd4 t ck = min, read/write command cycling 520 ma 1, 4, 5 auto (cbr) refresh current i dd5 t ck = min, cbr command cycling 740 ma 1, 6 self refresh current i dd6 cke0 0.2v 6400 ma 1, 6 serial pd device standby current i sb5 v in = gnd or v dd 30 m a 7 serial pd device active power supply current i cca scl clock frequency = 100khz 1 ma 8 1. the speci?ed values are for one so dimm bank in the speci?ed mode and the other so dimm bank in active standby (i cc3n ). 2. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed once during t ck (min). 3. input signals are changed up to three times during t rc (min). this assumes the 14 row address mode with four-bank operation using rows a0-a11 and ba0-ba1. 4. the speci?ed values are obtained with the outputs open. 5. input signals are changed once during three clock cycles. 6. 64ms refresh time (15.6 m s, 4k refresh). 7. v dd = 3.3v. 8. input pulse levels v dd x 0.1 to v dd x 0.9; input rise and fall times 10ns; input and output timing levels v dd x 0.5; output load 1 ttl gate and cl=100pf.
ibm13t16644npa 16m x 64 two bank sdram so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 16 06k2331.h00961 11/99 ac characteristics (t a = 0 to +70 c, v dd = 3.3v 0.3v) 1. an initial pause of 100 m s is required after power up, then a precharge all banks command must be given, followed by a minimum of two auto (cbr) refresh cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the 1.40v crossover point. 3. the transition time is measured between v ih and v il (or between v il and v ih ). 4. ac measurements assume t t =1ns. 5. in addition to meeting the transition rate speci?cation, the clock and cken must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. ac characteristics diagrams clock and clock enable parameters symbol parameter -10 units notes min. max. t ck3 clock cycle time, cas latency = 3 10 1000 ns t ck2 clock cycle time, cas latency = 2 15 1000 ns 1 t ac3 clock access time, cas latency = 3 9 ns 2 t ac2 clock access time, cas latency = 2 9 ns 2 t ckh clock high pulse width 3 ns 3 t ckl clock low pulse width 3 ns 3 t ces clock enable set-up time 2 ns t ceh clock enable hold time 1 ns t sb power down mode entry time 0 10 ns t t transition time (rise and fall) 0.5 10 ns 1. for 66mhz clock, cas latency = 2. 2. access time is measured at 1.4v. see ac characteristics diagrams . 3. t ckh is the pulse width of ck measured from the positive edge to the negative edge referenced to v ih (min). t ckl is the pulse width of ck measured from the negative edge to the positive edge referenced to v il (max). output input clock t oh t setup t hold t ac t lz 1.4v 0.8v 1.4v 1.4v 2.0v t t output 50pf z o = 50 w ac output load circuit
ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 16 common parameters symbol parameter -10 units notes min. max. t cs command set-up time 3 ns t ch command hold time 1 ns t as address and bank select set-up time 3 ns t ah address and bank select hold time 1 ns t rcd ras to cas delay 30 ns 1 t rc bank cycle time 90 ns 1 t ras active command period 60 100000 ns 1 t rp precharge time 30 ns 1 t rrd bank to bank delay time 20 ns 1 t ccd cas to cas delay time 1 clk 1. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/clock period (fractions counted as whole numbers). mode register set cycle symbol parameter -10 units notes min. max. t rsc mode register set cycle time 2 clk 1 1. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/clock period (fractions counted as whole numbers).
ibm13t16644npa 16m x 64 two bank sdram so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 16 06k2331.h00961 11/99 read cycle symbol parameter -10 units notes min. max. t oh data out hold time 3 ns t lz data out to low impedance time 0 ns t hz3 data out to high impedance time 3 7 ns 1 t hz2 data out to high impedance time 3 8 ns 1 t dqz dqm data out disable latency 2 clk 1. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. refresh cycle symbol parameter -10 units notes min. max. t ref refresh period 64ms 1 t srex self refresh exit time 10 ns 1. 4096 auto refresh cycles. write cycle symbol parameter -10 units min. max. t ds data in set-up time 3 ns t dh data in hold time 1 ns t dpl data input to precharge 10 ns t dqw dqm write mask latency 0 clk
ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 16 clock frequency and latency symbol parameter -10 units f ck clock frequency 100 66 mhz t ck clock cycle time 10 15 ns t aa cas latency 3 2 clk t rp precharge time 3 2 clk t rcd ras to cas delay 3 2 clk t rc bank cycle time 9 6 clk t ras minimum bank active time 6 4 clk t dpl data in to precharge 1 1 clk t dal data in to active/refresh 4 3 clk t rrd bank to bank delay time 2 2 clk t ccd cas to cas delay time 1 1 clk t wl write latency 0 0 clk t dqw dqm write mask latency 0 0 clk t dqz dqm data disable latency 2 2 clk t csl clock suspend latency 1 1 clk presence detect read and write cycle symbol parameter min max unit notes f scl scl clock frequency 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su:sta start condition set-up time (for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in set-up time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition set-up time 4.7 m s t dh data out hold time 300 ns t wr write cycle time 15 ms 1 1. the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resis- tor, and the device does not respond to its slave address.
ibm13t16644npa 16m x 64 two bank sdram so dimm ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 16 06k2331.h00961 11/99 functional description and timing diagrams refer to the ibm 128mb synchronous dram data sheet, document 33l8019, for the functional description and timing diagrams for sdram operation. refer to the ibm application notes: serial presence detect on memory dimms and sdram presence detect definitions for the serial presence detect functional description and timings. all ac timing information refers to the timings at the sdram devices. layout drawing 67.60 2.661 (2x) 0 1.800 .0709 3.30 .1299 63.60 2.504 32.80 1.293 2.00 min .0787 front 4.00 .157 29.21 20.00 1.15 .7874 6.00 .236 23.2 .9134 24.5 .9646 4.60 .1811 2.50 .0984 4.00 0.10 .1575 .0039 1.50 0.10 .0591 .0039 0.60 .05 width .0236 0.80 typ pitch .0315 2.55 .1004 0.25 max 0.009 note: all dimensions are typical unless otherwise stated. millimeters inches 3.80 max 0.1496 side 6.269 1.00 .039 0.10 .0039 .2468 min 16m x 64
ibm13t16644npa 16m x 64 two bank sdram so dimm 06k2331.h00961 11/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 16 revision log rev contents of modi?cation 11/99 initial release
intern ational business machines corp.1999 copyright printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a

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