integrated circuit systems, inc. general description features ICS9159-13 frequency generator and integrated buffer for pentium ? 9159-13 rev b 060497 block diagram the ICS9159-13 generates all clocks required for high speed risc or cisc microprocessor systems such as 486, pentium, powerpc, ? etc. four different reference frequency multiplying factors are externally selectable with smooth frequency transitions. a test mode is provided to drive all clocks directly. high drive bclk outputs provide typically greater than 1v/ns slew rate into 30pf loads. pclk outputs provide typically better than 1v/ns slew rate into 20pf loads while maintaining 505% duty cycle. ? generates up to six processor and six bus clocks, plus two reference clocks ? synchronous clocks skew matched to 250ps window on pclks and 500ps window on bclks ? processor and bus clocks synchronized to each other, pclk to bclk skew window 600ps max ? test clock mode eases system design 3.0v - 5.5v supply range ? 28-pin soic package ? pentium is a trademark of intel corporation. powerpc is a trademark of motorola corporation. pin cnfiguration 28-pin soic oen fs1 fs0 pclk bclk ref 1 0 0 50mhz 25 mhz 14.318 mhz 1 0 1 66.6 mhz 33.3 mhz 14.318 mhz 1 1 0 6 0 mhz 30 mhz 14.318 mhz 1 1 1 tclk/2 tclk/4 tclk 0 x x tristate tristate tristate ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. functionality
2 ICS9159-13 pin descriptions pin number pin name type description 1, 8, 14, 20, 26 vdd pwr power for logic, cpu and fixed frequency output buffers. 2x1 in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 12 - 16 mhz crystal, nominally 14.31818 mhz. 3 x2 out xtal output which includes xtal load capacitance. 4, 11, 17, 23 gnd pwr ground for logic, cpu and fixed frequency output buffers. 6, 7, 9, 10, 24, 25 pclk(0:3) out processor clock outputs which are a multiple of the input reference frequency as shown in the table above. 13, 12 fs(0:1) in frequency multiplier select pins. see table above. these inputs have internal pull-up devices. 15, 16, 18, 19, 21, 22 bclk(0:5) out bus clock outputs are fixed at one half the pclk frequency. 5 oen in oen tristates all outputs when low. this input has an internal pull-up device. 28, 27 ref(0:1) out ref is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 mhz.
3 ICS9159-13 absolute maximum ratings electrical characteristics at 3.3v supply v oltage .......................................................................................................... 7.0 v logic inputs ....................................................................... gnd ?0.5 v to v dd +0.5 v ambient operating t emperature ............................................................. 0c to +70c storage t emperature ........................................................................... ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il --0.2v dd v input high voltage v ih 0.7v dd --v input low current i il v in =0v -28.0 -10.5 - a input high current i ih v in =v dd -5.0 - 5.0 a output low current 1 i ol v ol =0.8v; for pclks & bclks 30.0 47.0 - ma output high current 1 i oh v ol =2.0v; for pclks & bclks - -66.0 -42.0 ma output low current 1 i ol v ol =0.8v; for ref clks 25.0 38.0 - ma output high current 1 i oh v ol =2.0v; for ref clks - -47.0 -30.0 ma output low voltage 1 v ol i ol =15ma; for pclks & bclks - 0.3 0.4 v output high voltage 1 v oh i oh =-30ma; for pclks & bclks 2.4 2.8 - v output low voltage 1 v ol i ol =12.5ma; for ref clks - 0.3 0.4 v output high voltage 1 v oh i oh =-20ma; for ref clks 2.4 2.8 - v supply current i dd @66.5 mhz; all outputs unloaded - 55 110 ma
4 ICS9159-13 electrical characteristics at 3.3v v dd = 3.1 ? 3.7 v, t a = 0 ? 70 c note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v pclk & bclk - 0.9 1.5 ns fall time 1 t f1 20pf load, 2.0 to 0.8v pclk & bclk - 0.8 1.4 ns rise time 1 t r2 20pf load, 20% to 80% pclk & bclk - 1.5 2.5 ns fall time 1 t f2 20pf load, 80% to 20% pclk & bclk - 1.4 2.4 ns duty cycle 1 d t 20pf load @ vout=1.4v 45 50 55 % jitter, one sigma 1 t j1s1 pclk & bclk clocks; load=20pf, fout>25 mhz - 50 150 ps jitter, absolute 1 t jab1 pclk & bclk clocks; load=20pf, fout>25 mhz -250 - 250 ps jitter, one sigma 1 t j1s2 ref clk; load=20pf - 1 3 % jitter, absolute 1 t jab2 ref clk; load=20pf -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator capacitance 1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1 st crossing of 66.5 mhz v dd supply ramp < 40ms -2.54.5ms frequency settling time 1 t s from 1st crossing of acquisition to < 1% settling -2.04.0ms clock skew window 1 t sk1 pclk to pclk; load=20pf; @1.4v - 150 250 ps clock skew window 1 t sk2 bclk to bclk; load=20pf; @1.4v - 300 500 ps clock skew window 1 t sk3 pclk to bclk; load=20pf; @1.4v - 400 600 ps
5 ICS9159-13 electrical characteristics at 5.0v v dd = 4.5 ? 5.5 v, t a = 0 ? 70 c note 1: parameter is guaranteed by design and characterization. not 100% tested in production. dc characteristics parameter symbol test conditions min typ max units input low voltage v il --0.8v input high voltage v ih 2.4 - - v input low current i il v in =0v -45 -15 - a input high current i ih v in =v dd -5.0 - 5.0 a output low current 1 i ol v ol =0.8v; for pclks & bclks 36.0 62.0 - ma output high current 1 i oh v ol =2.0v; for pclks & bclks - -152 -90.0 ma output low current 1 i ol v ol =0.8v; for ref clks 30.0 50.0 - ma output high current 1 i oh v ol =2.0v; for ref clks - -110.0 -65.0 ma output low voltage 1 v ol i ol =20ma; for pclks & bclks - 0.25 0.4 v output high voltage 1 v oh i oh =-70ma; for pclks & bclks 2.4 4.0 - v output low voltage 1 v ol i ol =15ma; for ref clks - 0.2 0.4 v output high voltage 1 v oh i oh =-50ma; for ref clks 2.4 4.7 - v supply current i dd @66.5 mhz; all outputs unloaded - 80.0 160.0 ma
6 ICS9159-13 electrical characteristics at 5.5v v dd = 4.5 ? 5.5 v, t a = 0 ? 70 c note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v pclk & bclk - 0.55 0.95 ns fall time 1 t f1 20pf load, 2.0 to 0.8v pclk & bclk - 0.52 0.90 ns rise time 1 t r2 20pf load, 20% to 80% pclk & bclk - 1.2 2.1 ns fall time 1 t f2 20pf load, 80% to 20% pclk & bclk - 1.1 2.0 ns duty cycle 1 d t1 20pf load @ vout=1.4v 52 57 62 % duty cycle 1 d t2 20pf load @ vout=50% 45 50 55 % jitter, one sigma 1 t j1s1 pclk & bclk clocks; load=20pf, rs=33w fout>25 mhz -50150ps jitter, absolute 1 t jab1 pclk & bclk clocks; load=20pf, rs=33w fout>25 mhz -250 - 250 ps jitter, one sigma 1 t j1s2 ref clks; load=20pf rs=33w - 1 3 % jitter, absolute 1 t jab2 ref clks; load=20pf rs=33w -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillatorcapacitance 1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1 st crossing of 66.5 mhz v dd supply ramp < 40ms -2.54.5ms frequency settling time 1 t s from 1st crossing of acquisition to < 1% settling -2.04.0ms clock skew window 1 t sk1 pclk to pclk; load=20pf; @1.4v - 150 250 ps clock skew window 1 t sk2 bclk to bclk; load=20pf; @1.4v - 300 500 ps clock skew window 1 t sk3 pclk to bclk; load=20pf; @1.4v - 400 600 ps
7 ICS9159-13 soic package lead count 28l dimensionl 0.704 ics xxxx m-ppp example: package type m=soic, sop device t ype (consists of 3 or 4 digit numbers) ics=standard device prefix ordering information ics9159m-13 pattern number(2 or 3 digit number for parts with rom code patterns) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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