; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 10-2 tran sfer data format figure 10-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 10-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 105 TMP86C807NG 10.4 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc3 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc3 source clock [hz] / ttreg3 setting value transfer rate [baud] = transfer clock [hz] / 16 10.5 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 10-4 data sampling method table 10-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 106 10. asynchronous serial interface (uart ) 10.6 stop bit length TMP86C807NG 10.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 10.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 10.8 transmit/receive operation 10.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 10.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 107 TMP86C807NG 10.9 status flag 10.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 10-5 generati on of parity error 10.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 10-6 generati on of framing error 10.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 108 10. asynchronous serial interface (uart ) 10.9 status flag TMP86C807NG figure 10-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 10.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 10-8 generat ion of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 10.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, that is, when data in tdbuf are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0 ? when the tdbuf is writte n after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 109 TMP86C807NG figure 10-9 generation of transmit data buffer empty 10.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is clear ed to ?0? when the data transmit is started after writing the tdbuf. figure 10-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 110 10. asynchronous serial interface (uart ) 10.9 status flag TMP86C807NG
page 111 TMP86C807NG 11. serial expansion interface (sei) sei is one of the serial interfaces incorporated in th e TMP86C807NG. it allows connection to peripheral devices via full-duplex synchronous communication protocol s. the TMP86C807NG contain one channel of sei. sei is connected with an ex ternal device through sclk, mosi, miso and the terminal ss . sclk, mosi, miso, and ss pins respectively are shared with p02, p03, p04 and p05. when using these ports as sclk, mosi, miso, or ss pins, set the each port output latch to ?1?. 11.1 features ? the master outputs the shift clock for only a data transfer period. ? the clock polarity and phase are programmable. ? the data is 8 bits long. ? msb or lsb-first can be selected. ? the programmable data and clock timing of sei can be connected to almost all synchronous serial peripheral devices. refer to ?" 11.5 sei transfer formats "?. ? the transfer rate can be selected from the following four (master only): 4 mbps, 2 mbps, 1 mbps, or 250 kbps (when operating at 16 mhz) ? the error detection circuit su pports the following functions: a. write collision detection: when the shift register is accessed for write during transfer b. overflow detection: when new data is received wh ile the transfer-finished fl ag is set (slave only) note: mode fault detect function is not supported. make sure to set secr bit to "1" for disabling the mode fault detection. figure 11-1 sei (ser ial extended interface) sei control unit port control unit clock control unit shift register read buffer sei control register sei status register bit order selection clock selection 4, 8, 16, 64 divide miso mode mstr cpha cpol bos ser sef wcol sovf see mosi sclk ss sei data register address data sei interrupt (intsei1) internal sei clock
page 112 11. serial expansion interface (sei) 11.2 sei registers TMP86C807NG 11.2 sei registers the sei interface has the sei control register (secr), sei status register (sesr), and sei data register (sedr) which are used to set up the sei system and enable/dis able sei operation. 11.2.1 sei control register (secr) 11.2.1.1 transfer rate (1) master mode (transfer rate = fc/int ernal clock divide ratio (unit : bps)) the table below shows the relationship between settings of the ser bit and transfer bit rates when the sei is operating as the master. 76543210 secr (002ah) mode see bos mstr cpol cpha ser (initial value: 0000 0100) read-modify-write instruction are prohibited mode mode fault detection #1 #1 if mode fault detection is enabled, an interrupt is generated when the modf flag (sesr) is set. 0: enables mode fault detection 1: disables mode fault detection it is available in master mode only. (note: make sure to set bit to "1" for disabling mode fault detection r/w see sei operation #2 #2 sei operation can only be disabled after transfer is co mpleted. before the sei can be used, the each port control register and output latch control must be set for the sei function (in case p0 port, p0outcr and p0dr). when using the sei as the master, set the secr bit to ?1? (to enable sei operation) and then place transmit data in the sedr register. this initiates transmission/reception. 0: disables sei operation 1: enables sei operation bos bit order selection 0: transmitted beginning with the msb (bit 7) of sedr register 1: transmitted beginning with the lsb (bit 0) of sedr register mstr mode selection #3 #3 master/slave settings must be made before enabling sei operation (this means that the secr bit must first be set before setting the secr bit to ?1?). 0: sets sei for slave 1: sets sei for master cpol clock polarity 0: selects active-?h? clock. sclk remains ?l? when idle. 1: selects active-?l? clock. sclk remains ?h? when idle. cpha clock phase selects clock phase. for details, refer to section ?sei transfer for- mats?. ser selects sei transfer rate 00: divide-by-4 01: divide-by-8 10: divide-by-16 11: divide-by-64 table 11-1 sei transfer rate ser internal clock divide ratio of sei transfer rate when fc = 16 mhz 00 4 4 mbps 01 8 2 mbps 10 16 1 mbps 11 64 250 kbps
page 113 TMP86C807NG (2) slave mode when the sei is operating as a slave, the serial clock is input from the master and the setting of the ser bit has no effect. the maximum transfer rate is fc/4. note: take note of the following relationship betwe en the serial clock speed and fc on the master side: 15.625 kbps < transfer rate < fc/4 bps example) 15.625 kbps < transfer rate < 4 mbps (fc = 16 mhz at v dd = 4.5 to 5.5 v) 15.625 kbps < transfer rate < 2 mbps (fc = 8 mhz at v dd = 2.7 to 5.5 v) 11.2.2 sei status register (sesr) 11.2.3 sei data register (sedr) the sei data register (sedr) is used to send and receive data. when the sei is set for master, data transfer is initiated by writing to this sedr register. if the ma ster device needs to write to the sedr register after transfer began, always check to s ee by means of an interrupt or by polling that the sef flag (sesr) is set, before writing to the sedr register. 76543210 sesr (0028h) sef wcol sovf ? (initial value: 0000 ****) sef transfer-finished flag #1 #1 the sef flag is automatically set at completion of trans fer. the sef flag thus se t is automatically cleared by reading the sesr register and accessing the sedr register. 0: transfer in progress 1: transfer completed read only wcol write collision error flag #2 #2 the wcol flag is automatically set by a write to t he sedr register while transfer is in progress. writing to the sedr register during transfer has no effect. the wc ol flag thus set is automat ically cleared by reading the sesr register and accessing the sedr register. no interrupts are generated for reasons that the wcol flag is set. 0: no write collision error occurred 1: write collision error occurred sovf overflow error flag (slave) #3 #3 during master mode: this bit does not function; its data when read is ?0?. during slave mode: the sovf flag is automatically set when the device fini shes reading the next data while the sef flag is set. the sovf flag thus set is automat ically cleared by reading the sesr register and accessing the sedr reg- ister. the sovf flag also is cleared by a switchover to master mode. no interrupts are generated for rea- sons that the sovf flag is set. 0: no overflow occurred 1: overflow occurred 76543210 sedr (0029h) sed7 sed6 sed5 sed4 sed3 sed2 sed1 sed0 r/w (initial value: 0000 0000)
page 114 11. serial expansion interface (sei) 11.3 sei operation TMP86C807NG 11.3 sei operation during a sei transfer, data transmissi on (serial shift-out) and reception (serial shift-in ) are performed simulta- neously. the serial clock synchronizes the timing at which information on the two serial data lines are shifted or sampled. slave device can be selected in dividually using the slave select pin ( ss pin). for unselected slave devices, data on the sei bus cannot be taken in. when operating as the master devices, the ss pin can be used to indicate multiple-master bus connection. 11.3.1 controlling sei clock polarity and phase the sei clock allows its phase and po larity to be selected in software from four combinations available by using two bits, cpha and cpol (secr). the clock polarity is set by cpol to select between act ive-high or active-low (the transfer format is unaf- fected). the clock phase is set by cpha. the master device an d the slave devices to communicate with must have the same clock phase and polarity. if multiple slave devices with differ ent transfer formats exis t on the same bus, the format can be changed to that of the slave device to which to transfer. 11.3.2 sei data and clock timing the programmable data and clock timing of sei allows connection to almost all synchronous serial periph- eral devices. refer to section ?" 11.5 sei transfer formats "?. table 11-2 clock phase and polarity cpha sei control register (secr 002ah) bit 2 cpol sei control register (secr 002ah) bit 3
page 115 TMP86C807NG 11.4 sei pin functions the TMP86C807NG have four input/output pins associated with sei transfer. the functionality of each pin depends on the sei device?s mode (master or slave). the sclk pin, mosi pin and miso pin of all sei devices are connected with the same name pin to each other . 11.4.1 sclk pin the sclk pin functions as an output pin when sei is se t for master, or as an input pin when sei is set for slave. when sei is set for master, serial clock is output from the sclk pin to external devices. after the master starts transfer, eight serial cl ock pulses are output from the sclk pin only during transfer. when sei is set for slave, the sclk pin functions as an input pin. during data transfer between master and slave, device operation is synchronized by the serial clock output from the master. when the ss pin of the slave device is ?h?, data is not taken in regardless of whether the serial clock is avail- able. for both master and slave devices, data is shifted in and ou t at a rising or falling edge of the serial clock, and is sampled at the opposite edge where the data is stable . the active edge is determin ed by sei transfer proto- cols. note:noise in a slave device?s sclk input may cause the device to operate erratically. 11.4.2 miso/mosi pins the miso and mosi pins are used for serial data tr ansmission/reception. the stat us of each pin during mas- ter and slave are shown in the table below. also, the sclk, mosi, and miso pins can be set fo r open-drain by the each pin?s input/output control reg- ister (in case p0 port, input/output control register is p0outcr). the miso pin of a slave device b ecomes an output when the secr bit is set to 1 (sei operation enabled). to set the miso pin of an inactive slave device to a high-imped ance state, clear the secr bit to 0. 11.4.3 ss pin the ss pin function differently when the sei is the master and when it is a slave. when the sei is a slave, this pin is used to en able the sei transmission/r eception. when the slave?s ss pin is high, the slave device ignores the seri al clock from the master. nor does it receive data from the miso pin. when the slave?s ss pin is l, the sei operates as slave. table 11-3 miso/mosi pin status miso mosi master input output slave output input
page 116 11. serial expansion interface (sei) 11.5 sei transfer formats TMP86C807NG 11.5 sei transfer formats the transfer formats are set using cpha and cpol (secr). cpha allows transfer protocols to be selected between two. 11.5.1 cpha (secr regi ster bit 2) = 0 format figure 11-2 shows a transfer format where cpha = 0. figure 11-2 transfer format where cpha = 0 ? in master mode, transfer is initiated by writing ne w data to the sedr register. at this time, the new data changes state on the mosi pin a half clock period before the shift clock starts pulsing. use bos (secr) to select whether the data should be shifted out beginning with the msb or lsb. the sef flag (sesr) is set after the last shift cycle. ? in slave mode, writing data to the sedr register is inhibited when the ss pin is ?l?. a write during this period causes collision of writes, so that the wcol flag (sesr) is set. therefore, when writing data to th e sedr (sei data register) after the sef flag is set upon comple- tion of transfer, make sure the ss pin goes ?h? again before writing th e next data to the sedr register. note:in slave mode, be careful not to write data while the sef flag is set and the ss pin remains ?l?. 11.5.2 cpha = 1 format figure 11-3 shows a transfer format where cpha = 1. table 11-4 transfer format details where cpha = 0 sclk level when not communicating (idle) data shift data sampling cpol = 0 ?l? level falling edge of transfer clock rising edge of transfer clock cpol = 1 ?h? level rising edge of transfer clock falling edge of transfer clock sclk cycle sclk (cpol = 0) sclk (cpol = 1) mosi miso ss sef 1 2 3 4 5 6 7 8 internal shift clock secr
page 117 TMP86C807NG figure 11-3 transfer format where cpha = 1 ? in master mode, transfer is initiated by writing new data to the sedr register. the new data changes state on the mosi pin at the first edge of the shif t clock. use bos (secr) to select whether the data should be shifted out beginning with the msb or lsb. ? in slave mode, unlike in the case of cpha = 0 format, data can be written to the sedr (sei data reg- ister) regardless of whether the ss pin is ?l? or ?h?. in both master and slave modes, the sef flag (sesr) is set after the last shift cycle. writing data to the sedr register while data transf er is in progress causes collision of writes. there- fore, wait until the sef flag is set before writing new data to the sedr register. table 11-5 transfer format details where cpha = 1 sclk level when not communicating (idle) data shift data sampling cpol=0 ?l? level rising edge of transfer clock falling edge of transfer clock cpol=1 ?h? level falling edge of transfer clock rising edge of transfer clock sclk cycle sclk (cpol = 0) sclk (cpol = 1) mosi miso ss sef 1 2 3 4 5 6 7 8 internal shift clock secr
page 118 11. serial expansion interface (sei) 11.6 functional description TMP86C807NG 11.6 functional description figure 11-4 shows how the sei master and slave are connected. when the master device sends data from its mosi pin to a slave device?s mosi pin, the slave device returns data from its miso pin to the master device?s miso pin. this means that data are exchanged between master and slave via full-duplex communication, with data output and input operations synchronized by the same clock signal. after end of transfer, the transmit byte in 8 bit shif t register is replaced with the receive byte. figure 11-4 master and slave connection in sei 8-bit shift register sei clock ss 8-bit shift register mosi master slave miso sclk mosi miso sclk 5 v 0v ss
page 119 TMP86C807NG 11.7 interrupt generation the sei for the TMP86C807NG uses in tsei1. when the sesr changes state from ?0? to ?1?, respective interrupts is generated. 11.8 sei system errors the sei has the facility to det ect following two system errors. ? write collision error: when the sedr register is acce ssed for write during transfer. ? overflow error: when the new data byte is shift in before the previous data byte is read in slave mode. 11.8.1 write collision error collision of writes occurs when an attempt is made to write to the sedr register while transfer is in progress. because the sedr register is not configured as dual-buffers when sending data, a write to the sedr register directly results in writing to the sei shift regi ster. therefore, writing to th e sedr register while trans- fer is in progress causes a write collision error. in no case is data transfer stopped in the middle, so that the write data which caused a write collision error will not be written to the shift regist er. because slaves cannot control the timing at which the master starts a transfer, collision of writes norma lly occurs on the slave side. write collision errors do no t normally occur on the master side because the master has the right to perform a transfer at any time, but in view of sei logic both the master and slaves have the facility to detect write colli- sion errors. a write collision error tends to occur on the slave side when the master sh ifts out data at a speed faster than that at which the slave processes the transferred data. more specifically, a write col lision error occurs in cases where the slave transfers a ne w value to the sedr register when the master already st arted a shift cycle for the next byte. 11.8.2 overflow error the transfer bit rate on the sei bus is determined by the master. a high bit rate causes a problem that a slave cannot keep abreast with transf er from the master, because the master is shifting out data faster than can be pro- cessed by the slave. the sei module uses the sovf flag (ses r) to detect that data has overflowed. the sovf flag is set in the following cases: ? when the sei module is set for slave ? when the old data byte remains to be read while a new data byte has been received when the sovf flag is set, the sedr regi ster is overwritten with a new data byte. note:please carefully examine the communication proc essing routine and communication rate when designing your application system. table 11-6 sei interrupt sei interrupt channel 1 (intsei1) interrupt generated for sef
page 120 11. serial expansion interface (sei) 11.9 bus driver protection TMP86C807NG 11.9 bus driver protection ? one method to protect the device against latch-up due to collision of the bus drivers is the use of an open- drain option. this means changing the sei pins? cmos outputs to the open-drain type, which is accom- plished by setting the sclk, mosi, a nd miso pins for open-drain indi vidually by using the each port input/output control register. in this case, these pins mu st be provided with pull-up resistors external to the chip. ? when using the sei pins as cmos outputs, we recommend connecting them to the bus via resistors in order to protect the device against collision of drivers. however, be sure to se lect the appropriate resistance value which will not affect actual device operation (example: 1 ? to several k ? ).
page 121 TMP86C807NG 12. 8-bit ad converter (adc) the TMP86C807NG have a 8-bit successive approximation type ad converter. 12.1 configuration the circuit configuration of the 8-bit ad converter is shown in figure 12-1. it consists of control registers adccr1 and adccr2, converted value registers adcdr1 and adcdr2, a da converter, a sample-and-hold circuit, a comp arator, and a successive comparison circuit. figure 12-1 8-bit ad converter (adc) 3 4 8 8 ainds analog input multiplexer adrs r/2 r/2 r ack irefon ad conversion result register1,2 ad converter control register 1,2 adbf eocf intadc interrupt sain successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit 0 y to n s en shift clock da converter reference voltage analog comparator control circuit vdd ain0 ain5 vss
page 122 12. 8-bit ad converter (adc) 12.1 configuration TMP86C807NG 12.2 control the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels in which to perform ad conversion and controls the ad con- verter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conver sion time and controls the connect ion of the da converter (ladder resistor network). 3. ad converted value register (adcdr1) this register is used to store the digital value after being converted by the ad converter. 4. ad converted value register (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input when ad converter stops (adcdr2 = ?0?). note 2: when the analog input is all use disabl ing, the adccr1 should be set to ?1?. note 3: during conversion, do not perform output instruction to ma intain a precision for all of the pins. and port near to analo g input, do not input intense signaling of change. note 4: the adrs is automatically cl eared to ?0? after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register 1 (adccr1) is all initialized and no data can be written in this register. therefore, to use ad conv erter again, set the adccr1 newly after returning to normal1 or normal2 mode. note 7: always set bit 5 in adccr1 to ?1? and set bit 6 in adccr1 to ?0?. ad converter control register 1 adccr1 (000eh) 76543210 adrs "0" "1" ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: ? start r/w ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
page 123 TMP86C807NG note 1: always set bit 0 in adccr2 to ?0? and set bit 4 in adccr2 to ?1?. note 2: when a read instruction for adccr2, bit 6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register 2 (adccr2) is all initialized and no data can be written in this register. therefore, to use ad conv erter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: settings for ? ? ? in the above table are inhibited. note 2: set conversion time by supply voltage(vdd) as follows. note 1: the adcdr2 is cleared to ?0? when reading the adcdr1. therefore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: adcdr2 is set to ?1? when ad conversion starts and cleared to ?0? when the ad conversion is finished. it also is cleared upon entering stop or slow mode. note 3: if a read instruction is executed for adcdr2, read data of bits 7, 6 and 3 to 0 are unstable. ad converter control register 2 adccr2 (000fh) 76543210 irefon ?1? ack ?0? (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved r/w table 12-1 conversion time according to ack setting and frequency condition conbersion time? 16mhz 8mhz 4 mhz 2 mhz 10mhz 5 mhz 2.5 mhz ack 000 39/fc - - - 19.5 s - - 15.6 s 001 reserved 010 78/fc - - 19.5 s39.0 s-15.6 s 31.2 s 011 156/fc - 19.5 s 39.0 s78.0 s 15.6 s 31.2 s 62.4 s 100 312/fc 19.5 s39.0 s 78.0 s 156.0 s 31.2 s 62.4 s 124.8 s 101 624/fc 39.0 s78.0 s156.0 s - 62.4 s 124.8 s- 110 1248/fc 78.0 s 156.0 s- -124.8 s- - 111 reserved - vdd = 4.5 to 5.5 v (15.6 s or more) - vdd = 2.7 to 5.5 v (31.2 s or more) ad conversion result register adcdr1 (0020h) 76543210 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 (initial value: 0000 0000) ad conversion result register adcdr2 (0021h) 76543210 eocf adbf (initial value: **00 ****) eocf ad conversion end flag 0: before or during conversion 1: conversion completed read only adbf ad conversion busy flag 0: during stop of ad conversion 1: during ad conversion
page 124 12. 8-bit ad converter (adc) 12.3 function TMP86C807NG 12.3 function 12.3.1 ad conveter operation when adccr1 is set to "1", ad conversion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1) and at the same time adcdr2 is set to ?1?, the ad conversion finished interrupt (intadc) is generated. adccr1 is automatically cleared after ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr to see that the conversion is completed or wait until the inte rrupt signal (intadc) is generated (e.g., interrupt han- dling routine). figure 12-2 ad c onverter operation 12.3.2 ad converter operation 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to table 12-1. ? choose irefon for da converter control. 3. after setting up 1. and 2. above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. adcdr1 status eocf cleared by reading conversion result conversion result read conversion result read adcdr2 intadc interrupt reading adcdr1 reading adcdr2 adcdr2 adccr1 first conversion result second conversion result indeterminate ad conversion start ad conversion start
page 125 TMP86C807NG 12.3.3 stop and slow m ode during ad conversion when the stop or slow mode is entered forcibly du ring ad conversion, the ad convert operation is sus- pended and the ad converter is initialized (adccr1 and adccr2 are initialized to initial value.). also, the conversion result is indeterminate. (c onversion results up to the previous operation are cleared, so be sure to read the conversion results before entering stop or slow mode.) when restored from stop or slow mode, ad conversion is not automatically restarted, so it is necessary to restart ad conversion. note that since the analog reference voltage is automa tically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time of 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad conversion once. after checking eocf, read the converted value and store the 8-bit data in address 009fh on ram. ; ain select : : : : ; before setting the ad converter register, set each port reg- ister suitably (for detail, see chapter of i/o port.) ld (adccr1), 00100011b ; select ain3 ld (adccr2), 11011000b ; select conversion time (312/fc) and operation mode ; ad convert start set (adccr1). 7 ; adrs = 1 sloop: test (adcdr2). 5 ; eocf = 1 ? jrs t, sloop ; result data read ld a, (adcdr1) ld (9fh), a
page 126 12. 8-bit ad converter (adc) 12.3 function TMP86C807NG 12.3.4 analog input volt age and ad conversion result the analog input voltage is corresponded to the 8-bit digital value converted by the ad as shown in figure 12-3. figure 12-3 analog i nput voltage and ad conv ersion result (typ.) 1 0 01h 02h 03h fdh feh ffh 2 3 253 254 255 256 analog input voltage ad conversion result 256 vdd vss
page 127 TMP86C807NG 12.4 precautions about ad converter 12.4.1 analog input pin voltage range make sure the analog input pins (ain0 to ain5) are used at voltages within vss below vdd. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 12.4.2 analog input shared pins the analog input pins (ain0 to ain5) are shared wi th input/output ports. when using any of the analog inputs to execute ad convers ion, do not execute in put/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input shared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 12.4.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 12-4. the higher the output imped- ance of the analog input source, more easily they are su sceptible to noise. therefor e, make sure the output impedance of the signal source in your design is 5 k ? or less. toshiba also reco mmends attaching a capacitor external to the chip. figure 12-4 analog input equivalent ci rcuit and example of input pin processing da converter ainx analog comparator internal resistance allowable signal source impedance internal capacitance 5 k ? (typ) c = 22 pf (typ.) 5 k ? (max) note) i = 5~0
page 128 12. 8-bit ad converter (adc) 12.4 precautions about ad converter TMP86C807NG
page 129 TMP86C807NG 13. key-on wakeup (kwu) TMP86C807NG have four pins p34 to p37, in addition to the p20 ( int5 / stop ) pin, that can be used to exit stop mode. when using these p34 to p37 pin?s input to exit stop mode, pay attention to the logic of p20 pin. in details, refer to the following section" 13.2 control ". 13.1 configuration figure 13-1 key-on wakeup circuit figure 13-2 example of st op mode release operation int5 p20 (int5/stop) p34 (ain2/stop2) p35 (ain3/stop3) stop mode release signal (1: release) stop mode control qd s stop2(stopcr) stop signal qd s stop3(stopcr) stop signal p36 (ain4/stop4) qd s stop4(stopcr) stop signal p37 (ain5/stop5) qd s stop5(stopcr) stop signal stop mode release operation(p34 to 37) example of stop mode release operation "l" "h" "l" rising or falling edge detect stop wake-up* operation the time required for wakeup from releasing stop mode includes the warming-up time. for details, refer to section "control of operation modes". p3i *
page 130 13. key-on wakeup (kwu) 13.2 control TMP86C807NG 13.2 control the p34 to p37 (stop2 to stop5) pins can individuall y be disabled/enabled using key-on wakeup control reg- ister (stopcr). before these pins can be used to place th e device out of stop mode, th ey must be set for input using the p3 port input/out put register (p3cr), p3port output latc h (p3dr), ad contro l register (adccr1). stop mode can be entered by setting up the system contro l register (syscr1), and ca n be released by detecting the active edge (rising or falling edge) on any stop2 to st op5 pins which are available for stop mode release. note: when using key-on wakeup function, select level mode ( set syscr1 to "1" ) for selection of stop mode release method. although p20 pin is shared with int5 and stop pin input, use mainly stop pin to release stop mode. this is because key-on wakeup fu nction is comprised of stop pin and stop2 to stop5 pins as shown in the configuration diagram. note 1: when stop mode release by an edge on stop pi n, follow one of the two methods described below. (1) disable all of stop2 to 5 pin inputs. (2) fix stop2 to 5 pin inputs high or low level. note 2: when using key-on wakeup (stop2 to 5 pins) to exit stop mode, make sure stop pin is held low and stop2 to 5 pin inputs are held high or low level, because stop mode release signal is created by oring the stop pin input and the stop2 to 5 pin input together. note: assertion of the stop mode release si gnal is not recognized within three inst ruction cycles after executing the stop instruction. key-on wakeup stop mode control register stopcr76543210 (0031h) stop5 stop4 stop3 stop2 (initial value : 0000 ****) stop2 stop mode release by p34 (stop2) 0: disable write only 1: enable stop3 stop mode release by p35 (stop3) 0: disable 1: enable stop4 stop mode release by p36 (stop4) 0: disable 1: enable stop5 stop mode release by p37 (stop5) 0: disable 1: enable the device is released from stop mode in the following condition. p20( stop )p3x stop mode release using p3x (stop2 to 5) level detection mode: low edge detection mode: disable edge detection rising or falling edge stop mode release using p20 ( stop ) level detection mode: high edge detection mode: rising edge stopcr: inhibited
page 131 TMP86C807NG 14. input/output circuitry 14.1 control pins the input/output circuitries of the TMP86C807NG control pins are shown below. note: the test pin of the tmp86p807 does not have a pull-down resi stor and protect diode(d1). fix the test pin at low-level in mcu mode. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins r f = 1.2 m ? (typ.) r o = 0.5 k ? (typ.) xtin xtout input resonator connecting pins r f = 6 m ? (typ.) r o = 220 k ? (typ.) reset input hysteresis input pull-up resistor r in = 220 k ? (typ.) r = 100 ? (typ.) test input with pull-down resistor r in = 70 k ? (typ.) r = 100 ? (typ.) fc rf r o osc.enable xin xout vdd vdd fs rf r o osc.enable xtin xten xtout vdd vdd r in r vdd address trap reset watchdog timer reset system clock reset vdd r in r d 1
page 132 14. input/output circuitry 14.2 input/output ports TMP86C807NG 14.2 input/output ports note: input status on pins set for input mode are read in into the internal circuit. therefore, when using the ports in a maxtur e of input and output modes, the contents of the output latches for t he ports that are set for input mode may be rewritten by exe- cution of bit manipulating instructions. control pin i/o input/output circuitry remarks p0 i/o sink open drain output or push-pull output hysteresis input high current output(nch) (programmable port option) r = 100 ? (typ.) p1 i/o tri-state i/o hysteresis input r = 100 ? (typ.) p2 i/o sink open drain output hysteresis input r = 100 ? (typ.) p3 i/o tri-state i/o hysteresis input r = 100 ? (typ.) initial "high-z" high-z control vdd r pch control data output input from output latch pin input initial "high-z" disable vdd r data output pin input initial "high-z" vdd r data output input from output latch pin input initial "high-z" disable vdd r data output pin input
page 133 TMP86C807NG 15. electrical characteristics 15.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (v ss = 0 v) parameter symbol pins ratings unit supply voltage v dd ? 0.3 to 6.5 v input voltage v in ? 0.3 to v dd + 0.3 output voltage v out ? 0.3 to v dd + 0.3 output current (per 1 pin) i out1 p0, p1, p3 port ? 1.8 ma i out2 p1, p2, p3 port 3.2 i out3 p0 port 30 output current (total) i out1 p0, p1, p3 port ? 30 i out2 p1, p2, p3 port 60 i out3 p0 port 80 power dissipation [topr = 85 c] p d sdip 300 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ? 55 to 150 operating temperature topr ? 40 to 85
page 134 15. electrical characteristics 15.1 absolute maximum ratings TMP86C807NG 15.2 operating condition the operating conditions show the conditions under which the device be used in orde r for it to operate normally while maintaining its quality. if the device is used outsid e the range of operating conditions (power supply voltage, operating temperature range, or ac/dc rated values), it may operate erratically. therefore, when designing your application equipment, always make sure its intended working conditio ns will not exceed th e range of operating conditions. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min max unit supply voltage v dd fc = 16 mhz normal1, 2 mode 4.5 5.5 v idle0, 1, 2 mode fc = 8 mhz normal1, 2 mode 2.7 idle0, 1, 2 mode fs = 32.768 khz slow1, 2 mode sleep0, 1, 2 mode stop mode input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 2.7 v to 5.5 v 1.0 8.0 mhz v dd = 4.5 v to 5.5 v 16.0 fs xtin, xtout v dd = 2.7 v to 5.5 v 30.0 34.0 khz
page 135 TMP86C807NG 15.3 dc characteristics note 1: typical values show those at topr = 25 c, v dd = 5 v note 2: input current (i in1 , i in3 ); the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref current. note 4: the power supply current in stop2 and sleep2 modes each are the same as in idle0, 1, and 2 modes. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input ? 0.9 ? v input current i in1 test v dd = 5.5 v, v in = 5.5 v/0 v ?? 2 a i in2 sink open drain, tri-state port i in3 reset , stop input resistance r in1 test pull-down ? 70 ? k ? r in2 reset pull-up 100 220 450 output leakage current i lo sink open drain, tri-state port v dd = 5.5 v, v out = 5.5 v/0 v ?? 2 a output high voltage v oh p0, p1, p3 port v dd = 4.5 v, i oh = ? 0.7 ma 4.1 ? ? v output low voltage v ol p1, p2, p3 port v dd = 4.5 v, i ol = 1.6 ma ??0.4 output low current i ol high current port (p0 port) v dd = 4.5 v, v ol = 1.0 v ?20? ma supply current in normal 1, 2 mode i dd v dd = 5.5 v v in = 5.3/0.2 v fc = 16.0 mhz fs = 32.768 khz ?7.59.0 supply current in idle 0, 1, 2 mode ?5.56.5 supply current in slow 1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz ? 14.0 25.0 a supply current in sleep 1 mode ? 7.0 15.0 supply current in sleep 0 mode ? 6.0 15.0 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v ? 0.5 10.0
page 136 15. electrical characteristics 15.5 sei operating conditions (slave mode) TMP86C807NG 15.4 ad conversi on characteristics note 1: the total error includes all errors except a quantizati on error, and is defined as a maximum deviation from the ideal conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please refe r to ?register configuration?. note 3: please use input voltage to ain input pin in limit of v dd ? v ss . when voltage of range outside is input, conversion value bec omes unsettled and gives affect to other channel conversion value. note 4: the relevant pin for i ref is v dd , so that the current flowing into v dd is the power supply current i dd + i ref . 15.5 sei operating c onditions (slave mode) (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog input voltage v ain v ss ? v dd v power supply current of analog reference voltage i ref v dd = 5.5 v v ss = 0.0 v ?0.61.0ma non linearity error v dd = 5.0 v, v ss = 0.0 v ?? 1 lsb zero point error ?? 1 full scale error ?? 1 total error ?? 2 (v ss = 0.0 v, 2.7 v v dd < 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog input voltage v ain v ss ? v dd v power supply current of analog reference voltage i ref v dd = 4.5 v v ss = 0.0 v ?0.50.8ma non linearity error v dd = 2.7 v, v ss = 0.0 v ?? 1 lsb zero point error ?? 1 full scale error ?? 1 total error ?? 2 (v ss = 0.0 v, 2.7 v v dd 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit transfer rate 15.625 k ? fc/4 bps
page 137 TMP86C807NG 15.6 ac characteristics (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 mode 0.25 ? 4 s idle0, 1, 2 mode slow1, 2 mode 117.6 ? 133.3 sleep0, 1, 2 mode high level clock pulse width t wch for external clock operation (xin input) fc = 16 mhz 25 ? ? ns low level clock pulse width t wcl high level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz 14.7 ? ? s low level clock pulse width t wsl (v ss = 0 v, v dd = 2.7 to 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 mode 0.5 ? 4 s idle0, 1, 2 mode slow1, 2 mode 117.6 ? 133.3 sleep0, 1, 2 mode high level clock pulse width t wch for external clock operation (xin input) fc = 8 mhz 50 ? ? ns low level clock pulse width t wcl high level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz 14.7 ? ? s low level clock pulse width t wsl
page 138 15. electrical characteristics 15.8 handling precaution TMP86C807NG 15.7 recommended osc illation conditions note 1: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will act ually be mounted. note 2: for the resonators to be used with toshiba microcont rollers, we recommend ceramic resonators manufactured by murata manufacturing co., ltd. for details, please visit the website of murata at the following url: http://www.murata.com 15.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in plac es exposed to high electric fields such as cathode-ray tubes, we recommend elec- trically shielding the package in order to maintain normal operating condition.
 

   

    
    
 
page 139 TMP86C807NG 16. package dimensions sdip28-p-400-1.78 rev 01 unit: mm
page 140 16. package dimensions TMP86C807NG
this is a technical document that de scribes the operating functi ons and electrical specif ications of the 8-bit microcontroller series tlcs-870/c (lsi). toshiba provides a variety of development tools a nd basic software to enable efficient software development. these development tools have specifi cations that support advances in microcomputer hardware (lsi) and can be used extensively. both the hardware and so ftware are supported continuous ly with version updates. the recent advances in cmos lsi production technology have be en phenomenal and microcomputer systems for lsi design are constant ly being improved. the products described in this document may also be revised in the future. be sure to check the latest specific ations before using. toshiba is developing highly integrated, high-perfo rmance microcomputers using advanced mos production technology and especially well proven cmos technology. we are prepared to meet the requests for custom packaging for a variet y of application areas. we are confident that our products can satisfy your application needs now and in the future.