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w83194r-630a 166mhz clock for sis chipset publication release date: may.2000 - 1 - revision 1.0 w83194r-630a data sheet revision history pages dates version version on web main contents 1 n.a. n.a. all of the versions before 0.50 are for internal use. 2 n.a. 02/apr 1.0 1.0 change version and version on web site to 1.0 3 4 5 6 7 8 9 10 please note that all data and specifications are subj ect to change without notice. all the trademarks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be ex pected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages re sulting from such improper use or sales.
w83194r-630a publication release date:may. 2000 1. general description the w83194r-630a is a clock synthesizer for sis 540/630 chipset. w83194r-630a provides all clocks required for high-speed risc or cisc micr oprocessor such as amd,cyrix,intel pentium, pentium ii and also provides 16 different frequencie s of cpu clocks frequency setting. all clocks are externally selectable with smooth transitions. the w83194r-630a makes sdram in synchronous or asynchronous frequency with cpu clocks. the w83194r-630a provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs and w83194r-630a provides the 0.5%, 0.75% center ty pe and 0~0.5% down type spread spectrum to reduce emi. the w83194r-630a accepts a 14.318 mhz reference crys tal as its input and runs on a 3.3v supply. high drive pci and sdram clock output s typically provide greater than 1 v /ns slew rate into 30 pf loads. cpu clock outputs typically provide better than 1 v /ns slew rate into 20 pf loads as maintaining 50 5% duty cycle. the fixed frequency outputs as ref, 24mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2. product features ? supports pentium ? , pentium ? ii, amd and cyrix cpus with i 2 c. ? 3 cpu clocks ? 14 sdram clocks for 3 dimms ? 7 pci synchronous clocks. ? optional single or mixed supply: (all vdd = 3.3v) or (o ther s vdd = 3.3v, vddlcpu=2.5v) ? skew form cpu to pci clock 1 to 4 ns, center 2.6 ns ? sdram frequency synchronous or asynchronous to cpu clocks ? smooth frequency switch with selections from 66 to 166mhz ? i 2 c 2-wire serial interface and i 2 c read back ? 0.5%, 0.75%center type, 0~0.5% down type spread spectrum to reduce emi ? programmable registers to enable/stop each output and select modes (mode as tri-state or normal ) ? 48 mhz for usb ? 24 mhz for super i/o ? packaged in 48-pin ssop - 2 - revision 1.0
w83194r-630a publication release date:may. 2000 3. block diagram pll2 xtal osc spread spectrum pll1 latch por stop 2 control logic config. reg. stop pci clock divder 5 14 7 48mhz 24_48mhz ref(0:1) cpuclk(0:2) sdram(0:13) pciclk(0:6) xin xout *fs(0:3) 4 *mode cpu_stop# pci_stop# *sdata *sclk 2 3 sel3.3_2.5# cpu_stop# pci_stop# pd# 4. pin configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vdd ref0x2/ *fs3 vss xin xout vddp pciclk_f/ *fs1 pciclk1/ *fs2 vss pciclk2/*mode pciclk3 pciclk4 pciclk5 sdram12 vddsd sdram_f sdram11 vddp sdram 10 sdram 8 *sdata *sdclk vddlcpu cpuclk_f vss cpuclk0 cpuclk1 vddsd sdram 0/cpu_stop# sdram 1/pci_stop# sdram 2/pd# vddsd sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vddsd vddsd 24_48mhz/sel2.5_3.3# ref1 vss sdram 9 48mhz/*fs0 pciclk6 vss vss - 3 - revision 1.0
w83194r-630a publication release date:may. 2000 5. pin description in - input out - output i/o - bi-directional pin # - active low * - internal 250k ? pull-up 5.1 crystal i/o symbol pin i/o function xin 4 in crystal input with internal loading capacitors and feedback resistors. xout 5 out crystal output at 14.318mhz nominally. 5.2 cpu, sdram, pci clock outputs symbol pin i/o function cpuclk_f 46 out low skew (< 250ps) clock outputs for host frequencies such as cpu, chipset and cache. vddlcpu is the supply voltage for these outputs. this pin will not be stopped by cpu_stop# cpuclk [ 0:1 ] 45,43 out low skew (< 250ps) clock outputs for host frequencies such as cpu, chipset and cache. vddlcpu is the supply voltage for these outputs. sdram_f 40 out sdram clock output s which have syn. or asyn. frequencies as cpu clocks. this pin will not be stopped by cpu_stop# sdram0/cpu_stop# 17 i/o sdram clock outputs which have syn. or asyn. frequencies as cpu clocks. cpu_stop# input pin when mode=0. sdram1/pci_stop# 18 i/o sdram clo ck outputs which have syn. or asyn. frequencies as cpu clocks. pci_stop# input pin when mode=0. sdram2/pd# 20 i/o sdram clock out puts which have syn. or asyn. frequencies as cpu clocks. pd# input pin when mode=0. sdram[3:12] 21,28,29,31,32 ,34,35,37,38, 41 out sdram clock outputs wh ich have syn. or asyn. frequencies as cpu clocks. pciclk_f/ *fs1 7 i/o latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. - 4 - revision 1.0
w83194r-630a publication release date:may. 2000 pci free-running clock during normal operation. pciclk 1/ *fs2 8 i/o latched input for fs2 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. pci clock during normal operation. pciclk 2/ *mode 9 i/o latched input fo r mode at initial power up for input selection of cpu_stop#, pci_stop# and pd#. when mode=1, the above pins are sdram clock outputs. when mode=0, the pins are inputs acpi pins. pci clock during normal operation. pciclk [ 3:6 ] 11,12,13,14 out low skew (< 250ps) pci clock outputs. 5.3 i 2 c control interface symbol pin i/o function *sdata 23 i/o serial data of i 2 c 2-wire control interface *sdclk 24 in serial clock of i 2 c 2-wire control interface 5.4 fixed frequency outputs symbol pin i/o function ref0x2 / *fs3 2 i/o 3.3v, 14.318mhz reference clock output . internal 250k ? pull-up. latched input for fs3 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. ref1 48 i/o 3.3v , 14.318mhz reference clock output. 24_48mhz/ sel2.5_3.3# 25 i/o sel2.5_3.3# controls the vdd of cpu. if logic 0 at power on, vddlcpu=3.3v. if logic 1, vddlcpu=2.5 24mhz or 48mhz selected by i2c for super i/o. 48mhz / *fs0 26 i/o internal 250k ? pull-up. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 48mhz output for usb during normal operation. - 5 - revision 1.0
w83194r-630a publication release date:may. 2000 5.5 power pins symbol pin function vdd 1 power supply for ref crystal and core logic. vddlcpu 47 power supply for cpuclk_f and cpuclk[0:1], either 2.5v or 3.3v. vddp 6,15 power supply for pci outputs. vddsd 19,27,30,36,42 power supply for sdram and 48/24nhz outputs. vss 3,10,16,22,33,39, 44 circuit ground. 6. frequency selection by hardware fs3 fs2 fs1 fs0 cpu (mhz) sdram (mhz) pci (mhz) ref (mhz) ioapic 0 0 0 0 66.8 100.2 33.4 14.318 0 0 0 1 100.2 100.2 33.4 14.318 0 0 1 0 83.3 83.3 33.2 14.318 0 0 1 1 133.6 100.2 33.4 14.318 0 1 0 0 75 75 37.5 14.318 0 1 0 1 100.2 133.6 33.4 14.318 0 1 1 0 100.2 150.3 33.4 14.318 0 1 1 1 133.6 133.6 33.4 14.318 1 0 0 0 66.8 66.8 33.4 14.318 1 0 0 1 97 97 32.3 14.318 1 0 1 0 97 129.3 32.3 14.318 1 0 1 1 95.2 95.2 31.7 14.318 1 1 0 0 140 140 35 14.318 1 1 0 1 112 112 37.3 14.318 1 1 1 0 96.2 96.2 32.1 14.318 1 1 1 1 166 166 33.3 14.318 7. sel3.3_2.5# buffer selection sel3.3_2.5# ( pin 25 ) input level cpu operate at 1 vddlcpu = 2.5v 0 vddlcpu = 3.3v - 6 - revision 1.0
w83194r-630a publication release date:may. 2000 8. function description 8.1 2-wire i 2 c control interface the clock generator is a slave i2c component which can be read back the data stored in the latches for verification. all proceeding bytes must be sent to change one of the control bytes. the 2-wire control interface allows each clock output indi vidually enabled or disabled. on power up, the w83194r-630a initializes with def ault register settings, and then it ptional to use the 2-wire control interface. the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high during normal data transfer. there are only two exc eptions. one is a high-to-low transition on sdata while sdclk is high used to indicate the beginning of a data transfer cycle. the other is a low-to- high transition on sdata while sdclk is high used to indicate the end of a data transfer cycle. data is always sent as complete 8-bit bytes followed by an acknowledge generated. byte writing starts with a start condition follo wed by 7-bit slave address [1101 0010], command code checking [0000 0000], and byte count checking. after successful reception of each byte, an acknowledge (low) on the sdata wire will be generated by the clock chip. controller can start to write to internal i 2 c registers after the string of data. the sequence order is as follows: bytes sequence order for i 2 c controller : clock address a(6:0) & r/w ack 8 bits dummy command code ack 8 bits dummy byte count ack byte0,1,2... until stop set r/w to 1 when read back the data s equence is as follows, [1101 0011] : clock address a(6:0) & r/w ack byte 0 ack ack byte2, 3, 4... until stop byte 1 8.2 serial control registers the pin column lists the affected pin number and the @powerup column gives the state at true power up. registers are set to the values shown onl y on true power up. "command code" byte and "byte count" byte must be sent following the acknowledge of the address byte. al though the data (bits) in these two bytes are considered "don't care", they must be sent and w ill be acknowledge. after that, the below described sequence (register 0, register 1, register 2, ....) will be valid and acknowledged. - 7 - revision 1.0
w83194r-630a publication release date:may. 2000 frequency table by i2c ssel3 ssel2 ssel1 ssel0 cpu (mhz) sdram (mhz) pci (mhz) ref (mhz) ioapic 0 0 0 0 66.8 100.2 33.4 14.318 0 0 0 1 100.2 100.2 33.4 14.318 0 0 1 0 83.3 83.3 33.2 14.318 0 0 1 1 133.6 100.2 33.4 14.318 0 1 0 0 75 75 37.5 14.318 0 1 0 1 100.2 133.6 33.4 14.318 0 1 1 0 100.2 150.3 33.4 14.318 0 1 1 1 133.6 133.6 33.4 14.318 1 0 0 0 66.8 66.8 33.4 14.318 1 0 0 1 97 97 32.3 14.318 1 0 1 0 97 129.3 32.3 14.318 1 0 1 1 95.2 95.2 31.7 14.318 1 1 0 0 140 140 35 14.318 1 1 0 1 112 112 37.3 14.318 1 1 1 0 96.2 96.2 32.1 14.318 1 1 1 1 166 166 33.3 14.318 8.2.1 register 0: cpu frequency select register (default = 0) bit @powerup pin description 7 0 - 0 = 0.5% center type spread spectrum modulation 1 = 0.75% center type spread spectrum modulation 6 0 - ssel2 (for frequency table selection by software via i 2 c) 5 0 - ssel1 (for frequency table selection by software via i 2 c) 4 0 - ssel0 (for frequency table selection by software via i 2 c) 3 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit 2, 6:4 2 0 - ssel3 (for frequency table selection by software via i 2 c) 1 0 - 0 = normal 1 = spread spectrum enabled 0 0 - 0 = running 1 = tristate all outputs - 8 - revision 1.0
w83194r-630a publication release date:may. 2000 8.2.2 register 1 : cpu clock regi ster (1 = active, 0 = inactive) bit @powerup pin description 7 x - latched fs2# 6 1 - reserved 5 1 - 0 = 0.5% down type spread, overrides byte0-bit7. 1= center type spread. 4 1 - reserved 3 1 43 cpuclk2 (active / inactive) 2 1 45 cpuclk1 (active / inactive) 1 1 46 cpuclk0 (active / inactive) 0 1 - reserved 8.2.3 register 2: pci clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - reserved 6 1 14 pciclk6 (active / inactive) 5 1 13 pciclk5 (active / inactive) 4 1 12 pciclk4 (active / inactive) 3 1 11 pciclk3 (active / inactive) 2 1 9 pciclk2 (active / inactive) 1 1 8 pciclk1 (active / inactive) 0 1 7 pciclk0 (active / inactive) 8.2.4 register 3: control regist er (1 = active, 0 = inactive) bit @powerup pin description 7 1 - 1 pin25 24_48mhz = 24mhz 0 pin25 24_48mhz = 48mhz 6 x - latched fs0# 5 1 26 48mhz (active / inactive) 4 1 25 24-48mhz (active / inactive) 3 1 - reserved 2 1 - reserved 1 1 48 ref1 (active / inactive) 0 1 2 ref0x2 (active / inactive) - 9 - revision 1.0
w83194r-630a publication release date:may. 2000 8.2.5 register 4: sdram regist er (1 = active, 0 = inactive) bit @powerup pin description 7 1 41 sdram13 (active / inactive) 6 1 40 sdram12 (active / inactive) 5 1 38 sdram11 (active / inactive) 4 1 37 sdram10 (active / inactive) 3 x x latched fs1# 2 1 35 sdram9 (active / inactive) 1 x x latched fs3# 0 1 34 sdram8 (active / inactive) 8.2.6 register 5: sdram regist er(1 = active, 0 = inactive) bit @powerup pin description 7 1 32 sdram7 (active / inactive) 6 1 31 sdram6 (active / inactive) 5 1 29 sdram5 (active / inactive) 4 1 28 sdram4 (active / inactive) 3 1 21 sdram3 (active / inactive) 2 1 20 sdram2 (active / inactive) 1 1 18 sdram1 (active / inactive) 0 1 17 sdram0 (active / inactive) 8.2.7 register 6: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 1 - winbond chip id 2 0 - winbond chip id 1 0 - winbond chip id 0 1 - winbond chip id - 10 - revision 1.0
w83194r-630a publ i c at i on rel e ase dat e :may. 2000 9. ordering information part number package ty pe production flow w83194r-630a 48 pin ssop commercial, 0 c to + 7 0 c 10. how to read the top marking - 11 - revision 1.0 w83194r-630a 28051234 942ged 1st line: winbond logo and the type number: w83194r-630a 2 n d l i n e : t r a c k i n g c o d e 2 8 0 5 1 2 3 4 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3 r d l i n e : t r a c k i n g c o d e 9 4 2 g e d 942 : p a c k a g e s m a d e i n ' 9 9 , w e e k 4 2 g : assembly house id; o means ose, g means gr e : internal use code d : ic revis i on all the trade marks of products and companies mentioned in this data sheet belong to their respective ow ners .
w83194r-630a publ i c at i on rel e ase dat e :may. 2000 11. package drawing and dimensions h e a dqu a r t e r s n o . 4 , c r e a t i on r d . iii s c i e n c e- b a s e d i n d u st ri al p a rk h s inc h u, ta iwa n t e l : 886 - 3 5 - 770 066 f a x : 886- 35- 78946 7 www: ht t p : //www. w inbond.c om .t w/ t a i p ei o f f i ce 11 f , n o . 115, s ec. 3 , m i n - s h en g e a s t r d . ta ipe i, ta iwa n t e l : 886 - 2 - 7190 505 f a x : 886- 2- 7 19750 2 t l x : 164 85 w i nt p e w i nbo nd el ec t r on i c s ( h . k . ) lt d. r m . 803, w o rld t r ad e s q u a re , t o w e r i i 1 2 3 h o i b u n r d ., k w un to ng k o wloo n, hon g kon g t e l : 85 2- 27 5160 23- 7 f a x : 852- 275 52064 w i nbond el e c t r oni cs (n o r th a m e r i c a ) c o rp . 273 0 o r ch ard p a rkw a y s a n jo se, c a 95 134 u . s . a . t e l : 1- 40 8- 9 4366 66 f a x : 1- 408 - 943 6668 please note that all data and specificati ons are subject to change w i thout notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective ow ners . these products are not designed for use in life support appliances, devices, or sy stems w h ere malfunction of these produc ts can reasonably be expected to result in personal injury . winbond cust omers using or selling these products for use in such applications do so at their ow n risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale. - 12 - revision 1.0

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