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aic157 4 5- b it d ac , synchronous p wm power regulator w ith triple linear controllers analog integrations corporation 4f, 9, industry e. 9th rd, science based industrial park, hsinchu taiwan, roc www.analog.com.tw ds-1 574- 00 may 22, 01 tel: 886-3-5772500 fax: 886-3-5772510 1 n features l compatible with hip60 21 . l provides 4 regulated voltages for microprocessor core, agp bus, memory and gtl bus power. l ttl compatible 5-bit digital-to-analog core output voltage selection. range from 1.3v to 3.5v. 0.1v steps from 2.1v to 3.5v. 0.05v steps from 1.3v to 2.05v. l 1.0% output voltage for vcore, 3.0% acc u - racy for linear controller outputs. l simple voltage-mode pwm control and b uilt in i nternal compensation network s . l n-channel mosfet driver for pwm b uck c o n - verter. l linear controller drives compatible with both n ? chanel mosfet and npn bipolar series pass transistor. l operates from +3.3v, +5v and +12v i n puts. l fast transient response. l full 0% to 100% duty ratios. l adjustable current limit without external sense r e sistor. l microprocessor core voltage protection against upper mosfet shorted to +5v. l power good output voltage monitor. l over-voltage and over-current fault monitors. l 200khz free-running oscillator programmable up to 70 0khz. n applications l full motherboard power regulation for compu t ers. n description the aic157 4 combines a synchronous voltage mode controller with three linear controller as well as the monitoring and protection functions in this chip. the pwm controller regulates the microprocessor core voltage with a synchronous rectified buck converter. the three linear controller s regulate power for the 1.5v or 3.3v agp bus power, the 1.5v gtl bus and the 1.8v power for the chip set core voltage and/or c a che memory circuits. an integrated 5 bit d/a converter that adjusts the core pwm output voltage from 2.1v to 3.5v in 0.1v increments and from 1.3v to 2.05v in 0.05v incr e - ments. the linear controller for agp bus power is selectable by ttl-compatible select pin status for 1.5v or 3.3v with 3% accuracy. the other two linear controller provide 1.5v 3% and 1.8v 3% or adjustable output voltage by means of external d i - vided resistor based on fix pin status. this chip monitors all the output voltages. power good signal is issued when the core voltage is within 10% of the dac setting and the other levels are above their under-voltage levels. over-voltage protection for the core output uses the lower n- channel mosfet to prevent output voltage above 11 6 % of the dac se t ting. the pwm over-current function monitors the output current by using the voltage drop across the upper mosfet?s r ds( on ) , eliminating the need for a cu r - rent sensing resistor .
aic157 4 2 n typical application + + + vaux drive2 vsen2 select drive3 vsen3 sd drive4 vesn4 fix 2 9 11 10 16 cout2 q3 +3.3vin 3.3v or 1.5v vout2 +12vin 10 2.2 m f cout4 1.8v q5 q4 cout3 14 vout4 15 vout3 19 18 1.5v 1 gnd 28 23 vcc 17 7 6 5 4 3 8 13 12 20 21 22 24 25 26 27 + + ugate1 phase1 lgate1 pgnd vsen1 fb nc vid0 vid1 vid2 vid3 vid4 pgood fault/rt ss cout1 css ocset1 l1 gnd +5vin d5820 1 m h l1 q2 q1 vout1
aic157 4 3 n ordering information order number pin configuration aic157 4 - c x aic157 4 cs (so2 8 ) packaging type s: small outline 1 3 4 2 5 7 6 8 9 10 vid 1 fix vid 4 vid 3 drive2 vid 2 vsen2 vid0 sd pgood 11 12 ss select phase1 vcc ugate1 ocset lgate1 pgnd 20 1 9 vsen1 vsen3 fb nc 28 26 27 25 24 23 21 22 1 8 1 7 gnd drive3 13 1 4 vsen4 fault/rt 1 6 15 drive4 vaux n absolute maximum ratings supply voltage, v cc ...............?????.....???? . ..??...?.. ??..................... +15v pgood, fault and gate voltage ...????.....??? .. ?.... gnd -0.3v to v cc +0.3v input, output , or i/o voltage ......?...????????.. ??............ gnd -0.3v to 7v recommended operating conditions supply voltage; vcc ??...............???? .. ................... +12v10% ambient temperature range ??.. ??????................. 0 c~70 c junction temperature range ??......? .. ?? . ................. 0 c~1 25 c thermal information thermal resistance, q ja soic package ??????????? .. ?? .. ?? . ............. 7 0 c/w soic package (with 3in 2 of copper) ?...??? .... .....?......... 5 0 c/w maximum junction temperature (plastic package) ??????? .. ??...... 150 c maximum storage temperature range ???????????.... -65 c ~ 150 c maximum lead temperature (soldering 10 sec) ??????????.. ?... 300 c n test circuit refer to application circuit.
aic157 4 4 n electrical characteristics (vcc=12v, tj=25 c , unless otherwise specified) parameter test conditions symbol min. typ. max. unit vcc supply current supply current ugate, lgate, gate3 and vout2 open i cc 3 ma power on reset rising vcc threshold vocset=4.5v v ccthr 10.4 v falling vcc threshold vocset=4.5v v ccthf 8.2 v rising vaux threshold vaux thr 2.5 v vaux threshold hy s teresis vaux hys 500 mv rising vocset1 threshold v ocseth 1.26 v oscillator free running frequency rt=open f 1 70 200 2 30 khz total variation 6k w 2.0v v reg2 3.3 v vsen3 regulation vol t age v reg3 1.5 v vsen3 regulation vol t age v reg4 1.8 v under-voltage level ( v sen /v reg ) v sen rising v senuv 75 % under-voltage hysteresis (v sen /v reg ) v sen falling 5 % output drive current (all linears ) v aux -v drive > 0.6v 20 30 ma
aic157 4 5 n electrical characteristics (conti n ued) parameter test conditions symbol min. typ. max. unit synchronous pwm controller amplifier dc gain (g.b.d.) 8 0 db gain-bandwidth product (g.b.d.) g bwp 13 mhz slew rate (g.b.d.) note 1. s r 6 v/ m s pwm controller gate driver upper drive source v cc =12v, v u gate = 6v i ugh 0.9 a upper drive sink v ug ate =1v r ugl 2.8 3.5 w lower drive source v cc =12v, v lgate =6v i lgh 1 a lower drive sink v lgate =1v r lgl 2.2 3.0 w protection vsen1 over-voltage ( v sen1 /d acout ) v sen1 rising ovp 116 120 % fault sourcing current v cc - v fault /r t =2.0v i ovp 20 ma ocset current source v ocset =4.5vdc i o cset 170 200 230 m a soft-start current i ss 25 m a power good v sen1 upper threshold ( v sen1 /da cout ) v sen1 rising 108 111 % v sen1 under-voltage ( vsen1/dacout ) v sen falling 92 95 % v sen1 hysteresis (vsen1/dacout) upper and lower threshold 2 % p good voltage low i pgood =-4ma v pgood 0.4 0.8 v note 1. without internal compensation network, the gain bandwidth product is 13mhz. being associated with i n - ternal compensation networks, the bode plot is shown in fig. 3, ? internal compensation gain of pwm error a m - plifier ? .
aic157 4 6 n typical performance characteristics pgood v out4 v out3 ss v out2 v out1 fig. 1 soft start interval with 4 outputs and p good ss vdac=3.5v vdac=2v vdac=1.3v fig. 2 soft start initiates pwm output 1k 10k 100k 1m -5 0 5 10 15 20 25 30 90 c internal compensation gain of pwm error amplifier gain (db) fig. 3 frequency (hz) -40 c 22 c 10k 100k 1m 1k 10k 100k 1m 10m r t pull up to 12v resistance ( w ) fig. 4 switching frequency (hz) r t pull down to gnd r t resistance vs. frequency 200k 300k 400k 500k 600k 700k 800k 900k 1m 0 20 40 60 80 100 120 c=0 c=680pf c=1.5nf c=3.3nf c=4.7nf v cc=12v c ug1 =c lg1 =c supply current vs. frequency i cc ( ma) fig. 5 switching frequency (hz) ss inductor current 5a/div over load applied fault over current on inductor fig. 6
aic157 4 7 n typical performance characteristics (continued) 0.1a to 3a load step v out fig. 7 load transient of linear controller -40 -20 0 20 40 60 80 100 120 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 f sw =200khz temperature vs. switching frequency drift switching frequency drift (%) fig. 8 temperature ( c) -40 -20 0 20 40 60 80 100 120 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 ocset current = 200 m a temperature vs. ocset current drift ocset current drift (%) fig. 9 temperature ( c) -40 -20 0 20 40 60 80 100 120 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 - 0 . 1 0.0 0.1 0.2 0.3 0.4 temperature drift of 9 different parts vreg2=3.3v vsen2 voltage drift (%) fig. 10 temperature ( c) - 40 - 20 0 20 40 60 80 100 120 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0 . 1 0.0 0.1 0 . 2 0 .3 0.4 temperature drift of 13 different parts dacout=1. 6 v pwm output voltage drift (%) fig. 11 temperature ( c) -40 -20 0 20 40 60 80 100 120 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 temperature drift of 9 different parts vreg4=1.8v vsen4 voltage drift (%) fig. 12 temperature ( c)
aic157 4 8 n typical performance characteristics (continued) v out1 0 to 20a load step fig. 13 load transient of pwm output 0 to 20a load step v out1 fig. 14 stringent load transient of pwm output -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0 10 20 30 40 50 60 mean= -0.03% 3 std.= 0.56% dacout=1. 6 v ta = 25 c fb voltage accuracy number of parts fig. 15 accuracy (%) 1.255 1.260 1.265 1.270 1.275 0 10 20 30 40 50 60 70 bandgap voltage accuracy fix=0v ta = 25 c mean=1.266v 3 std.= 0.8% number of parts fig. 16 bandgap voltage (v)
aic157 4 9 n block diagram ramp1 off dacout ramp1 inhb ov vsen1 por ss reset oc1 up luv ss por inhb ss inhb inhb nc fault / rt fb vcc vcc pgnd 3 p, 2z x 116% 1.26v vaux power on reset phase1 ugate1 comp. comp1 amp1 error drive2 vcc drv-h drv-l r r r 4v 0.2v 200ua fix vsen3 x 75% sd vcc vaux 1.5v or 3.3v x 75% vaux vsen2 select vaux drive4 drive3 logic soft start vsen4 ocset1 lgate1 gnd ss vid4 vid3 vid2 vid1 vid0 converter ttl d/a latch current oscillator control gate 4.5v 25ua x 110% x 90% vsen1 pgood vcc (3) counter latch fault over
aic157 4 10 n pin description pin 1: drive2: connect this pin to the gate of the external n-mos to supply agp power. pin 2 : fix: left this pin open, its voltage is pulled high, enabling fixed output voltage operation for 1.5v and 1.8v linear regulators. if connect this pin to ground, the new output voltage set by external resistors r gnd (connected b e - tween vsen and gnd) and r o ut (connected between vsen and vout ) . gnd out gnd out r ) r (r 1.265v v + = pin 7: vid4: pin 6: vid3: pin 5: vid2: pin 4: vid1: pin 3: vid0: 5bit dac voltage select pin. ttl- compatible inputs used to set the internal voltage reference vdac. when left open, these pins are i n - ternally pulled up to 5v and provide logic ones. the level of vdac sets the converter output voltage as well as the pgood and ovp thres h olds. table 1 specifies the vdac vol t - age for the 32 combinations of dac inputs. pin 8: pgood: power good indic ator pin. pgood is an open drain output. this pin is pulled low when the converter output is 10% out of the vdac reference voltage and the other outputs are below their under-voltage thresholds. the pgood output is open for vid codes that inhibit operation. see t able 1. pin 9 : sd: a ttl-compatibe logic level high signal applied this pin immediately discharges the soft-start capacitors, di s - abling all the outputs. dedicated internal circuitry insures the core output voltage does not go ne c - tive during this process. when re-enabled, this ic undergoes a new soft-start cycle. left open, this pin is pulled low by an inte r - nal pull-down resistor, enabling oper a tion. pin 10:vsen2: connect this pin to the output of the agp linear regulator. the voltage at this pin is regulated to the 1.5v/3.3v predetermined by the logic low/high level ststus of the select pin. this pin is also monitored for under-voltage events. pin 11:select: this pin determines the output voltage of the agp bus linear regulator. a low ttl input sets the output voltage to 1.5v, while a high input sets the output vol t - age to 3.3v.
aic157 4 11 pin 12:ss: soft-start pin. connect a c a - pacitor from this pin to ground. this capacitor, along with an internal 2 5 m a (typically) cu r - rent source, sets the soft-start interval of the converter. pulling this pin low will shut down the ic. pin 13: fault/rt: frequency adjustment pin. connecting a resistor (rt) from this pin to gnd, increa s - ing the frequency. connecting a resistor (rt) from this pin to vcc, decreasing the freque n - cy by the following figure (fig. 4 ). this pin is 1.26v during normal operation, but it is pulled to vcc in the event of an over- voltage or over-current cond i tion. ? ? ? ? ? + = t r k . f f 2 25 1 0 , r t pulled to gnd ? ? ? ? ? - - = t r v vcc f f 5 26 . 1 1 0 , r t pulled to vcc, where 0 f is free run frequency. pin14: vsen4: connect this pin to the 1.8v linear regulator?s output. this pin is monitored for under- voltage events. pin15: drive4: connect this pin to the gate of the external n-mos to drive for the 1~8v power. pin 16: vaux: this pin provides boost current for the linear regulator?s output. the voltage at this pin is also mon i - tored for power-on-reset purpose. pin 17: gnd: signal gnd for ic. all voltage le v - els are measured with respect to this pin. pin 18: drive3: connect this pin to the gate of the external n-mos for providing 1.5v power to gtl bus. pin 19: vsen3: connect this pin to the 1.5v linear regulator?s output. this pin is monitored for under- voltage events. pin 20: nc: not connected. pin 21: fb: the error amplifier inverting input pin. pin 22: vsen 1 : converter output voltage sense pin. connect this pin to the co n - verter output. the pgood and ovp comparator circuits use this signal to report output vol t - age status and for over-voltage protection fun c tion. pin 23: ocset :current limit sense pin. connect a resistor r ocset from this pin to the drain of the external high- side n-mosfet. r ocset , an i n - ternal 200 m a current source (i ocset ), and the upper n- mosfet on-resistance ( r ds( on) ) set the over-current trip point according to the following equ a - tion: ds(on) ocset ocset peak r r i i = pin 24:pgnd: driver power gnd pin. pgnd should be connected to a low impedance ground plane in close to lower n-mosfet source.
aic157 4 12 pin 25: lgate: lower n-mosfet gate drive pin. pin 26: phase: over-c urrent detection pin. co n - nect the phase pin to source of the external upper n-mosfet. this pin detects the voltage drop across the upper n-mosfet r ds( on) for over-current prote c tion. pin 27: ugate: connect ugate to pin of the e x - ternal upper n-mosfet gate. pin 28: vcc: the chip power supply pin. it a lso provides the gate bias charge for all the mosfets controlled by the ic. recommended supply voltage is 12v. the voltage at this pin is monitored for power-on- reset purpose. n application informations the AIC1574 is designed for microprocessor computer applications with 3.3v and 5v power, and 12v bias i n - put. this ic has one synchronous pwm controller and three linear controllers. the pwm controller is de s - igned to regulate the microprocessor core voltage (v out 1 ) by driving 2 mosfets (q1 and q2) in a sy n - chronous rectified buck converter configuration. the core voltage is regulated to a level programmed by the 5-bit d/a converter. one of the linear controllers is designed to regulate the advanced graphic port (agp) bus voltage (v out2 ) to a digitally programmable level 1.5v or 3.3v. selection of either output voltage is achieved by applying the proper logic level at the s e - lect pin. the remaining two linear controllers supply the 1.5v gtl bus power (v out3 ) and 1.8v memory power (v out4 ). all linear controllers are designed to employ an external pass transistor. the power-on reset (por) function continually mon i - tors the input supply voltage +12v at vcc pin, the 5v input voltage at ocset pin, and the 3.3v input at vaux pin. the por function initiates soft-start oper a - tion after all three input supply voltage exceed their por thres h olds. soft-start the por function initiates the soft-start sequence. a n internal 2 5 a current source charges an external c a - pacitor (c ss ) on the ss pin from 0v to 4.5v. the pwm error amplifier reference input (non-inverting te r - minal) and output is clamped to a level proportional to the ss pin voltage. as the ss pin voltage slew from 1v to 4v, the output clamp generates phase pulses of increasing width that charge the output capacitors. a f - ter the the output voltage increases to approximately 70% of the set value, the reference input clamp slows the output voltage rate-to rise and provides a smooth transi t ion to the final set voltage. additionally, all linear regulator?s reference inputs are clamped to a voltage proportional to the ss pin voltage. this method provides a rapid and controlled output voltage rise. fig. 1 and fig. 2 show the soft-start sequence for the typical application. the internal oscillator?s triangular waveform is compared to the clamped error amplifier output voltage. as the ss pin voltage increases, the pulse width on phase pin increases. the interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input refe r - ence clamp. each linear output initially follows a ramp. when each output reaches sufficient voltage the input reference clamp slows the rate of output voltage rise. the pgood signal toggles ?high? when all output voltage levels have exceeded their under-voltage levels. fault protection all four outputs are monitored and protected against
aic157 4 13 extreme overload. a sustained overload on any output or over-voltage on pwm output disable all converters and drive the fault/rt pin to vcc. + + 0.15v ov latch over current 4.0v ss oc1 r luv q s fault vcc fault latch por q r s r s counter inhibit fig. 1 7 simplified schematic of fault logic a simplified schematic is shown in figure 1 7 . an over-voltage detected on vsen1 immediately sets the fault latch. a sequence of three over-current fault signals also sets the fault latch. an under- voltage event on either linear output (vsen2, vsen3, vsen4) is ignored until the soft-start inte r - val. cycling the bias input voltage (+12v off then on) resets the counter and the fault latch. gate drive overlap protection the overlap protection circuit ensures that the bo t - tom mosfet does not turn on until the upper mosfet source has reached a voltage low enough to ensure that shoot-through will not occur. over-voltage protection during operation, a short on the upper pwm mosfet (q1) causes v out1 to increase. when the output exceed the over-voltage threshold of 11 6 % of dacout, the fault pin is set to fault latch and turns q2 on as required in order to reg u - late vout1 to 115% of dacout. the fault latch raises the fault/rt pin close to vcc p o tential. a separate over-voltage circuit provides protection during the initial application of power. for voltage on vcc pin below the power-on reset (and above ~4v), should vsen1 exceed 1. 0 v, the lower mosfet (q2) is driven on as needed to regulate vout1 to 1. 0 v. over-current protection all outputs are protected against excessive over- current. the pwm controller uses upper mosfet?s on-resistance, r ds( on) to monitor the current for protection against shorted outputs. all linear controllers monitor vsen for under-voltage events to protect against exce s sive current. when the voltage across q1 (id ?e r ds(on) ) exceeds the level (200 m a ?e r ocset ), this signal inhibit all outputs. discharge soft-start capacitor (css) with 25 m a current sink, and increments the counter. css recharges and initiates a soft-start cycle again until the counter increments to 3. this sets the fault latch to disable all outputs. fig. 6 illustrates the over-current protection until an over load on out1. should excessive current cause vsen to fall below
aic157 4 14 the linear under-voltage threshold, the luv signal sets the over-current latch if c ss is fully charged. cycling the bias input power (off then on ) reset the cou n ter and the fault latch. the over-current function for pwm controller will trip at a peak inductor current (i peak ) determined by: i i r r peak ocset ocset ds(on) = the oc trip point varies with mosfet?s temper a - ture. to avoid over-current tripping in the normal o p - erating load range, determine the r o c set resistor from the equation above with: 1. the maximum r ds( on) at the temperature. 2. the minimum i ocset from the specification t a ble. 3. determine i peak > i out( max) + (inductor ripple cu r rent) /2. pwm out1 voltage program the output voltage of the pwm converter is pr o - grammed to discrete levels between 1.3v to 3.5v. the vid pins program an internal voltage reference (dacout) through a ttl compatible 5 bit digital to analog converter. the vid pins can be left open for a logic 1 input, because they are internally pulled up to 5v by a 70 k w resistor. changing the vid i n - puts during operation is not recommended. all vid pin combinations resulting in an inhibit disable the ic and the open colle c tor at the pgood pin. out2 voltage program the agp regulator output voltage is internally set to one of two discrete levels based on the select pin status. left select pin open, internal pulled high , the output voltage is 3.3v. grounding s e - lect pin to ground will get the 1.5v output vol t - age. the status of the select pin can not be changed during operation of the ic without immediatelly causing a fault condition. out3 and out4 voltage program the gtl bus voltage (1.5v, out3) and the chip set and/or cache memorey voltage (1.8v,out4) are i n - ternally set for simpe, low cost implementation b a - se on the fix pin left open. grounding fix pin a l - lows both output voltages to be set by means of e x - ternal resistor dividers. + AIC1574 fix drv vsen rgnd rout vout 3.3v ? ? ? ? ? + = gnd out out r r 1 265 . 1 v v adjusting the output voltage of output 3 and 4 shutdown the AIC1574 features a dedicated shetdown pin (sd). a ttl-compatible logic high signal applied to this pin shuts down all four outputs and discharge the soft-start capacitor. the vid codes resulting in an inhibit as shown in table 1 also shut down the ic. n application guide lines layout considerations any inductance in the switched current path gene r - ates a large voltage spike during the switching i n - terval. the voltage spikes can degrade efficiency,
aic157 4 15 radiate noise into the circuit, and lead to device over-voltage stress. careful component selection and tight layout of critical components, and short, wide metal trace min i mize the voltage spike. a ground plane should be used. locate the input capacitors (c in ) close to the power switches. minimize the loop formed by c in , the upper mosfet (q1) and the lower mosfet (q2) as possible. connections should be as wide as short as possible to minimize loop i n ductance. the connection between q1, q2 and output indu c - tor should be as wide as short as practical. since this connection has fast voltage transitions will e a - sily i n duce emi. the output capacitor (c out ) should be located as close the load as possible. because minimize the transient load magnitude for high slew rate requires low inductance and resistance in circuit board the AIC1574 is best placed over a quiet ground plane area. the gnd pin should be connected to the groundside of the output capacitors. under no circumstances should gnd be returned to a ground inside the c in , q1, q2 loop. the gnd and pgnd pins should be shorted right at the ic. this help to minimize internal ground disturbances in the ic and prevents differences in ground potential from di s - rupting internal circuit operation. the wiring traces from the control ic to the mo s - fet gate and source should be sized to carry peak current. the vcc pin should be decoupled directly to gnd by a 2.2 m f ceramic capacitor, trace lengths should be as short as possible.
aic157 4 16 table 1 vout1 voltage program (0=connected to gnd, 1=open or connected to 5v) for all package version s pin name pin name vid4 vid3 vid2 vid1 vid0 dacout voltage vid4 vid3 vid2 vid1 vid0 dacout voltage 0 1 1 1 1 1.30v 1 1 1 1 1 inhibit 0 1 1 1 0 1.35v 1 1 1 1 0 2.1 v 0 1 1 0 1 1.40v 1 1 1 0 1 2.2 v 0 1 1 0 0 1.45v 1 1 1 0 0 2.3 v 0 1 0 1 1 1.50v 1 1 0 1 1 2.4 v 0 1 0 1 0 1.55v 1 1 0 1 0 2.5 v 0 1 0 0 1 1.60v 1 1 0 0 1 2.6 v 0 1 0 0 0 1.65v 1 1 0 0 0 2.7 v 0 0 1 1 1 1.70v 1 0 1 1 1 2.8 v 0 0 1 1 0 1.75v 1 0 1 1 0 2.9 v 0 0 1 0 1 1.80 v 1 0 1 0 1 3.0 v 0 0 1 0 0 1.85 v 1 0 1 0 0 3.1 v 0 0 0 1 1 1.90 v 1 0 0 1 1 3.2 v 0 0 0 1 0 1.95 v 1 0 0 1 0 3.3 v 0 0 0 0 1 2.00 v 1 0 0 0 1 3.4 v 0 0 0 0 0 2.05 v 1 0 0 0 0 3.5 v a multi-layer-printed circuit board is reco m - mended. figure 11 shows the connections of the critical components in the converter. the c in and c out could each represent numerous physical capacitors. dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. pwm output capacitors the load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demand. the esr (equivalent series resistance) and esl (equivalent series inductance) parameters rather than actual capacitance determine the buck c a - pacitor values. for a given transient load magn i - tude, the output voltage transient change due to the output capacitor can be note by the follo w - ing equ a tion: d d d d v esr i esl i t out out out = + , where d i out is transient load current step. after the initial transient, the esl dependent term drops off. because the strong relationship between output capacitor esr and output load transient, the output capacitor is usually chosen for esr, not for capacitance value. a capacitor with suitable esr will usually have a larger c a - pacitance value than is needed for energy sto r - age. a common way to lower esr and raise ripple
aic157 4 17 current capability is to parallel several capac i - tors. in most case, multiple electrolytic capac i - tors of small case size are better than a single large case c a pacitor. output inductor selection inductor value and type should be chosen based on output slew rate requirement, output ripple requirement and expected peak current. indu c - tor value is primarily controlled by the required current response time. the aic1570 will provide either 0% or 100% duty cycle in response to a load transient. the response time to a transient is different for the application of load and remove of load. t l i v v rise out in out = - d , t = l i v fall out out d . where d i out is transient load current step . in a typical 5v input, 2v output application, a 3 m h inductor has a 1a/ m s rise time, resulting in a 5 m s delay in responding to a 5a load current step. to optimize performance, different comb i - nations of input and output voltage and expected loads may require different inductor value. a smaller value of inductor will improve the tra n - sient response at the expense of increase ou t - put ripple voltage and inductor core saturation rating. peak current in the inductor will be equal to the maximum output load current plus half of indu c - tor ripple current. the ripple current is approx i - mately equal to: i = (v v ) v l v ripple in out out in - f ; f = AIC1574 oscillator frequency. the inductor must be able to withstand peak current without saturation, and the copper resi s - tance in the winding should be kept as low as possible to min i mize resistive power loss input capacitor selection most of the input supply current is supplied by the input bypass capacitor , the resulting rms current flow in the input capacitor will heat it up. use a mix of input bulk capacitors to control the voltage overshoot across the upper mosfet. the ceramic capacitance for the high frequency decoupling should be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedance. the buck c a - pacitors to supply the rms current is approx i - mate equal to: i (1 d) d i 1 12 v d f l rms 2 out in 2 = - + ? ? ? ? , where d v v out in = the capacitor voltage rating should be at least 1.25 times greater than the maximum input vol t - age. pwm mosfet selection in high current pwm application, the mosfet power dissipation, package type and heatsink are the dominant design factors. the conduction loss is the only component of power dissipation for the lower mosfet, since it turns on into near zero voltage. the upper mosfet has co n - duction loss and switching loss. the gate cha r - ge losses are proportional to the switching fr e - quency and are dissipated by the AIC1574. however, the gate charge increases the switc h - ing interval, t sw , which increase the upper mo s - fet switching losses. ensure that both mo s - fets are within their maximum junction te m -
aic157 4 18 perature at high ambient temperature by calc u - lating the temperature rise according to package thermal resistance specific a tions. p i r d i v t f 2 upper out 2 ds(on) out in sw = + d) 1 ( r i p ds(on) 2 out lower - = the equations above do not model power loss due to the reverse recovery of the lower mosfet?s body d i ode. the r ds( on) is different for the two previous equations even if the type devices is used for both. this is because the gate drive applied to the upper mosfet is different than the lower mosfet. logic level mosfets should be s e - lected based on on-resistance considerations, r ds( on) should be chosen base on input and output voltage, allowable power dissipation and maximum required output current. power diss i - pation should be calculated based primarily on required efficiency or allowable thermal dissip a - tion. rectifier schottky diode is a clamp that prevent the loss parasitic mosfet body diode from conducting during the dead time between the turn off of the lower mosfet and the turn on of the upper mosfet. the diode?s rated reverse breakdown voltage must be greater than twice the maximum input voltage. linear controller mosfet selection the power dissipated in a linear regulator is : ) v (v i p out2 in2 out2 linear - = select a package and heatsink that maintains junction temperature below the maximum rating while operation at the highest expected ambient te m perature. linear output capacitor the output capacitors for the linear regulator and linear controller provide dynamic load current. the linear controller uses dominant pole co m - pensation integrated in the error amplifier and is insensitive to output capacitor selection. c out2 , c out3 and c out4 should be selected for tra n - sient load regulation. pwm feedback analysis + vdac v out vea pwm comp. networks compensation error amp. r esr l o d v osc c o q2 q1 v in modulation gain
aic157 4 19 the compensation network consists of the error amplifier and built in compensation networks. the goal of the compensation network is to provide for fast response and adequate phase margin. phase margin is the difference between the closed loop phase at 0db and 180 degree. closed loop gain(db) = modulation gain(db) + co m pensation gain (db) modulation gain(db) ? ? ? ? ? ? ? ? ? ? ? + + ? ? ? ? ? d ? 2 1 log 10 log 20 esr osc in f f v v ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? - - 2 2 2 1 log 10 q f f f f lc lc where o o lc c l f p 2 1 = ; o esr esr c r f = p 2 1 ; load o o esr o o r c l r l c q 1 1 + = the break frequency of internal compensation gain are given by khz f z 6 . 2 1 = ; khz f z 24 2 = ; khz f p 30 1 = ; khz f p 400 2 = 100 1k 10k 100k 1m 10m -20 0 20 40 60 f frequency ( khz) f odb 20log(v in / d v osc ) f esr f lc f z1 f z2 f p2 f p1 modulation gain compensation gain closed loop gain gain (d b ) bode plot of converter gain sampling theory shows that f 0db must be less that half the switching frequency for the loop stables . but it must be considerably less than that, or there will be large amplitude switching frequency ripple at the output. thus, the usual practices is to fix f 0db at 1/4 to 1/5 the switching frequency.
aic157 4 20 n physical dimensions l 2 8 lead plastic so (unit: mm) symbol min max a 2.35 2.65 a1 0.10 0.30 b 0.33 0.51 c 0.23 0.32 d 17.70 18.10 e 7.40 7.60 e 1.27 (typ) h 10.00 10.65 l 0.40 1.27 d c l e h e b a a1

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