1 extended commercial temperature range idt74lvc14a 3.3v cmos hex schmitt-trigger inverter february 2000 2000 integrated device technology, inc. dsc-4592/- c idt74lvc14a extended commercial temperature range description: the lvc14a hex schmitt-trigger inverter is built using advanced dual metal cmos technology. this device contains six independent inverters and performs the boolean function y = a . inputs can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v supply system. the lvc14a has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. functional block diagram soic/ ssop/ tssop top view features: C 0.5 micron cmos technology C esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) C 1.27mm pitch soic, 0.65mm pitch ssop and 0.65mm pitch tssop packages C extended commercial range of C 40c to +85c Cv cc = 3.3v 0.3v, normal range Cv cc = 2.3v to 3.6v, extended range C cmos power levels (0.4 w typ. static) C rail-to-rail output swing for increased noise margin C all inputs, outputs and i/o are 5 volt tolerant C supports hot insertion pin configuration 3.3v cmos hex schmitt- trigger inverter with 5 volt tolerant i/o drive features for lvc 14a: C high output drivers: 24ma C reduced system switching noise pin description pin names description xa inputs xy outputs ay 2 3 1 1 y v cc 1 a 5 6 4 gnd 7 13 12 14 10 9 11 8 2 a 3 a 2 y 3 y 6 y 6 a 5 a 4 a 5 y 4 y so14-1 so14-2 so14-3 function table (each inverter) (1) inputs outputs xa xy hl lh note: 1. h = high volta g e level l = low volta g e level applications: ? 5v and 3.3v mixed voltage systems ? data communication and telecommunication systems
2 extended commercial temperature range idt74lvc14a 3.3v cmos hex schmitt-trigger inverter 1998 integrated device technology, inc. dsc-123456 c capacitance (t a = +25c, f = 1.0mh z ) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf lvc quad link note: 1. as applicable to the device type. absolute maximum ratings (1) symbol description max. unit v term terminal voltage with respect to gnd C 0.5 to +6.5 v t stg storage temperature C 65 to +150 c i out dc output current C 50 to +50 ma i ik i ok continuous clamp current, v i < 0 or v o < 0 C 50 ma i cc i ss continuous current through each v cc or gnd 100 ma lvc quad link note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = C 40c to +85c symbol parameter test conditions min. typ. (1) max. unit i ih i il input leakage current v cc = 3.6v v i = 0 to 5.5v 5 a i off input/output power off leakage v cc = 0v, v in or v o 5.5v 50a v ik clamp diode voltage v cc = 2.3v, i in = C 18ma C 0.7 C 1.2 v i ccl i cch quiescent power supply current v cc = 3.6v v in = gnd or v cc 10a d i cc quiescent power supply current variation one input at v cc C 0.6v other inputs at v cc or gnd 500 a note: 1. typical values are at v cc = 3.3v, +25c ambient.
3 extended commercial temperature range idt74lvc14a 3.3v cmos hex schmitt-trigger inverter output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = C 0.1ma v cc C 0.2 v v cc = 2.3v i oh = C 6ma 2 v cc = 2.3v i oh = C 12ma 1.7 v cc = 2.7v 2.2 v cc = 3.0v 2.4 v cc = 3.0v i oh = C 24ma 2.2 v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma 0.2 v v cc = 2.3v i ol = 6ma 0.4 i ol = 12ma 0.7 v cc = 2.7v i ol = 12ma 0.4 v cc = 3.0v i ol = 24ma 0.55 lvc quad link note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriate v cc range. t a = C 40c to +85c. hysteresis characteristics parameter test conditions v cc min. typ. max. unit v t+ positive-going threshold input voltage, from v il to v ih , in a linear ramp observing the output transition. 2.7v 3v 3.6v 0.8 0.8 0.8 2 2 2 v v tC negative-going threshold input voltage, from v ih to v il , in a linear ramp observing the output transition. 2.7v 3v 3.6v 0.4 0.6 0.8 1.4 1.5 1.8 v d v t hysteresis (v t+ C v tC ) d v t min = | v t+ min C v t- max | d v t max = | v t+ max C v t- min | 2.7v 3v 3.6v 0.3 0.3 0.3 1.1 1.2 1.2 v operating characteristics, v cc = 3.3v 0.3v, t a = 25c symbol parameter test conditions typical unit c pd power dissipation capacitance per inverter c l = 0pf, f = 10mhz 7 pf switching characteristics (1) v cc = 2.5v0.2v v cc = 2.7v v cc = 3.3v0.3v symbol parameter min max min max min max unit t plh t phl propagation delay xa to xy 7.5 1 6.4 ns tsk(o) output skew (2) 1 ns notes: 1. see test circuits and waveforms. t a = C 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction.
4 extended commercial temperature range idt74lvc14a 3.3v cmos hex schmitt-trigger inverter open v load gnd v cc pulse generator d.u.t. 500 w 500 w c l r t v in v out (1, 2) lvc quad link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 lvc quad link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t low-high-low pulse high-low-high pulse v t t w same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v t v ih v t v t v ih v t control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz lvc quad link lvc quad link lvc quad link lvc quad link test cir cuits and w a veforms test conditions propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times switch position output skew - tsk (x) pulse width symbol v cc (1) = 2.5v 0.2v v cc (2) = 3.3v 0.3v & 2.7v unit v load 2 x vcc 6 v v ih vcc 2.7 v v t v cc / 2 1.5 v v lz 150 300 mv v hz 150 300 mv c l 30 50 pf lvc quad link definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. 2. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. note: 1. diagram shown for input control enable-low and input control disable-high. test switch open drain disable low enable low v load disable high enable high gnd all other tests open lvc quad link notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank.
5 extended commercial temperature range idt74lvc14a 3.3v cmos hex schmitt-trigger inverter corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information idt xx lvc xxx xx package device type hex schmitt-trigger inverter with 5 volt tolerant i/o, 24ma 14a dc py pg small outline ic (so14-1) shrink small outline package (so14-2) thin shrink small outline package (so14-3) temp. range 74 C40c to +85c
|
