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| www.littelfuse.com ?2011 littelfuse pgb2 series speci?cations are subject to change without notice. 1 revised: march 8, 2011 pulseguard ? suppressors surface mount polymeric esd suppressors pulseguard esd suppressors help protect sensitive electronic equipment against electrostatic discharge (esd). they use polymer composite materials to suppress fast- rising esd transients (as speci?ed in iec 61000-4-2), while adding virtually no capacitance to the circuit. they supplement the on-chip protection of integrated circuitry and are best suited for low-voltage, high-speed applications where low capacitance is important to ensure minimal interference of data signal integrity. the new and ultra-small surface mount pgb2 0402 series offers a rohs compliant, halogen free, and 100% lead free circuit protection alternative. pgb2 series halogen free / lead-free description features applications t ) % 5 7 ) b s e x b s f t - b q u p q % f t l u p q computer t / f u x p s l ) b s e x b s f t $ p n q v u f s 1 f s j q i f s b m t t % j h j u b m $ b n f s b t & y u f s o b m 4 u p s b h f t 4 f u 5 p q # p y t " o u f o o b t 3 p ) 4 d p n q m j b o u t - f b e g s f f t ) b m p h f o g s f f t 6 m u s b m p x d b q b d j u b o d f t - p x m f b l b h f d v s s f o u t ' b t u s f t q p o t f u j n f t 0 o f m j o f p g q s u f d u j p o t # j e j s f d u j p o b m t 8 j u i t u b o e t n v m u j q m f & 4 % t u s j l f t t $ p n q b u j c m f x j u i q j d l b o e q m b d f q s p d f t t f t equivalent circuits 2 1 product characteristics part number lines protected component package PGB2010402KRHF 1 0402 electrical characteristics speci?cation pgb2010402 notes esd capability: iec 61000-4-2 direct discharge * & $ " j s % j t d i b s h f l 7 l 7 5 s j h h f s 7 p m u b h f u z q j d b m $ m b n q j o h 7 p m u b h f u z q j d b m 7 7 measured per iec 61000-4-2 l 7 % j s f d u % j t d i b s h f . f u i p e 5 s j h h f s 7 p m u b h f u z q j d b m $ m b n q j o h 7 p m u b h f u z q j d b m 7 7 . f b t v s f e v t j o h 7 5 - 1 % j s f d u discharge method 3 b u f e 7 p m u b h f n b y j n v n 7 % $ n b y capacitance (typical) 0.07 pf, typical measured at 250 mhz response time <1ns measured per iec 61000-4-2 l 7 % j s f d u % j t d i b s h f . f u i p e - f b l b h f $ v s s f o u u z q j d b m o " . f b t v s f e b u 7 % $ & 4 % 1 v m t f 8 j u i t u b o e 1000 pulses min some shifting in characteristics may occur when tested over multiple pulses at a very rapid rate www.littelfuse.com ?2011 littelfuse pgb2 series speci?cations are subject to change without notice. 2 revised: march 8, 2011 pulseguard ? suppressors surface mount polymeric esd suppressors typical device capacitance typical esd response curve l 7 * & $ % j s f d u % j t d i b s h f 0 100 200 300 400 500 -25 0 25 50 75 100 125 150 175 time (ns) voltage (v) dimensions 0.559 (0.022") recommended for re?ow soldering only 0.381 (0.015") .584 (0.023") 1.55 (0.061") recommended pad layout 0.99 +/- 0.05 (0.039" +/- 0.002") 0.51 +/- 0.05 (0.020" +/- 0.002") 0.23 nom. (0.009") 0.23 +/- 0.10 (0.009" +/- 0.004") 0.18 +/- 0.10 (0.007" +/- 0.004") 0.30 +/- 0.08 (0.012" +/- 0.003") part numbering system pgb2 01 0402 kr hf quantity & packaging code: k r = 10,000 pieces lines protected: 01 = 1 line device size code: 0402 = 0402 (100 5 ) lead-free halogen-free pulseguard ? esd suppressors halogen free dimensions: mm (inch) typical tlp response curve 7 % j s f d u % j t d i b s h f typical insertion loss 0 50 100 150 200 -15 0 15 30 45 60 75 time (ns) voltage (v) -12 -10 -8 -6 -4 -2 0 2 10 100 1000 10000 100000 frequency (mhz) insertion loss (db) 0.01 0.1 100 1000 10000 frequency (mhz) capacitance (pf) www.littelfuse.com ?2011 littelfuse pgb2 series speci?cations are subject to change without notice. 3 revised: march 8, 2011 pulseguard ? suppressors surface mount polymeric esd suppressors environmental speci?cations operating temperature -65c to +125c biased humity: biased heat: 40c, 95% rh, 1000 hours 85c, 1000 hours thermal shock mil-std-202, method 107g, -65c to 125c, 30 min. cycle, 10 cycles vibration . * - 4 5 % . f u i p e " chemical resistance mil-std-202, method 215 solder leach resistance and terminal adhesion * 1 $ & * " + 4 5 % physical speci?cations materials # p e z & q p y z ( m b t t 4 v c t u s b u f 5 f s n j o b u j p o t $ v / j 4 o device weight 0.349 mg solderability mil-std-202, method 208 soldering parameters 8 b w f t p m e f s ? $ t f d p o e t n b y j n v n 3 f n p x t p m e f s ? $ t f d p o e t n b y j n v n design consideration because of the fast rise-time of the esd transient, proper q m b d f n f o u p g 1 v m t f ( v b s e t v q q s f t t p s t b s f b l f z e f t j h o consideration to achieving optimal esd suppression. the devices should be placed on the circuit board as close to the source of the esd transient as possible. install pulseguard t v q q s f t t p s t d p o o f d u f e g s p n t j h o b m e b u b m j o f u p h s p v o e directly behind the connector so that they are the ?rst board- level circuit component encountered by the esd transient. soldering parameters re?ow condition pb C free assembly pre heat - temperature min (t s(min) ) 150c - temperature max (t s(max) ) 200c - time (min to max) (t s ) 60 C 180 seconds average ramp up rate (liquidus temp (t l ) to peak ? $ t f d p o e n b y t s(max) to t l - ramp-up rate ? $ t f d p o e n b y re?ow - temperature (t l ) (liquidus) 217c - temperature (t l ) 60 C 150 seconds peak temperature (t p ) 260c time within 5 c of actual peak temperature (t p ) 10 C 30 seconds ramp-down rate ? $ t f d p o e n b y time 2 5 c to peak temperature (t p ) n j o v u f t n b y notes: - pgb2 series recommended for re?ow soldering only 3 f d p n n f o e f e q s p m m f c b t f e p o * 1 $ + & % & % + 4 5 % $ - for recommended soldering pad layout dimensions, please refer to dimensions section of this data sheet www.littelfuse.com ?2011 littelfuse pgb2 series speci?cations are subject to change without notice. 4 revised: march 8, 2011 pulseguard ? suppressors surface mount polymeric esd suppressors typical esd pulse test setup agilent infiniium 1.5 ghz 8 gs/s 30db pasternak attenuator pe7025-30 tektronix low cap probe 6158 (20x tip) resistance test fixture quadtech 1865 resistance meter computer faraday cage esd pulse generator test board w/ dut esd test fixture tape and reel speci?cations description 0402 series (mm) c t $ p w f s u b q f u i j d l o f t t 0.053 d d - drive hole diameter 1.55 d s - drive hole spacing 4.00 p d 1 p d l f u e f q u i 0.41 p h 1 p d l f u i f j h i u 1. 12 p s 1 p d l f u t q b d j o h 2.00 p w 1 p d l f u x j e u i 0.62 t t $ b s s j f s u b q f u i j d l o f t t 0.61 t w - carrier tape width 8.00 t w d s p h p d d d c t p s p w t t packaging part number quantity & packaging code quantity packaging option packaging speci?cation pgb2010402 kr 10000 t ape & reel (7 reel) & * " 3 4 * & $ q b s u carrier tape: 8mm, paper reel: 7 (178mm) notes: - quadquadtech 1865 high resistance meter: measures insulation resistance values , f z 5 f l . j o j ; b q & 4 % t j n v m b u p s x j u i * & $ u j q 4 j n v m b u f t l 7 e j s f d u e j t d i b s h f & 4 % f w f o u q f s * & $ - faraday cage: shields the acquisition equipment from the electromagnetic ?elds generated by the simulator " h j m f o u ( ) [ " 0 t d j m m p t d p q f 3 f d p s e t u i f w p m u b h f x b w f g p s n g s p n u i f e f w j d f v o e f s u f t u 5 f l u s p o j y q s p c f x j u i e # b u u f o v b u p s 5 s b o t n j u t u i f x b w f g p s n g s p n u i f e f w j d f u p u i f p t d j m m p t d p q f www.littelfuse.com ?2011 littelfuse pgb2 series speci?cations are subject to change without notice. 5 revised: march 8, 2011 pulseguard ? suppressors surface mount polymeric esd suppressors two of the most common methods used in industry for characterizing the performance of esd suppressors are esd transient testing, per iec 61000-4-2 esd wavef orm, b o e 5 - 1 4 j o d f o p t u b o e b s e t f y j t u g p s n f b t v s f n f o u b o e quali?cation of esd suppressor performance, these two methods have become the de-facto standard for determining device trigger and clamp speci?cations. it is common to see trigger values to be based on the tlp method and clamping values based on the esd transient method. low voltage tlp obtained trigger values most closely resemble device dc turn-on .since the two test n f u i p e t b s f e j g g f s f o u b o e o p n f u i p e f y j t u t u p b d d v s b u f m z correlate suppressor response between the two test methods, trigger and clamp values should be speci?ed for each method. esd transient testing, which is based on the iec 61000-4-2 standard wavef orm, consists of subjecting a esd suppressor to an subnanosecond risetime 8kv transient generated by a commercial esd simulator and recording trigger and clamp voltage levels. clamp voltage level is obtained at 25ns. the basic esd simulator circuit consists p g b 3 $ e j t d i b s h f o f u x p s l x j u i 3 b o e $ w b m v f t p g p i n t b o e q j d p g b s b e t 8 b w f g p s n t b s f d b q u v s f e v t j o h b 4 ghz oscilloscope(50 ohm input) with 20x resistive divider probes and a 30db attenuator. figures 1 and 2 show iec current wavef orm and test setup. 5 s b o t n j t t j p o m j o f 1 v m t f u f t u j o h d p n n p o m z l o p x b t tlp testing consists of subjecting a esd suppressor to a 50 ohm transmission line discharge pulse with a subnanosecond risetime and a pulse width of 65ns. trigger values are obtained by varying the tlp voltage until a e f w j d f u s j h h f s w p m u b h f j t e f u f s n j o f e 0 o d f u i f e f w j d f j t u s j h h f s f e b d m b n q w b m v f j t e f u f s n j o f e b u o t 8 b w f g p s n t are captured using a 4 ghz oscilloscope(50 ohm input) with 20x resistive divider probes and a 30db attenuator. figures 3 and 4 show a typical tlp voltage wavef orm and test setup. * u t i p v m e c f o p u f e u i b u o p n f b t v s f n f o u t u b o e b s e f y j u t for obtaining trigger and clamp voltage levels. trigger and clamp values will vary from one test setup to another. due to the subnanosecond risetime of esd and tlp wavef orms, any parasitic inductance and capacitance in u i f u f t u t z t u f n x j m m b g g f d u n f b t v s f n f o u t " o z f g g f d u t due to inductance and capacitance need to be subtracted from the ?nal measurement. it is important to remember that the test system will introduce a load across the esd suppressor under test and this will also affect n f b t v s f n f o u t " i j h i c b o e x j e u i 0 i n p t d j m m p t d p q f and probes(>1ghz) need to be used for obtaining best s f t v m u t " u u f o v b u j p o w b m v f t g p s u i f q s p c f u j q t i p v m e c f at least 20x in order to obtain high input impedance for measurements. characterization methods for esd suppressors time in nanoseconds 020406080 volts 0 100 200 300 400 5 00 600 100% 90% i i 10% 30n 60n tr = 0.7 to 1.0ns current (i) % 30 60 5 0 3.16 5 1 5 0pf 8000 dut 12 330 9 5 0 46.93 46.93 + - esd simulator scope probe 30db attenuator 50 ohm scope input 50 ohm scope input 5 0 3.16 5 5 00 dut 12 9 5 0 46.93 46.93 + - tlp scope probe 30db attenuator figure 3 figure 4 figure 1 figure 2 |
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