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cmos-ccd 1h/2h delay line for ntsc description the cxl5509m/p is a cmos-ccd delay line developed for video signal processing. usage in conjunction with an external low-pass filter provide 1h and 2h delay signals simultaneously (for ntsc signals). features single power supply (5v) low power consumption 130mw (typ.) built-in peripheral circuits built-in quadruple pll circuit for ntsc signals 1 input and 2 outputs (outputs for both 1h and 2h delays) functions 906-bit (1h) and 1816-bit (2h) ccd register clock driver auto-bias circuit sync tip clamp circuit sample-and-hold circuit quadruple pll circuit structure cmos-ccd absolute maximum ratings (ta = 25?) supply voltage v dd 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxl5509m 400 mw cxl5509p 800 mw recommended operating condition (ta = 25?) supply voltage v dd 5 5% v recommended clock conditions (ta = 25?) input clock amplitude v clk 0.3 to 1.0 vp-p (0.5vp-p typ.) clock frequency f clk 3.579545 mhz input clock waveform sine wave input signal amplitude v sig 571mvp-p (max.) (at internal clamp condition) ?1 e91401b7x-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxl5509m/p blook diagram and pin configuration (top view) output circuit (s/h 1bit) clk 1 2 3 4 5 7 auto-bias circuit timing circuit ccd (1816bit) driver bias circuit clamp circuit 6 vco in v dd ab out1 (1h) vg2 vg1 in 9 10 11 12 13 14 v ss v ss v ss (vco out) v ss v ss pc out pll 15 16 output circuit (s/h 1bit) 8 v dd 906bit 1816bit out2 (2h) cxl5509m 16 pin sop (plastic) cxl5509p 16 pin dip (plastic)
? 2 cxl5509m/p pin description pin no. symbol description impedance i/o 1 2 3 * 4 5 6 7 8 9 10 11 12 13 14 15 16 in vg1 vg2 out1 v ss out2 v ss (vco out) v ss v dd clk v ss pc out vco in v dd ab v ss i o i o o (o) i o i o signal input (non-inverted signal) gate bias 1 dc output gate bias 2 dc input 1h signal output (inverted signal) gnd 2h signal output (inverted signal) gnd or vco output (4fsc) gnd power supply (5v) clock input (fsc) gnd phase comparator output vco input power supply (5v) autobias dc output gnd > 10k (at no clamp) 40 to 500 40 to 500 > 10k 600 to 200k * description of pin 3 (vg2) control of input signal clamp condition 0v ........ sync tip clamp condition 5v ........ center bias condition the input signal is biased to approx. 2.1v by means of the ic internal resistance (approx. 10k ). in this mode, the input signal is limited to apl 50% and the maximum input signal amplitude is at 200mvp-p.
? 3 cxl5509m/p b b b a a b b b b b b b b a a b a b a b a b a b a b 16 ? ? ?.0 ?.0 52 52 26 0 0 ?.0 ?.0 3 3 3 3 56 56 36 2 2 0 0 5 5 5 5 350 350 ma db db % degree db mvp-p 2 3 4 5 5 6 7 unit note max. min. typ. electrical characteristics (ta = 25 c, v dd = 5v, f clk = 3.579545mhz, v clk = 500mvp-p, sine wave) see "electrical characteristics test circuit" item symbol test conditions (note 1) sw conditions 1 2 3 4 a a a b ? ? c b ? ? c d d d d e e f f a b b b b c c c c d d a a 200khz, 500mvp-p, sine wave 200khz ? ? 3.58mhz, 150mvp-p, sine wave 5-staircase wave 5-staircase wave 50% white video signal no signal input i dd gl1 gl2 fr1 fr2 dg1 dg2 dp1 dp2 sn1 sn2 cp1 cp2 supply current low frequency gain frequency response differential gain differential phase s/n ratio s/h pulse coupling
electrical characteristics test circuit 1 0 0 0 p 1 a b v d d v c o i n c l k 1 0 0 0 p 8 2 k 3 . 3 0 . 1 c l k f s c ( 3 . 5 7 9 5 4 5 m h z ) , 5 0 0 m v p - p s i n e w a v e i n v g 2 o u t 1 v s s a b 1 m 5 v 1 s w 1 c a b d e a s w 4 b c d 3 3 l p f b p f 0 3 5 0 6 m 1 4 . 3 m [ d b ] 6 m 1 4 . 3 m 2 0 0 1 0 0 0 p 0 3 5 0 [ d b ] f 1 2 3 4 5 7 8 6 9 1 0 1 1 1 2 1 3 1 4 v s s p c o u t v s s v s s v g 1 v s s ( v c o o u t ) 1 0 0 0 p 3 . 3 0 . 1 1 2 0 1 5 1 6 v d d o u t 2 c x l 5 5 0 9 m / p s w 2 s w 3 a b 0 0 2 0 0 k h z 5 0 0 m v p - p s i n e w a v e 2 0 0 k h z 1 5 0 m v p - p s i n e w a v e 3 . 5 8 m h z 1 5 0 m v p - p s i n e w a v e 5 - s t a i r c a s e w a v e 5 0 % w h i t e v i d e o s i g n a l o s c i l l o s c o p e s p e c t r u m a n a l y z e r v e c t o r s c o p e n o i s e m e t e r n o t e 1 ) n o t e 2 ) n o t e 1 ) l p f f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] n o t e 2 ) b p f f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] ? 4 cxl5509m/p
? 5 cxl5509m/p application circuit 1 0 0 0 p 1 0 0 0 p 3 . 3 0 . 1 1 c l k f s c ( 3 . 5 7 9 5 4 5 m h z ) , 5 0 0 m v p - p s i n e w a v e 1 m 1 3 3 0 k 5 v s i g n a l i n p u t ( n o n - i n v e r t e d s i g n a l ) 5 1 0 5 6 0 k 1 k l p f 2 . 2 k 2 . 2 k 5 v 2 . 2 k 1 t r a n s i s t o r u s e d p n p : 2 s a 1 1 7 5 t r a n s i s t o r u s e d n p n : 2 s c 4 0 3 d e l a y t i m e 1 7 0 n s a a a ( n o n - i n v e r t e d s i g n a l ) a a ( i n v e r t e d s i g n a l ) 1 2 3 4 5 7 6 8 9 1 0 1 1 1 2 1 3 1 4 1 0 0 0 p 3 . 3 0 . 1 8 2 k 1 2 0 1 . 8 k 7 1 . 8 k 5 v 4 f s c o u t n o t e ) w h e n v c o o u t ( p i n 7 ) i s u s e d t h e c i r c u i t b e l o w . w h e n n o t u s e d , g n d . 1 5 1 6 1 0 0 0 p 1 k 3 0 p 3 3 0 k 5 1 0 5 6 0 k 1 k l p f 2 . 2 k 2 . 2 k 5 v 2 . 2 k 1 1 h o u t p u t t r a n s i s t o r u s e d p n p : 2 s a 1 1 7 5 t r a n s i s t o r u s e d n p n : 2 s c 4 0 3 d e l a y t i m e 1 7 0 n s a a ( n o n - i n v e r t e d s i g n a l ) a ( i n v e r t e d s i g n a l ) 1 k 3 0 p t r a n s i s t o r u s e d n p n : 2 s c 4 0 3 v 1 2 h o u t p u t application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 6 cxl5509m/p notes (1) by switching sw2, input condition turns out as follows. (2) this is the ic supply current value during clock and signal input. (3) gl is the output gain of out pin when a 500mvp-p, 200khz sine wave is fed to in pin. gl = 20 log [db] (4) indicates the dissipation at 3.58mhz in relation to 200khz. from the output voltage at out pin when a 150mvp-p, 200khz sine wave is fed to in pin, and from the output voltage at out pin when a 150mvp-p, 3.58mhz sine wave is fed to same, calculation is made according to the following formula. fr = 20 log [db] (5) the differential gain (dg) and the differential phase (dp), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: out pin output voltage [mvp-p] 500 [mvp-p] out pin otuput voltage (3.58mhz) [mvp-p] out pin output voltage (200khz) [mvp-p] 1 h 6 3 . 5 6 s 1 4 3 m v 2 8 5 . 5 m v 5 0 0 m v 1 4 3 m v sw2 condition a b input condition center bias condition (approx. 2.1v) approx. 2.1v bias is applied internally to the input signal sync tip clamp conditions (6) s/n ratio during 50% white video signal input shown in figure below is tested at video noise meter, in bpf 100khz to 4mhz, sub carrier trap mode. 1 h 6 3 . 5 6 s 1 4 3 m v 1 7 8 m v 3 2 1 m v
? 7 cxl5509m/p 5 0 0 m v p - p ( t y p . ) f s c ( 3 . 5 7 9 5 4 5 m h z ) s i n e w a v e clock (7) the internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. t e s t v a l u e ( m v p - p )
? 8 cxl5509m/p example of representative characteristics 4 . 7 5 s u p p l y v o l t a g e [ v ] s u p p l y c u r r e n t v s . s u p p l y v o l t a g e s u p p l y c u r r e n t [ m a ] 2 6 3 6 1 6 5 . 2 5 5 . 0 l o w f r e q u e n c y g a i n ( 2 h ) v s . s u p p l y v o l t a g e l o w f r e q u e n c y g a i n ( 2 h ) [ d b ] 0 2 2 1 1 4 . 7 5 s u p p l y v o l t a g e [ v ] 5 . 2 5 5 . 0 l o w f r e q u e n c y g a i n ( 1 h ) v s . s u p p l y v o l t a g e l o w f r e q u e n c y g a i n ( 1 h ) [ d b ] 0 2 2 1 1 4 . 7 5 s u p p l y v o l t a g e [ v ] 5 . 2 5 5 . 0 f r e q u e n c y r e s p o n s e ( 1 h ) v s . s u p p l y v o l t a g e f r e q u e n c y r e s p o n s e ( 1 h ) [ d b ] 1 1 3 2 0 4 . 7 5 s u p p l y v o l t a g e [ v ] 5 . 2 5 5 . 0 f r e q u e n c y r e s p o n s e ( 2 h ) v s . s u p p l y v o l t a g e 4 . 7 5 s u p p l y v o l t a g e [ v ] 5 . 2 5 5 . 0 f r e q u e n c y r e s p o n s e ( 2 h ) [ d b ] 1 1 3 2 0
? 9 cxl5509m/p d i f f e r e n t i a l g a i n ( 1 h ) v s . s u p p l y v o l t a g e d i f f e r e n t i a l g a i n ( 1 h ) [ % ] 3 5 1 2 4 4 . 7 5 s u p p l y v o l t a g e [ v ] 5 . 2 5 5 . 0 d i f f e r e n t i a l g a i n ( 2 h ) v s . s u p p l y v o l t a g e d i f f e r e n t i a l g a i n ( 2 h ) [ % ] 3 5 1 2 4 4 . 7 5 s u p p l y v o l t a g e [ v ] 5 . 2 5 5 . 0 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] s u p p l y c u r r e n t v s . a m b i e n t t e m p e r a t u r e s u p p l y c u r r e n t [ m a ] 2 6 3 6 1 6 8 0 2 0 4 0 6 0 l o w f r e q u e n c y g a i n ( 2 h ) v s . a m b i e n t t e m p e r a t u r e l o w f r e q u e n c y g a i n ( 2 h ) [ d b ] 0 2 2 1 1 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] 8 0 2 0 4 0 6 0 l o w f r e q u e n c y g a i n ( 1 h ) v s . a m b i e n t t e m p e r a t u r e l o w f r e q u e n c y g a i n ( 1 h ) [ d b ] 0 2 2 1 1 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] 8 0 2 0 4 0 6 0
? 10 cxl5509m/p f r e q u e n c y r e s p o n s e ( 1 h ) v s . a m b i e n t t e m p e r a t u r e f r e q u e n c y r e s p o n s e ( 1 h ) [ d b ] 1 1 3 2 0 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] 8 0 2 0 4 0 6 0 f r e q u e n c y r e s p o n s e ( 2 h ) v s . a m b i e n t t e m p e r a t u r e f r e q u e n c y r e s p o n s e ( 2 h ) [ d b ] 1 1 3 2 0 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] 8 0 2 0 4 0 6 0 d i f f e r e n t i a l g a i n ( 2 h ) v s . a m b i e n t t e m p e r a t u r e d i f f e r e n t i a l g a i n ( 2 h ) [ % ] 4 8 0 2 6 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] 8 0 2 0 4 0 6 0 d i f f e r e n t i a l g a i n ( 1 h ) v s . a m b i e n t t e m p e r a t u r e d i f f e r e n t i a l g a i n ( 1 h ) [ % ] 4 8 0 2 6 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] 8 0 2 0 4 0 6 0
? 11 cxl5509m/p f r e q u e n c y r e s p o n s e s ( 1 h ) f r e q u e n c y [ h z ] g i a n [ d b ] 4 2 6 0 2 1 0 k 1 m 1 0 0 k 1 0 m f r e q u e n c y r e s p o n s e s ( 2 h ) f r e q u e n c y [ h z ] g i a n [ d b ] 4 2 6 0 2 1 0 k 1 m 1 0 0 k 1 0 m note) 1h means 1h output; 2h means 2h output.
? 12 cxl5509m/p package outline unit: mm p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s s o n y c o d e e i a j c o d e j e d e c c o d e s o p - 1 6 p - l 0 1 s o p 0 1 6 - p - 0 3 0 0 c o p p e r a l l o y s o l d e r p l a t i n g e p o x y r e s i n 1 6 p i n s o p ( p l a s t i c ) 9 . 9 0 . 1 + 0 . 4 1 6 9 1 8 1 . 2 7 0 . 4 5 0 . 1 5 . 3 0 . 1 + 0 . 3 7 . 9 0 . 4 6 . 9 1 . 8 5 0 . 1 5 + 0 . 4 0 . 5 0 . 2 0 . 2 0 . 0 5 + 0 . 1 0 . 1 0 . 0 5 + 0 . 2 0 . 2 g 0 . 1 5 m 0 . 2 4 p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g c o p p e r a l l o y 1 9 . 2 0 . 1 + 0 . 4 9 1 8 2 . 5 4 0 . 5 0 . 1 1 . 2 0 . 1 5 3 . 0 m i n 0 . 5 m i n 3 . 7 0 . 1 + 0 . 4 6 . 4 0 . 1 + 0 . 3 7 . 6 2 0 . 2 5 0 . 0 5 + 0 . 1 0 t o 1 5 1 6 1 6 p i n d i p ( p l a s t i c ) 1 . 0 g s o n y c o d e e i a j c o d e j e d e c c o d e d i p - 1 6 p - 0 1 d i p 0 1 6 - p - 0 3 0 0 s i m i l a r t o m o - 0 0 1 - a e 1 . a l l m a t s u r f a c e t y p e . t w o k i n d s o f p a c k a g e s u r f a c e : 2 . a l l m i r r o r s u r f a c e t y p e . cxl5509m cxl5509p

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