this document is a general product descripti on and is subject to change without notice. hynix electronics does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev.01 / nov.02 hynix semiconductor HY62KF16403E series 256kx16bit full cmos sram document title 256k x 16bit 2.7 ~ 3.6v super low power fcmos slow sram revision history revision no history draft date remark 00 initial draft dec.26.2001 pre liminary 01 absolute maximum ratings nov.14.2002 final - vcc changed -0.3v to 4.6v -> -0.3v to 4.0v dc electric characteristics - icc changed 4ma -> 3ma - icc1 changed 25ma at 55ns -> 20ma at 55ns - icc1 changed 20ma at 70ns -> 15ma at 70ns - icc1 changed 3ma at 1us -> 2ma at 1us ac test conditions - output load changed 5pf -> 30pf data retention electric characteristics - iccdr changed 10ua -> 6ua marking information - part name changed hy62kf6403e ->HY62KF16403E
HY62KF16403E series rev.01 / nov.02 2 description the HY62KF16403E is a high speed, super low power and 4mbit full cmos sram organized as 256k words by 16bits. the HY62KF16403E uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particularly well-suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2v. features ? fully static operati on and tri-state output ? ttl compatible inputs and outputs ? battery backup -. 1.2v(min) data retention ? standard pin configuration -. 44pin 400mil tsop-ii (forward) standby current(ua) product no. voltage (v) speed (ns) operation current/icc(ma) sl ll temperature ( c) HY62KF16403E-i 2.7~3.6 55/70 3 6 15 -40~85 note 1. i : industrial 2. current value is max. pin connection block diagram pin description pin name pin function pin name pin function /cs chip select i/o1~i/o16 data inputs/outputs /we write enable a0~a17 address inputs /oe output enable vcc power (2.7~3.6v) /lb lower byte control (i/o1~i/o8) vss ground /ub upper byte control ( i/o9~i/o16) nc no connection a5 a6 / oe / ub / lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 a11 a12 a7 a4 a3 a2 a1 a0 / cs i/o1 i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 / we a17 a16 a15 a14 a13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a5 a6 / oe / ub / lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 nc a8 a9 a10 a11 a12 a7 a4 a3 a2 a1 a0 / cs i/o1 i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 / we a17 a16 a15 a14 a13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 tsopii (forward) memory array 256k x 16 row decoder sense amp write driver data i/o buffer i/o1 i/o8 i/o9 i/o16 column decoder block decoder pre decoder add input buffer a0 a17 /cs /oe /lb /ub /we
HY62KF16403E series rev.01 / nov.02 2 ordering information part no. speed power temp . package HY62KF16403E-sd(i) 55/70 sl-part i tsop-ii HY62KF16403E-dd(i) 55/70 ll-part i tsop-ii note 1. i : industrial absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output voltage -0.3 to v cc +0.3v v vcc power supply -0.3 to 4.0 v t a operating temperature -40 to 85 c HY62KF16403E-i t stg storage temperature -55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 ? 10 c ? sec note 1. stresses greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is stress rating only and the f unctional operation of the device under these or any other conditions above those indicated in t he operation of this specification is not implied. exposure to the absolute maximum rating condi tions for extended period may affect reliability. truth table i/o pin /cs /we /oe /lb /ub mode i/o1~i/o8 i/o9~i/o16 power h x x x x deselected high-z high-z standby h h x x l x x h h output disabled high-z high-z active l h d out high-z h l high-z d out l h l l l read d out d out active l h d in high-z h l high-z d in l l x l l write d in d in active note: 1. h=v ih , l=v il , x=don't care (v il or v ih ) 2. /ub, /lb(upper, lower byte enable) these active low inputs allow individual bytes to be written or read. when /lb is low, data is written or read to the lower byte, i/o 1 -i/o 8. when /ub is low, data is written or read to the upper byte, i/o 9 -i/o 16.
HY62KF16403E series rev.01 / nov.02 3 recommended dc operating condition symbol parameter min. typ max. unit vcc supply voltage 2.7 3.0 or 3.3 3.6 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0.3 v v il input low voltage -0.3 1. - 0.6 v note : 1. undershoot : vil = -1.5v for pulse width less than 30ns 2. undershoot is sampled, not 100% tested. dc electrical characteristics t a = -40 c to 85 c sym parameter test condition min typ 1. max unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il -1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il, i i/o = 0ma 3 ma 55ns 20 ma /cs = v il, v in = v ih or v il, cycle time = min, 100% duty, i i/o = 0ma 70ns 15 ma i cc1 average operating current /cs < 0.2v , v in < 0.2v or v in > vcc-0.2v , cycle time = 1us, 100% duty, i i/o = 0ma 2 ma i sb standby current (ttl input) /cs = v ih v in = v ih or v il 300 ua sl 0.2 6 ua 3.0~ 3.6v ll 0.2 15 ua sl 0.2 6 ua i sb1 standby current (cmos input) /cs > vcc - 0.2v, v in > vcc - 0.2v or v in < vss + 0.2v 2.7~ 3.3v ll 0.2 12 ua v ol output low i ol = 2.1ma - - 0.4 v v oh output high i oh = -1.0ma 2.4 - - v note 1. typical values are at vcc = 3.0v t a = 25 c 2. typical values are not 100% tested capacitance (temp = 25 c, f= 1.0mhz) symbol parameter condition max. unit c in input capacitance (add, /cs, /we, /oe) v in = 0v 8 pf c out output capacitance (i/o) v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested
HY62KF16403E series rev.01 / nov.02 4 ac characteristics t a = -40 c to 85 c, unless otherwise specified 55ns 70ns # symbol parameter min. max. min. max. unit 1 trc read cycle time 55 - 70 - ns 2 taa address access time - 55 - 70 ns 3 tacs chip select access time - 55 - 70 ns 4 toe output enable to output valid - 30 - 35 ns 5 tba /lb, /ub access time - 55 - 70 ns 6 tclz chip select to output in low z 10 - 10 - ns 7 tolz output enable to output in low z 5 - 5 - ns 8 tblz /lb, /ub enable to output in low z 10 - 10 - ns 9 tchz chip deselection to output in high z 0 20 0 25 ns 10 tohz out disable to output in high z 0 20 0 25 ns 11 tbhz /lb, /ub disable to output in high z 0 20 0 25 ns 12 toh output hold from address change 10 - 10 - ns 13 twc write cycle time 55 - 70 - ns 14 tcw chip selection to end of write 50 - 60 - ns 15 taw address valid to end of write 50 - 60 - ns 16 tbw /lb, /ub valid to end of write 50 - 60 - ns 17 tas address set-up time 0 - 0 - ns 18 twp write pulse width 45 - 50 - ns 19 twr write recovery time 0 - 0 - ns 20 twhz write to output in high z 0 20 0 20 ns 21 tdw data to write time overlap 25 - 30 - ns 22 tdh data hold from write time 0 - 0 - ns 23 tow output active from end of write 5 - 5 - ns ac test conditions t a = -40 c to 85 c, unless otherwise specified parameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing reference level 1.5v tclz, tolz, tchz, tohz, twhz, tow cl = 30pf + 1ttl load output load others cl = 30pf + 1ttl load ac test loads d out 1728 ohm cl ( 1 ) 1029 ohm v tm =2.8v note 1. including jig and scope capacitance read cycle write cycle
HY62KF16403E series rev.01 / nov.02 5 timing diagram read cycle 1 (note 1,4) read cycle 2 (note 1,2,4) t rc taa data valid previous data toh toh addr data out read cycle 3(note 1,2,4) /cs /ub, /lb tacs data valid tclz(3) tchz(3) data out notes: 1. a read occurs during the overlap of a low /o e, a high /we, a low /cs and /ub and/or /lb . 2. /oe = v il 3. tchz and tohz are defined as the time at wh ich the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active addr trc /cs taa tacs toh data valid high-z data out /ub ,/ lb /oe tba toe tclz (3) tblz (3) tolz (3) tchz (3) tbhz (3) tohz (3)
HY62KF16403E series rev.01 / nov.02 6 write cycle 1 (1,4,8) (/we controlled) write cycle 2 (note 1,4,8) (/cs controlled) data valid addr data out /cs /ub,/lb /we twc tcw twr(2) tbw taw twp data in high-z tas twhz(3,7) tdw tdh tow (5) (6) data valid addr data out /cs /ub,/lb /we twc tcw twr (2) tbw taw twp data in tdw tdh high-z high-z tas
HY62KF16403E series rev.01 / nov.02 7 notes: 1. a write occurs during the overlap of a low /we, a low /cs and a low /ub and/or /lb . 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output st ate so that the input signal s of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simult aneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. /cs in high for the standby, low for active /ub and /lb in high for the standby, low for active data retention electric characteristic t a = -40 c to 85 c symbol parameter test condition min typ 1. max unit v dr vcc for data retention /cs > vcc - 0.2v, v in > vcc - 0.2v or v in < vss + 0.2v 1.2 - 3.6 v sl - 0.1 3 ua iccdr data retention current vcc=1.5v, /cs > vcc - 0.2v or v in > vcc - 0.2v or v in < vss + 0.2v ll - 0.1 6 ua tcdr chip deselect to data retention time 0 - - ns tr operating recovery time see data retention timing diagram trc - - ns notes: 1. typical values are under the condition of t a = 25 c. 2. typical value are sampled and not 100% tested data retention timing diagram /cs vdr /cs >vcc-0.2v tcdr tr vss vcc 2.7v v ih data retention mode
HY62KF16403E series rev.01 / nov.02 8 package information 44pin 400mil thin small outline package forward (d) #22 #23 #44 #1 0.016(0.4) 0.012(0.3) 0.0315(0.800) bsc 0.0059 ( 0.150 ) 0.002 ( 0.050 ) 0.047 ( 1.194 ) 0.039(0.991) 0.721(18.313) 0.729(18.517) 0.10max 0.004max 0.404 ( 10.262 ) 0.396(10.058) 0.0235 ( 0.597 ) 0.0160(0.406) 0.0083(0.21) 0.0047 ( 0.120 ) 0~5 unit : inch(mm) 0.462(11.735) 0.470(11.938) min. max.
HY62KF16403E series rev.01 / nov.02 9 marking information h y n i x y y w h y 6 2 k f 6 4 0 3 e c s s k o r e a tsop-ii (forward) package marking example index ? hynix : hynix logo ? yy : year ( ex : 02 = year 2002, 03 = year 2002 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code ? HY62KF16403E : part name ? c : power consumption - d : low low power - s : super low power ? ss : speed -55 : 55ns -70 : 70ns ? t : temperature - i : industrial ( -40 ~ 85 c) ? korea : origin country note - capital letter : fixed item - small letter : non-fixed item (except hynix) w t p 1 h y n i x y y w h y 6 2 k f 6 4 0 3 e c s s k o r e a tsop-ii (forward) package marking example index ? hynix : hynix logo ? yy : year ( ex : 02 = year 2002, 03 = year 2002 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code ? HY62KF16403E : part name ? c : power consumption - d : low low power - s : super low power ? ss : speed -55 : 55ns -70 : 70ns ? t : temperature - i : industrial ( -40 ~ 85 c) ? korea : origin country note - capital letter : fixed item - small letter : non-fixed item (except hynix) w t p 1
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