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ds04-21361-3e fujitsu semiconductor data sheet assp dual serial input pll frequency synthesizer mb15f07sl n description the fujitsu mb15f07sl is a serial input phase locked loop (pll) frequency synthesizer with two 1100 mhz prescalers. the two 1100 mhz prescalers have a dual modulus division ratio of 128/129 or 64/65 enabling pulse swallowing operation. the supply voltage range is between 2.4 v and 3.6 v. the mb15f07sl uses the latest bicmos process. as a result, the supply current is typically 5 ma at 2.7 v. a refined charge pump supplies a well-balanced output current of 1.5 ma or 6 ma. the charge pump current is selectable by serial data. mb15f07sl is ideally suited for wireless mobile communications, such as gsm and pdc. n features ? high frequency operation: pll 1, 2: 1100 mhz max ? low power supply voltage: v cc = 2.4 to 3.6 v ? ultra low power supply current: i cc = 5.0 ma typ. (v cc = 2.7 v, ta = +25 c, in pll1, 2 locking state) i cc = 5.5 ma typ. (v cc = 3.0 v, ta = +25 c, in pll1, 2 locking state) ? direct power saving function: power supply current in power saving mode typ. 0.1 m a (v cc = 3.0 v, ta = +25 c), max. 10 m a (v cc = 3.0 v) ? dual modulus prescaler: 1100 mhz prescaler (64/65, 128/129) ? serial input 14-bit programmable reference divider: r = 3 to 16,383 ? serial input programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 3 to 2,047 ? software selectable charge pump current ? on-chip phase control for phase comparator ? operating temperature: ta = C40 to +85 c n packages 16-pin plastic ssop (fpt-16p-m05) 16-pad plastic bcc (lcc-16p-m04)
2 mb15f07sl n pin assignments gnd 2 osc in gnd 1 fin 1 v cc1 ld/fout ps 1 d o1 clock data le fin 2 v cc2 xfin 2 ps 2 d o2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 top view top view gnd 2 clock d o1 d o2 1 2 3 4 5 6 78 9 10 11 12 13 14 15 16 osc in gnd 1 fin 1 v cc1 ps 1 ld/fout data le fin 2 v cc2 ps 2 xfin 2 (fpt-16p-m05) (lcc-16p-m04) 16-pin ssop 16-pad bcc
3 mb15f07sl n pin descriptions pin no. pin name i/o descriptions ssop-16 bcc-16 116gnd 2 C ground for pll 2 section. 21osc in i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 32gnd 1 C ground for the pll 1 section. 43fin 1 i prescaler input pin for the pll 1. connection to an external vco should be via ac coupling. 54v cc1 C power supply voltage input pin for the pll 1 section. 6 5 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout). the output signal is selected by lds bit in a serial data. lds bit = h ; outputs fout signal lds bit = l ; outputs ld signal 76ps 1 i power saving mode control for the pll 1 section. this pin must be set at l during power-on. (open is prohibited.) ps 1 = h ; normal mode ps 1 = l ; power saving mode 87do 1 o charge pump output for the pll 1 section. phase characteristics of the phase detector can be selected via programming of the fc-bit. 98do 2 o charge pump output for the pll 2 section. phase characteristics of the phase detector can be selected via programming of the fc-bit. 10 9 ps 2 i power saving mode control for the pll 2 section. this pin must be set at l during power-on. (open is prohibited.) ps 2 = h ; normal mode ps 2 = l ; power saving mode 11 10 xfin 2 i prescaler complementary input for the pll 2 section. this pin should be grounded via a capacitor. 12 11 v cc2 C power supply voltage input pin for the pll 2 section, the shift register and the oscillator input buffer. when power is off, latched data of pll 2 is lost. 13 12 fin 2 i prescaler input pin for the pll 2. connection to an external vco should be via ac coupling. 14 13 le i load enable signal inpunt (with a schmitt trigger input buffer.) when the le bit is set h, data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. 15 14 data i serial data input (with a schmitt trigger input buffer.) data is transferred to the corresponding latch (pll 1-ref counter, pll 1- prog. counter, pll 2-ref. counter, pll 2-prog. counter) according to the control bit in the serial data. 16 15 clock i clock input for the 23-bit shift register (with a schmitt trigger input buffer.) one bit of data is shifted into the shift register on a rising edge of the clock.
4 mb15f07sl n block diagram 16 clock 15 data 14 le 10 ps 2 11 xfin 2 13 fin 2 osc in fin 1 ps 1 3-bit latch 7-bit latch 11-bit latch 3-bit latch latch selector 23-bit shift register 7-bit latch 11-bit latch phase comp. (pll 1) lock det. ( pll 1 ) lock det. ( pll 2 ) charge pump (pll 1) current switch phase comp. ( pll 2 ) charge pump ( pll 2 ) current switch 2-bit latch 14-bit latch 1-bit latch 2-bit latch 14-bit latch 1-bit latch intermittent mode control (pll 1) intermittent mode control (pll 2) schmitt circuit schmitt circuit schmitt circuit binary 7-bit swallow counter (pll 1) binary 14-bit programmable ref. counter (pll 1) c/p setting current cp binary 11-bit programmable counter (pll 1) binary 7-bit swallow counter (pll 2) binary 11-bit programmable counter (pll 2) prescaler (pll 1) 64/65, 128/129 prescaler (pll 2) 64/65, 128/129 fc 1 sw 1 lds fc 2 sw 2 lds v cc1 gnd 1 5 3 fp 1 8 do 1 ld 1 selector t1 t2 t1 t2 9 do 2 or 6 ld / fout fr 2 fp 2 fr 1 c n 1 c n 2 and ld fr 1 fr 2 fp 1 fp 2 v cc2 gnd 2 7 (6) (3) (1) (12) (10) (9) (13) (14) (15) 4 2 (8) (5) (7) (2) (4) binary 14-bit programmable ref. counter (pll 2) c/p setting current cp 1-bit latch 12 (11) 1 (16) o : ssop ( ) : bcc
5 mb15f07sl n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit remark min. max. power supply voltage v cc C0.5 +4.0 v input voltage v i C0.5 v cc +0.5 v output voltage v o gnd v cc v storage temperature tstg C55 +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.4 3.0 3.6 v input voltage v i gnd C v cc v operating temperature ta C40 C +85 c
6 mb15f07sl n electrical characteristics (v cc = 2.4 v to 3.6 v, ta = C40 to +85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current* 1 i cc *1 pll 1, pll 2 total, fin 1 = fin 2 = 1100 mhz, v cc1 = v cc2 = 2.7 v (v cc1 = v cc2 = 3.0 v) C 5.0 (5.5) Cma power saving current i ps ps 1 = ps 2 = l C 0.1* 2 10 m a operating frequency fin 1 *3 fin 1 pll 1 100 C 1100 mhz fin 2 *3 fin 2 pll 2 100 C 1100 mhz osc in fosc C 3 C 40 mhz input sensitivity fin 1 pfin 1 pll 1, 50 w system C15* 8 C+2dbm fin 2 pfin 2 pll 2, 50 w system C15* 8 C+2dbm osc in v osc C0.5 v cc vp-p h level input voltage data, clock, le v ih schmitt trigger input v cc 0.7 + 0.4 CC v l level input voltage v il schmitt trigger input C C v cc 0.3 C 0.4 h level input voltage ps 1 , ps 2 v ih Cv cc 0.7 C C v l level input voltage v il CCCv cc 0.3 h level input current data, clock, le, ps 1 , ps 2 i ih *4 CC1.0C+1.0 m a l level input current i il *4 CC1.0C+1.0 h level input current osc in i ih C0C+100 m a l level input current i il *4 C C100 C 0 h level output voltage ld/fout v oh v cc = 3.0 v, i oh = C1 ma v cc C 0.4 C C v l level output voltage v ol v cc = 3.0 v, i ol = 1 ma C C 0.4 h level output voltage do 1 do 2 v doh v cc = 3.0 v, i doh = C0.5 ma v cc C 0.4 C C v l level output voltage v dol v cc = 3.0 v, i dol = 0.5 ma C C 0.4 high impedance cutoff current do 1 do 2 i off v cc = 3.0 v, v off = 0.5 v to v cc C 0.5 v CC2.5na h level output current ld/fout i oh *4 v cc = 3.0 v C C C1.0 ma l level output current i ol *4 v cc = 3.0 v 1.0 C C
7 mb15f07sl (continued) (v cc = 2.4 to 3.6 v, ta = C40 to +85 c) *1: conditions; fosc = 12 mhz, ta = +25 c, in locking state. *2: v cc1 = v cc2 = 3.0 v, fosc = 12.8 mhz, ta = +25 c, in power saving mode. *3: ac coupling. 1000pf capacitor is connected under the condition of min. operating frequency. *4: the symbol C (minus) means direction of current flow. *5: v cc = 3.0 v, ta = +25 c (|i 3 | C |i 4 |)/[(|i 3 | + |i 4 |)/2] 100(%) *6: v cc = 3.0 v, ta = +25 c [(|i 2 | C |i 1 |)/2]/[(|i 1 | + |i 2 |)/2] 100(%) (applied to each i dol , i doh ) *7: v cc = 3.0 v, [|i do(+85 c) C i do(C40 c) |/2]/[|i do(+85 c) + i do(C40 c) |/2] 100(%) (applied to each i dol , i doh ) *8: parameter symbol condition value unit min. typ. max. h level output current do 1 do 2 i doh *4 v cc = 3.0 v, v doh = v cc /2, ta = + 2 5 c cs bit = h C C6.0 C ma cs bit = l C C1.5 C l level output current i dol v cc = 3.0 v, v dol = v cc /2, ta = + 2 5 c cs bit = h C 6.0 C cs bit = l C 1.5 C charge pump current rate i dol /i doh i domt *5 v do = v cc /2 C 3 C % vs v do i dovd *6 0.5 v v do v cc C 0.5 v C 10 C % vs ta i dota *7 C40 c ta + 85 c, v do = v cc /2 C10C% prescaler divided ratio 64/65 128/129 prescaler divided ratio 64/65 128/129 charge pump current 1.5 ma mode 6.0 ma mode 1.5 ma mode 6.0 ma mode charge pump current 1.5 ma mode 6.0 ma mode 1.5 ma mode 6.0 ma mode vfin 1 (min) C10 dbm C10 dbm C15 dbm C15 dbm vfin 2 (min) C15 dbm C10 dbm C15 dbm C15 dbm fin 2 fin 1 i 1 i 1 i 3 i 2 i 2 i 4 i dol i doh 0.5 vcc/2 vcc vcc - 0.5 charge pump output voltage (v)
8 mb15f07sl n functional description the divide ratio can be calculated using the following equation: f vco = {(m n) + a} f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) m : preset divide ratio of dual modulus prescaler (64 or 128 for pll 1/pll 2) n : preset divide ratio of binary 11-bit programmable counter (3 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : reference oscillation frequency r : preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of pll 1/pll 2 sections, programmable reference dividers of pll 1/pll 2 sections are controlled individually. serial data of binary data is entered through data pin. on rising edge of clock, one bit of serial data is transferred into the shift register. when the le signal is taken high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. table 1. control bit shift register configuration control bit destination of serial data cn1 cn2 l l the programmable reference counter for the pll 1 h l the programmable reference counter for the pll 2 l h the programmable counter and the swallow counter for the pll 1 h h the programmable counter and the swallow counter for the pll 2 programmable reference counter msb data flow cn1, cn2 : control bit [table 1] r1 to r14 : divide ratio setting bits for the programmable reference counter (3 to 16,383)[table 2] t1, t2 : test purpose bit [table 3] cs : charge pump currnet select bit [table 9] x : dummy bits (set 0 or 1) note: data input with msb first. 1234567891011121314151617181920212223 c n 1 c n 2 t 1 t 2 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 c s xxxx lsb
9 mb15f07sl table 2. binary 14-bit programmable reference counter data setting note: divide ratio less than 3 is prohibited. table 3. test purpose bit setting divide ratio (r) r14r13r12r11r10r9r8r7r6r5r4r3r2r1 3 0 0 000000000011 4 0 0 000000000100 16383 1 1 111111111111 t1 t2 ld/fout pin state l l outputs fr 1 . h l outputs fr 2 . l h outputs fp 1 . h h outputs fp 2 . programmable counter lsb msb data flow cn1, cn2: control bit [table 1] n1 to n11: divide ratio setting bits for the programmable counter (3 to 2,047) [table 4] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table 5] sw 1 / sw 2 : divide ratio setting bit for the prescaler [table 6] (pll 1 for the sw 1 , pll 2 for the sw 2 ) fc 1 / fc 2 : phase control bit for the phase detector (pll 1: fc 1 , pll 2: fc 2 ) [table 7] lds : ld/fout signal select bit [table 8] note: data input with msb first. 1 2 3 4 5 6 7 8 9 1011121314151617181920212223 c n 1 c n 2 l d s s w 1/2 f c 1/2 a 1 a 2 a 3 a 4 a 5 a 6 a 7 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 11
10 mb15f07sl table 4. binary 11-bit programmable counter data setting note: divide ratio less than 3 is prohibited. table 5. binary 7-bit swallow counter data setting note: divide ratio (a) range = 0 to 127 table 6. prescaler data setting table 7. phase comparator phase switching data setting note: z = high-impedance depending upon the vco and lpf polarity, fc bit should be set. divide ratio (n) n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 3 0 0000000011 4 0 0000000100 2047 1 1 1 1 1 1 1 1 1 1 1 divide ratio (n) a7 a6 a5 a4 a3 a2 a1 0 0000000 1 0000001 127 1111111 sw = h sw = l prescaler divide ratio pll 1 64/65 128/129 pll 2 64/65 128/129 fc 1, fc 2 = h fc 1, fc 2 = l do 1, do 2 fr > fp h l fr = fp z z fr < fp l h vco polarity (1) (2) (1) (2) lpf output voltage vco output frequency
11 mb15f07sl table 8. ld/fout output select data setting table 9. charge pump current setting power saving mode (intermittent mode control circuit) table 10. ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. notes: when power (v cc ) is first applied, the device must be in standby mode, ps = low, for at least 1 m s. ps pins must be set at l for power-on . lds ld/fout output signal hfout (fr 1 /fr 2 , fp 1 /fp 2 ) signals l ld signal cs current value h 6.0 ma l 1.5 ma ps pin status h normal mode l power saving mode (1) (2) (3) v cc clock data le ps on tv 3 1 m s tps 3 100 ns off (1) ps = l (power saving mode) at power-on (2) set serial data 1 m s later after power supply remains stable (v cc > 2.2 v). (3) release power saving mode (ps: l ? h ) 100 ns later after setting serial data.
12 mb15f07sl n serial data input timing lsb msb 1st data 2nd data control bit invalid data clock data le t 7 t 1 t 2 t 3 t 4 t 5 t 6 on rising edge of the clock, one bit of the data is transfered into the shift register. note: le should be l when the data is transferred into the shift register. parameter min. typ. max. unit t 1 20 C C ns t 2 20 C C ns t 3 30 C C ns t 4 30 C C ns parameter min. typ. max. unit t 5 100 C C ns t 6 20 C C ns t 7 100 C C ns
13 mb15f07sl n phase comparator output waveform n otes: phase error detection range = C2 p to +2 p pulses on do 1/2 signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on osc in input frequency as follows. t wu > 2/fosc: i. e. t wu > 156.3 ns when fosc = 12.8 mhz t wu < 4/fosc: i. e. t wl < 312.5 ns when fosc = 12.8 mhz fr 1 / fr 2 fp 1 / fp 2 ld (fc bit = high) (fc bit = low) d o1 / d o2 t wu t wl d o1 / d o2 ld output logic table if-pll section rf-pll section ld output locking state/power saving state locking state/power saving state h locking state/power saving state unlocking state l unlocking state locking state/power saving state l unlocking state unlocking state l
14 mb15f07sl n measurment circuit ( f or measuring input sensitivity fin/osc i n ) s.g. s.g. 50 w 1000 pf 0.1 m f 50 w 1000 pf v cc1 fout 50 w 1000 pf 1000 pf s.g. 0.1 m f v cc2 1 23 controller (divide ratio setting) oscilloscope 45678 161514131211109 d o1 ps 1 ld/fout v cc1 fin 1 gnd 1 osc in gnd 2 d o2 ps 2 xfin 2 v cc2 fin 2 le data clock note: ssop-16
15 mb15f07sl n typical characteristics 1. fin input sensitivity 10 5 0 - 5 - 10 - 15 - 20 - 25 - 30 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v v cc = 2.4 v ta = +25 c spec pll1 input sensitivity - input frequency fin 1 (mhz) pfin 1 (dbm) 10 5 0 - 5 - 10 - 15 - 20 - 25 - 30 - 35 - 40 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = +25 c 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 pll2 input sensitivity - input frequency pfin 2 (dbm) fin 2 (mhz) spec fin 1 input sensitivity fin 2 input sensitivity
16 mb15f07sl 2. osc in input sensitivity osc in 10 0 - 10 - 20 - 30 - 40 - 50 0 5 10 15 20 25 30 35 40 45 50 v cc = 2.7 v v cc = 2.4 v v cc = 3.0 v v cc = 3.6 v ta = + 25 c input sensitivity - input frequency f osc (mhz) v osc (dbm) spec
17 mb15f07sl 3. do output current (pll1) 10.00 - 10.00 0 .6000 / div 4.800 2.000 / div 0 ta = +25 c v cc = 3 v i doh i dol 10.00 - 10.00 0 .6000 / div 4.800 2.000 / div 0 ta = +25 c v cc = 3 v i doh i dol v do - i do change pump output voltage v do (v) change pump output current i do (ma) v do - i do change pump output voltage v do (v) change pump output current i do (ma) 1.5 ma mode 6.0 ma mode
18 mb15f07sl 4. do output current (pll2) 1.5 ma mode 6.0 ma mode 10.00 - 10.00 0 .6000 / div 4.800 2.000 / div 0 ta = +25 c v cc = 3 v i doh i dol 10.00 - 10.00 0 .6000 / div 4.800 2.000 / div 0 ta = +25 c v cc = 3 v i doh i dol v do - i do v do - i do change pump output voltage v do (v) change pump output current i do (ma) change pump output voltage v do (v) change pump output current i do (ma)
19 mb15f07sl 5. fin input impedance 360.88 w - 683.25 w 100 mhz 30.641 w - 206.18 w 400 mhz 10.805 w - 92.172 w 800 mhz 1 : 2 : 3 : 4 : 10.076 w - 54.955 w 1100 mhz 1 3 2 start 100.000 000 mhz stop 1 100.000 000 mhz 4 299.88 w - 658.06 w 100 mhz 26.68 w - 184.5 w 400 mhz 11.949 w - 75.16 w 800 mhz 1 : 2 : 3 : 4 : 14.246 w - 36.49 w 1100 mhz start 100.000 000 mhz stop 1 100.000 000 mhz 4 1 2 3 fin 1 input impedance fin 2 input impedance
20 mb15f07sl 6. osc in input impedance 9.451 k w - 3.1875 k w 3 mhz 4.7255 k w - 5.1685 k w 10 mhz 1.6918 k w - 3.8045 k w 20 mhz 1 : 2 : 3 : start 3.000 000 mhz stop 40.000 000 mhz 4 : 463.75 w - 2.1069 k w 40 mhz 2 3 4 1 osc in input impedance
21 mb15f07sl n reference information (continued) atten 10 db rl 0 dbm 10 db / rbw 10 khz vbw 10 khz swp 50.0 ms mkr - 71.16 db 200 khz center 1.005000 ghz span 1.000 mhz atten 10 db rl 0 dbm 10 db / rbw 300 khz vbw 300 khz swp 1.40 s mkr - 54.83 db 9.58 khz center 1.005000 ghz span 50.00 khz c/n = 79.6 (dbc/hz) bw = 16 khz s.g. spectrum analyzer osc in fin do lpf vco test circuit f vco = 1005 mhz k v = 20 mhz/v fr = 200 khz f osc = 13 mhz v cc = 3.0 v v vco = 3.3 v ta = +25 c cp : 6 ma mode 1.1 k w 2.2 k w 0.018 m f 330 pf 1800 pf lpf pll reference leakag e pll phase noise
22 mb15f07sl (continued) 50.00000 mhz 10.00000 mhz/div 0 hz 1005 mh ? 1031 mhz within 1 khz lch ? hch 299 m s 50.00000 mhz 10.00000 mhz/div 10.00000 mhz 1031 mh ? 1005 mhz within 1 khz hch ? lch 330 m s 0 s 2.0000000 ms 0 s 2.0000000 ms 30.00500 mhz 2.000 khz/div 29.99500 mhz 30.00500 mhz 2.000 khz/div 29.99500 mhz 0 s 2.0000000 ms 0 s 2.0000000 ms meas # 91 pll lock up time pll lock up time
23 mb15f07sl n application example n usage precautions (1) v cc2 must equal vcc 1 . even if either pll 2 or pll 1 is not used, power must be supplied to both v cc2 and v cc1 to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. 1000 pf 0.1 m f 12345678 16 15 14 13 12 11 10 9 1000 pf output from controller 3 v mb15f07sl 1000 pf 1000 pf 3 v 0.1 m f output lockdet vco vco tcxo do 2 ps 2 xfin 2 v cc2 fin 2 le data clock do 1 ps 1 ld / fout v cc1 fin 1 gnd 1 osc in gnd 2 lpf lpf note: ssop-16
24 mb15f07sl n ordering information part number package remarks mb15f07slpfv1 16-pin plastic ssop (fpt-16p-m05) MB15F07SLPV1 16-pad plastic bcc (lcc-16p-m04)
25 mb15f07sl n package dimensions (continued) c 1999 fujitsu limited f16013s-3c-5 5.00?.10(.197?004) * 4.40?.10 6.40?.20 (.252?008) (.173?004) * .049 ?004 +.008 ?.10 +0.20 1.25 (mounting height) 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 8 16 9 "a" 0.10?.10 (stand off) 0.17?.03 (.007?001) m 0.13(.005) (.004?004) details of "a" part 0~8 (.018/.030) 0.45/0.75 (.020?008) 0.50?.20 0.25(.010) lead no. index dimensions in mm (inches ) 16-pin plastic ssop (fpt-16p-m05) note 1 ) * : these dimensions do not include resin protrusion. note 2 ) pins width and pins thickness include plating thickness.
26 mb15f07sl c 1999 fujitsu limited c16015s-1c-1 0.325?.10 (.013?004) 3.40(.134)typ "a" 0.40?.10 (.016?004) 3.25(.128) 0.80(.031) ref typ 4.20?.10 (.165?004) 4.55?.10 (.179?004) 0.80(.031)max mounting height 0.075?.025 (.003?001) (stand off) 0.05(.002) 6 9 1 14 9 14 1 6 0.40?.10 (.016?004) 0.75?.10 (.030?004) details of "a" part 1.725(.068) ref 1.55(.061) ref "b" details of "b" part (.024?004) 0.60?.10 (.024?004) 0.60?.10 0.65(.026) typ index area dimensions in mm (inches) 16-pad plastic bcc (lcc-16p-m04)
mb15f07sl fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, usa tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ f0002 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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