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44-pin lqfp case: 10 x 10 mm 2 64-pin lqfp case: 10 x 10 mm 2 48-pin lqfp case: 7 x 7 mm 2 freescale semiconductor technical data document number: mc56f825x rev. 3, 04/2011 ? freescale semiconductor, inc., 2009-2011. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. mc56f825x/mc56f824x the mc56f825x/mc56f824x is a member of the 56800e core-based family of digital signal controllers (dscs). it combines, on a single chip, the processing power of a dsp and the functionality of a microc ontroller with a flexible set of peripherals to create a cost-eff ective solution. because of its low cost, configuration flex ibility, and compact program code, it is well-suited for many applications. the mc56f825x/mc56f824x includes many peripherals that are especially useful for cost-sen sitive applications, including: ? industrial control ? home appliances ? smart sensors ? fire and security systems ? solar inverters ? battery chargers and management ? switched-mode power supplies and power management ?power metering ? motor control (acim, bldc, pmsm, sr, and stepper) ? handheld power tools ? arc detection ? medical devices/equipment ? instrumentation ? lighting ballast the 56800e core is based on a modified harvard-style architecture consisting of thr ee execution units operating in parallel, allowing as many as six operations per instruction cycle. the mcu-style progra mming model and optimized instruction set allow straightforward generation of efficient, compact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the mc56f825x/mc56f824x supports program execution from internal memories. two data operands per instruction cycle can be accessed from the on-chip data ram. a full set of programmable peripherals supports various applications. each peripheral can be independently shut down to save power. any pin, except power pins and the reset pin, can also be configured as general pu rpose input/outputs (gpios). on-chip features include: ? 60 mhz operation frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? on-chip memory ? 56f8245/46: 48 kb (24k x 16) flash memory; 6 kb (3k x 16) unified data/program ram ? 56f8247: 48 kb (24k x 16) flash memory; 8 kb (4k x 16) unified data/program ram ? 56f8255/56/57: 64 kb (32k x 16) flash memory; 8 kb (4k x 16) unified data/program ram ? eflexpwm with up to 9 channels, including 6 channels with high (520 ps) reso lution nanoedge placement ? two 8-channel, 12-bit analog-t o-digital converters (adcs) with dynamic x2 and x4 programmable amplifier, conversion time as short as 600 ns, and input current-injection protection ? three analog comparators w ith integrated 5-bit dac references ? cyclic redundancy check (crc) generator ? two high-speed queued serial communication interface (qsci) modules with lin slave functionality ? queued serial peripheral interface (qspi) module ? two smbus-compatible inter-integrated circuit (i 2 c) ports ? freescale?s scalable controller area network (mscan) 2.0 a/b module ? two 16-bit quad timers (2 x 4 16-bit timers) ? computer operating properly (cop) watchdog module ? on-chip relaxation oscillator: 8 mhz (400 khz at standby mode) ? crystal/resonator oscillator ? integrated power-on reset (por) and low-voltage interrupt (lvi) and brown-out reset module ? inter-module crossbar connection ? up to 54 gpios ? 44-pin lqfp, 48-pin lqfp, and 64-pin lqfp packages ? single supply: 3.0 v to 3.6 v mc56f825x/mc56f824x digital signal controller www..net
mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 2 table of contents 1 mc56f825x/mc56f824x family configuration . . . . . . . . . . . .3 2 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 mc56f825x/mc56f824x features. . . . . . . . . . . . . . . . .4 2.2 award-winning development environment. . . . . . . . . . .8 2.3 architecture block diagram. . . . . . . . . . . . . . . . . . . . . . .8 2.4 product documentation . . . . . . . . . . . . . . . . . . . . . . . .11 3 signal/connection descriptions . . . . . . . . . . . . . . . . . . . . . . .11 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.3 mc56f825x/mc56f824x signal pins . . . . . . . . . . . . . .18 4 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.2 program map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.3 data map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.4 interrupt vector table and reset vector . . . . . . . . . . . .33 4.5 peripheral memory-mapped registers . . . . . . . . . . . . .34 4.6 eonce memory map . . . . . . . . . . . . . . . . . . . . . . . . . .35 5 general system control information . . . . . . . . . . . . . . . . . . .36 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.2 power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.3 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.4 on-chip clock synthesis . . . . . . . . . . . . . . . . . . . . . . . .37 5.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.6 system integration module (sim) . . . . . . . . . . . . . . . . .39 5.7 inter-module connections. . . . . . . . . . . . . . . . . . . . . . .40 5.8 joint test action group (jtag)/enhanced on-chip emulator (eonce) . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6 security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.1 operation with security enabled. . . . . . . . . . . . . . . . . .46 6.2 flash access lock and unlock mechanisms . . . . . . . .47 6.3 product analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 7 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 7.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . .48 7.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .49 7.3 esd protection and latch-up immunity . . . . . . . . . . . .50 7.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .50 7.5 recommended operating conditions . . . . . . . . . . . . . .52 7.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . 53 7.7 supply current characteristics . . . . . . . . . . . . . . . . . . 55 7.8 power-on reset, low voltage detection specification 56 7.9 voltage regulator specifications . . . . . . . . . . . . . . . . . 56 7.10 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . 56 7.11 enhanced flex pwm characteristics . . . . . . . . . . . . . 57 7.12 flash memory characteristics . . . . . . . . . . . . . . . . . . . 57 7.13 external clock operation timing. . . . . . . . . . . . . . . . . 57 7.14 phase locked loop timing . . . . . . . . . . . . . . . . . . . . . 58 7.15 external crystal or resonator requirement . . . . . . . . 59 7.16 relaxation oscillator timing . . . . . . . . . . . . . . . . . . . . 59 7.17 reset, stop, wait, mode select, and interrupt timing. 60 7.18 queued serial peripheral interface (spi) timing . . . . 60 7.19 queued serial communication interface (sci) timing 64 7.20 freescale?s scalable controller area network (mscan)65 7.21 inter-integrated circuit interface (i2c) timing . . . . . . . 65 7.22 jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.23 quad timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.24 cop specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.25 analog-to-digital converter (adc) parameters. . . . . . 68 7.26 digital-to-analog converter (dac) parameters . . . . . . 70 7.27 5-bit digital-to-analog converter (dac) parameters. . 71 7.28 hscmp specifications . . . . . . . . . . . . . . . . . . . . . . . . 71 7.29 optimize power consumption . . . . . . . . . . . . . . . . . . . 71 8 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.1 thermal design considerations . . . . . . . . . . . . . . . . . 72 8.2 electrical design considerations. . . . . . . . . . . . . . . . . 73 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10 package mechanical outline drawings . . . . . . . . . . . . . . . . . 76 10.1 44-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.2 48-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.3 64-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 appendix a interrupt vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
mc56f825x/mc56f824x family configuration mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 3 1 mc56f825x/mc56f824x family configuration table 1 compares the mc56f825x/mc56f824x devices. table 1. mc56f825x/mc56f824x device comparison feature 56f8245 56f8246 56f 8247 56f8255 56f8256 56f8257 operation frequency (mhz) 60 high speed peripheral clock (mhz) 120 flash memory size (kb) with 1024 words per page 48 48 48 64 64 64 ram size (kb) 668888 enhanced flex pwm (eflexpwm) high resolution nanoedge pwm (520ps res.) 666666 enhanced flex pwm with input capture 003003 pwm fault inputs (from crossbar input) 444444 12-bit adc with x1, 2x, 4x programmable gain 2 x 4ch 2 x 5ch 2 x 8ch 2 x 4ch 2 x 5 ch 2 x 8 ch analog comparators (acmp) each with integrated 5-bit dac 3 12-bit dac 1 cyclic redundancy check (crc) yes inter-integrated circuit (i 2 c) / smbus 2 queued serial peripheral interface (qspi) 1 high speed queued serial communications interface (qsci) 1 1 can be clocked by high speed peripheral clock up to 120 mhz 2 controller area network (mscan) 0 1 high speed 16-bit multi-purpose timers (tmr) 2 2 can be clocked by high speed peripheral clock up to 120 mhz 8 computer operating properly (cop) watchdog timer yes integrated power-on reset and low voltage detection yes phase-locked loop (pll) yes 8 mhz (400 khz at standby mode) on-chip rosc yes crystal/resonator oscillator yes crossbarinput pins 666666 output pins 226226 general purpose i/o (gpio) 3 3 shared with other function pins 35 39 54 35 39 54 ieee 1149.1 joint te st action group (jtag) interface yes enhanced on-chip emulator (eonce) yes operating temperature range -40 c to 105 c package 44lqfp 48lqfp 64lq fp 44lqfp 48lqfp 64lqfp
mc56f825x/mc56f824x digital si gnal controller, rev. 3 overview freescale semiconductor 4 2 overview 2.1 mc56f825x/mc56f824x features 2.1.1 core ? efficient 56800e digital signal processor (dsp) engine with modified harvard architecture ? three internal address buses ? four internal data buses ? as many as 60 million instructions per second (mips) at 60 mhz core frequency ? 155 basic instructions in conjunction with up to 20 address modes ? 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical operation ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? 32-bit arithmetic and logic multi-bit shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? instruction set supports dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, processor speed?independent, real-time debugging 2.1.2 operation range ? 3.0 v to 3.6 v operation (power supplies and i/o) ? from power-on-reset: approximately 2.7 v to 3.6 v ? ambient temperature operating range: ?40 c to +105 c 2.1.3 memory ? dual harvard architecture that perm its as many as three simultaneous accesses to program and data memory ? 48 kb (24k x 16) to 64 kb (32k x 16) on-chip flash memory with 2048 bytes (1024 x 16) page size ? 6 kb (3k x 16) to 8 kb (4k x 16) on-chip ram with byte addressable ? eeprom emulation capability using flash ? support for 60 mhz program execution from both internal flash and ram memories ? flash security and protection that prevent unauthorized users from ga ining access to the internal flash 2.1.4 interrupt controller ? five interrupt priority levels ? three user programmable priority levels for each interrupt source: level 0, 1, 2 ? unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, and swi3 instruction ? maskable level 3 interrupts include: eonce step co unter, eonce breakpoint unit, and eonce trace buffer
overview mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 5 ? lowest-priority software interrupt: level lp ? nested interrupts: higher priority level interrupt re quest can interrupt lower priority interrupt subroutine ? two programmable fast interrupts that can be assigned to any interrupt source ? notification to system integration module (sim) to restart clock out of wait and stop states ? ability to relocate interrupt vector table the masking of interrupt priority level is managed by the 56800e core. 2.1.5 peripheral highlights ? one enhanced flex pulse width modulator (eflexpwm) module ? up to nine output channels ? 16-bit resolution for center aligned, edge aligned, and asymmetrical pwms ? each complementary pair can op erate with its own pwm frequency based and deadtime values ?4 time base ? independent top and bottom deadtime insertion ? pwm outputs can operate as complimentary pairs or independent channels ? independent control of both edges of each pwm output ? 6-channel nanoedge high resolution pwm ? fractional delay for enhanced resoluti on of the pwm period and edge placement ? arbitrary eflexpwm edge placement - pwm phase shifting ? nanoedge implementation: 520 ps pwm frequency resolution ? 3 channel pwm with full input capture features ? three pwm channels - pwma, pwmb, and pwmx ? enhanced input capture functionality ? support for synchronization to external hardware or other pwm ? double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability ? multiple output trigger events can be generated per pwm cycle via hardware ? support for double switching pwm outputs ? up to four fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? individual software control for each pwm output ? all outputs can be progra mmed to change simultane ously via a force_out event ? pwmx pin can optionally output a th ird pwm signal from each submodule ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation can be used for input capture functions ? enhanced dual edge capture functionality ? option to supply the source for each complementary pwm signal pa ir from any of the following: ? crossbar module outputs ? external adc input, taking into account values set in adc high and low limit registers ? two independent 12-bit analog-to-digital converters (adcs) ? 2 x 8 channel external inputs ? built-in x1, x2, x4 program mable gain pre-amplifier
mc56f825x/mc56f824x digital si gnal controller, rev. 3 overview freescale semiconductor 6 ? maximum adc clock frequency: up to 10 mhz ? single conversion time of 8.5 adc clock cycles (8.5 x 100 ns = 850 ns) ? additional conversion time of 6-adc clock cycles (6 x 100 ns = 600 ns) ? sequential, parallel, and independent scan mode ? first 8 samples have offset, limit and zero-crossing calculation supported ? adc conversions can be synchronized by eflexpwm and timer modules via in ternal crossbar module ? support for simultaneous and software triggering conversions ? support for multi-trigg ering mode with a programmable numb er of conversions on each trigger ? inter-module crossbar switch (xbar) ? programmable internal module connections among th e eflexpwm, adcs, quad ti mers, 12-bit dac, hscmps, and package pins ? user-defined input/output pins for pwm fault inputs, timer input/output, adc triggers, and comparator outputs ? three analog comparators (cmps) ? selectable input source includes external pins, internal dacs ? programmable output polarity ? output can drive timer input, eflexpwm fault input, eflexpwm source, external pin output, and trigger adcs ? output falling and rising edge detection able to generate interrupts ? 32-tap programmable voltage reference per comparator ? one 12-bit digital-to-analog converter (12-bit dac) ? 12-bit resolution ? power down mode ? output can be routed to inte rnal comparator, or off chip ? two four-channel 16-bit multi-purpose timer (tmr) modules ? four independent 16-bit counter/timers with cascading capability per module ? up to 120 mhz operating clock ? each timer has capture and compare and quadrature decoder capability ? up to 12 operating modes ? four external inputs an d two external outputs ?two queued serial communication interface (qsci) modules with lin slave functionality ? up to 120 mhz operating clock ? four-byte-deep fifos available on both transmit and receive buffers ? full-duplex or single-wire operation ? programmable 8- or 9-bit data format ? 13-bit integer and 3-bit fractional baud rate selection ? two receiver wakeup methods: ? idle line ? address mark ? 1/16 bit-time noise detection ? support lin slave operation ? one queued serial peripheral in terface (qspi) module ? full-duplex operation ? four-word deep fifos available on both transmit and receive buffers ? master and slave modes ? programmable length transactions (2 to 16 bits) ? programmable transmit and recei ve shift order (msb as fi rst or last bit transmitted)
overview mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 7 ? maximum slave module frequency = module clock frequency/2 ? 13-bit baud rate divider for low speed communication ? two inter-integrated circuit (i 2 c) ports ? operation at up to 100 kbps ? support for master and slave operation ? support for 10-bit address mode and broadcasting mode ? support for smbus, version 2 ? one freescale scalable controller area network (mscan) module ? fully compliant with can protocol version 2.0 a/b ? support for standard and extended data frames ? support for data rate up to 1 mbit/s ? five receive buffers and three transmit buffers ? computer operating properly (cop) watchdog timer capable of selecting different clock sources ? programmable prescaler and timeout period ? programmable wait, stop, and partial powerdown mode operation ? causes loss of reference reset 128 cycles after loss of reference clock to the pll is detected ? choice of clock sources from four sources in support of en60730 and iec61508: ? on-chip relaxation oscillator ? external crystal oscillat or/external clock source ? system clock (ip bus to 60 mhz) ? power supervisor (ps) ? on-chip linear regulator for digital and an alog circuitry to lower cost and reduce noise ? integrated low voltage detection to generate warning interrupt if vdd is below low voltage detection (lvi) threshold ? integrated power-on reset (por) ? reliable reset process du ring power-on procedure ? por is released after vdd passes low voltage detection (lvi) threshold ? integrated brown-out reset ? run, wait, and stop modes ? phase lock loop (pll) providing a high- speed clock to the co re and peripherals ? 2x system clock provided to quad timers and scis ? loss of lock interrupt ? loss of reference clock interrupt ? clock sources ? on-chip relaxation oscillator with two user selectab le frequencies: 400 khz for low speed mode, 8 mhz for normal operation ? external clock: crystal oscillator, ceram ic resonator, and external clock source ? cyclic redundancy check (crc) generator ? hardware crc generator circu it using 16-bit shift register ? crc16-ccitt complian cy with x16 + x12 + x5 + 1 polynomial ? error detection for all single, double, odd, and most multi-bit errors ? programmable initial seed value ? high-speed hardware crc calculation ? optional feature to transpose input data and crc result via transpose register, required on applications where bytes are in lsb (least significant bit) format.
mc56f825x/mc56f824x digital si gnal controller, rev. 3 overview freescale semiconductor 8 ? up to 54 general-purpose i/o (gpio) pins ? 5 v tolerant i/o ? individual control for each pin to be in peripheral or gpio mode ? individual input/output direction control for each pin in gpio mode ? individual control for each output pin to be in push-pull mode or open-drain mode ? hysteresis and configurable pullup device on all input pins ? ability to generate interrupt with programmabl e rising or falling edge and software interrupt ? configurable drive strength: 4 ma / 8 ma sink/source current ? jtag/eonce debug programming interface for real-time debugging ? ieee 1149.1 joint test action group (jtag) interface ? eonce interface for real-time debugging 2.1.6 power saving features ? low-speed run, wait, and stop modes: as low as 781 hz clock provided by occs and internal rosc ? large regulator standby mode available for reducing power consumption at low-speed mode ? less than 30 s typical wakeup time from stop modes ? each peripheral can be indivi dually disabled to save power 2.2 award-winning development environment processor expert (pe) provides a rapid application design (r ad) tool that combines easy-t o-use component-based software application creation with an expert knowledge system. the codewarrior integrated development environment (ide) is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms), dem onstration board kit, and development system cards supports concurrent engineering. together, pe, codewarrior, and evms create a complete, scalable tool s solution for easy, fast, and efficient development. 2.3 architecture block diagram the mc56f825x/mc56f824x?s architecture appears in figure 1 and figure 2 . figure 1 illustrates how the 56800e system buses communicate with internal memories and the ip bus interface as well as th e internal connections among the units of the 56800e core.
overview mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 9 figure 1. 56800e core block diagram figure 2 shows the peripherals and control blocks connected to the ip bus bridge. refer to the system integration module (sim) section in the device?s reference manual fo r information about which signals are multiplexed with those of other peripherals. data dsp56800e core arithmetic logic unit (alu) xab2 pab pdb cdbw cdbr xdb2 program memory data/ ip bus interface bit- manipulation unit n3 m01 address xab1 generation unit (agu) pc la la2 hws0 hws1 fira omr sr fisr lc lc2 instruction decoder interrupt unit looping unit program control unit alu1 alu2 mac and alu a1 a2 a0 b1 b2 b0 c1 c2 c0 d1 d2 d0 y1 y0 x0 enhanced jtag tap r2 r3 r4 r5 sp r0 r1 n y multi-bit shifter once? program ram
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signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 11 2.4 product documentation the documents listed in table 2 are required for a complete description and proper design with the mc56f825x/mc56f824x. documentation is available from local freescale distributo rs, freescale semiconductor sales offices, freescale literature distribution centers, or online at http://www.freescale.com . 3 signal/connection descriptions 3.1 introduction the input and output signals of the mc56f825x/mc56f824x are organized into functional groups, as detailed in table 3 . table 2. mc56f825x/mc56f824x device documentation topic description order number dsp56800e reference manual detailed description of the 56800e family archit ecture, 16-bit digital signal controller core processor, and the instruction set dsp56800erm mc56f825x reference manual detailed description of peripherals of the mc56f825x/mc56f824x devices mc56f825xrm mc56f824x/5x serial bootloader user guide detailed description of the serial bootloader in the 56f800x family of devices tbd mc56f825x technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f825x mc56f825x errata detailed description of any chip issues that might be present mc56f825xe table 3. functional group pin allocations functional group number of pins in 44 lqfp number of pins in 48 lqfp number of pins in 64 lqfp power inputs (v dd , v dda, v cap )556 ground (v ss , v ssa )444 reset 1 111 enhanced flex pulse width modulator (eflexpwm) ports 1 669 queued serial peripheral interface (spi) ports 1 444 queued serial communications interface 0&1 (qsci0 & qsci1) ports 1 669 inter-integrated circuit interface 0&1 (i 2 c0 & i 2 c0) ports 1 446 analog-to-digital converter (adc) inputs 1 81016 high speed analog com parator inputs/outputs 1 11 12 15 12-bit digital-to-analog converter (dac_12b) output 1 1 1 quad timer module (tmra & tmrb) ports 1 558 freescale?s scalable controller-area-network (mscan) 1, 2 222 inter-module cross bar package inputs/outputs 1 10 12 17 clock 1 344 jtag/enhanced on-chip emulation (eonce) 1 444
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 12 table 4 summarizes all device pins. each table row describes th e signal or signals present on a pin, sorted by pin number. peripheral pins in bold identify reset state. 1 pins may be shared with other peripherals. see ta b l e 4 . 2 exclude mc56f824x. table 4. mc56f825x/mc56f824x pins pin number pin name peripherals 44 lqfp 48 lqfp 64 lqfp gpio i 2 cscispi ms can 1 adc cross bar comp quad timer eflex pwm power jtag misc. 111 tck/ gpiod2 gpiod2 tck 222 reset / gpiod4 gpiod4 reset 333 gpioc0 /xtal/clkin gpioc0 xtal/ clkin 444 gpioc1 /extal gpioc1 extal 5 5 5 gpioc2 /txd0/tb0/xb_in2/ clko gpioc2 txd0 xb_in2 tb0 clko 6gpiof8 /rxd0/tb1 gpiof8 rxd0 tb1 6 6 7 gpioc3 /ta0/cmpa_o/rxd0 gpioc3 rxd0 cmpa_o ta0 778 gpioc4 /ta1/cmpb_o gpioc4 cmpb_o ta1 9gpioa7 /ana7 gpioa7 ana7 10 gpioa6 /ana6 gpioa6 ana6 11 gpioa5 /ana5 gpioa5 ana5 812 gpioa4 /ana4 gpioa4 ana4 8913 gpioa0 /ana0& cmpa_p2/cmpc_o gpioa0 ana0 cmpa_p2/ cmpc_o 91014 gpioa1 / ana1&cmpa_m0 gpioa1 ana1 cmpa_m0 10 11 15 gpioa2 /ana2&vrefha& cmpa_m1 gpioa2 ana2& vrefha cmpa_m1 11 12 16 gpioa3 /ana3&vrefla& cmpa_m2 gpioa3 ana3& vrefla cmpa_m2 17 gpiob7 /anb7&cmpb_m2 gpiob7 anb7 cmpb_m2 12 13 18 gpioc5 /daco/xb_in7 gpioc5 xb_in7 daco 19 gpiob6 /anb6&cmpb_m1 gpiob6 anb6 cmpb_m1 20 gpiob5 /anb5&cmpc_m2 gpiob5 anb5 cmpc_m2 14 21 gpiob4 /anb4&cmpc_m1 gpiob4 anb4 cmpc_m1 13 15 22 v dda v dda 14 16 23 v ssa v ssa 15 17 24 gpiob0 / anb0&cmpb_p2 gpiob0 anb0 cmpb_p2 16 18 25 gpiob1 / anb1&cmpb_m0 gpiob1 anb1 cmpb_m0 17 19 26 v cap v cap 18 20 27 gpiob2 / anb2&vrefhb&cmpc_p2 gpiob2 anb2& vrefhb cmpc_p2
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 13 19 21 28 gpiob3 / anb3&vreflb&cmpc_m0 gpiob3 anb3& vreflb cmpc_m0 29 v dd v dd 20 22 30 v ss v ss 21 23 31 gpioc6 /ta2/xb_in3/ cmp_ref gpioc6 xb_in3 cmp_ref ta2 22 24 32 gpioc7 /ss /txd0 gpioc7 txd0 ss 23 25 33 gpioc8 /miso/rxd0 gpioc8 rxd0 miso 24 26 34 gpioc9 /sclk/xb_in4 gpioc9 sclk xb_in4 25 27 35 gpioc10/mosi/xb_in5/miso gpioc10 mosi/ miso xb_in5 28 36 gpiof0 /xb_in6 gpiof0 xb_in6 26 29 37 gpioc11 /cantx/scl1/txd1 gpioc11 scl1 txd1 cantx 27 30 38 gpioc12 /canrx/sda1/rxd1 gpioc12 sda1 rxd1 canrx 39 gpiof2 /scl1/xb_out2 gpiof2 scl1 xb_out2 40 gpiof3 /sda1/xb_out3 gpiof3 sda1 xb_out3 41 gpiof4 /txd1/xb_out4 gpiof4 txd1 xb_out4 42 gpiof5 /rxd1/xb_out5 gpiof5 rxd1 xb_out5 28 31 43 v ss v ss 29 32 44 v dd v dd 30 33 45 gpioe0 /pwm0b gpioe0 pwm0b 31 34 46 gpioe1 /pwm0a gpioe1 pwm0a 32 35 47 gpioe2/ pwm1b gpioe2 pwm1b 33 36 48 gpioe3 /pwm1a gpioe3 pwm1a 34 37 49 gpioc13 /ta3/xb_in6 gpioc13 xb_in6 ta 3 38 50 gpiof1 /clko/xb_in7 gpiof1 xb_in7 clko 35 39 51 gpioe4/ pwm2b/xb_in2 gpioe4 xb_in2 pwm2b 36 40 52 gpioe5/ pwm2a/xb_in3 gpioe5 xb_in3 pwm2a 53 gpioe6/ pwm3b/xb_in4 gpioe6 xb_in4 pwm3b 54 gpioe7/ pwm3a/xb_in5 gpioe7 xb_in5 pwm3a 37 41 55 gpioc14 /sda0/xb_out0 gpioc14 sda0 xb_out0 38 42 56 gpioc15 /scl0/xb_out1 gpioc15 scl0 xb_out1 39 43 57 v cap v cap 58 gpiof6 /tb2/pwm3x gpiof6 tb2 pwm3x 59 gpiof7 /tb3 gpiof7 tb3 40 44 60 v dd v dd table 4. mc56f825x/mc56f824x pins (continued) pin number pin name peripherals 44 lqfp 48 lqfp 64 lqfp gpio i 2 cscispi ms can 1 adc cross bar comp quad timer eflex pwm power jtag misc.
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 14 41 45 61 v ss v ss 42 46 62 tdo /gpiod1 gpiod1 tdo 43 47 63 tms /gpiod3 gipod3 tms 44 48 64 tdi /gpiod0 gpiod0 tdi 1 the mscan module is not available on the mc56f824x devices. table 4. mc56f825x/mc56f824x pins (continued) pin number pin name peripherals 44 lqfp 48 lqfp 64 lqfp gpio i 2 cscispi ms can 1 adc cross bar comp quad timer eflex pwm power jtag misc.
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 15 3.2 pin assignment figure 3 shows the pin assignments of the 56f8245 and 56f825 5?s 44-pin low-profile quad flat pack (44lqfp). figure 4 shows the pin assignments of the 56f8246 and 56f8256?s 48-pin low-profile quad flat pack (48lqfp). figure 5 shows the pin assignments of the 56f8247 and 56f8257?s 64-pi n low-profile quad fl at pack (64lqfp). note the canrx and cantx signals of the mscan module are not available on the mc56f824x devices. figure 3. top view: 56f8245 and 56f8255 44-pin lqfp package gpiod2/tck gpiod4/reset gpioc0/xtal/clkin gpioc1/extal gpioc2/txd0/tb0/xb_in2/clko gpioc3/ta0/cmpa_o/rxd0 gpioc4/ta1/cmpb_o gpioa0/ana0/cmpa_p2/cmpc_o gpioa1/ana1/cmpa_m0 gpioa2/ana2/vrefha/cmpa_m1 gpioa3/ana3/vrefla/cmpa_m2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 gpioc5/daco/xb_in7 vdda vssa gpiob0/anb0/cmpb_p2 gpiob1/anb1/cmpb_m0 vcap gpiob2/anb2/vrefhb/cmpc_p2 gpiob3/anb3/vreflb/cmpc_m0 vss gpioc6/ta2/xb_in3/cmp_ref gpioc7/ss /txd0 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 gpiod0/tdi gpiod3/tms gpiod1/tdo vss vdd vcap gpioc15/scl0/xb_out1 gpioc14/sda0/xb_out0 gpioe5/pwm2a/xb_in3 gpioe4/pwm2b/xb_in2 gpioc13/ta3/xb_in6 gpioe3/pwm1a gpioe2/pwm1b gpioe1/pwm0a gpioe0/pwm0b vdd vss gpioc12/canrx0/sda1/rxd1 gpioc11/cantx0/scl1/txd1 gpioc10/mosi/xb_in5/miso gpioc9/sclk/xb_in4 gpioc8/miso/rxd0
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 16 figure 4. top view: 56f8246 and 56f8256 48-pin lqfp package gpiod2/tck gpiod4/reset gpioc0/xtal/clkin gpioc1/extal gpioc2/txd0/tb0/xb_in2/clko gpioc3/ta0/cmpa_o/rxd0 gpioc4/ta1/cmpb_o gpioa4/ana4 gpioa0/ana0/cmpa_p2/cmpc_o gpioa1/ana1/cmpa_m0 gpioa2/ana2/vrefha/cmpa_m1 gpioa3/ana3/vrefla/cmpa_m2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 gpioc5/daco/xb_in7 gpiob4/anb4/cmpc_m1 vdda vssa gpiob0/anb0/cmpb_p2 gpiob1/anb1/cmpb_m0 vcap gpiob2/anb2/vrefhb/cmpc_p2 gpiob3/anb3/vreflb/cmpc_m0 vss gpioc6/ta2/xb_in3/cmp_ref gpioc7/ss /txd0 36 35 34 33 32 31 30 29 28 27 26 25 gpioe3/pwm1a gpioe2/pwm1b gpioe1/pwm0a gpioe0/pwm0b vdd vss gpioc12/canrx0/sda1/rxd1 gpioc11/cantx0/scl1/txd1 gpiof0/xb_in6 gpioc10/mosi/xb_in5/miso gpioc9/sclk/xb_in4 gpioc8/miso/rxd0 48 47 46 45 44 43 42 41 40 39 38 37 gpiod0/tdi gpiod3/tms gpiod1/tdo vss vdd vcap gpioc15/scl0/xb_out1 gpioc14/sda0/xb_out0 gpioe5/pwm2a/xb_in3 gpioe4/pwm2b/xb_in2 gpiof1/clko/xb_in7 gpioc13/ta3/xb_in6
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 17 figure 5. top view: 56f8247 and 56f8257 64-pin lqfp package gpiod2/tck gpiod4/reset gpioc0/xtal/clkin gpioc1/extal gpioc2/txd0/tb0/xb_in2/clko gpiof8/rxd0/tb1 gpioc3/ta0/cmpa_o/rxd0 gpioc4/ta1/cmpb_o gpioa7/ana7 gpioa6/ana6 gpioa5/ana5 gpioa4/ana4 gpioa0/ana0/cmpa_p2/cmpc_o gpioa1/ana1/cmpa_m0 gpioa2/ana2/vrefha/cmpa_m1 gpioa3/ana3/vrefla/cmpa_m2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 gpiob7/anb7/cmpb_m2 gpioc5/daco/xb_in7 gpiob6/anb6/cmpb_m1 gpiob5/anb5/cmpc_m2 gpiob4/anb4/cmpc_m1 vdda vssa gpiob0/anb0/cmpb_p2 gpiob1/anb1/cmpb_m0 vcap gpiob2/anb2/vrefhb/cmpc_p2 gpiob3/anb3/vreflb/cmpc_m0 vdd vss gpioc6/ta2/xb_in3/cmp_ref gpioc7/ss /txd0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gpioe3/pwm1a gpioe2/pwm1b gpioe1/pwm0a gpioe0/pwm0b vdd vss gpiof5/rxd1/xb_out5 gpiof4/txd1/xb_out4 gpiof3/sda1/xb_out3 gpiof2/scl1/xb_out2 gpioc12/canrx/sda1/rxd1 gpioc11/cantx/scl1/txd1 gpiof0/xb_in6 gpioc10/mosi/xb_in5/miso gpioc9/sclk/xb_in4 gpioc8/miso/rxd0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gpiod0/tdi gpiod3/tms gpiod1/tdo vss vdd gpiof7/tb3 gpiof6/tb2/pwm3x vcap gpioc15/scl0/xb_out1 gpioc14/sda0/xb_out0 gpioe7/pwm3a/xb_in5 gpioe6/pwm3b/xb_in4 gpioe5/pwm2a/xb_in3 gpioe4/pwm2b/xb_in2 gpiof1/clko/xb_in7 gpioc13/ta3/xb_in6
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 18 3.3 mc56f825x/mc56f824x signal pins after reset, each pin is confi gured for its primary function (listed first). a ny alternative functionality, shown in parenthese s and as italic , must be programmed via the gpio module?s peripheral enable registers (gpio_x_per) and the sim module?s gpio peripheral select (gpsx) registers. table 5. mc56f825x/mc56f824x signal and package information signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description v dd 29 supply supply i/o power ? this pin supplies 3.3 v power to the chip i/o interface. v dd 29 32 44 v dd 40 44 60 v ss 20 22 30 supply supply i/o ground ? these pins provide ground for chip i/o interface. v ss 28 31 43 v ss 41 45 61 v dda 13 15 22 supply supply analog power ? this pin supplies 3.3 v power to the analog modules. it must be connected to a clean analog power supply. v ssa 14 16 23 supply supply analog ground ? this pin supplies an analog ground to the analog modules. it must be connected to a clean power supply. v cap 17 19 26 supply supply v cap ? connect a bypass capacitor of 2.2 f or greater between this pin and v ss to stabilize the core voltage regulator output required for proper device operation. see section 8.2, ?electrical design considerations ,? on page 73 . v cap 39 43 57 tdi (gpiod0) 44 48 64 input input/ output input, internal pullup enabled test data input ? this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pullup resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tdi. tdo (gpiod1) 42 46 62 output input/ output output test data output ? this tri-stateable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tdo. tck (gpiod2) 111 input input/ output input, internal pullup enabled test clock input ? this input pin provides a gated clock to synchronize the test logic and shi ft serial data to the jtag/eonce port. the pin is connected internally to a pullup resistor. a schmitt-trigger input is used for noise immunity. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tck
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 19 tms (gpiod3) 43 47 63 input input/ output input, internal pullup enabled test mode select input ? this input pin is used to sequence the jtag tap controller?s state machin e. it is sampled on the rising edge of tck and has an on-chip pullup resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tms note : always tie the tms pin to vdd through a 2.2k resistor if need to keep on-board debug capability. otherwise directly tie to vdd reset (gpiod4) 222 input input/ open-drain output input, internal pullup enabled reset ? this input is a direct hardware reset on the processor. when reset is asserted low, the device is initialized and placed in the reset state. a schmitt-trigger input is used for noise immunity. the internal reset signal is deasserted synchronous with the internal clocks after a fixed number of internal clocks. port d gpio ? this gpio pin can be individually programmed as an input or open-drain output pin.if reset functionality is disabled in this mode and the chip can be reset only via por, cop reset, or software reset. after reset, the default state is reset . gpioa0 (ana0& cmpa_p2) (cmpc_o) 8 9 13 input/ output input output input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana0 and cmpa_p2 ? analog input to channel 0 of adca and positive input 2 of analog comparator a. cmpc_o? analog comparator c output when used as an analog input, the signal goes to the ana0 and cmpa_p2. after reset, the default state is gpioa0. gpioa1 (ana1& cmpa_m0) 9 10 14 input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana1 and cmpa_m0 ? analog input to channel 1of adca and negative input 0 of analog comparator a. when used as an analog input, the signal goes to the ana1 and cmpa_m0. after reset, the default state is gpioa1. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 20 gpioa2 (ana2& vrefha& cmpa_m1) 10 11 15 input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana2 and vrefha and cmpa_m1 ? analog input to channel 2 of adca and analog references high of adca and negative input 1 of analog comparator a. when used as an analog input, the signal goes to ana2 and vrefha and cmpa_m1. adc control re gister configures this input as ana2 or vrefha. after reset, the default state is gpioa2. gpioa3 (ana3& vrefla& cmpa_m2) 11 12 16 input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana3 and vrefla and cmpa_m2 ? analog input to channel 3 of adca and analog references low of adca and negative input 2 of analog comparator a. when used as an analog input, the signal goes to ana3 and vrefla and cmpa_m2. adc control register configures this input as ana3 or vrefla. after reset, the default state is gpioa3. gpioa4 (ana4) 8 12 input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana4 ? analog input to channel 4 of adca. after reset, the default state is gpioa4. gpioa5 (ana5) 11 input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana5 ? analog input to channel 5 of adca. after reset, the default state is gpioa5. gpioa6 (ana6) 10 input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana6 ? analog input to channel 5 of adca. after reset, the default state is gpioa6. gpioa7 (ana7) 9 input/ output input input, internal pullup enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. ana7 ? analog input to channel 7 of adca. after reset, the default state is gpioa7. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 21 gpiob0 (anb0& cmpb_p2) 15 17 24 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb0 and cmpb_p2 ? analog input to channel 0 of adcb and positive input 2 of analog comparator b. when used as an analog input, the signal goes to anb0 and cmpb_p2. after reset, the default state is gpiob0. gpiob1 (anb1& cmpb_m0) 16 18 25 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb1 and cmpb_m0? analog input to channel 1 of adcb and negative input 0 of analog comparator b. when used as an analog input, the signal goes to anb1 and cmpb_m0. after reset, the default state is gpiob1. gpiob2 (anb2& vrefhb& cmpc_p2) 18 20 27 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb2 and vrefhb and cmpc_p2 ? analog input to channel 2 of adcb and analog references high of adcb and positive input 2 of analog comparator c. when used as an analog input, the signal goes to anb2 and vrefhb and cmpc_p2. adc control register configures this input as anb2 or vrefhb. after reset, the default state is gpiob2. gpiob3 (anb3& vreflb& cmpc_m0) 19 21 28 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb3 and vreflb and cmpc_m0 ? analog input to channel 3 of adcb and analog references low of adcb and negative input 0 of analog comparator c. when used as an analog input, the signal goes to anb3 and vreflb and mpc_m0. adc control register configures this input as anb3 or vreflb. after reset, the default state is gpiob3. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 22 gpiob4 (anb4& cmpc_m1) 14 21 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb4 and cmpc_m1 ? analog input to channel 4 of adcb and negative input 1 of analog comparator c. after reset, the default state is gpiob4. gpiob5 (anb5& cmpc_m2) 20 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb5 and cmpc_m2 ? analog input to channel 5 of adcb and negative input 2 of analog comparator c. after reset, the default state is gpiob5. gpiob6 (anb6& cmpb_m1) 19 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb6 and cmpb_m1 ? analog input to channel 6 of adcb and negative input 1 of analog comparator b. after reset, the default state is gpiob6. gpiob7 (anb7& cmpb_m2) 17 input/ output input input, internal pullup enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. anb7 and cmpb_m2 ? analog input to channel 7 of adcb and negative input 2 of analog comparator b. after reset, the default state is gpiob7. gpioc0 xtal clkin 333 input/ output analog output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. xtal ? external crystal oscillator output. this output connects the internal crystal oscillator output to an external crystal or ceramic resonator. clkin ? this pin serves as an external clock input. 1 after reset, the default state is gpioc0. gpioc1 (extal) 444 input/ output analog input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. extal ? external crystal oscillator input. this input connects the internal crystal oscillator input to an external crystal or ceramic resonator. after reset, the default state is gpioc1. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 23 gpioc2 (txd0) (tb0) (xb_in2) (clko) 555 input/ output output input/ output input output input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. txd0 ? the sci0 transmit data output or transmit/receive in single wire operation. tb0 ? quad timer module b channel 0 input/output. xb_in2 ? crossbar module input 2 clko ? this is a buffered clock outp ut; the clock source is selected by clockout select (clkosel) bits in the clock output select register (clkout) of the sim. after reset, the default state is gpioc2. gpioc3 (ta0) (cmpa_o) (rxd0) 667 input/ output input/ output output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. ta0 ? quad timer module a channel 0 input/output. cmpa_o? analog comparator a output rxd0 ? the sci0 receive data input. after reset, the default state is gpioc3. gpioc4 (ta1) (cmpb_o) 778 input/ output input/ output output input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. ta1 ? quad timer module a channel 1input/output cmpb_o ? analog comparator b output after reset, the default state is gpioc4. gpioc5 (daco) (xb_in7) 12 13 18 input/ output analog output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. daco ? 12-bit digital-to-analog controller output xb_in7 ? crossbar module input 7 after reset, the default state is gpioc5. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 24 gpioc6 (ta2) (xb_in3) (cmp_ref) 21 23 31 input/ output input/ output input analog input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. ta2 ? quad timer module a channel 2 input/output xb_in3 ? crossbar module input 3 cmp_ref? positive input 3 of analog comparator a and b and c after reset, the default state is gpioc6 gpioc7 (s s ) (txd0) 22 24 32 input/ output input/ output output input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. ss ? ss is used in slave mode to in dicate to the spi module that the current transfer is to be received. txd0 ? sci0 transmit data output or transmit/receive in single wire operation after reset, the default state is gpioc7. gpioc8 (miso) (rxd0) 23 25 33 input/ output input/ output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. miso ? master in/slave out. in mast er mode, this pin serves as the data input. in slave mode, this pin serves as the data output. the miso line of a slave device is pl aced in the high-impedance state if the slave device is not selected. rxd0 ? sci0 receive data input after reset, the default state is gpioc8. gpioc9 (sclk) (xb_in4) 24 26 34 input/ output input/ output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. sclk ? the spi serial clock. in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. xb_in4 ? crossbar module input 4 after reset, the default state is gpioc9. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 25 gpioc10 (mosi) (xb_in5) (miso) 25 27 35 input/ output input/ output input input/ output input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. mosi ? master out/slave in. in mast er mode, this pin serves as the data output. in slave mode, this pin serves as the data input. xb_in5 ? crossbar module input 5 miso ? master in/slave out. in mast er mode, this pin serves as the data input. in slave mode, this pin serves as the data output. the miso line of a slave device is pl aced in the high-impedance state if the slave device is not selected. after reset, the default state is gpioc10. gpioc11 (cantx) (scl1) (txd1) 26 29 37 input/ output open-drain output input/ open-drain output output input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. cantx ? can transmit data out put (not available on 56f8245/46/47) scl1 ? i 2 c1 serial clock txd1 ? sci1 transmit data output or transmit/receive in single wire operation after reset, the default state is gpioc11. gpioc12 (canrx) (sda1) (rxd1) 27 30 38 input/ output input input/ open-drain output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. canrx ? can receive data input (not available on 56f8245/46/47) sda1 ? i 2 c1 serial data line rxd1 ? sci1 receive data input after reset, the default state is gpioc12. gpioc13 (ta3) (xb_in6) 34 37 49 input/ output input/ output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. ta3 ? quad timer module a channel 3input/output. xb_in6 ? crossbar module input 6 after reset, the default state is gpioc13. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 26 gpioc14 (sda0) (xb_out0) 37 41 55 input/ output input/ open-drain output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. sda0 ? i 2 c0 serial data line xb_out0 ? crossbar module output 0 after reset, the default state is gpioc14. gpioc15 (scl0) (xb_out1) 38 42 56 input/ output input/ open-drain output input input, internal pullup enabled port c gpio ? this gpio pin can be individually programmed as an input or output pin. scl0 ? i 2 c0 serial clock xb_out1 ? crossbar module output 1 after reset, the default state is gpioc15. gpioe0 pwm0b 30 33 45 input/ output input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm0b ? nanoedge pwm submodule 0 output b after reset, the default state is gpioe0. gpioe1 (pwm0a) 31 34 46 input/ output output input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm0a ? nanoedge pwm submodule 0 output b after reset, the default state is gpioe1. gpioe2 (pwm1b) 32 35 47 input/ output output input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm1b ? nanoedge pwm submodule 1 output a after reset, the default state is gpioe2. gpioe3 (pwm1a) 33 36 48 input/ output output input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm1a ? nanoedge pwm submodule 1 output a after reset, the default state is gpioe3. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
signal/connection descriptions mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 27 gpioe4 (pwm2b) (xb_in2) 35 39 51 input/ output output input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm2b ? nanoedge pwm submodule 2 output b xb_in2 ? crossbar module input 2 after reset, the default state is gpioe4. gpioe5 (pwm2a) (xb_in3) 36 40 52 input/ output output input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm2a ? nanoedge pwm submodule 2 output a xb_in3 ? crossbar module input 3 after reset, the default state is gpioe5. gpioe6 (pwm3b) (xb_in4) 53 input/ output input/ output input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm3b ? enhanced pwm submodule 3 output b or input capture b xb_in4 ? crossbar module input 4 after reset, the default state is gpioe6. gpioe7 (pwm3a) (xb_in5) 54 input/ output input/ output input input, internal pullup enabled port e gpio ? this gpio pin can be individually programmed as an input or output pin. pwm3a ? enhanced pwm submodule 3 output a or input capture a xb_in5 ? crossbar module input 5 after reset, the default state is gpioe7. gpiof0 (xb_in6) 28 36 input/ output input input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. xb_in6 ? crossbar module input 6 after reset, the default state is gpiof0. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
mc56f825x/mc56f824x digital si gnal controller, rev. 3 signal/connect ion descriptions freescale semiconductor 28 gpiof1 (clko) (xb_in7) 38 50 input/ output output input input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. clko ? this is a buffered clock outp ut; the clock source is selected by clockout select (clkosel) bits in the clock output select register (clkout) of the sim. xb_in7 ? crossbar module input 7 after reset, the default state is gpiof1. gpiof2 (scl1) (xb_out2) 39 input/ output input/ open-drain output output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. scl1 ? the i 2 c1 serial clock. xb_out2 ? crossbar module output 2 after reset, the default state is gpiof2. gpiof3 (sda1) (xb_out3) 40 input/ output input/ open-drain output output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. sda1 ? the i 2 c1 serial data line. xb_out3 ? crossbar module output 3 after reset, the default state is gpiof3. gpiof4 (txd1) (xb_out4) 41 input/ output output output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. txd1 ? the sci1 transmit data output or transmit/receive in single wire operation. xb_out4 ? crossbar module output 4 after reset, the default state is gpiof4. gpiof5 (rxd1) (xb_out5) 42 input/ output output output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. rxd1 ? the sci1 receive data input. xb_out5 ? crossbar module output 5 after reset, the default state is gpiof5. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
memory maps mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 29 4 memory maps 4.1 introduction the mc56f825x/mc56f824x device is based on the 56800e core. it uses a dual harvard-style architecture with two independent memory spaces for data and pr ogram. on-chip ram is shar ed by both data and program spaces; flash memory is used only in program space. this section provides memory maps for: ? program address space, including the interrupt vector table ? data address space, including the eonc e memory and peri pheral memory maps on-chip memory sizes for the device are summarized in table 6 . flash memories? restrictions are identified in the ?use restrictions? column of table 6 . gpiof6 (tb2) (pwm3x) 58 input/ output input/ output input/ output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. tb2 ? quad timer module b channel 2 input/output. pwm3x ? enhanced pwm submodule 3 output x or input capture x after reset, the default state is gpiof6. gpiof7 (tb3) 59 input/ output input/ output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. tb3 ? quad timer module b channel 3 input/output. after reset, the default state is gpiof7. gpiof8 (rxd0) (tb1) 6 input/ output input input/ output input, internal pullup enabled port f gpio ? this gpio pin can be individually programmed as an input or output pin. rxd0 ? the sci0 receive data input. tb1 ? quad timer module b channel 1 input/output. after reset, the default state is gpiof8. 1 if clkin is selected as the device?s external clock input, bo th the gps_c0 bit in gps1 and the ext_sel bit in the occs oscillator control register (osctl) must be set. in this case , it is also recommended to power down the crystal oscillator. table 5. mc56f825x/mc56f824x signal and package information (continued) signal name 44 lqfp 48 lqfp 64 lqfp type state during reset signal description
mc56f825x/mc56f824x digital si gnal controller, rev. 3 memory maps freescale semiconductor 30 4.2 program map the mc56f825x/mc56f824x series provide up to 64 kb on-chip flash memory. it primarily accesses through the program memory buses (pab; pdb). pab is used to select program memo ry addresses; instruction fetc hes are performed over pdb. data can be read from and wr itten to the program memory sp ace through the primary data memo ry buses: cdbw for data write and cdbr for data read. access time for accessing the program me mory space over the data memory buses is longer than for accessing data memory space. the special mo ve instructions are provid ed to support these accesse s. the benefit is that non-time-critical constants or tables can be stored a nd accessed in program memory. the program memory map appears in table 7 , table 8, and table 9 , depending on the device. table 6. chip memory configurations on-chip memory 56f8245 56f8246 56f8247 56f8255 56f8256 56f8357 use restrictions program flash (pflash) 24k x 16 or 48 kb 24k x 16 or 48 kb 32k x 16 or 64 kb erase/program via flash interface unit and word writes to cdbw unified ram (ram) 3k x 16 or 6 kb 4k x 16 or 8kb 4k x 16 or 8kb usable by the program and data memory spaces table 7. program memory map 1 for 56f8255/56/57 at reset 1 all addresses are 16-bit word addresses. begin/end address memory allocation p: 0x1f ffff p: 0x00 8800 reserved p: 0x00 8fff p: 0x00 8000 on-chip ram 2 : 8 kb 2 this ram is shared with data space st arting at address x: 0x00 0000. see figure 6 . p: 0x00 7fff p: 0x00 0000 ? internal program flash: 64 kb ? interrupt vector table locates from 0x00 0000 to 0x00 0085 ? cop reset address = 0x00 0002 ? boot location = 0x00 0000 table 8. program memory map 1 for 56f82447 at reset begin/end address memory allocation p: 0x1f ffff p: 0x00 8800 reserved p: 0x00 8fff p: 0x00 8000 on-chip ram 2 : 8 kb p: 0x00 7fff p: 0x00 2000 ? internal program flash: 48 kb ? interrupt vector table locates from 0x00 2000 to 0x00 2085 ? cop reset address = 0x00 2002 ? boot location = 0x00 2000 p: 0x00 2000 p: 0x00 0000 reserved
memory maps mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 31 4.3 data map the mc56f825x/mc56f824x series contains dual access memory. it can be accessed from core primary data buses (xab1, cdbw, cdbr) and secondary data buses (xab2, xdb2). addr esses in data memory are se lected on the xab1 and xab2 buses. byte, word, and long data transfers occur on the 32-bi t cdbr and cdbw buses. a second 16-bit read operation can be performed in parallel on the xdb2 bus. peripheral registers and on-chip jtag/eon ce controller registers are memory ma pped into data memory access. a special direct address mode is suppor ted for accessing a first 64-location in data me mory by using a single word instruction. the data memory map appears in table 10 and table 11 . 1 all addresses are 16-bit word addresses. 2 this ram is shared with data space st arting at address x: 0x00 0000. see figure 7 . table 9. program memory map 1 for 56f8245/46 at reset 1 all addresses are 16-bit word addresses. begin/end address memory allocation p: 0x1f ffff p: 0x00 8800 reserved p: 0x00 8bff p: 0x00 8000 on-chip ram 2 : 6 kb 2 this ram is shared with data space st arting at address x: 0x00 0000. see figure 7 . p: 0x00 7fff p: 0x00 2000 ? internal program flash: 48 kb ? interrupt vector table locates from 0x00 2000 to 0x00 2085 ? cop reset address = 0x00 2002 ? boot location = 0x00 2000 p: 0x00 2000 p: 0x00 0000 reserved table 10. 56f8247 and 56f8255/56/57 data memory map 1 1 all addresses are 16-bit word addresses. begin/end address memory allocation x:0xff ffff x:0xff ff00 eonce 256 locations allocated x:0xff feff x:0x01 0000 reserved x:0x00 ffff x:0x00 f000 on-chip peripherals 4096 locations allocated x:0x00 efff x:0x00 9000 reserved x:0x00 8fff x:0x00 8000 on-chip data ram alias x:0x00 7fff x:0x00 1000 reserved x:0x00 0fff x:0x00 0000 on-chip data ram 8kb 2
mc56f825x/mc56f824x digital si gnal controller, rev. 3 memory maps freescale semiconductor 32 on-chip ram is also mapped into program space starting at p: 0x00 8000. this mapping eases online reprogramming of on-chip flash. figure 6. 56f8255/56/57 dual port ram map figure 7. 56f8247 dual port ram map 2 this ram is shared with program s pace starting at p: 0x00 8000. see figure 6 and figure 7 . reserved ram reserved eonce peripherals reserved ram dual port ram program data flash 0x00 0000 0x00 1000 0x00 f000 0x01 0000 0xff ff00 0x00 0000 0x00 8000 0x00 9000 0x00 9000 ram alias 0x00 8000 reserved reserved ram reserved eonce peripherals reserved ram dual port ram program data flash 0x00 0000 0x00 1000 0x00 f000 0x01 0000 0xff ff00 0x00 0000 0x00 8000 0x00 9000 0x00 9000 ram alias 0x00 8000 reserved reserved 0x00 2000
memory maps mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 33 figure 8. 56f8245/46 dual port ram map 4.4 interrupt vector table and reset vector the location of the vector table is determin ed by the vector base address register (vba ). the value in this register is used as the upper 14 bits of the interrupt vector vab[20:0]. the lower seven bits are determined based on the highest priority interrup t and are then appended to vba before pres enting the full vab to the core. refer to the device?s reference manual for details. the reset startup addresses of 56f824x and 56f825x are different. ? the 56f825x?s startup address is located at 0x00 0000. th e reset value of vba is reset to a value of 0x0000 that corresponds to the address 0x00 0000. table 11. 56f8245/56 data memory map 1 1 all addresses are 16-bit word addresses. begin/end address memory allocation x:0xff ffff x:0xff ff00 eonce 256 locations allocated x:0xff feff x:0x01 0000 reserved x:0x00 ffff x:0x00 f000 on-chip peripherals 4096 locations allocated x:0x00 efff x:0x00 8c00 reserved x:0x00 8bff x:0x00 8000 on-chip data ram alias x:0x00 7fff x:0x00 0c00 reserved x:0x00 0bff x:0x00 0000 on-chip data ram 6kb 2 2 this ram is shared with program sp ace starting at p: 0x00 8000. see figure 8 . reserved ram reserved eonce peripherals reserved ram dual port ram program data flash 0x00 0000 0x00 0c00 0x00 f000 0x01 0000 0xff ff00 0x00 0000 0x00 8000 0x00 8c00 0x00 8c00 ram alias 0x00 8000 reserved reserved 0x00 2000
mc56f825x/mc56f824x digital si gnal controller, rev. 3 memory maps freescale semiconductor 34 ? the 56f824x?s startup address is located at 0x00 2000. th e reset value of vba is reset to a value of 0x0020 that corresponds to the address 0x00 2000. by default, the chip reset address and cop reset address correspo nd to vector 0 and 1 of the interrupt vector table. in these instances, the first two locations in the vector table must contai n branch or jmp instructions. all other entries must contain jsr instructions. table 48 on page 85 provides the mc56f825x/mc56f824x?s interrupt table contents and interrupt priority structure. 4.5 peripheral memory-mapped registers the locations of on-chip peripheral registers are part of the data memory map on the 56800e series. these locations may be accessed with the same addressing modes used for ordinary data memory. however, all peripheral registers should be read or written using word accesses only. table 12 summarizes the base addresses for the set of periphe rals on the mc56f825x/mc56f824x devices. peripherals are listed in order of the base address. table 12. data memory periphe ral base address map summary peripheral prefix base address quad timer a tmra x:0x00 f000 quad timer b tmrb x:0x00 f040 analog-to-digital converter adc x:0x00 f080 interrupt controller intc x:0x00 f0c0 system integration module sim x:0x00 f0e0 crossbar module xbar x:0x00 f100 computer operating proper ly module cop x:0x00 f110 on-chip clock synthesis module occs x:0x00 f120 power supervisor ps x:0x00 f130 gpio port a gpioa x:0x00 f140 gpio port b gpiob x:0x00 f150 gpio port c gpioc x:0x00 f160 gpio port d gpiod x:0x00 f170 gpio port e gpioe x:0x00 f180 gpio port f gpiof x:0x00 f190 12-bit digital-to-analog converter dac x:0x00 f1a0 analog comparator a cmpa x:0x00 f1b0 analog comparator b cmpb x:0x00 f1c0 analog comparator c cmpc x:0x00 f1d0 queued serial communication interface 0 qsci0 x:0x00 f1e0 queued serial communication interface 1 qsci1 x:0x00 f1f0 queued serial peripheral interface qspi x:0x00 f200 inter-integrated circuit 0 i 2 c0 x:0x00 f210 inter-integrated circuit 1 i 2 c1 x:0x00 f220
memory maps mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 35 4.6 eonce memory map control registers of the eonce are located at the top of data memory space. these lo cations are fixed by th e 56800e core. these registers can also be accessed through the jtag port if flash security is not set. table 13 lists all eonce registers necessary to access or control the eonce. cyclic redundancy check generator crc x:0x00 f230 comparator voltage reference a refa x:0x00 f240 comparator voltage reference b refb x:0x00 f250 comparator voltage reference c refb x:0x00 f260 enhanced flex pwm module eflexpwm x:0x00 f300 flash memory interface fm x:0x00 f400 freescale controller area network 1 mscan x:0x00 f440 1 the core must enable clocks to the freescale controller area network module prior to accessing mscan addresses. for details, refer to the mscan chapter of the device?s reference manual. table 13. eonce memory map address register abbreviation register name x:0xff ffff otx1/orx1 trans mit register upper word receive register upper word x:0xff fffe otx/orx (32 bits) transmit register receive register x:0xff fffd otxrxsr transmit and receive status and control register x:0xff fffc oclsr core lock/unlock status register x:0xff fffb? x:0xff ffa1 reserved x:0xff ffa0 ocr control register x:0xff ff9f?x:0xff ff9e oscntr (24 bits) instruction step counter x:0xff ff9d osr status register x:0xff ff9c obase periphera l base address register x:0xff ff9b otbcr trace buffer control register x:0xff ff9a otbpr trace buffer pointer register x:0xff ff99?x:0xff ff98 otb (21?24 bits/stage) trace buffer register stages x:0xff ff97?x:0xff ff96 obcr (24 bits) breakpoint unit control register x:0xff ff95?x:0xff ff94 obar1 (24 bits) breakpoint unit address register 1 x:0xff ff93?x:0xff ff92 obar2 (32 bits) breakpoint unit address register 2 table 12. data memory peripheral base address map summary (continued) peripheral prefix base address
mc56f825x/mc56f824x digital si gnal controller, rev. 3 general system control information freescale semiconductor 36 5 general system control information 5.1 overview this section discusses power pins, reset sources, interrupt sour ces, clock sources, the system in tegration module (sim), adc synchronization, and jtag/eonce interfaces. 5.2 power pins v dd , v ss and v dda , v ssa are the primary power supply pins for the device. the voltage source supplies power to all on-chip peripherals, i/o buffer circuitry, and internal voltage regulato rs. the device has multiple internal voltages to provide regula ted lower-voltage sources for the peripherals, core , memory, and on-chip relaxation oscillators. typically, at least two separate capacitors are across the power pi ns to bypass the glitches and provide bulk charge storage. i n this case, a bulk electrolytic or tantalum capacitor, such as a 10 f tantalum cap acitor, should provide bulk charge storage for the overall system, and a 0.1 f ceramic bypass capacitor should be located as near to the device power pins as is practical to suppress high-frequency nois e. each pin must have a bypass capacitor for optimal noise suppression. v dda and v ssa are the analog power supply pins fo r the device. this voltage source supplies power to the adc, pga, and cmp modules. a 0.1 f ceramic bypass capacitor should be located as near to the device v dda and v ssa pins as is practical to suppress high-frequency noise. v dda and v ssa are also the voltage reference high and voltage reference low inputs, respectively, for the adc module. 5.3 reset resetting the device provides a way to start processing from a known set of initial conditions. during reset, most control and status registers are forced to initial valu es, and the program counter is loaded from the reset vector. on-chip peripheral modu les are disabled and i/o pins are initially configured at the reset status shown in table 5 on page 18 . the mc56f825x/mc56f824x has the following sources for reset: ? power-on reset (por) ? partial power-down reset (ppd) ? low-voltage detect (lvd) ? external pin reset (extr) ? computer operating properly loss of reference reset (cop_lor) ? computer operating properly time-out reset (cop_cpu) x:0xff ff91?x:0xff ff90 obmsk (32 bits ) breakpoint unit mask register 2 x:0xff ff8f reserved x:0xff ff8e obcntr eonce breakpoint unit counter x:0xff ff8d reserved x:0xff ff8c reserved x:0xff ff8b reserved x:0xff ff8a oescr externa l signal control register x:0xff ff89 ?x:0xff ff00 reserved table 13. eonce memory map address register abbreviation register name
general system control information mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 37 ? software reset (swr) each of these sources has an associated bit in the reset stat us register (rstat) in the system integration module (sim). the external pin reset function is shar ed with a gpio port a7 on the reset /gpioa7 pin. the reset function is enabled following any reset of the device. bit 7 of the gpioa_per register must be cleared to use this pin as a gpio port pin. when the pin is enabled as the reset pin, an internal pullup device is automatically enabled. 5.4 on-chip clock synthesis the on-chip clock synthesis (occs) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56f8000 family devices at user-selectable frequencies up to 60 mhz. the features of occs module include: ? ability to power down the internal relaxation oscillator or crystal oscillator ? ability to put the internal relaxation oscillator into standby mode ? ability to power down the pll ? provides a 2x system clock that operates at two tim es the system clock to the timer and sci modules ? safety shutdown feature if th e pll reference clock is lost ? ability to be driven from an external clock source the clock generation module provides the programming interface for the pll, internal relaxation oscillator, and crystal oscillator. it also provides a postscaler to divide clock frequenc y down by 1, 2, 4, 8, 16, 32, 64, 128, or 256 before feeding it to the sim. the sim is responsible for further dividing these freque ncies by 2, which ensures a 50% du ty cycle in the system clock output. for details, refer to the occs section of the device?s reference manual. 5.4.1 internal clock source when an external frequency source or crysta l is not used, an internal relaxation osc illator can supply th e reference frequency. it is optimized for accu racy and programmability while providing several power-saving c onfigurations that accommodate different operating conditions. the internal relaxation oscillator has little temperature and voltage variability. to optimize power, the internal relaxation oscillator supports a run st ate (8 mhz), standby state (400 khz), and a power-down state. during a boot or reset sequence, the relaxation oscillator is enable d by default (the precs bit in the pllcr word is set to 0). application code can then also switch to the external clock source and power down the internal oscillator, if desired. if a changeover between internal and external cl ock sources is required at power-on, ensure that the clock source is not switched until the desired external clock source is enabled and stable. to compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.078% of 8 mhz by trimming an internal capacitor. bits 0?9 of the oscill ator control (osctl) register allow you to set an additional offset (trim) to this preset va lue to increase or decrease capac itance. each unit added or subtr acted changes the output frequency by about 0.078% of 8 mhz, allowing incremental adjustment until the desired frequency accuracy is achieved. the center frequency of the internal oscillat or is calibrated at the factory to 8 mhz, an d the trim value is stored in the flash information block and loaded to the hfm ifr option register 0 at reset. when using the relaxation oscillator, the boot code should read the hfm ifr option register 0 and set this value as osctl trim. for further information, refer to the device?s reference manual. 5.4.2 crystal oscillator/ceramic resonator the internal crystal oscillator circuit is designed to interface with a parallel -resonant crystal resona tor in the frequency ra nge, specified for the external crystal, of 4 m hz to 16 mhz. a ceramic resonator can be substituted for the 4 mhz to 16 mhz range. when used to supply a source to the inte rnal pll, the recommended crystal/resona tor is in the 8 mhz to 16 mhz range to optimize pll performance. osc illator circuits appear in figure 9 and figure 10 . follow the crystal supplier ? s recommendations
mc56f825x/mc56f824x digital si gnal controller, rev. 3 general system control information freescale semiconductor 38 when selecting a crystal, because crystal parameters determ ine the component values required to provide maximum stability and reliable startup. the load capacitance values used in the oscillator circuit design should include all stray layout capacit ances. the crystal and associated components should be mounted as near as possible to the extal and xtal pins to minimize output distortion and startup stabilization time. when using low-frequency, low-power mode, the only external component is the crystal itself. in the other osci llator modes, load capacitors (c x , c y ) and feedback resistor (r f ) are required. in addition, a series resistor (r s ) may be used in high-gain modes. r ecommended component values appear in table 27 . figure 9. typical crystal oscillator circuit without frequency compensation capacitor figure 10. typical crystal or ceramic resonator circuit 5.4.3 alternate external clock input the recommended method of connectin g an external clock appears in figure 11 . the external clock source is connected to the clkin pin while: ? both the ext_sel bit and the clk_mode b it in the osctl register are set, and ? corresponding bits in the gpiob_per register in the gpio module and the gps_c0 bit in the gps0 register in the system integration module (sim) are set to the correct values. the external clock input must be generated using a relatively low-impedance driver with a maximum frequency not greater than 120 mhz. extal xtal mc56f825x/mc56f824x crystal frequency = 4?16 mhz osc_div2 = 1 if 16 mhz is chosen r f extal xtal c 1 c 2 mc56f825x/mc56f824x crystal frequency = 4?16 mhz osc_div2 = 1 if 16 mhz is chosen
general system control information mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 39 figure 11. connecting an external clock signal using gpio 5.5 interrupt controller the mc56f825x/mc56f824x interrupt controller (intc) module arb itrates the various interrupt requests (irqs). when an interrupt of sufficient priority exists, the intc signals to the 56800e core and provides the address to which to jump to servi ce the interrupt. the interrupt controller co ntains registers that allow each of the 66 interrupt sources to be se t to one of three priority leve ls (excluding certain interrupt sources that have fixed priority) or to be disabled. next , all interrupt requests of a given level are priority encoded to determine the lowest numeric value of the active interrupt requests for that level. within a given priority level, the lowest vector number is the highest priority, and the highest vector number is the lowest priority. any two interrupt sources can be assigned to faster interrupts. fast interrupts are described in the dsp56800e reference manual . the interrupt controller recognizes fast interrupts before the core does. a fast interrupt is defined by: 1. setting the priority of the interrupt as level 2 with the appropriate field in the interrupt priority register (ipr) registers 2. setting the fast interrupt match (fim n ) register to the appropriate vector number 3. setting the fast interrupt vector address low (fival n) and fast interrupt vector address high (fivah n) registers with the address of th e code for the fast interrupt when an interrupt occurs, its v ector number is compared with the fim0 and fim1 register values. if a match occurs, and it is a level 2 interrupt, the intc handles it as a fast interrupt. the intc takes the vector address from the appropriate fival n and fivah n registers, instead of generating an ad dress that is an of fset from the vba. the core then fetches the instruction from the indicated vector address instead of jumping to the vector table. if the instruct ion is not a jsr, the core starts its fast inte rrupt handling. refer to section 9.3.3.3 of dsp56800e 16-bit core reference manual for details. table 48 on page 85 provides the mc56f825x/mc56f824x?s interrupt table contents and interrupt priority structure. 5.6 system integration module (sim) the sim module consists of the glue logic that ties together th e system-on-a-chip. it controls distribution of resets and clock s and provides a number of control features, including pin muxing control, inter-module connection control (such as connecting comparator output to eflexpwm fault input), individual peripher al enabling/disabling, clock rate control for quad timers and scis, enabling peripheral operation in stop mode, and port configuration overwrite protection. for more information, refer to the device?s reference manual . the sim is responsible for the following functions: ? chip reset sequencing ? core and peripheral clock control and distribution ? stop/wait mode control ? system status control ? registers containing the jtag id of the chip ? controls for programmable pe ripheral and gpio connections clkin external clock ( 120 mhz) ext_sel & clk_mode = 1 gpioc_per0 = 0 gps_c0 = 1 mc56f825x/mc56f824x
mc56f825x/mc56f824x digital si gnal controller, rev. 3 general system control information freescale semiconductor 40 ? peripheral clocks for quad timers and scis with a high-speed (2x) option ? power-saving clock gating for peripherals ? controls for enabling/disabling functions of large regulator standby mode with write protection capability ? allowing selected peripherals to run in stop mode to generate stop recovery interrupts ? controls for programmable pe ripheral and gpio connections ? software chip reset ? i/o short address base location control ? peripheral protection control to provide runaway code protection for safety-critical applications ? controls for output of internal clock sources to clko pin ? four general-purpose software control regi sters that are reset only at power-on ? peripheral stop mode clocking control 5.7 inter-module connections the operations between on-chip peripherals can be synchronized or cascaded through internal module connections to support particular applications. examples include synchronization between adc sampling and pwm waveform generation for a power conversion application, and synchronization between timer pulse outputs and dac waveform generation for a printer application. the user can progr am the internal crossbar switch or comparat or input multiplexes to connect one on-chip peripheral?s outputs to other peripherals? inputs. 5.7.1 comparator connections the mc56f825x/mc56f824x includes three high-speed comparators. each comparator input has a 4-to-1 input mux, allowing it to sample a variety of analog sources. some of thes e inputs share package pins with the on-chip adcs; see table 5 on page 18 . each comparator is paired w ith a dedicated, programmable, 5-bit on-chip voltage reference dac (vref_dac). optionally, an on-chip 12-bit dac can be internally fe d to each comparator?s positive input 1 (cmpn_p1) or negative input 3 (cmpn_m3). in addition, all three comparators? positive input 3 (cmpn_p3) can be connected together to package pin cmp_ref. other inputs can be routed to package pins when the corresponding pin is configured for peripheral mode in the gpio module.
general system control information mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 41 figure 12. on-chip comparator connections table 14. connections by comparator inputs comparator input comparator a comparator b comparator b p0 (from internal) 5-bit vrefa_da c 5-bit vrefb_dac 5-bit vrefc_dac p1 (from internal) 12-bit dac 12-bit dac 12-bit dac p2 (from package pin) cmpa_p2 cmpb_p2 cmpc_p2 p3 (from package pin) cmp_ref cmp_ref cmp_ref
mc56f825x/mc56f824x digital si gnal controller, rev. 3 general system control information freescale semiconductor 42 5.7.2 crossbar switch connections the crossbar switch module provides a generic mechanism for making connections between on- chip peripherals as well as between peripherals and pins. it provides a purely combinational path from input to output. the module groups 30 identical multiplexes with 22 shared inputs. all crossbar control register s that are used to select one of the 22 input signals to output are write protected. control of th e write protection setting is in the sim_prot register. in general, the crossbar modul e connects the enhanced flex pwm, adc, quad ti mers, and comparators t ogether, which allows synchronization between pwm pulse generation and adc sampling. in addition, several crossbar inputs and outputs are routed to package pins. for example, th e user can define an xb_inn pin as a pwm faul t protection input that is routed to the pwm module through the crossbar, increasing the flexibility of pin use and reducing the complexity of pcb layout. m0 (from package pin) cmpa_m0 cmpb_m0 cmpc_m0 m1 (from package pin) cmpa_m1 cmpb_m1 cmpc_m1 m2 (from package pin) cmpa_m2 cmpb_m2 cmpc_m2 m3 (from internal) 12-bit dac 12-bit dac 12-bit dac table 14. connections by comparator inputs (continued) comparator input comparator a comparator b comparator b
general system control information mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 43 figure 13. crossbar switch connections 5.7.2.1 crossbar switch inputs table 15 lists the signal assignment s of crossbar switch inputs. xbar_ ou t3 xbar_ ou t4 xbar_ ou t5 xbar_ ou t9 xbar_in9 xbar_ ou t2 xbar_ ou t1 xbar_ ou t0 xbar_in4 xbar_in3 xbar_in2 xbar_in5 xbar_in6 xbar_in7 window/ sample cmpa cout fault0 fault1 fault2 fault3 ext_clk ext_force exta ext_sync out_trig0 out_trig1 exta ext_sync out_trig0 out_trig1 exta ex t_sync out_trig0 out_trig1 exta ex t_sync out_trig0 out_trig1 submodule 3 xbar_out6 xbar_out7 xbar_out8 adca trigger adca sync_in dac ad cb trigger adcb submodule 2 submodule 1 submodule 0 or or or or tb0 ou t in 1 0 xbar_in12 xbar_out26 xbar_in10 window/ sample cmpb cout xbar_out10 xbar_in11 window/ sample cmpc cout xbar_out11 tb1 out in 1 0 xbar _in13 xbar_out27 tb2 out in 1 0 xbar _in14 xbar_out28 tb3 out in 1 0 xbar _in15 xbar_out29 xbar_out23 xbar_out24 xbar_out25 xbar_out22 xbar_out21 xbar_out20 xbar_out19 xbar_in0 vss vdd xbar_in1 xbar_out15 xbar_in20 xbar_in21 xbar_out18 xbar_out14 xbar_in18 xbar_ out17 xbar_ out13 xbar_ in17 xbar_out16 xbar_out12 xbar_in16 xbar_in19 enhanced flex pwm module crossbar switch gpio mux gpio mux + + + - - - ana0-7 anb0-7 dac0 xbar_ ou t3 xbar_ ou t4 xbar_ ou t5 xbar_ ou t9 xbar_in9 xbar_ ou t2 xbar_ ou t1 xbar_ ou t0 xbar_in4 xbar_in3 xbar_in2 xbar_in5 xbar_in6 xbar_in7 window/ sample cmpa cout fault0 fault1 fault2 fault3 ext_clk ext_force exta ext_sync out_trig0 out_trig1 exta ext_sync out_trig0 out_trig1 exta ex t_sync out_trig0 out_trig1 exta ex t_sync out_trig0 out_trig1 submodule 3 xbar_out6 xbar_out7 xbar_out8 adca trigger adca sync_in dac ad cb trigger adcb submodule 2 submodule 1 submodule 0 or or or or tb0 ou t in 1 0 xbar_in12 xbar_out26 xbar_in10 window/ sample cmpb cout xbar_out10 xbar_in11 window/ sample cmpc cout xbar_out11 tb1 out in 1 0 xbar _in13 xbar_out27 tb2 out in 1 0 xbar _in14 xbar_out28 tb3 out in 1 0 xbar _in15 xbar_out29 xbar_out23 xbar_out24 xbar_out25 xbar_out22 xbar_out21 xbar_out20 xbar_out19 xbar_in0 vss vdd xbar_in1 xbar_out15 xbar_in20 xbar_in21 xbar_out18 xbar_out14 xbar_in18 xbar_ out17 xbar_ out13 xbar_ in17 xbar_out16 xbar_out12 xbar_in16 xbar_in19 enhanced flex pwm module crossbar switch gpio mux gpio mux + + + - - - ana0-7 anb0-7 dac0
mc56f825x/mc56f824x digital si gnal controller, rev. 3 general system control information freescale semiconductor 44 5.7.2.2 crossbar switch outputs table 16 lists the signal assignments of crossbar switch outputs. table 15. crossbar input signal assignments xbar_inn input from function xbar_in0 logic zero v ss xbar_in1 logic one v dd xbar_in2 xb_in2 package pin xbar_in3 xb_in3 package pin xbar_in4 xb_in4 package pin xbar_in5 xb_in5 package pin xbar_in6 xb_in6 package pin xbar_in7 xb_in7 package pin xbar_in8 unused xbar_in9 cmpa_out comparator a output xbar_in10 cmpb_out comparator b output xbar_in11 cmpc_out comparator c output xbar_in12 tb0 quad timer b0 output xbar_in13 tb1 quad timer b1 output xbar_in14 tb2 quad timer b2 output xbar_in15 tb3 quad timer b3 output xbar_in16 pwm0_trig_comb eflexpwm submodule 0: pwm0_out_trig0 or pwm0_out_trig1 xbar_in17 pwm1_trig_comb eflexpwm submodule 1: pwm1_out_trig0 or pwm1_out_trig1 xbar_in18 pwm2_trig_comb eflexpwm submodule 2: pwm2_out_trig0 or pwm2_out_trig1 xbar_in19 pwm[012]_trig_comb eflexpwm subm odule 0, 1, or 2; pwm0_trig_comb or pwm1_trig_comb or pwm2_trig_comb xbar_in20 pwm3_trig0 eflexpwm submodule 3: pwm3_out_trig0 xbar_in21 pwm3_trig1 eflexpwm submodule 3: pwm3_out_trig1 table 16. crossbar output signal assignments xbar_outn output to function xbar_out0 xb_out0 package pin xbar_out1 xb_out1 package pin xbar_out2 xb_out2 package pin xbar_out3 xb_out3 package pin xbar_out4 xb_out4 package pin xbar_out5 xb_out5 package pin xbar_out6 adca adca trigger
general system control information mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 45 5.7.3 interconnection of pwm module and adc module in addition to how pwm0_exta, pwm1_exta, pwm2_exta, and pwm3_exta connect to cr ossbar outputs, the adc conversion high/low limit compare results of sample0, sample 1, and sample2 are used to drive pwm0_extb, pwm1_extb, and pwm2_extb, respectively. pwm3_e xtb is permanently tied to gnd. state of pwm0_extb: ? if the adc conversion result in samp le0 is greater than the value programme d into the high limit register 0, pwm0_extb is driven low. ? if the adc conversion result in sample0 is less than the value programmed into the low limit register 0, pwm0_extb is driven high. state of pwm1_extb: ? if the adc conversion result in samp le1 is greater than the value programme d into the high limit register 1, pwm1_extb is driven low. xbar_out7 adcb adcb trigger xbar_out8 dac 12-bit dac sync_in xbar_out9 cmpa comparator a window/sample xbar_out10 cmpb comparator b window/sample xbar_out11 cmpc comparator c window/sample xbar_out12 pwm0 exta eflexpwm submodule 0 alternate control signal xbar_out13 pwm1 exta eflexpwm submodule 1 alternate control signal xbar_out14 pwm2 exta eflexpwm submodule 2 alternate control signal xbar_out15 pwm3 exta eflexpwm submodule 3 alternate control signal xbar_out16 pwm0 ext_sync eflexpwm submodule 0 external synchronization signal xbar_out17 pwm1 ext_sync eflexpwm submodule 1 external synchronization signal xbar_out18 pwm2 ext_sync eflexpwm submodule 2 external synchronization signal xbar_out19 pwm3 ext_sync eflexpwm submodule 3 external synchronization signal xbar_out20 pwm ext_clk eflexpwm external clock signal xbar_out21 pwm fault0 eflexpwm module fault0 xbar_out22 pwm fault1 eflexpwm module fault1 xbar_out23 pwm fault2 eflexpwm module fault2 xbar_out24 pwm fault3 eflexpwm module fault3 xbar_out25 pwm force eflexpwm ex ternal output force signal xbar_out26 tb0 quad timer b0 inpu t when sim_gps3[12] is set xbar_out27 tb1 quad timer b1 inpu t when sim_gps3[13] is set xbar_out28 tb2 quad timer b2 inpu t when sim_gps3[14] is set xbar_out29 tb3 quad timer b3 inpu t when sim_gps3[15] is set table 16. crossbar output signal assignments (continued) xbar_outn output to function
mc56f825x/mc56f824x digital si gnal controller, rev. 3 security features freescale semiconductor 46 ? if the adc conversion result in sample1 is less than the value programmed into the low limit register 1, pwm1_extb is driven high. state of pwm2_extb: ? if the adc conversion result in samp le2 is greater than the value programme d into the high limit register 2, pwm2_extb is driven low. ? if the adc conversion result in sample2 is less than the value programmed into the low limit register 2, pwm2_extb is driven high. 5.8 joint test action group (jta g)/enhanced on-chip emulator (eonce) the 56800e family includes extensive integrated support for ap plication software development and real-time debugging. two modules, the enhanced on-chip emulati on (eonce) module and the core test acces s port (tap, commonly called the jtag port), work together to provide these capabilities. both are accessed through a common 4-pin jt ag/eonce interface. these modules allow you to insert the mc56f825x/mc56f824x into a target system while retaining debug control. this capability is especially important for devices without an external bus, because it eliminates the need for a costly cable to bring out the footprint of the chip, as is required by a traditional emulator system. the 56800e?s eonce module is a freescale-designed module fo r developing and debugging application software used with the chip. this module allows non-intrusiv e interaction with the cpu and is accessibl e through the pins of the jtag interface or by software program control of the 56800e core. among the many features of the eonce module is support, in real-time program execution, for data communicati on between the controller and the host software development and debug systems. other features allow for hardware breakpoints, the monitoring and tracking of program execution, and the ability to examine and modify the contents of registers, me mory, and on-chip peripherals, all in a sp ecial debug environmen t. no user-accessible resources must be sacrificed to perform debugging operations. the 56800e?s jtag port provides an interface for the eonce module to the jtag pins. the joint test action group (jtag) boundary scan is an ieee 1149.1 standard methodology enabling access to test featur es using a test access port (tap). a jtag boundary scan consists of a tap controller and boundary scan registers. contact your freescale sales representative or authorized distributor for de vice-specific bsdl information. note in normal operation, an exte rnal pullup on the tm s pin is highly reco mmend to place the jtag state machine in reset state (if this pin is not configured as gpio). 6 security features the mc56f825x/mc56f824x offers security f eatures intended to prevent unauthor ized users from gaining access to and reading the contents of the flash memory (fm) array. the mc56f825x/mc56f824x?s flash memory security consists of several hardware interlocks. after flash memory security is set, the a pplication software can allow an authorized user to access on-chip memory by including a user-defined software subroutine that r eads and transfers the contents of internal memory via peripherals. this application software can communicate over a se rial port, for example, to vali date the authenticity of the requested access and then to gran t it until the next device reset. the system designer must use discretion when deciding whether to support this type of ?back doo r? access technique. 6.1 operation with security enabled after you have programmed flash with the application code, or as part of programming the flash with the application code, you can secure the mc56f825x/mc56f824x by programming the values 1 and 0 into bits 1 and 0, respectively, of program memory location 0x00_7ff7. the codewarrior ide menu flash lock comman d can also accomplish this ta sk. the nonvolatile security
security features mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 47 word ensures that the device remains secure after the next rese t (caused, for example, by the device powering down). refer to the flash memory section of the device?s reference manual for details. when flash security mode is enabled, the mc56f825x/mc56f824x disables the core?s eonce debug capabilities. normal program execution is otherwise unaffected. 6.2 flash access lock and unlock mechanisms several methods effectively lock or unlock the on-chip flash. 6.2.1 disabling eonce access you can read on-chip flash by issuing commands across the eonce port, which is the debug interface for the 56800e core. the tck, tms, tdo, and tdi pins compose a jtag interface onto which the eonce port function ality is mapped. when the device boots, the chip-level jt ag port is active and provides the chip?s boundary scan capability and access to the id register . however, proper implementation of flash se curity blocks any attempt to access the in ternal flash memory via the eonce port when security is enabled. this protection is effective when th e device comes out of reset, even prior to the execution of any code at startup. 6.2.2 flash lockout recovery using jtag if the device is secured, one lockout recove ry mechanism is the complete erasure of the internal flash contents, including the configuration field. the erasure disables security by clearing the protection register. this approach does not compromise security. the entire contents of your secured code stored in flas h are erased before the next reset or power-up sequence, when security becomes disabled. to start the lockout recovery sequence vi a jtag, first shift the jtag public instruction (lockout_recovery) into the chip-level tap controller?s inst ruction register. then shift the clock divider value into the corresponding 7-bit data register . finally, the tap controller must enter the run-test/idle stat e for the lockout sequence to co mmence. the controller must remain in this state until the erase sequence is complete. refe r to the device?s reference manual for details, or contact frees cale. note after completion of the lockout recovery sequence, you must reset the jtag tap controller and the device to return to normal unsecured operation. a power-on reset resets both. 6.2.3 flash lockout recovery using codewarrior you can use codewarrior to unlock a device by selecting the following items in the indicated sequence: 1. debug menu 2. dsp56800e 3. unlock flash you can accomplish the same task with another codewarrior mech anism that uses the device?s memory configuration file: the command ?unlock_flash_on_connect 1? in the .cfg file. this lockout recovery mechanism completely erases the internal flash contents, in cluding the configuration field, thereby disabling security (the prot ection register is cleared).
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 48 6.2.4 flash lockout recovery without mass erase 6.2.4.1 without presenting back do or access keys to the flash unit a user can unsecure a secured device by programming the wo rd 0x0000 into program flash location 0x00 7ff7. after completing the programming, the jtag tap controller and the devi ce must be reset to return to normal unsecured operation. the user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word 0x0000 into program flash location 0x00 7ff7. you can do so, for example, by togg ling a specific pin or downloading a user-defined key through serial interfaces. note flash contents can be programmed only from ones to zeroes. 6.2.4.2 presenting back door ac cess key to the flash unit the user can temporarily bypass security through a ?back door ? access scheme, using a four-word key to temporarily unlock the flash. ?back door? access requires suppor t from the embedded software. this softwa re would typically permit an external user to enter the four-word code through one of the communications interfaces and th en use it to attempt the unlock sequence. if the input matches the four-word code stored at location 0x00 7ffc?0x00 7fff in the flash memory, the device immediately becomes unsecured (at runtime) and intern al memory is accessible via the jtag/eonce port. refer to the device?s reference manual for details. the key must be entered in four consecutive accesses to the flash, so this ro utine should be designed to ru n in ram. 6.3 product analysis to analyze a product?s failures in the field, the reco mmended method of unsecuring a secured device appears in section 6.2.4.2, ?presenting back door access key to the flash unit .? the customer must supply technical-support details about the protocol to access the subroutines in flash memory. an alternative method for perf orming analysis on a secured device is to mass-erase and reprogram the flash memory with the original code, but also to modify or not program the security word. 7 specifications 7.1 general characteristics the mc56f825x/mc56f824x is fabricated in high-density, lo w-power, low-leakage cmos pr ocess with 5 v?tolerant, ttl-compatible digital inputs. the term 5 v?tolerant refers to the capability of an i/o pin, built on a 3.3 v?compatible process technology, to withstand a voltage up to 5.5 v without damaging the device. many systems have a mixture of devices designed for 3.3 v and 5 v power supplies. in such systems, a bus ma y carry both 3.3 v?compatible and 5 v?compatible i/o voltage levels (a standard 3.3 v i/o is designed to receive a maximum voltage of 3.3 v 10% during normal operation without causing damage). this 5 v?tolerant capability therefore combines the powe r savings of 3.3 v i/o levels wi th the ability to receive 5 v levels without damage. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 49 7.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. caution stress beyond the limits specified in table 17 may affect device reliability or cause permanent damage to the device. unless otherwise stated, all specifications within this section apply over the ambien t temperature range of ?40 oc to +105 oc over the following supply ranges: v ss =v ssa =0v,v dd =v dda = 3.0 v to 3.6 v, cl < 50 pf, f op =60mhz. for functional operating conditions, refer to the remaining tables in the section. table 17. absolute maximum ratings (v ss = 0 v, v ssa = 0 v) characteristic symbol notes min max unit supply voltage range v dd - 0.3 4.0 v analog supply voltage range v dda - 0.3 4.0 v adc high voltage reference v refhx - 0.3 4.0 v voltage difference v dd to v dda v dd - 0.3 0.3 v voltage difference v ss to v ssa v ss - 0.3 0.3 v digital input voltage range v in pin groups 1, 2 - 0.3 6.0 v oscillator voltage range v osc pin group 4 - 0.4 4.0 v analog input voltage range v ina pin group 3 - 0.3 4.0 v input clamp current, per pin (v in < 0) 1 1 continuous clamp current per pin is ?2.0 ma default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc and comparator analog inputs pin group 4: xtal, extal pin group 5: dac analog output v ic ?-20.0ma output clamp current, per pin (v o < 0) 1 v oc ?-20.0ma output voltage range (normal push-pull mode) v out pin group 1 - 0.3 4.0 v output voltage range (open drain mode) v outod pin group 2 - 0.3 6.0 v dac output voltage range v out_dac pin group 5 - 0.3 4.0 v ambient temperature industrial t a - 40 105 c storage temperature range (extended industrial) t stg - 55 150 c
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 50 7.3 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much le ss common on these devices than on early cmos circuits, use normal handling precautions to avoid exposure to static discharge. qualification tests are performed to ensure that these devic es can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing conforms with aec-q100 stress test qualificat ion. during device qualification, esd stresses are performed for the human body model (hbm), the machine mo del (mm), and the charge device model (cdm). all latch-up testing conforms with aec-q100 stress test qualification. a device is defined as a failure if, after exposure to esd pulses, the device no longer meets the device specification. comprehensive dc parametric and functional testing is perfor med according to the applicable device sp ecification at room temperature and then at hot te mperature, unless specified othe rwise in the device specification. 7.4 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to power dissi pation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the device design. to account for p i/o in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd is very small. table 18. mc56f825x/mc56f824x esd/latch-up protection characteristic 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions, unless otherwise noted min typ max unit esd for human body model (hbm) 2000 ? ? v esd for machine model (mm) 200 ? ? v esd for charge device model (cdm) 750 ? ? v latch-up current at t a = 85 o c (i lat ) 100 ma table 19. 44lqfp package thermal characteristics characteristic comments symbol value (lqfp) unit junction to ambient natural convection single layer board (1s) r ja 70 c/w junction to ambient natural convection four layer board (2s2p) r jma 48 c/w junction to ambient (@200 ft/min) single layer board (1s) r jma 57 c/w junction to ambient (@200 ft/min) four layer board (2s2p) r jma 42 c/w junction to board r jb 30 c/w junction to case r jc 13 c/w junction to package top natural convection jt 2c/w
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 51 note junction-to-ambient thermal resistance dete rmined per jedec jesd51?3 and jesd51?6. thermal test board meets jedec specification for this package. junction-to-board thermal resistance determ ined per jedec jesd51?8. thermal test board meets jedec specificatio n for the specified package. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. thermal characterization parameter indicat ing the temperature difference between the package top and the junction temperature per jedec jesd51?2. when greek letters are not available, the therma l characterization parameter is written as psi-jt. table 20. 48lqfp package thermal characteristics characteristic comments symbol value (lqfp) unit junction to ambient natural convection single layer board (1s) r ja 67 c/w junction to ambient natural convection four layer board (2s2p) r jma 48 c/w junction to ambient (@200 ft/min) single layer board (1s) r jma 60 c/w junction to ambient (@200 ft/min) four layer board (2s2p) r jma 44 c/w junction to board r jb 24 c/w junction to case r jc 15 c/w junction to package top natural convection jt 2c/w table 21. 64lqfp package thermal characteristics characteristic comments symbol value (lqfp) unit junction to ambient natural convection single layer board (1s) r ja 67 c/w junction to ambient natural convection four layer board (2s2p) r jma 48 c/w junction to ambient (@200 ft/min) single layer board (1s) r jma 55 c/w junction to ambient (@200 ft/min) four layer board (2s2p) r jma 42 c/w junction to board r jb 31 c/w junction to case r jc 14 c/w junction to package top natural convection jt 3c/w
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 52 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperatur e, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. see section 8.1, ?thermal design considerations ,? for more detail on thermal design considerations. 7.5 recommended oper ating conditions this section contains information about recommended operating conditions. table 22. recommended operating conditions (v reflx = 0 v, v ssa = 0 v, v ss = 0 v) characteristic symbol notes min typ max unit supply voltage v dd, v dda 33.33.6 v adc reference voltage high v refhx 3.0 v dda v voltage difference v dd to v dda v dd -0.1 0 0.1 v voltage difference v ss to v ssa v ss -0.1 0 0.1 v device clock frequency using relaxation oscillator using external clock source fsysclk 0.001 0 60 60 mhz input voltage high (digital inputs) v ih pin groups 1, 2 2.0 5.5 v input voltage low (digital inputs) v il pin groups 1, 2 -0.3 0.8 v oscillator input voltage high xtal driven by an external clock source v ihosc pin group 4 2.0 v dd + 0.3 v oscillator input voltage low v ilosc pin group 4 -0.3 0.8 v dac output load resistance r ld pin group 5 3k dac output load capacitance c ld pin group 5 400 pf output source current high at v oh min.) 1 when programmed for low drive strength when programmed for high drive strength i oh pin group 1 pin group 1 ? ? -4 -8 ma output source current low (at v ol max.) 1 when programmed for low drive strength when programmed for high drive strength i ol pin groups 1, 2 pin groups 1, 2 ? ? 4 8 ma ambient operating temperature (extended industrial) t a -40 105 c flash endurance (program erase cycles) n f t a = -40c to 125c 10,000 ? cycles flash data retention t r t j <= 85c avg 15 ? years flash data retention with <100 program/erase cycles t flret t j <= 85c avg 20 ? ? years
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 53 7.6 dc electrical characteristics this section includes informatio n about power supply requiremen ts and i/o pin characteristics. 1 total chip source or sink current cannot exceed 75 ma default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc and comparator analog inputs pin group 4: xtal, extal pin group 5: dac analog output
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 54 figure 14. i in /i oz versus v in (typical; pull-up disabled) table 23. dc electrical characteristics at recommended operating conditions characteristic symbol notes min typ max unit test conditions output voltage high v oh pin group 1 2.4 ? ? v i oh = i ohmax output voltage low v ol pin groups 1, 2 ? ? 0.4 v i ol = i olmax digital input current high (a) pull-up enabled or disabled i ih pin groups 1, 2 ? 0 +/- 2.5 av in = 2.4 v to 5.5 v comparator input current high i ihc pin group 3 ? 0 +/- 2 av in = v dda oscillator input current high i ihosc pin group 3 ? 0 +/- 2 av in = v dda digital input current low 1 pull-up enabled pull-up disabled 1 see figure 14 . default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc and comparator analog inputs pin group 4: xtal, extal pin group 5: dac analog output i il pin groups 1, 2 -15 ? -30 0 -60 +/- 2.5 av in = 0 v internal pull-up resistance r pull-up 60 110 220 k ? comparator input current low i ilc pin group 3 ? 0 +/- 2 av in = 0 v oscillator input current low i ilosc pin group 3 ? 0 +/- 2 av in = 0 v dac output voltage range v dac pin group 5 typically v ssa + 40 mv ? typically v dda ? 40 mv v? output current 1 high impedance state i oz pin groups 1, 2 ? 0 +/- 2.5 a? schmitt trigger input hysteresis v hys pin groups 1, 2 ? 0.35 ? v ? input capacitance c in ?10?pf ? output capacitance c out ?10?pf ? 2.0 0.0 - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 6.0 3.54.04.55.05.5 a volt
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 55 7.7 supply current characteristics the following table specifies supply current characteristics. table 24. current consumption mode conditions typical @ 3.3 v 25c (ma) maximum @ 3.6 v 105c,125c (ma) i dd 1 1 no output switching all ports configured as inputs all inputs low no dc loads i dda i dd 1 i dda run 60 mhz device clock relaxation oscillator on pll powered on continuous mac instructions with fetches from program flash memory all peripheral modules enabled; tmrs and scis using 1x clock adc/dac powered on and clocked comparator powered on 92 38 97 44 wait 60 mhz device clock relaxation oscillator on pll powered on processor core in wait state all peripheral modules enabled; tmrs and scis using 1x clock adc/dac/comparator powered off 49 4.5 53 5.5 stop 4 mhz device clock relaxation oscillator on pll powered off processor core in stop state all peripheral module and core clocks are off adc/dac/comparator powered off 8.0 3.6 9.2 4.9 standby > stop 100 khz device clock relaxation oscillator in standby mode pll powered off processor core in stop state all peripheral module and core clocks are off adc/dac/comparator powered off voltage regulator in standby mode 0.76 0 3.0 0 powerdown device clock is off relaxation oscillator powered off pll powered off processor core in stop state all peripheral module and core clocks are off adc /dac/comparator powered off voltage regulator in standby mode 0.66 0 2.0 0
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 56 7.8 power-on reset, low voltage detection specification 7.9 voltage regulator specifications the mc56f825x/mc56f824x has two on-chip regulators. one supp lies the pll, crystal osci llator, nanoedge placement pwm, and relaxation oscillator. it has no external pins and therefore has no external characteristics that must be guaranteed (other than proper operation of the device). the second regulator supplies approximately 2.5 v to the mc56f825x/mc56f824x?s core logic. for proper operation, this re gulator requires an external capacitor of 2.2 f or greater. ceramic and tantalum capacitors tend to provide better perfor mance tolerances. the output volta ge can be measured directly on the v cap pin. the specifications for this regulator appear in table 26 . 7.10 ac electrical characteristics tests are conducted using th e input levels specified in table 23 . unless otherwise specified, prop agation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 15 . figure 15. input signal measurement references table 25. power-on reset and low-voltage detection parameters characteristic symbol min typ max unit low-voltage interrupt for 3.3 v supply 1 1 when v dd drops below lvi27, an interrupt is generated. v lvi27 2.6 2.7 2.8 v low-voltage interrupt for 2.5 v supply 2 2 when v dd drops below lvi21, an interrupt is generated. v lvi21 ?2.18? v low-voltage interrupt recovery hysteresis v eih ?50?mv power-on rese t threshold 3 3 while power is ramping up, this signal remains active for as long as the internal 2.5 v is below 2.18 v or the 3.3 v v dd voltage is below 2.7 v, no matter how long t he ramp-up rate is. the internally regulated voltage is typically 100 mv less than v dd during ramp-up until 2.5 v is reached, at which time it self-reg- ulates. por 2.6 2.7 2.8 v brown-out reset threshold 4 4 brown-out reset occurs whenever the internally regulated 2.5 v digital supply drops below 1.8 v. bor ? 1.8 1.9 v table 26. regulator parameters characteristic symbol min typical max unit short circuit current i ss ? 900 1300 ma short circuit tolerance (v cap shorted to ground) t rsc ??30minutes v ih v il fall time midpoint1 low high 90% 50% 10% rise time the midpoint is v il + (v ih ? v il )/2. input signal
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 57 figure 16 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bu s or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 16. signal states 7.11 enhanced flex pwm characteristics 7.12 flash memory characteristics 7.13 external clock operation timing table 27. enhanced flex pwm timing parameters characteristic symbol min typ max unit nanoedge placement (nep) step size 1 2 3 1 required: ip bus clock is between 50 mhz and ~60 mhz in nanoedge placement mode. 2 nanoedge placement step size is a function of clock freq uency only. temperature and volt age variations do not affect nanoedge placement step size. 3 in nanoedge placement mode, the minimum pulse ed ge-to-edge cannot be less than 4 pwm clock cycles. ? ? 521 ? ps delay for fault input activating to pwm output deactivated ? 1 ? ns table 28. flash timing parameters characteristic symbol min typ max unit program time 1 1 additional overhead is part of the programming sequence. refer to the device?s reference manual for details. t prog 20 ? 40 s erase time 2 2 specifies page erase time. there are 1024 bytes per page in the program flash memory. t erase 20 ? ? ms mass erase time t me 100 ? ? ms table 29. external clock operation timing requirements 1 characteristic symbol min typ max unit frequency of operation (external clock driver) 2 f osc ??120 mhz clock pulse width 3 t pw 6.25 ? ? ns data invalid state data1 data3 valid data2 data3 data1 valid data active data active data2 valid data three-stated
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 58 figure 17. external clock timing 7.14 phase locked loop timing external clock input rise time 4 t rise ?? 3ns external clock input fall time 5 t fall ?? 3ns input high voltage overdrive by an external clock v ih 0.85v dd ??v input high voltage overdrive by an external clock v il ??0.3v dd v 1 parameters listed are guaranteed by design. 2 see figure 17 for details on using the recommended connection of an external clock driver. 3 the chip may not function if the high or low pulse width is smaller than 6.25 ns. 4 external clock input rise time is measured from 10% to 90%. 5 external clock input fall time is measured from 90% to 10%. table 30. phase locked loop timing characteristic symbol min typ max unit pll input reference frequency 1 1 an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8 mhz input. f ref 488 mhz pll output frequency 2 2 the core system clock operates at 1/6 of the pll output frequency. f op 120 ? 240 mhz pll lock time 3 4 3 this is the time required after the pll is enabled to ensure reliable operation. 4 from powerdown to powerup state at 60 mhz system clock state. t plls ?40100s accumulated jitter using an 8 mhz external crystal as the pll source 5 5 this is measured on the clko signal (programmed as system clock) over 264 system clocks at 60 mhz system clock frequency and using an 8 mhz oscillator frequency. j a ??tbd% cycle-to-cycle jitter t jitterpll ?350? ps table 29. external clock operation timing requirements 1 (continued) characteristic symbol min typ max unit 90% 50% 10% 90% 50% 10% external clock t pw t pw t fall t rise v il v ih note: the midpoint is v il + (v ih ? v il )/2.
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 59 7.15 external crystal or resonator requirement 7.16 relaxation oscillator timing figure 18. relaxation oscillator temperature variation (typical) after trim table 31. crystal or resonator requirement characteristic symbol min typ max unit frequency of operation f xosc 4816 mhz table 32. relaxation oscillator timing characteristic symbol minimum typical maximum unit relaxation oscillator output frequency 1 normal mode standby mode 1 output frequency after factory trim. f op ? 8.05 400 ? mhz khz relaxation oscillator stabilization time 2 2 this is the time required from standby to normal mode transition. t roscs ?1 3ms cycle-to-cycle jitter. this is measured on the clko signal (programmed prescaler_clock) over 264 clocks 3 3 j a is required to meet qsci requirements. t jitterrosc ?400? ps variation over temperature ?40 c to 150 c 4 4 see figure 18 . ? +1.5 to ?1.5 +3.0 to ?3.0 % variation over temperature 0 c to 105 c 4 ? 0 to +1 +2.0 to ?2.0 % 8.16 8.08 8 7.92 7.84 175 -25 -50 0 50 75 100 125 150 25 degrees c (junction) mhz
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 60 7.17 reset, stop, wait, mode select, and interrupt timing note all address and data buses described here are internal. figure 19. gpio interrupt timi ng (negative edge-sensitive) 7.18 queued serial peripheral interface (spi) timing table 33. reset, stop, wait, mode select, and interrupt timing 1,2 1 in the formulas, t = system clock cycle and t osc = oscillator clock cycle. for an operating frequency of 32 mhz, t = 31.25 ns. at 4 mhz (used coming out of reset and stop modes), t = 250 ns. 2 parameters listed are guaranteed by design. characteristic symbol typical mi n typical max unit see figure minimum reset assertion duration 3 3 this minimum number guarantees that a reliable reset occurs. t ra 4t ? ns ? minimum gpio pin assertion for interrupt t iw 2t ? ns figure 19 reset deassertion to first address fetch t rda 96t osc + 64t 97t osc + 65t ns ? delay from interrupt assertion to fetch of first instruction (exiting stop) t if ?6tns? table 34. spi timing 1 characteristic symbol min max unit refer to cycle time master slave t c 125 62.5 ? ? ns ns figure 20 , figure 21 , figure 22 , figure 23 enable lead time master slave t eld ? 31 ? ? ns ns figure 23 enable lag time master slave t elg ? 125 ? ? ns ns figure 23 clock (sck) high time master slave t ch 50 31 ? ? ns ns figure 20 , figure 21 , figure 22 , figure 23 clock (sck) low time master slave t cl 50 31 ? ? ns ns figure 23 gpio pin (input) t iw
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 61 data set-up time required for inputs master slave t ds 20 0 ? ? ns ns figure 20 , figure 21 , figure 22 , figure 23 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figure 20 , figure 21 , figure 22 , figure 23 access time (time to data acti ve from high-impedance state) slave t a 4.8 15 ns figure 23 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns figure 23 data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns figure 20 , figure 21 , figure 22 , figure 23 data invalid master slave t di 0 0 ? ? ns ns figure 20 , figure 21 , figure 22 , figure 23 rise time master slave t r ? ? 11.5 10.0 ns ns figure 20 , figure 21 , figure 22 , figure 23 fall time master slave t f ? ? 9.7 9.0 ns ns figure 20 , figure 21 , figure 22 , figure 23 1 parameters listed are guaranteed by design. table 34. spi timing 1 (continued) characteristic symbol min max unit refer to
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 62 figure 20. spi master timing (cpha = 0) figure 21. spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t f t c t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14?1 master lsb out ss (input) t ch ss is held high on master t f sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14? 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 63 figure 22. spi slave timing (cpha = 0) figure 23. spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t f t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 64 7.19 queued serial communication interface (sci) timing figure 24. rxd pulse width figure 25. txd pulse width table 35. sci timing 1 1 parameters listed are guaranteed by design. characteristic symbol min max unit see figure baud rate 2 2 f max is the frequency of operation of the sci in mhz, which ca n be selected system clock (max. 60 mhz) or 2x system clock (max. 120 mhz) for the mc56f825x/mc56f824x device. br ? (f max /16) mbps ? rxd pulse width rxd pw 0.965/br 1.04/br ns figure 24 txd pulse width txd pw 0.965/br 1.04/br ns figure 25 lin slave mode deviation of slave node clock from nominal clock rate before synchronization f tol_unsynch ?14 14 % ? deviation of slave node clock relative to the master node clock after synchronization f tol_synch ?2 2 % ? minimum break character length t break 13 ? master node bit periods ? 11 ? slave node bit periods ? rxd pw rxd sci receive data pin (input) txd pw txd sci receive data pin (input)
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 65 7.20 freescale?s scalable controller area network (mscan) figure 26. bus wake-up detection 7.21 inter-integrated circuit interface (i 2 c) timing table 36. mscan timing characteristic symbol min max unit baud rate br can ? 1 mbps bus wake-up detection t wakeup t ipbus ? s table 37. i 2 c timing characteristic symbol standard mode unit minimum maximum scl clock frequency f scl 0 100 khz hold time (repeated) start conditi on. after this period, the first clock pulse is generated. t hd; sta 4.0 ? s low period of the scl clock t low 4.7 ? s high period of the scl clock t high 4.0 ? s set-up time for a repeated start condition t su; sta 4.7 ? s data hold time for i 2 c bus devices t hd; dat 0 1 1 the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the sda and scl lines. 3.45 2 2 the maximum t hd; dat must be met only if the device does not stretch the low period (t low ) of the scl signal. s data set-up time t su; dat 250 3 3 a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t su; dat > = 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. ?ns rise time of sda and scl signals t r ? 1000 ns fall time of sda and scl signals t f ? 300 ns set-up time for stop condition t su; sto 4.0 ? s bus free time between stop and start condition t buf 4.7 ? s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a ns t wakeup mscan_rx can receive data pin (input)
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 66 figure 27. timing defini tion for standard mode devices on the i 2 c bus 7.22 jtag timing figure 28. test clock input timing diagram table 38. jtag timing characteristic symbol min max unit see figure tck frequency of operation 1 1 tck frequency of operation must be le ss than 1/8 the processor rate. f op dc sys_clk/8 mhz figure 28 tck clock pulse width t pw 50 ? ns figure 28 tms, tdi data set-up time t ds 5?ns figure 29 tms, tdi data hold time t dh 5?ns figure 29 tck low to tdo data valid t dv ?30ns figure 29 tck low to tdo tri-state t ts ?30ns figure 29 sda scl t hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r tck (input) v m v il v m = v il + (v ih ? v il )/2 t pw 1/f op t pw v m v ih
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 67 figure 29. test access port timing diagram 7.23 quad timer timing figure 30. timer timing table 39. timer timing 1, 2 1 in the formulas listed, t = the clock cycl e. for 32 mhz operation, t = 31.25 ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure timer input period p in 2t + 6 ? ns figure 30 timer input high/low period p inhl 1t + 3 ? ns figure 30 timer output period p out 125 ? ns figure 30 timer output high/low period p outhl 50 ? ns figure 30 input data valid output data valid t ds t dh t dv t ts tck (input) tdi (input) tdo (output) tdo (output) tms p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 68 7.24 cop specifications 7.25 analog-to-digital converter (adc) parameters table 40. cop specifications parameter symbol min typ max unit oscillator output frequency lpfosc 500 1000 1500 hz oscillator current consumption in partial power down mode idd tbd na table 41. adc parameters 1 parameter symbol min typ max unit dc specifications resolution r es 12 ? 12 bits adc internal clock f adic 0.1 ? 15 mhz conversion range r ad v refl ?v refh v adc and vref power-up time 2 (from power down mode) t adpu ?13 ? t aic cycles 3 vref power-up time (from low power mode) t refpu ?6 ? t aic cycles 3 adc run current (speed control setting) at 100 khz adc clock (standby mode) at adc clock 5 mhz (00) at 5 mhz < adc clock 12 mhz (01) at 12 mhz < adc clock 15 mhz (10) i adrun ? ? ? ? 0.6 10 17 27 ? ? ? ? ma conversion time t adc ?6 ? t aic cycles 3 sample time t ads ?1 ? t aic cycles 3 accuracy (dc or absolute) (gain of 1x, 2x, 4x and f adc 10 mhz) (all data in single-ended mode) 4 integral non-linearity 5 (full input signal range) inl ? +/- 3 +/- 6 lsb 6 differential non-linearity 5 dnl ? +/- 0.6 +/- 1 lsb 5 monotonicity guaranteed offset voltage internal ref v offset ? +/- 8 +/- 15 mv offset voltage external ref v offset ? +/- 8 +/- 15 mv gain error (transfer gain) e gain ? 0.995 to 1.005 1.01 to 0.99 ? adc inputs 7 (pin group 3) input voltage (external reference) v adin v refl ?v refh v input voltage (internal reference) v adin v ssa ?v dda v input leakage i ia ?0 +/- 2 a v refh current i vrefh ?0.001 ? a input injection current 8 , per pin i adi ?? 3ma input capacitance c adi ?see figure 31 ?pf
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 69 7.25.1 equivalent circuit for adc inputs figure 31 illustrates the adc input circuit during sample and hold . s1 and s2 are always open ed/closed at non-overlapping phases and operate at the adc clock frequency. equivalent i nput impedance, when the input is selected, is as follows: (2 x k / adcclockrate x c gain ) + 100 ohms + 125 ohms eqn. 1 where k = ? 1 for first sample ? 6 for subsequent samples and c gain is as described in note 4 below. 1. parasitic capacitance due to p ackage, pin-to-pin, and pin-to -package base coupling: 1.8 pf input impedance x in ?see figure 31 ?ohms ac specifications 9 (gain of 1x, 2x, 4x and f adc 10 mhz) 4 signal-to-noise ratio snr ? 59 db total harmonic distortion thd ? 64 db spurious free dynamic range sfdr ? 65 db signal-to-noise plus distortion sinad ? 59 db effective number of bits enob ? 9.5 bits 1 all measurements were made at v dd = 3.3v, v refh = 3.3v, and v refl = ground 2 includes power-up of adc and v ref 3 adc clock cycles 4 speed register setting must be 00 for adc clock 5 mhz, 01 for 5 mhz < adc clock 12 mhz, and 10 for adc clock > 12 mhz 5 inl and dnl measured from v in = v refl to v in = v refh 6 lsb = least significant bit = 0.806 mv at x1 gain 7 pin groups are detailed following table 17 . 8 the current that can be injected or sourced from an unselected adc signal input without affecting the performance of the adc 9 adc pga gain is x1 table 41. adc parameters 1 (continued) parameter symbol min typ max unit 1 2 3 analog input s1 s1 s2 c1 c1 s/h c1: single ended mode 2xc1: differential mode (v refhx - v reflx ) / 2 125-ohm esd resisto r s2 s1 s1 channel mux equivalent resistance 100 ohms c1: single ended mode 2xc1: differential mode
mc56f825x/mc56f824x digital si gnal controller, rev. 3 specifications freescale semiconductor 70 2. parasitic capacitance due to the chip bond pad, esd protection devices, and signal routing: 2.04 pf 3. 8 pf noise damping capacitor 4. sampling capacitor at the sample and hold circuit. capacitor c1 is normally disconnected from the input and is only connected to it at sampling time: c gain = 1.4 pf for x1 gain, 2.8 pf for x2 gain, and 5.6 pf for x4 gain. 5. s1 and s2 switch phases are non-overlappi ng and operate at the adc clock frequency. figure 31. equivalent circuit for a/d loading 7.26 digital-to-analog converter (dac) parameters table 42. dac parameters parameter conditions/comm ents symbol min typ max unit dc specifications resolution 12 ? 12 bits settling time at output load r ld = 3 k c ld = 400 pf tbd ? 2 s power-up time time from release of pwrdwn signal until dacout signal is valid t dapu ? ? 11 s accuracy integral non-linearity 1 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range inl ? +/- 3 +/- 8.0 lsb 2 differential non-linearity 1 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range dnl ? +/- 0.8 +/- 1.0 lsb 2 monotonicity > 6 si gma monotonicity, < 3.4 ppm non-monotonicity guaranteed ? offset error 1 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range v offset ? +/- 25 +/- 40 mv gain error 1 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range e gain ? +/- .5 +/- 1.5 % dac output output voltage range within 40 mv of either v reflx or v refhx v out v reflx +0.04v ?v refhx - 0.04v v ac specifications signal-to-noise ratio snr ? tbd ? db spurious free dynamic range sfdr ? tbd ? db effective number of bits enob ? ? ? bits s1 s2
specifications mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 71 7.27 5-bit digital-to-analog converter (dac) parameters 7.28 hscmp specifications 7.29 optimize power consumption see section 7.7, ?supply current characteristics ,? for a list of i dd requirements for the mc56f825x/mc56f824x. this section provides additional details for optimizing power consumption for a given application. power consumption is given by the following equation: a, the internal [static] component, consis ts of the dc bias currents for the osci llator, leakage currents, pll, and voltage references. these sources operate independentl y of processor state or operating frequency. 1 no guaranteed specification within 5% of v dda or v ssa 2 lsb = 0.806 mv table 43. 5-bit dac specifications parameter symbol min typ max unit reference inputs vin v dda ? v dda mv setup delay t prgst tbd tbd tbd ns step size v step 3vin/128 vin/32 5vin/128 v output range v dacout vin/32 ? vin ns table 44. hscmp specifications parameter symbol min typ max unit analog input voltage v ain v ssa ? 0.01 ? v dda + 0.01 v analog input offset voltage 1 1 offset when the degree of hysteresis is set to its minimum value. v aio ?? 40 mv analog comparator hysteresis 2 2 the range of hysteresis is based on simulati on only. this range varies from part to part. v h ? 1 to 16 ? mv propagation delay, high speed mode (en=1, pmode=1), t dhsn 3 3 measured with an input waveform that switches 30 mv above and below the reference, to the cmpo output pin. v dda > v lvi_warning => lvi_warning not asserted. ? 70 140 ns propagation delay, low speed mode (en=1, pmode=0), t ainit 4 4 measured with an input waveform that switches 30 mv above and below the reference, to the cmpo output pin. v dda > v lvi_warning => lvi_warning not asserted. ? 400 600 ns total power = a: internal [static] component +b: internal [state-dependent] component +c: internal [dynamic] component +d: external [dynamic] component +e: external [static] component
mc56f825x/mc56f824x digital si gnal controller, rev. 3 design considerations freescale semiconductor 72 b, the internal [state-dependent] componen t, reflects the supply current required by certain on-chip resour ces only when those resources are in use. these resources include ram, flash memory, and the adcs. c, the internal [dynamic] component, is classic c*v 2 *f cmos power dissipation corresponding to the 56800e core and standard cell logic. d, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins o f the chip. this component is al so commonly described as c*v 2 *f, although simulations on two of the i/o cell types used on the 56800e reveal that the power-versus-load curve does have a non-zero y-intercept. power due to capacitive loading on output pins is (first or der) a function of the capacitive load and frequency at which the outputs change. table 45 provides coefficients for calculating power di ssipated in the i/o cells as a function of capacitive load. in these cases, equation 2 applies. totalpower = ((intercept + slope*c load )*frequency/10 mhz) eqn. 2 where: ? summation is performed over all output pins with capacitive loads. ? total power is expressed in mw. ?c load is expressed in pf. because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. e, the external [static] component, reflect s the effects of placing re sistive loads on the outputs of the device. total all v 2 /r or iv to arrive at the resistive load contribution to power. assume v = 0.5 for the purposes of these rough calculations. for instance, if there is a total of nine pwm outputs driving 10 ma into leds, then p = 8*0.5*0.01 = 40 mw. in previous discussions, power consumption due to parasites a ssociated with pure input pins is ignored and assumed to be negligible. 8 design considerations 8.1 thermal design considerations an estimation of the chip junction temperature, t j , can be obtained from equation 3 . t j = t a + (r j x p d ) eqn. 3 where: the junction-to-ambient thermal resistance is an industry-standard value that provides a quick and eas y estimation of thermal performance. unfortunately, there are two values in common usage: the value determ ined on a single-layer board and the value obtained on a board with two planes. for pack ages such as the pbga, these values can be different by a factor of two. which table 45. i/o loading coefficients at 10 mhz intercept slope 8 ma drive 1.3 0.11 mw/pf 4 ma drive 1.15 mw 0.11 mw/pf t a = ambient temperature for the package ( o c) r j = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w)
design considerations mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 73 value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. th e value obtained on the board with the intern al planes is usually appropriate if the board has low- power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case therma l resistance and a case-to-ambient thermal resistance. r ja = r jc + r ca eqn. 4 where: r jc is device related and cannot be adjusted. you control the thermal environment to change the case to ambient thermal resistance, r ca . for instance, you can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or the ther mal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat si nks are not used, the thermal characterizati on parameter ( jt ) can be used to determine the junction temperature with a measurement of the temper ature at the top center of the package case. refer to equation 5 . t j = t t + ( jt x p d ) eqn. 5 where: the thermal characterization parameter is measured per jesd5 1?2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple juncti on and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction te mperature is determined from a thermocoupl e inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to mini mize the change in th ermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this tec hnique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate m easurement of the thermal resistan ce of the interface. from this case temperature, the junction temp erature is determined from the junction-to-case thermal resistance. 8.2 electrical design considerations caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, take normal pr ecautions to avoid application of any voltages higher than maximum-rated voltages to th is high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. r ja = package junction-to-ambient thermal resistance (c/w) r jc = package junction-to-case thermal resistance (c/w) r ca = package case-to-ambient thermal resistance (c/w) t t = thermocouple temperature on top of package ( o c) jt = thermal characterization parameter ( o c/w) p d = power dissipation in package (w)
mc56f825x/mc56f824x digital si gnal controller, rev. 3 ordering information freescale semiconductor 74 use the following list of considerations to a ssure correct operation of the mc56f825x/mc56f824x: ? provide a low-impedance path from the board power supply to each v dd pin on the mc56f825x/mc56f824x and from the board ground to each v ss (gnd) pin. ? the minimum bypass requirement is to place 0.01?0.1 f cap acitors positioned as near as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacitors te nd to provide better tolerances. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are as short as possible. ? bypass the v dd and v ss with approximately 100 f, plus the number of 0.1 f ceramic capacitors. ? pcb trace lengths should be minimal for high-frequency signals. ? consider all device loads as well as parasitic capacitance due to pcb traces when calcu lating capacitance. this is especially critical in systems with higher capacitive load s that could create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the v ref , v dda , and v ssa pins. ? using separate power planes for v dd and v dda and separate ground planes for v ss and v ssa is recommended. connect the separate analog and digital power and ground plan es as near as possible to power supply outputs. if an analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with v dda and v ssa traces. ? physically separate analog components from noisy digital components by gr ound planes. do not place an analog trace in parallel with digital traces. place an analog ground trace ar ound an analog signal trace to isolate it from digital traces. ? because the flash memory is programmed thr ough the jtag/eonce por t, spi, sci, or i 2 c, the designer should provide an interface to this port if in-circuit flash programming is desired. ? if desired, connect an exte rnal rc circuit to the reset pin. the resistor value should be in the range of 4.7 k to 10 k ; the capacitor value should be in the range of 0.22 f to 4.7 f. ? configuring the reset pin to gpio output in normal operation in a high-noise environment may help to improve the performance of noise transient immunity. ?add a 2.2k external pullup on the tms pin of the jtag port to keep eonce in a restate during normal operation if a jtag converter is not present. ? during reset and after reset but before i/o initialization, all i/o pins are at input state with internal pullup enabled. the typical value of internal pullup is around 110 k . these internal pullups can be disabled by software. ? to eliminate pcb trace impedance effect , each adc input should have an rc filter of no less than 33 pf 10 . ? external clamp diodes on analog input pins are recommended. 9 ordering information table 46 lists the pertinent information needed to place an order. consult a freescale se miconductor sales office or authorized distributor to determine availability and to order devices.
ordering information mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 75 table 46. mc56f825x/mc56f824x ordering information device supply voltag e package type pin count frequency (mhz) ambient temperature range order number 1 1 all of the packages are rohs compliant. mc56f8245 3.0?3.6 v low-profile quad flat pack (lqfp) 44 60 ?40 to + 105 c ?40 to + 125 c mc56f8245vld mc56f8245mld MC56F8246 3.0?3.6 v low-profile quad flat pack (lqfp) 48 60 ?40 to + 105 c ?40 to + 125 c MC56F8246vlf MC56F8246mlf mc56f8247 3.0?3.6 v low-profile quad flat pack (lqfp) 64 60 ?40 to + 105 c ?40 to + 125 c mc56f8247vlh mc56f8247mlh mc56f8255 3.0?3.6 v low-profile quad flat pack (lqfp) 44 60 ?40 to + 105 c ?40 to + 125 c mc56f8255vld mc56f8255mld mc56f8256 3.0?3.6 v low-profile quad flat pack (lqfp) 48 60 ?40 to + 105 c ?40 to + 125 c mc56f8256vlf mc56f8256mlf mc56f8257 3.0?3.6 v low-profile quad flat pack (lqfp) 64 60 ?40 to + 105 c ?40 to + 125 c mc56f8257vlh mc56f8257mlh
mc56f825x/mc56f824x digital si gnal controller, rev. 3 package mechanical outline drawings freescale semiconductor 76 10 package mechanical outline drawings to ensure you have the latest version of a package drawing, go to www.freescale.com and pe rform a keyword search for the drawing?s document number (shown in th e following sections for each package). 10.1 44-pin lqfp
package mechanical outline drawings mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 77
mc56f825x/mc56f824x digital si gnal controller, rev. 3 package mechanical outline drawings freescale semiconductor 78 figure 32. 56f8245 and 56f8255 44-pin lqfp mechanical information
package mechanical outline drawings mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 79 10.2 48-pin lqfp
mc56f825x/mc56f824x digital si gnal controller, rev. 3 package mechanical outline drawings freescale semiconductor 80 figure 33. 56f8246 and 56f8256 48-pin lqfp mechanical information
package mechanical outline drawings mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 81 10.3 64-pin lqfp
mc56f825x/mc56f824x digital si gnal controller, rev. 3 package mechanical outline drawings freescale semiconductor 82
package mechanical outline drawings mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 83 figure 34. 56f8247 and 56f8257 64-pin lqfp mechanical information
mc56f825x/mc56f824x digital si gnal controller, rev. 3 revision history freescale semiconductor 84 11 revision history table 47 summarizes changes to the document sin ce the release of the previous version. table 47. revision history revision date description ta bl e 4 6 on page 75 : added ?m? orderable part numbers rev. 3 2011-04-22 ta bl e 2 4 on page 55 : updated data for run, wait, and stop modes, and added data for standby and powerdown modes ta bl e 2 3 on page 54 : added minimum and maximum values for internal pull-up resistance renumbered sections: section 9 (was 8.3), section 10 (was 9), section 11 (was 10)
interrupt vector table mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 85 appendix a interrupt vector table table 48 provides the mc56f825x/mc56f824x?s rese t and interrupt priority structure, including on-chip peripherals. the table is organized with higher-priority vectors at the top and lower- priority interrupts lower in the table. as indicated, the priori ty of an interrupt can be assigned to different levels, allowing some control over interrupt prioriti es. all level 3 interrupts are s erviced before level 2 and so on. for a selected priority leve l, the lowest vector number has the highest priority. the location of the vector table is determin ed by the vector base address (vba). s ee the device?s reference manual for details. by default, the chip reset addre ss and cop reset address correspond to vector 0 an d 1 of the interrupt vector table. in these c ases, the first two locations in the vector ta ble must contain branch or jmp instructions. all other entries must contain jsr instructions. table 48. interrupt vector table contents 1 peripheral vector number priority level vector base address + interrupt function core p:0x00 reserved for reset overlay 2 core p:0x02 reserved for cop reset overlay core 2 3 p:0x04 illegal instruction core 3 3 p:0x06 sw interrupt 3 core 4 3 p:0x08 hw stack overflow core 5 3 p:0x0a misaligned long word access core 6 1 - 3 p:0x0c eonce step counter core 7 1 - 3 p:0x0e eonce breakpoint unit core 8 1 - 3 p:0x10 eonce trace buffer core 9 1 - 3 p:0x12 eonce transmit register empty core 10 1 - 3 p:0x14 eonce receive register full core 11 2 p:0x16 sw interrupt 2 core 12 1 p:0x18 sw interrupt 1 core 13 0 p:0x1a sw interrupt 0 ps 14 1 - 3 p:0x1c low-voltage interrupt occs 15 1 - 3 p:0x1e phase-locked loop loss of locks and loss of clock tmrb3 16 0 - 2 p:0x20 quad timer b, channel 3 interrupt tmrb2 17 0 - 2 p:0x22 quad timer b, channel 2interrupt tmrb1 18 0 - 2 p:0x24 quad timer b, channel 1interrupt tmrb0 19 0 - 2 p:0x26 quad timer b, channel 0 interrupt adcb_cc 20 0 - 2 p:0x28 adcb conversion complete interrupt adca_cc 21 0 - 2 p:0x2a adca conversion complete interrupt adc_err 22 0 - 2 p:0x2c adc zero crossing, low limit, and high limit interrupt can 23 0 - 2 p:0x2e can transmit interrupt can 24 0 - 2 p:0x30 can receive interrupt
mc56f825x/mc56f824x digital si gnal controller, rev. 3 interrupt vector table freescale semiconductor 86 can 25 0 - 2 p:0x32 can error interrupt can 26 0 - 2 p:0x34 can wake-up interrupt qsci1 27 0 - 2 p:0x36 qsci1 receiver overrun/errors qsci1 28 0 - 2 p:0x38 qsci1 receiver full qsci1 29 0 - 2 p:0x3a qsci1 transmitter idle qsci1 30 0 - 2 p:0x3c qsci1 transmitter empty qsci0 31 0 - 2 p:0x3e qsci0 receiver overrun/errors qsci0 32 0 - 2 p:0x40 qsci0 receiver full qsci0 33 0 - 2 p:0x42 qsci0 transmitter idle qsci0 34 0 - 2 p:0x44 qsci0 transmitter empty qspi 35 0 - 2 p:0x46 spi transmitter empty qspi 36 0 - 2 p:0x48 spi receiver full i 2 c1 37 0 - 2 p:0x4a i 2 c1 interrupt i 2 c0 38 0 -2 p:0x4c i 2 c0 interrupt tmra3 39 0 -2 p:0x4e quad timer a, channel 3 interrupt tmra2 40 0 -2 p:0x50 quad timer a, channel 2 interrupt tmra1 41 0 -2 p:0x52 quad timer a, channel 1 interrupt tmra0 42 0 -2 p:0x54 quad timer a, channel 0 interrupt eflexpwm 43 0 -2 p:0x56 pwm fault eflexpwm 44 0 -2 p:0x58 pwm reload error eflexpwm 45 0 -2 p:0x5a pwm sub-module 3 reload eflexpwm 46 0 -2 p:0x5c pwm sub-module 3 input capture eflexpwm 47 0 -2 p:0x5e pwm sub-module 3 compare eflexpwm 48 0 -2 p:0x60 pwm sub-module 2 reload eflexpwm 49 0 -2 p:0x62 pwm sub-module 2 compare eflexpwm 50 0 -2 p:0x64 pwm sub-module 1 reload eflexpwm 51 0 -2 p:0x66 pwm sub-module 1 compare eflexpwm 52 0 -2 p:0x68 pwm sub-module 0 reload eflexpwm 53 0 -2 p:0x6a pwm sub-module 0compare fm 54 0 -2 p:0x6c flash memory access error fm 55 0 -2 p:0x6e flash memory programming command complete fm 56 0 -2 p:0x70 flash memory buffer empty request cmpc 57 0 - 2 p:0x72 comparator c rising/falling flag cmpb 58 0 - 2 p:0x74 comparator b rising/falling flag table 48. interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
interrupt vector table mc56f825x/mc56f824x digital si gnal controller, rev. 3 freescale semiconductor 87 cmpa 59 0 - 2 p:0x76 comparator a rising/falling flag gpiof 60 0 - 2 p:0x78 gpiof interrupt gpioe 61 0 - 2 p:0x7a gpioe interrupt gpiod 62 0 - 2 p:0x7c gpiod interrupt gpioc 63 0 - 2 p:0x7e gpioc interrupt gpiob 64 0 - 2 p:0x80 gpiob interrupt gpioa 65 0 - 2 p:0x82 gpioa interrupt swilp 66 -1 p:0x84 sw in terrupt low priority 1 two words are allocated for each entry in the vector table. this does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2 if the vba is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the reset address would match the base of this vector table. table 48. interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
document number: mc56f825x rev. 3 04/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale, the freescale logo, and codewarrior are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm . off. processor exper t is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009-2011. all rights reserved.

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