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1 tm file number 3039.2 hs-81c55rh, hs-81c56rh radiation hardened 256 x 8 cmos ram the hs-81c55/56rh are radiation hardened ram and i/o chips fabricated using the intersil radiation hardened self- aligned junction isolated (saji) silicon gate technology. latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic scr effect seen in conventional bulk cmos devices. the hs-81c55/56rh is intended for use with the hs-80c85rh radiation hardened microprocessor system. the ram portion is designed as 2048 static cells organized as 256 x 8. a maximum post irradiation access time of 500ns allows the hs-81c55/56rh to be used with the hs-80c85rh cpu without any wait states. the hs-81c55rh requires an active low chip enable while the hs-81c56rh requires an active high chip enable. these chips are designed for operation utilizing a single 5v power supply. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-96766. a ?ot-link?is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.asp features electrically screened to smd # 5962-96766 qml quali?d per mil-prf-38535 requirements radiation hardened epi-cmos - total dose. . . . . . . . . . . . . . . . . . . . . 100 krad(si) (max) - transient upset . . . . . . . . . . . . . . . . . .>1 x 10 8 rad(si)/s - latch-up free . . . . . . . . . . . . . . . . . . >1 x 10 12 rad(si)/s electrically equivalent to sandia sa 3001 pin compatible with intel 8155/56 bus compatible with hs-80c85rh single 5v power supply low standby current . . . . . . . . . . . . . . . . . . . .200 a max low operating current . . . . . . . . . . . . . . . . . . . . 2ma/mhz completely static design internal address latches two programmable 8-bit i/o ports one programmable 6-bit i/o port programmable 14-bit binary counter/timer multiplexed address and data bus self aligned junction isolated (saji) process military temperature range . . . . . . . . . . . -55 o c to 125 o c functional diagram ordering information ordering number internal mkt. number temp. range ( o c) 5962r9676601qxc hs1-81c55rh-8 -55 to 125 5962r9676601qyc hs9-81c55rh-8 -55 to 125 5962r9676601vxc hs1-81c55rh-q -55 to 125 5962r9676601vyc hs9-81c55rh-q -55 to 125 5962r9676602qxc HS1-81C56RH-8 -55 to 125 5962r9676602qyc hs9-81c56rh-8 -55 to 125 5962r9676602vxc hs1-81c56rh-q -55 to 125 5962r9676602vyc hs9-81c56rh-q -55 to 125 256 x 8 static ram a b c timer io/ m ad0 - ad7 ce or ce ? ale rd wr reset timer clk timer out 8 pa0 - pa7 port a 8 pb0 - pb7 port b 8 pc0 - pc5 port c vdd (10v) gnd ? 81c55rh = ce 81c56rh = ce data sheet august 2000 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000
2 pinouts 40 lead dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t40 top view 42 lead ceramic metal seal flatpack package intersil outline k42.a top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 timer in reset gnd pc4 pc5 ale ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 vdd pc3 pc2 pc1 pc0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 timer out ce or ce ? wr rd io / m ? 81c55rh = ce 81c56rh = ce pc1 pc2 pb6 pb1 pb2 vdd pb4 pb0 pa7 pa6 pa5 nc pa4 pa3 pa2 pa1 pc0 pa0 wr ale reset pc5 timer out io/ m ce or ce rd pc3 pc4 ad0 ad1 ad2 ad3 nc ad6 ad7 gnd timer in ad4 ad5 pb3 pb5 pb7 33 32 39 38 37 36 35 34 42 41 31 30 29 28 27 24 23 22 40 26 25 10 11 4 5 6 7 8 9 1 2 12 13 14 15 16 19 20 21 3 17 18 hs-81c55rh, hs-81c56rh
3 pin descriptions symbol type name and function reset i reset: pulse provided by the hs-80c85rh to initialize the system (connect to hs-80c85rh reset out). input high on this line resets the chip and initializes the three i/o ports to input mode. the width of reset pulse should typically be two hs-80c85rh clock cycle times. ad0 - ad7 i/o address/data: three-state address/data lines that interface with the cpu lower 8-bit address/data bus. the 8-bit address is latched into the address latch inside the hs-81c55 and hs-81c56rh on the falling edge of ale. the address can be either for the memory section or the i/o section depending on the io/ m input. the 8-bit data is either written into the chip or read from the chip, depending on the wr or rd input signal. ce or ce i chip enable: on the hs-81c55rh, this pin is ce and is active low. on the hs-81c56rh, this pin is ce and is active high. rd i read control: input low on this line with the chip enable active enables and ad0 - ad7 buffers. if io/ m pin is low, the ram content will be read out to the ad bus. otherwise the content of the selected i/o port or command/status registers will be read to the ad bus. wr i write control: input low on this line with the chip enable active causes the data on the address/data bus to be written to the ram or i/o ports and command/status register, depending on io/ m. ale i address latch enable: this control signal latches both the address on the ad0 - ad7 lines and the state of the chip enable and io/ m into the chip at the falling edge of ale. io/ mi i/o memory: selects memory if low and i/o and command/status registers if high. pa0 - pa7 (8) i/o port a: these 8 pins are general purpose i/o pins. the in/out direction is selected by programming the command register. pb0 - pb7 (8) i/o port b: these 8 pins are general purpose i/o pins. the in/out direction is selected by programming the command register. pc0 - pc7 (8) i/o port c: these 6 pins can function as either input port, output port, or as control signals for pa and pb. programming is done through the command register. when pc0 - pc5 are used as control signals, they will provide the following: pc0 - a intr (port a interrupt) pc1 - abf (port a buffer full) pc2 - a stb (port a strobe) pc3 - b intr (port b interrupt) pc4 - b bf (port b buffer full) pc5 - b stb (port b strobe) timer in i timer input: input to the counter-timer. timer out o timer output: this output can be either a square wave or a pulse, depending on the timer mode. vdd i voltage: +5v. gnd i ground: ground reference. hs-81c55rh, hs-81c56rh
4 waveforms trv read ce (81c55rh) or ce (81c56rh) io/ m ad 0-7 ale rd address data valid tad tal tla tll tlc tcc tride trd trdf tcl write ce (81c55rh) or ce (81c56rh) io/ m ad 0-7 ale wr address data valid trv tal tla tll tlc tcc tdw tcl tcl twd hs-81c55rh, hs-81c56rh
5 waveforms (continued) trdi strobed input tss bf str obed intr rd input data from port tsbf tsi tpss trbe tphs strobed output twbf bf str obe intr wr output data to port twi twp tsi tsbe hs-81c55rh, hs-81c56rh
6 functional description the hs-81c55rh and 81c56rh contains the following: 2k bit static ram organized as 256 x 8 two 8-bit i/o ports (pa and pb) and one 6-bit i/o port (pc) 14-bit timer-counter the io/ m (io/memory select) pin selects either the ?e register (command, status, pa0 - pa7, pb0 - pb7, pc0 - pc5) or the memory (ram) portion. the 8-bit address on the address/data lines, chip enable input ce or ce and io/ m are all latched on-chip at the falling edge of ale. waveforms (continued) rd input data bus tpr trp basic input basic input rd input data bus twp reload counter clr load counter clr timer output countdown from 5 to 1 2 1 5 432 1 5 timer in timer out (pulse) timer out (square wave) (note 1) (note 1) tr tf t2 t1 tcyc ttl tth tth ttl note: the timer output is periodic if in an automatic reload mode (m, mode bit = 1) command status pc pb pa timer msb timer lsb 8-bit internal data bus 6 8 8 timer mode figure 1. internal registers hs-81c55rh, hs-81c56rh
7 programming of the command register the command register consists of eight latches. four bits (0- 3) define the mode of the ports, two bit (4-5) enable or disable the interrupt from port c when it acts as control port, and the last two bits (6-7) are for the timer. the command register contents can be altered at anytime by using the i/o address xxxxx000 during a write operation with the chip enable active and io/ m = 1. the meaning of each bit of the command byte is de?ed in figure 3. the contents of the command register may never be read. reading the status register the status register consists of seven latches, one for each bit six (0-5) for the status of the ports and one (6) for the status of the timer. the status of the timer and the i/o section can be polled by reading the status register (address xxxxx000). status word format is shown in figure 4. note that you may never write to the status register since the command register shares the same i/o address and the command register is selected when a write to that address is issued. input/output section the i/o section of the hs-81c55rh and hs-81c56rh consists of ?e registers: (see figure 5) command/status register (c/s) - both register are assigned the address xxxxx000. the c/s address serves the dual purpose. when the c/s registers are selected during write operation, a command is written into the command register. the contents of this register are not accessible through the pins. when the c/s (xxxxx000) is selected during a read operation, the status information of the i/o ports and the timer becomes available on the ad0 - ad7 lines. pa register - this register can be programmed to be either input or output ports depending on the status of the contents of the c/s register. also depending on the command, this port can operate in either the basic mode or the strobed mode (see timing diagram). the i/o pins assigned in relation to this register are pa0 - pa7. the address of this register is xxxxx001. pb register - this register functions the same as pa register. the i/o pins assigned are pb0 - pb7. the address of this register is xxxxx010 pc register - this register has the address xxxxx011 and contains only 6 bits. the 6 bits can be programmed to be either input ports, output ports or as ce (81c55rh) or ce (81c56rh) io/ m ad0 - ad7 ale rd or wr address data valid figure 2. on-board memory read/write cycle tm2 tm1 ieb iea pc2 pc1 pb pa 76543210 defines defines defines enable port a interrupt enable port b interrupt 00 = nop - do not affect counter operation 01 = stop - nop if timer has not started; stop counting if the timer is running 10 = stop after tc - stop imme- diately after present tc is reached (nop if timer has not started) 11 = start - load mode and cnt length and start immediate- ly after loading (if timer is not presently running). if timer is running, start the new mode and cnt length immediately after present tc is reached. 0 = input 1 = output 00 = alt1 11 = alt2 01 = alt3 10 = alt4 0 = input 1 = output pa0 - pa7 pb0 - pb7 pc0 - pc5 timer command figure 3. command register bit assignment timer inte b b bf intr b inte a a bf intr a ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 port a interrupt request port a buffer full/empty (input/output) port a interrupt enable port b interrupt request port b buffer full/empty (input/output) port b interrupt enable timer interrupt (this bit is latched high when terminal count is reached, and is reset to low reading of the c/s register & by hardware reset). figure 4. status register bit assignment hs-81c55rh, hs-81c56rh
8 control signals for pa and pb by properly programming the ad2 and ad3 bits of the c/s register. when pc0 - pc5 is used as a control port, 3 bits are assigned for port a and 3 for port b. the first bit is an interrupt that the hs-81c55rh and hs-81c56rh sends out. the second is an output signal indicating whether the buffer is full or empty, and the third is an input pin to accept a strobe for the strobed input mode. (see table 1). when the ? port is programmed to either alt3 or alt4, the control signals for pa and pb are initialized as follows: figure 6 shows how i/o ports a and b are structured within the hs-81c55rh and hs-81c56rh. note in the diagram that when the i/o ports are programmed to be output ports, the contents of the output ports can still be read by a read operation when appropriately addressed. the outputs of the hs-81c55/56rh are ?litch-free meaning that you can write a ??to a bit position that was previously ??and the level at the output pin will not change. note also that the output latch is cleared when the port enters the input mode. the output latch cannot be loaded by writing to the port if the port is in the input mode. the result is that each time a port mode is changed from input to output, the output pins will go low. when the hs- 81c55/56rh is reset, the output latches are all cleared and all 3 ports enter the input mode. when in the alt1 or alt2 modes, the bits of port c are structured like the diagram above in the simple input or output mode, respectively. reading from an input port with nothing connected to the pins will provide unpredictable results. control input mode output mode bf low low intr low high stb input control input control i/o address ? selection a7 a6 a5 a4 a3 a2 a1 a0 xxxxx0 0 0 interval command/ status register xxxxx0 0 1 general purpose i/o port a xxxxx0 1 0 general purpose i/o port b xxxxx0 1 1 general purpose i/o or control port c xxxxx1 0 0 low-order 8 bits of timer count xxxxx1 0 1 high 6 bits of timer count and 2 bits of timer mode ? i/o address must be qualified by ce = 1(81c56rh) or ce = 0(81c55rh) and io/ m = 1 in order to select the appropriate register. x = don? care figure 5. i/o port and timer addressing scheme hs-81c55rh, hs-81c56rh
9 figure 7 shows how the hs-81c55/56rh i/o ports might be con?ured in a typical system. timer section the timer is a 14-bit down counter that counts the timer in pulses and provides either a square wave or pulse when terminal count (tc) is reached. the timer has the i/o address xxxxx100 for the low order byte of the register and the i/o address xxxxx101 for the high order byte of the register. (see figure 5). to program the timer, the count length reg is loaded ?st, one byte at a time, by selecting the timer addresses. bits 0-13 of the high order count register will specify the length of the next count and bits 14-15 of the high order register will specify the timer output mode (see figure 8). the value loaded into the count length register can have any value from 2h through 3ffh in bits 0-13. there are four modes to choose from: m2 and m1 de?e the timer mode, as shown in figure 9. figure 6. hs-81c55rh and hs-81c56rh port function output latch dq clk clr d q latch clk stb (1) (2) (3) read port mode (4) write port pa/pb pin internal data bus mux hs-81c55rh and hs-81c56rh one bit of port a or port b (1) output mode (2) simple input (3) strobed input (4) = 1 for output mode = 0 for input mode multiplexer control notes: 1. read port = (io/ m = 1)(rd = 0)(ce active) (port address selected) 2. write port = (io/ m = 1)(wr = 0)(ce active) (port address selected) port a port c port b output port a a intr (signal data received) a bf (signals data ready) a stb (acknowl. data rcv?) b stb (load port b latch) b bf (signals buffer is full) b intr (signals buffer ready for reading) input to hs-80c85rh rst input to/from peripheral interface to input port (optional) to hs-80c85rh rst input figure 7. example: command register = 00111001 m2 m1 t13 t12 t11 t10 t9 t8 76543210 t7 t6 t5 t4 t3 t2 t1 t0 76543210 timer mode msb of cnt length lsb of cnt length figure 8. timer format hs-81c55rh, hs-81c56rh
10 bits 6-7 (tm2 and tm1) of command register contents are used to start and stop the counter. there are four commands to choose from: note that while the counter is counting, you may load a new count and mode into the count length registers. before the new count and mode will be used by the counter, you must issue a start command to the counter. this applies even thought you may only want to change the count and use the previous mode. in case of an odd-numbered count, the ?st half-cycle of the squarewave output, which is high, is one count longer than the second (low) half-cycle, as shown in figure 10. the counter in the hs-81c55/56rh is not initialized to any particular mode or count when hardware reset occurs, but reset does stop the counting. therefore, counting cannot begin following reset until a start command is issued via the c/s register. please note that the timer circuit on the hs-81c55/56rh chip is designed to be a square-wave timer, not an event counter. to achieve this, it counts down by twos twice in completing one cycle. thus, its registers do not contain values directly representing the number of timer in pulses received. you cannot load an initial value of 1 into the count register and cause the timer to operate, as its terminal count value is 10 (binary) or 2 (decimal). (for the detection of single pulses, it is suggested that one of the hardware interrupt pins on the hs-80c85rh be used.) after the timer has started counting down, the values residing in the count registers can be used to calculate the actual number of timer in pulses required to complete the timer cycle if desired. to obtain the remaining count, perform the following operations in order: 1. stop the count 2. read in the 16-bit value from the count length registers 3. reset the upper two mode bits 4. reset the carry and rotate right one position all 16 bits through carry 5. if carry is set, add 1/2 of the full original count (1/2 full count - 1 if full count is odd). note: if you started with an odd count and you read the count length register before the third count pulse occurs, you will not be able to discern whether one or two counts has occurred. regardless of this, the hs-81c55/56rh always counts out the right number of pulses in generating the timer out waveforms. tm2 tm1 0 0 nop - do not affect counter operation 0 1 stop-nop - if timer has not started; stop counting if the timer is running 1 0 stop after tc - stop immediately after present tc is reached (nop if timer has not started) 1 1 start - load mode and cnt length and start immediately after loading (if timer is not presently running). if timer is running, start the new mode and cnt length immediately after present tc is reached. timer out waveforms: start count terminal count (terminal count) 0 0 1 1 0 1 0 1 1. single sq. wave 2. continuous sq. wave 4. continuous pulses mode bits m2 m1 3. single pulse on term. count figure 9. timer modes 5 4 figure 10. asymmetrical square-wave output resulting from count of 9 hs-81c55rh, hs-81c56rh
11 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com die characteristics die dimensions: 222mils x 202mils x 14mils 1mil (die thickness) interface materials: glassivation: type: sio2 thickness: 8k ? 1k ? top metallization: type: alsi thickness: 11k ? 2k ? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) metallization mask layout hs-81c55rh, hs-81c56rh timer out (6) io/m (7) ce or ce (8) ad3 (15) ad4 (16) ad5 (17) ad6 (18) (5) pc5 (4) reset (3) timer in (2) pc4 (1) pc3 (40) vdd (39) pc2 (38) pc1 (37) pc0 (36) pb7 (35)pb6 ad7 (19) gnd (20) pa0 (21) pa1 (22) pa2 (23) pa3 (24) pa4 (25) pa5 (26) rd (9) wr (10) ale (11) ad0 (12) ad1 (13) ad2 (14) (34) pb5 (33) pb4 (32) pb3 (31) pb2 (30) pb1 (29) pb0 (28) pa7 (27) pa6 hs-81c55rh, hs-81c56rh

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