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hy57v658020b 4 banks x 2m x 8bit synchronous dram this document is a general produc t description and is subject to change without not ice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.2/nov. 01 description the hynix hy57v658020b is a 67,108,864-bit cmos synchronous dram , ideally suited for the mobile applications which require low power consumption and extended temperature range. hy57v658020b is organized as 4banks of 2,097,152x8. hy57v658020b is offering fully synchronous operation referenced to a positive edge of the clock. all inputs and outputs are syn chro- nized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all inpu t and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles in itiated by a single control command (burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). a burs t of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst re ad or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features ? single 3.3 0.3v power supply ? all device pins are compatible with lvttl interface ? jedec standard 400mil 54pin tsop-ii with 0.8mm of pin pitch ? all inputs and outputs referenced to positive edge of sys- tem clock ? data mask function by dqm ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency power organization interface package HY57V658020BTC-7I 143mhz normal power 4banks x 4mbits x4 lvttl 400mil 54pin tsop ii hy57v658020btc-75i 133mhz hy57v658020btc-10si 100mhz
hy57v658020b rev. 0.2/nov. 01 2 pin configuration pin description pin pin name description clk clock the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables al l inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca8 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq7 data input/output multiplexed data input / output pin vdd/vss power supply/ground power supply for internal circuits and input buffers vddq/vssq data output power/ground power supply for output buffers nc no connection no connection v ss dq7 v ssq nc dq6 v ddq nc dq5 v ssq nc dq4 v ddq nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v dd dq0 v ddq nc dq1 v ssq nc dq2 v ddq nc dq3 v ssq nc v dd nc /we /cas /ras /cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd 54pin tsop ii 400mil x 875mil 0.8mm pin pitch
hy57v658020b rev. 0.2/nov. 01 3 functional block diagram 2mbit x 4banks x 8 i/o synchronous dram state machine a0 a1 a11 ba0 ba1 address buffers address registers mode registers row pre decoders column pre decoders column add counter row active column active burst counter data out control cas latency x decoders internal row counter dq0 dq1 dq6 dq7 refresh self refresh logic & timer pipe line control i/o buffer & logic bank select sense amp & i/o gate clk cke cs ras cas we dqm x decoders x decoders memory cell array y decoders x decoders 2mx8 bank 1 2mx8 bank 0 2mx8 bank 2 2mx8 bank3
hy57v658020b rev. 0.2/nov. 01 4 absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating condition (ta= -40 to 85 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with 3ns of duration 3.v il (min) is acceptable -2.0v ac pulse width with 3ns of duration ac operating condition (ta= -40 to 85 c , v dd =3.3 0.3v, v ss =0v) note : 1. output load to measure access time is equi valent to two ttl gates and one capacitor (50pf) for details, refer to ac/dc output circuit parameter symbol rating unit ambient temperature t a -40 ~ 85 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature ? time t solder 260 ? 10 c ? sec parameter symbol min typ. max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 2.0 v 1,2 input low voltage v il v ssq - 2.0 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voutref 1.4 v output load capacitance for access time measurement cl 50 pf 1
hy57v658020b rev. 0.2/nov. 01 5 capacitance (ta=25 c , f=1mhz) output load circuit dc characteristics i (ta= -40 to 85 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6v parameter pin symbol min max unit input capacitance clk c i1 24pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , dqm ci 2 2.5 5 pf data input / output capacitance dq0 ~ dq7 c i/o 26.5pf parameter symbol min. max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol -0.4vi ol = +4ma vtt=1.4v rt=250 ? 50pf output 50pf output dc output load circuit ac output load circuit
hy57v658020b rev. 0.2/nov. 01 6 dc characteristics ii (ta= -40 to 85 c , v dd =3.3 0.3v, v ss =0v) note : 1.i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2.min. of trrc (refresh ras cycle time) is shown at ac characteristics ii parameter symbol test condition speed unit note 7i -75i -10si operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 100 90 70 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 2ma i dd2ps cke v il (max), t ck = 2ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 15 ma i dd2ns cke v ih (min), t ck = input signals are stable. 15 ma active standby current in power down mode i dd3p cke v il (max), t ck = min 5ma i dd3ps cke v il (max), t ck = 5ma active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = min input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 30 ma i dd3ns cke v ih (min), t ck = input signals are stable. 30 ma burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 90 ma 1 ma auto refresh current i dd5 t rrc t rrc (min), all banks active 210 200 160 ma 2 self refresh current i dd6 cke 0.2v 2ma3 500 ua 4
hy57v658020b rev. 0.2/nov. 01 7 ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns 2.access times to be measured with input signals of 1v/ns edge rate parameter symbol -7i -75i -10si unit note min max min max min max system clock cycle time cas latency = 3 t ck3 7 1000 7.5 1000 10 1000 ns cas latency = 2 t ck2 10 10 12 ns clock high pulse width t chw 2.5 - 2.5 - 3- ns 1 clock low pulse width t clw 2.5 - 2.5 - 3- ns 1 access time from clock cas latency = 3 t ac3 - 5.4 - 5.4 -6 ns 2 cas latency = 2 t ac2 -6 - 6 -6 ns data-out hold time t oh 2.5 - 2.5 - 2.5 - ns data-input setup time t ds 1.5 - 1.5 - 2- ns 1 data-input hold time t dh 0.8 - 0.8 - 1- ns 1 address setup time t as 1.5 - 1.5 - 2- ns 1 address hold time t ah 0.8 - 0.8 - 1- ns 1 cke setup time t cks 1.5 - 1.5 - 2- ns 1 cke hold time t ckh 0.8 - 0.8 - 1- ns 1 command setup time t cs 1.5 - 1.5 - 2- ns 1 command hold time t ch 0.8 - 0.8 - 1- ns 1 clk to data output in low-z time t olz 1- 1 - 1- ns clk to data output in high-z time cas latency = 3 t ohz3 2.7 5.4 - 5.4 -6 ns cas latency = 2 t ohz2 36 - 6 -6 ns
hy57v658020b rev. 0.2/nov. 01 8 ac characteristics i note : 1. a new command can be given trrc after self refresh exit parameter symbol -7i -75i -10si unit note min max min max min max ras cycle time operation t rc 65 - 65 - 70 - ns auto refresh t rrc 65 - 65 - 70 - ns ras to cas delay t rcd 20 - 20 - 20 - ns ras active time t ras 45 100k 45 100k 50 100k ns ras precharge time t rp 20 - 20 - 20 - ns ras to ras bank active delay t rrd 14 - 15 - 20 - ns cas to cas delay t ccd 1- 1 - 1- clk write command to data-in delay t wtl 0- 0 - 0- clk data-in to precharge command t dpl 2- 2 - 2- clk data-in to active command t dal 5- 5 - 4- clk dqm to data-out hi-z t dqz 2- 2 - 2- clk dqm to data-in mask t dqm 0- 0 - 0- clk mrs to new command t mrd 2- 2 - 2- clk precharge to data output hi-z cas latency = 3 t proz3 3- 3 - 3- clk cas latency = 2 t proz2 2- 2 - 2- clk power down exit time t pde 1- 1 - 1- clk self refresh exit time t sre 1- 1 - 1- clk 1 refresh time t ref -64 - 64 -64 ms
hy57v658020b rev. 0.2/nov. 01 9 command truth table note : 1. exiting self refresh occurs by asyn chronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x llllx op code no operation h x hxxx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-writeh x llllx a9 pin high (other pins op code) self refresh 1 entry h l lllhx x exit l h hxxx x lhhh precharge power down entry h l hxxx x x lhhh exit l h hxxx x lhhh clock suspend entry h l hxxx x x lvvv exit l h x x
hy57v658020b device operating option table HY57V658020BTC-7I hy57v658020btc-75i hy57v658020btc-10si cas latency trcd tras trc trp tac toh 143mhz(7ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2.5ns 133mhz(7.5ns) 3clks 3clks 7clks 10clks 3clks 5.4ns 2.5ns 100mhz(8ns) 3clks 3clks 7clks 10clks 3clks 6ns 2.5ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.5ns 100mhz(10ns) 3clks 3clks 5clks 8clks 3clks 6ns 2.5ns cas latency trcd tras trc trp tac toh 100mhz(10.0ns) 3clks 3clks 5clks 8clks 3clks 6ns 2.5ns 83mhz(12.0ns) 2clks 2clks 4clks 6clks 2clks 9ns 3ns
hy57v658020b rev. 0.2/nov. 01 11 package information 400mil 54pin thin small outline package 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 22.327(0.8790) 22.149(0.8720) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) 1.194(0.0470) 0.991(0.0390) 0.80(0.0315)bsc 0.400(0.016) 0.300(0.012) unit : mm(inch) 0.150(0.0059) 0.050(0.0020)

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