dd-00429 arinc 429 microprocessor interface description ddc's dd-00429 provides a complete and flexible interface between a microproces- sor and an arinc 429 data bus. the dd- 00429 interfaces to a processor through a 128 x 32 bit static ram as well as four 32 x 32 receive fifos and two 32 x 32 trans- mit fifos. the dd-00429 can be easily interfaced to 8- or 16-bit processors via a buffered shared ram configuration. the dd-00429, when configured with two dd-03282 transceivers, supports four arinc 429 receive channels (rx0, rx1, rx2 and rx3) each receiving data inde- pendently. the receive data rates (high or low speed) for channel rx0 and rx1 can be programmed independently from rx2 and rx3. the dd-00429 can decode and sort data based on the arinc 429 label and sdi bits via the data match processor and store it in ram and/or fifos via the data store processor. the dd-00429, when configured with two dd-03182 line drivers, supports two arinc 429 transmit channels (tx0 and tx1) and can transmit data indepen- dently. the transmit data rate can also be programmed independently. there are two 32 x 32 bit fifos for each of the transmitters that send out data. the dd-00429 has the capability of pro- gramming three general purpose inter- rupts as well as generating an interrupt based on an error condition. the general purpose interrupts can be programmed to trigger other external hardware. they can either be level or pulse triggered. the features built into the dd-00429 enable the user to off-load the host processor and use that processing time to implement operations other than polling the arinc 429 bus. the decod- ing and sorting of data allows the user to gather data much quicker than past designs. if the user requires a micro- processor in the avionics box, this device will facilitate a clean and quick design. features ? four arinc 429 receive channels, (configured with dd-03282 transceivers) 128 x 32 shared ram interface label and destination decoding and sorting two arinc 429 transmit channels (configured with dd-03182 line drivers) two 32 x 32 transmit fifo's interfaces easily to 8- or 16-bit microprocessor built-in fault detection circuitry free ?c? library software application note an/a-6 ?faq?s? arinc 429 rx 0 logic arinc 429 rx 1 logic arinc 429 rx 2 logic arinc 429 rx 3 logic arinc 429 tx 0 logic arinc 429 tx 1 logic tx fifo 32 words tx fifo 32 words rx 0 fifo 32 words rx 1 fifo 32 words rx 2 fifo 32 words rx 3 fifo 32 words arinc 429 receive 0 arinc 429 receive 1 arinc 429 receive 2 arinc 429 receive 3 arinc 429 transmit 0 arinc 429 transmit 1 2 2 wraparound rx data data match processor data addr ctrl data addr 128 x 16 static ram dmt ram ctrl data addr 128 x 32 static ram rx ram data store processor data addr dmp data addr addr data data interrupt controller 3 16 12 irq data addr control microprocessor or cpu cpu interface data dd-00429vp asic dd-03282 transceiver (2) wraparound wraparound wraparound dd-03182 line driver (2) dd-03182 line driver dd-03182 line driver a2 out a1 out b2 out b1 out ? 1998, 1999 data device corporation figure 1. chip set block diagram
2 data device corporation www.ddc-web.com dd-00429 arinc 429 line outputs - see dd-03182 data sheet arinc 429 line inputs - see dd-03282 data sheet symbol min max units notes parameter vol voh ioz input logic voltage low for all d0 - d15 and dtac k , ready and irq outputs. na +500 -500 vil note: clk input has hysteresis of 2.0 v max positive going, 1.0 v min negative going. vdc 0.8 output leakage current hi z vdc vdd-0.5 -350 +350 na output voltage logic high vdc 0.5 all other inputs and i/o pins. output voltage logic low vdd input logic current high idd na +350 -350 input logic voltage high vdc input logic current low vih input pins with internal pull-up resistor, intel/moto, pol. sel, 8/16 zero wait, master reset . ma -0.2 -1.5 iil iih vdc 2.0 dc supply current device operation @ 16 mhz, typical idd = 30 ma @ 5.0v. ma 50 5.5 4.5 dc supply voltage logic inputs/outputs table 2. dd-00429 specifications (tc = +25c unless otherwise specified ) c 210 ( for 30 sec) c 280 (for 3 sec) lead temperature (soldering) c 125 -55 operating temperature c 150 -65 storage temperature body temperature (soldering) vdc +29 -29 signal input voltage (arinc 429 inputs vdc vdd+0.3 -0.3 signal input voltage (logic inputs) vdc 7.0 -0.3 dc supply voltage units max min parameter table 1. dd-00429 absolute maximum ratings (tc = +25c unless otherwise specified)
3 data device corporation www.ddc-web.com dd-00429 the incoming arinc 429 data contains a 00 in its s/d bit pair. 3) receive channel number: bits 12 and 13 of each dmt entry are compared to the number of the channel which received the arinc 429 data. a data match has occurred when all of the previous conditions are satisfied; the data will then be stored in a ram location whose address equals the matching dmt entry minus 200 hex. bit 11 of each dmt entry, when set, will cause the incoming arinc 429 data to be stored in the corresponding receive chan- nel fifo (as well as the rx ram) when the data match condi- tions are met. bits 14 and 15 of each dmt entry provide the ability to cause one of three general purpose interrupts upon a data match con- dition. if set to ?00? then no interrupt will occur upon a data match condition (more information on interrupts is described later). arinc 429 transmitter(s) the dd-00429 supports two arinc 429 transmitters. each of these channels transmits data independently and are designat- ed tx0 and tx1. the transmit output of the dd-00429 is a ttl encoded digital data stream which can be connected directly to ddc?s dd-03182 arinc 429 line driver. transmit data rates can be programmed for channels 0 and 1 independently. the transmit data rate is determined by the high- speed/low-speed bit for each of the tx channels in arinc control register 1 and the associated arinc clock input (arinc clk 0 or arinc clk 1). the two, 1 mhz arinc clock inputs may be tied to the 1 mhz clock output or they may be con- nected to another clock source to achieve transmit data rates other than 100 khz or 12.5 khz. the transmit clock input should be 10 times (for high-speed mode) or 80 times (for low-speed mode) the desired arinc transmit data rate. transmit fifos: each transmitter channel is provided with an output fifo which is 32 words deep by 32 bits wide. when writ- ing data to the tx fifo, the associated disable txn bit in arinc control register 2 can be set to a logic zero until the fifo is loaded with the desired data. upon setting the disable txn low the transmit channel will send the 32-bit message words with appropriate interword gaps on the arinc 429 output. a status bit indicating that the fifo is empty is supplied for each trans- mitter in the arinc status register. wraparound testing can be performed from tx0 to rx0 and rx1 and from tx1 to rx2 and rx3. the data received on rx1 and rx3 in wraparound test mode is inverted. wraparound testing is enabled by setting the appropriate bits in arinc control register 1. the parity of the transmitted word can be altered to even parity (instead of the usual odd parity) by setting the asso- arinc 429 receivers the dd-00429 supports four arinc 429 inputs, designated receive channels 0 through 3 (rx0, rx1, rx2 and rx3). the architecture of each of the four receiver circuits is identical and each receives data independently. arinc 429 data is directly received into the dd-03282 arinc 429 transceiver. input pro- tection, in accordance with the arinc 429 specification, is pro- vided along with voltage level translation from +5 v bipolar, non- return-to-zero data to conventional, +5 v logic levels. receive data rates can be programmed for channels 0 and 1 independently of channels 2 and 3 via bits 2 and 3 of arinc control register 2. the receiver circuitry will successfully decode an incoming arinc 429 data stream as long as the data rate is within 5% of the nominal rate as determined by the hi speed/low speed bit and the associated arinc clock input (arinc clk 0 or arinc clk 1). the two 1 mhz arinc clock inputs may be tied to the 1 mhz receive clock output or may be connected to another clock source. the arinc clk input should nominally be 10 times (for high-speed mode) or 80 times (for low-speed mode) the desired arinc data rate. arinc clk 0 is used by channels rx0 and rx1 while arinc clk 1 is used by channels rx2 and rx3. filtering and sorting rx data: the receiver circuitry converts the serial data stream into a 32-bit-wide parallel data word. the 32-bit word is processed internally by a data match processor (dmp). it compares the incoming data to a table of data initial- ized by the processor. this determines what incoming data is to be saved, where it is going to be saved, and if any interrupts are to be generated. the table of data is stored in a 128 word x 16 bit data match table (dmt) ram. when a match between the received arinc 429 data and the criteria stored in a dmt entry is found, the received data, the storage address and modes, and interrupt parameters are passed to the data store processor (dsp). the storage address in the receive ram is the address of the first matching dmt entry minus 200 hex. there are three requirements that must be met in order to match incoming arinc 429 data to each dmt entry: 1) system address label: bits 0-7 of the dmt are compared to the system address label (sal) of the incoming arinc 429 data word. if the dmt sal entry is zero then the sal of the incoming data word is ignored (or considered a match). 2) source/destination bits: bits 8 and 9 of each dmt entry are compared to the source/destination (s/d) bits of the incoming arinc 429 data word. if these bits match, or if bit 10 of the dmt entry is set to a 1, then the s/d bit comparison is considered a match. it is also possible, through dmp control register 1, to enable ?all call mode? as defined in the arinc 429 specification. when enabled for a particular receive channel, the s/d bits will be considered a match when
4 data device corporation www.ddc-web.com dd-00429 ciated txn parity bit in the arinc control register 1. this is use- ful to verify proper operation of the parity check circuitry for each of the receive circuits during wraparound test mode. processor interface the processor interface allows for the use of either an 8- or 16-bit data bus. intel or motorola control signal formats can also be used. interrupt operational modes the dd-00429 provides four interrupt outputs. three of these interrupt outputs (irq1, irq2, and irq3) are general purpose programmable interrupts. the fourth interrupt is an error interrupt output which is specifically used to provide indications of various error conditions and is nonmaskable. error interrupt operation when an error condition occurs, the err or output pin goes low to indicate the presence of an error. the error pin will go high again when the error status register is clear. each of these bits is cleared by either reading the error status register or remov- ing the error condition. general purpose interrupts the three general purpose interrupt outputs can be used for mul- tilevel interrupts or to trigger other external hardware for various conditions. each condition can be mapped to any one of the three general purpose interrupts or disabled (by mapping to irq0 which does not exist). each interrupt output can be pro- grammed to be either a level interrupt or pulse interrupt via table 3. dd-00429vp (144-pin tqfp) asic pinouts pin no. description pin no. description pin no. description pin no. description 1 +5v 37 +5v 73 +5v 109 +5v 2 tx db11 38 xtal1 (n/c) 74 osc clk out (n/c) 110 reset 1 3 tx db12 39 gnd 75 bist dmt (n/c) 111 cw strb1 4 tx db13 40 tsb2 (n/c) 76 bist ram 7 (n/c) 112 en tx1 out 5 tx db14 41 tsb3 (n/c) 77 bist ram 24 (n/c) 113 tx1 empty 6 tx db15 42 tsa0 (n/c) 78 d0 114 ld tx1 hi 7 en rx1 43 tsa1 (n/c) 79 d1 115 ld tx1 lo w 8 en rx0 44 tsa2 (n/c) 80 d2 116 +5v 9 select 45 tsa3 (n/c) 81 d3 117 gnd 10 rx rd y1 46 tma0 (n/c) 82 d4 118 +5v 11 rx rd y0 47 tma1 (n/c) 83 d5 119 16 mhz clock 12 gnd 48 tma2 (n/c) 84 d6 120 en rx3 13 gnd 49 tma3 (n/c) 85 d7 121 en rx2 14 gnd 50 tma4 (n/c) 86 gnd 122 rx rd y3 15 int/ mo t o 51 tma5 (n/c) 87 +5v 123 rx rd y2 16 8/16 52 tma6 (n/c) 88 gnd 124 +5v 17 +5v 53 tma7 (n/c) 89 +5v 125 gnd 18 gnd 54 tsb0 (n/c) 90 d8 126 reset 0 19 a0 55 tsb1 (n/c) 91 d9 127 cw strb 0 20 a1 56 +5v 92 d10 128 en tx0 out 21 a2 57 gnd 93 d11 129 tx0 empty 22 a3 58 tmb4 (n/c) 94 d12 130 ld tx0 hi 23 a4 59 tmb5 (n/c) 95 d13 131 ld tx0 lo w 24 a5 60 tmb6 (n/c) 96 d14 132 gnd 25 a6 61 tmb7 (n/c) 97 d15 133 tx db0 26 a7 62 zero wait mode 98 gnd 134 tx db1 27 a8 63 ready 99 gnd 135 tx db2 28 a9 64 rd or ds 100 irq3 136 tx db3 29 a10 65 wr or rd/wr 101 irq2 137 tx db4 30 cs0 66 dt a ck 102 irq1 138 tx db5 31 cs1 67 err or 103 reset rc 139 tx db6 32 cs2 68 master reset 104 arinc clk out 140 tx db7 33 bist r3 (n/c) 69 +5v 105 arinc clk 1 141 tx db8 34 gnd 70 bist toa (n/c) 106 arinc clk 0 142 tx db9 35 +5v 71 bist tob (n/c) 107 bist r2 (n/c) 143 tx db10 36 gnd 72 gnd 108 gnd 144 gnd
5 data device corporation www.ddc-web.com dd-00429 irq control register 2. when programmed for pulse interrupt mode, the associated interrupt pin will go low for 1 s and return high again. when programmed for level interrupt mode, the interrupt will remain until the associated irq status register is read, thus clearing the associated bits in each interrupt register. each of the individual interrupt registers can be masked by set- ting their corresponding bit in irq control register 1. it should be noted that the masking function only prevents the associated irq pin from becoming active. when the mask bit is cleared, an interrupt can occur in level irq mode if one or more interrupt conditions occurred during the time when the mask was set. if the user needs to ensure the interrupt will not occur upon clear- ing the mask bit, the cpu should be programmed to read the associated interrupt status register immediately prior to clearing the irq mask bit. zero wait mode operation: when zero wait mode is enabled by not grounding the zero wait pin, the host microprocessor may read data from the dd-00429 shared memory resources (dmt and rx ram) without using the ready or dtack signals to insert wait states into the microprocessor cycle. this is accomplished by an additional ?dummy read? of the desired address. this dummy read causes the dd-00429 to fetch the data from the source and place it in a latch. the data can then be read from the latch (word-by-word or byte-by-byte) by read- ing the same addresses. thus for a 32-bit read in 8-bit mode, the microprocessor would perform a total of five read operations. the first read would be the dummy read; subsequent reads would transfer the data. 40 gnd 80 gnd 120 table 4. dd-00429fp (160-pin pqfp) asic pinouts gnd 160 gnd 39 +5v 79 bist tob (n/c) 119 bist r2 (n/c) 159 tx db10 pin no. description pin no. description pin no. description pin no. description 1 +5v 41 +5v 81 +5v 121 +5v 2 tx db11 42 xtal1 (n/c) 82 osc clk out (n/c) 122 reset 1 3 tx db12 43 gnd 83 bist t1a (n/c) 123 cw strb1 4 tx db13 44 tsb2 (n/c) 84 bist t1b (n/c) 124 en tx1 out 5 tx db14 45 tsb3 (n/c) 85 bist dmt (n/c) 125 tx1 b in 6 tx db15 46 tsa0 (n/c) 86 bist ram7 (n/c) 126 tx1 a in 7 en rx1 47 tsa1 (n/c) 87 bist ram24 (n/c) 127 tx1 empty 8 en rx0 48 tsa2 (n/c) 88 d0 128 ld tx1 h i 9 select 49 tsa3 (n/c) 89 d1 129 ld tx1 lo w 10 rx rd y1 50 tma0 (n/c) 90 d2 130 +5v 11 rx rd y0 51 tma1 (n/c) 91 d3 131 gnd 12 gnd 52 tma2 (n/c) 92 d4 132 +5v 13 gnd 53 tma3 (n/c) 93 d5 133 16 mhz clock 14 gnd 54 tma4 (n/c) 94 d6 134 en rx3 15 int/ mo t o 55 tma5 (n/c) 95 d7 135 en rx2 16 8/16 56 tma6 (n/c) 96 gnd 136 rx rd y 3 17 +5v 57 tma7 (n/c) 97 +5v 137 rx rd y 2 18 tx0 a 58 tsb0 (n/c) 98 gnd 138 +5v 19 tx0 b 59 tsb1 (n/c) 99 +5v 139 gnd 20 tx1 a 60 +5v 100 d8 140 reset 0 21 tx1 b 61 gnd 101 d9 141 cw strb0 22 gnd 62 tmb0 (n/c) 102 d10 142 en tx0 out 23 a0 63 tmb1 (n/c) 103 d11 143 tx0b in 24 a1 64 tmb2 (n/c) 104 d12 144 tx0a in 25 a2 65 tmb3 (n/c) 105 d13 145 tx0 empty 26 a3 66 tmb4 (n/c) 106 d14 146 lo ad tx0 hi 27 a4 67 tmb5 (n/c) 107 d15 147 ld tx0 lo w 28 a5 68 tmb6 (n/c) 108 gnd 148 gnd 29 a6 69 tmb7 (n/c) 109 gnd 149 tx db0 30 a7 70 zero wait mode 110 irq3 150 tx db1 31 a8 71 ready 111 irq2 151 tx db2 32 a9 72 rd or ds 112 irq1 152 tx db3 33 a10 73 wr or rd/ wr 113 reset rc 153 tx db4 34 cs0 74 dt a ck 114 arinc clk out 154 tx db5 35 cs1 75 err or 115 arinc clk 1 155 tx db6 36 cs2 76 master reset 116 arinc clk 0 156 tx db7 37 bist r3 (n/c) 77 +5v 117 bist r0 (n/c) 157 tx db8 38 gnd 78 bist toa (n/c) 118 bist r1 (n/c) 158 tx db9
6 data device corporation www.ddc-web.com dd-00429 dd-00429vp pin 1 .059 0.004 (1.50 0.1 ) .004 0.002 (0.1 0.05 ) .055 0.002 (1.40 0.05 ) .866 0.004 (22.00 0.1 ) .787 0.004 (20.00 0.1 ) .866 0.004 (22.00 0.1 ) .787 0.004 (20.00 0.1 ) .024 0.006 (0.60 0.15 ) .0197 (0.50) .008 (0.22 0.05 ) +0.02 ? 0.01 dimensions in inches (millimeters). figure 2. dd-00429vp mechanical outline (144-pin tqfp) 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 39 eq. sp. @ 0.0256 = 0.998 (0.65 = 25.36) (tol. noncum) 1 pin no. 1 index 1 160 120 121 81 80 41 40 pin numbers for ref. only 0.0256 (.65) (typ) 0.133 (3.38) (ref) 0.077(1.96) (typ) 1.256 0.01 (31.9) (typ) see detail "a" detail "a" nts 0.016 (0.41) (min) (typ) 0.031(.79) (typ) 0.007 0.002 (0.18) (typ) 0.146 +0.008 (3.71) -0.000 0.013 +0.000 (0.33) -0.003 0.012 0.003 (0.3 0.08 ) (typ) 1.102 0.004 (27.99 0.1 ) 1.102 0.004 (27.99 0.1 ) notes: 1 lead cluster to be centralized about case centerline within 0.010 (0.25). 2. dimensions in inches (millimeters). dd-00429fp figure 3. dd-00429fp asic mechanical outline (160-pin pqfp)
7 data device corporation www.ddc-web.com dd-00429 ordering information chip set: dd-00429xp - x00 temperature range: 2 = -40 - +85 c 9 = -55 - +85 c (fp package only) asic package type: p = plastic lead type: f = 160-pin quad flat pack v = 144-pin tqfp note: the dd-03182 and dd-03282 are required to complete the arinc 429 interface (see additional ordering information). the dd-00429 is only the microprocessor interface/ram/fifo and interrupt controller. dd-03182xx-xxx ? arinc 429 line driver options: 0 = with resistors and fuses 1 = with resistors, no fuses* screening: 0 = standard ddc procedures 2 = burn-in temperature range: 1 = -55 to +125 c (ceramic only) 2 = -40 to +85 c 9 = -55 to +85 c (gp package only) package style/type: dc = 16-pin ceramic dip gp = 16-pin plastic soic pp = 28-pin plastic plcc vp = 14-pin plastic soic *vp version only. additional ordering information dd-03282xx-xx0 ? arinc 429 transceiver screening: 0 = standard ddc procedures 2 = burn-in (dc package only) temperature range: 1 = -55 to +125 c (dc package only) 2 = -40 to +85 c 9 = -55 to +85 c (gp package only) asic package style/type: dc = 40-pin ceramic dip pp = 44-pin plastic plcc gp = 44-pin plastic pqfp note: these transceiver/line driver part numbers are provided for historical reference only. these components are now provided by device engineering inc. for a complete cross-reference chart, please visit dei at www.deiaz.com, (480) 303-0822.
8 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. d1-02/01-0 printed in the u.s.a. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7435 headquarters - tel: (631) 567-5600 ext. 7435, fax: (631) 567-7358 west coast - tel: (714) 895-9777, fax: (714) 895-4988 southeast - tel: (703) 450-7900, fax: (703) 450-6610 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u
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