dual 5-bit bus switch cybus3384 cybus3l384 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 may 1994 C revised march 1996 1cy bus 3 l3 84 features ? zero propagation delay ?2 w switches connect inputs to outputs ? direct bus connection when switches are on ? high (>500 meg w ) resistance when switch is off ? performs bidirectional translator function between 3.3v and 5.0v power supplies ? cmos for low power dissipation ? edge-rate control circuitry for significantly improved noise characteristics ? inputs and outputs interface with 5.0v cmos, ttl, or 3.3v cmos ? esd > 2000v ? power-off disable cybus3l384 ? low power version functional description the cybus3384 and cybus3l384 are ten-bit, two-port bidi- rectional bus switches that allow one bus to be connected di- rectly to, or isolated from, another without introducing addition- al propagation delay or ground noise. the input and output voltage levels allow direct interface with ttl and cmos de- vices. two bus enable signals, be 1 and be 2 , turn on the upper and lower five bits, respectively. designed with a low resistance of 2 w , the cybus3384 and cybus3l384 are ideal for use in vme or other high dc drive applications. the power-off disable feature enables modules and cards to be either inserted or withdrawn from operating equi pment without shutting down power. additionally, they facilitate bidi- rectional interfacing between 3.3v and 5v systems by placing a single diode in series with the 5v v cc line and a resistor from pin 24 to ground. the cybus3384 and cybus3l384 are also suitable for small signal analog application where crosstalk and off isola- tion perfor mance of C66 db at 50 mhz is required. the cybus3l384 is a low-power version of the cybus3384 with a typical i cc of 0.2 m a. a 7 a 6 a 4 a 5 a 3 logic block diagram pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 b 6 b 5 b 4 b 3 b 2 b 1 b 0 gnd v cc 15 dip/soic/qsop top view bus3384-1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 1 a 2 a 0 bus3384-2 a 8 a 9 b 8 b 9 be 1 be 2 b 7 b 9 a 9 a 8 b 8 be 2 be 1 pin description name descr iption a bus a, inputs or outputs b bus b, inputs or outputs be 1 , be 2 bus switch enable function table [1] inputs function be 1 be 2 b 0C4 b 5C9 h h high-z high-z non-connect l h a 0C4 high-z connect h l high-z a 5C9 connect l l a 0C4 a 5C9 connect note: 1. h = high voltage level. l = low voltage level. x = dont care.
cybus3384 cybus3l384 2 maximum ratings [2, 3] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. C65 c to +165 c ambient temperature with power applied............................................. C65 c to +135 c supply voltage to ground potential ............... C0.5v to +7.0v dc input voltage............................................ C0.5v to +7.0v dc output voltage ......................................... C0.5v to +7.0v dc output current (maximum sink current/pin)....... 120 ma power dissipation.......................................................... 0.5w static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) operating range range ambient temperature v cc commercial C40 c to +85 c 4.0v to 5.5v military C55 c to +125 c 4.0v to 5.5v electrical characteristics over the operating range parameter description test conditions min. typ. [4] max. unit v ih input high voltage control inputs only 2.0 v v il input low voltage control inputs only 0.8 v v h hysteresis [5] control inputs only 0.2 v v ik input clamp diode voltage v cc =min., i in =C18 ma C0.7 C1.2 v r on switch on resistance [6] v cc =4.75v, v in =0.0v, i on =30 ma 2 4 w v cc =4.75v, v in =2.4v, i on =15 ma 4 8 w i in input l eakage current v cc =max., v in =v cc 1 m a i oz off state current (high-z) v cc =max., v out =0.5v 0.001 1 m a i off power-off disable v cc =0v, v out =4.5v, v in =v cc 1 m a i os output short circuit current [7] v cc =max., v out =0.0v 100 ma on resistance vs. v in @ 4.75 v cc notes: 2. unless otherwise noted, these limits are over the operating free-air temperature range. 3. unused inputs must always be connected to an appropriate logic voltage level, preferably either v cc or ground. 4. typical values are at v cc =5.0v, t a =+25c ambient. 5. this parameter is guaranteed but not tested. 6. measured by voltage drop between a and b pin at indicated current through the switch. on resistance is determined by the lower of the voltages on pin a or pin b. 7. not more than one output should be shorted at a time. duration of short should not exceed one second. the use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. in any sequence of parameter tests, i os tests sho uld be performed last. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 r on w v in , volts
cybus3384 cybus3l384 3 capacitance [6] parameter description typ. [4] max. unit c in input capacitance 3 4 pf c out output capacitance 7 8 pf power supply characteristics parameter description test conditions [8] typ. [4] max. unit i cc quiescent power supply current v cc =max., v in gnd or v cc , f=0 3384 0.2 3.0 m a 3l384 0.2 3.0 m a d i cc quiescent power supply current (input high) [9] v cc =max., v in =3.4v, f=0, per control input 2.0 ma i ccd dynamic power supply cur rent [10] v cc =max., control input toggling, @ 50% duty cycle, a & b pins open 0.12 ma/ mhz i c total power supply current [11, 12] v cc =max., two control inputs toggling, @ 50% duty cycle, f 1 =10 mhz, v in =3.4v 3384 4.4 ma 3l384 4.4 ma switching characteristics over the operating range [13] military commercial parameter description min. max. min. max. unit t plh t phl propagation delay a to b [14, 15] 0.25 .25 ns t pzh t pzl switch turn on delay, be 1 , be 2 to a, b [13] 1.5 7.5 1.5 6.5 ns t phz t phz switch turn off delay, be 1 , be 2 to a, b [13, 14] 1.5 6.5 1.5 5.5 ns |q ci | charge injection, typical [16, 17] 1.5 1.5 pc notes: 8. for conditions shown as min or max use the appropriate values specified un der dc specifications. 9. per ttl driven input (v in =3.4v); a and b pins do not contribute to i cc . all other inputs at v cc or gnd. 10. this current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequ ency. the a and b inputs generate no significant ac or dc currents as they transition. this parameter is not tested but is guaranteed by design. 11. i c =i quiescent + i inputs + i dynamic i c =i cc + d i cc d h n t +i ccd (f 0 /2 + f 1 n 1 ) i cc = quiescent current with cmos input levels d i cc = power supply current for a ttl high input (v in =3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f 0 = clock frequency for registered devices, otherwise zero f 1 = input signal frequency n 1 = number of inputs ch anging at f 1 12. note that activity on a or b inputs do not contribute to i c . the switches merely connect and pass through activity on these pins. 13. see test circuit and waveform. minimum limits are guaranteed but not tested. 14. this parameter is guaranteed by design but not tested. 15. the bus switch contributes no prop agation delay other than the rc delay of the on resistance of the switch and the load capacita nce. the time constant for the switch is much smaller than the rise/fall times of typical driving signals, it adds very l ittle propagation delay to the system. propa gation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 16. measured at switch turn off, a to c, load=50 pf in parallel with 10 meg scope probe, v in at a=0.0v. 17. tested ini tially and after any design change which may affect this parameter.
cybus3384 cybus3l384 4 applic ation information the cybus3384 is a ten-channel bidirectional solid state bus switch with a near zero propagation delay. the cybus3384 is organized into two groups of five n-chan- nel mosfets. each group has an independent control input for output enable (see figure 1 ). because the n-channel mosfet is physically symmetric, the device pin can act as an input or an output. the two enable input (be 1 and be 2 ) sense ttl level signals and drive the gates of the n-channel mosfets to vcc. with the gate at v cc , the output voltage will follow the input voltage up to v cc minus the threshold voltage. at this point the n-channel mosfet begins to turn off, rapidly inc reasing the effective resistance (r on ) such that further increases to input voltage no longer increase the output voltage (see figure 2 ). when either the input or output of the cybus3384 is near zero volts and the gate is at v cc , the device is fully on, (low resis- tance) and available to pass large currents in either direction. in this condition, the cybus3384 inputs are directly connect- ed to the outputs. the cybus3384 provides no signal drive itself. as a result the rise and fall times of the cybus3384 outputs are deter mined by the device driving the cybus3384 inputs rather than the cybus3384 itself. the propagation delay contributed by the cybus3384 is es- sentially zero when the n-channel gate is at v cc . when the device is unpowered, the cybus3384 draws no current from the i/o or control inputs, and there is no current ordering information cybus3384 speed (ns) ordering code package name package type operating range 0.25 cybus3384pc p13/13a 24-lead (300-mil) molded dip commercial cybus3384qc q13 24-lead (150-mil) qsop cybus3384soc s13 24-lead (300-mil) molded soic 0.25 cybus3384dmb d14 24-lead (300-mil) cerdip military CYBUS3384LMB l64 28-square leadless chip carrier ordering information cybus3l384 speed (ns) ordering code package name package type operating range 0.25 cybus3l384pc p13/13a 24-lead (300-mil) molded dip commercial cybus3l384qc q13 24-lead (150-mil) qsop cybus3l384soc s13 24-lead (300-mil) molded soic figure 1. cybus3384 figure 2. v out vs. volts bus3384-3 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 8 a 9 b 8 b 9 be 1 be 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.0 2.0 3.0 4.0 5.0 0 1k ohm 10k ohm 10 meg v in , volts bus3384-4
cybus3384 cybus3l384 5 path from the i/o or control to the p ower pins. there are no back power or current drain problems when the device is un- powered. the cybus3384 provides an ideal inter face between 5v and 3.3v components, since the cybus3384 provides no signal drive, the i cc demands are small, limited to ac switching of the n-channel gates, control circuitry, and a minute amount of i/o leakage. due to the low current demands of the cybus3384, it is possible to lower the cybus3384 vcc from a standard 5.0v supply with a small, inex pensive diode and a resistor to provide a low-current full-bidirectional signal com- patibility between 5v logic family signals and 3.3v logic family signals. by adding a small, inexpensive diode and a resistor, the cybus3384 v cc supply voltage can be shifted to 4.3v as shown in figure 3 . 5v signals will then be limited to 3.3v as they pass through the cybus3384. 3.3v signals will pass back through the cybus3384 unaltered and provide compat- ibility with 5v ttl input requirements. note that the conversion is bidirectional and is l imited to 3.3v independent of which side is driven to 5v. the cybus3384 could convert 5v signals for use on a 3.3v bus of convert a 5v bus to signals compatible with 3.3v components. 3.3v/5v supply operation in certain system applications, the cybus3384 must operate from either a 5v or 3.3v power supply, depending on the state of the system. if this occurs, the circuit shown in figure 4 can be added to step the 3.3v supply up to a nominal 5v level. the low-cost, high-efficiency step up regulator shown in the figure is available for linear technology, maxim, and other suppliers. the diode arrangement will automatically select the active supply. standard silicon diodes can be used because the cybus3384 v cc is specified at 4.0v. low power bus isolation modern battery-operated systems rely on internal power man- agement schemes to disconn ect power from s ubsystems not in use. usually the subsystem bus input esd protection cir- cuits consist of a pair of clamp diodes to limit input voltage excursions to a maxi mum of v cc +vt and Cvt (see figure 5 ). removing power from these causes the vcc esd clamp di- ode to connect the dead ci rcuit inputs to gnd, often signifi- cantly inc reasing bus loading and power dis sipation (see fig- ure 6 ). the cybus3384 placed on the input of the load to be disconnected effectively prevents bus loading and its associ- ated problems. figure 3. system with cybus3384 as 5v ttl to 3v converter 3.3v logic 3.3v cpu 3.3v dram 5.0v eprom 5.0v bus chip set 5.0v i/o 5.0v i/o cybus3384 3.3v < C > 5.0v converter 4.3 v cc +5v bus3384-5 figure 4. 3.3v/5v supply switch figure 5. gate input (power on) figure 6. gate input (power off) 5v step-up reg. cybus3384 5v 3.3v v cc bus3384-6 v t v t v cc bus3384-7 v t v t v cc bus3384-8
cybus3384 cybus3l384 6 high speed dual port ram as shown in figure 7 , a high-speed, dual-port memory is im- plemented using a combination of commodity sram, a simple arbitration circuit, and the cybus3384. processor 1 is the system host processor while processor 2 is dedicated periph- eral processor (such as a dsp for acquisitioning and manipu- lating data). either pro cessor can own the sram by first read- ing the busy bit to determine if the sram is available. if so, the requesting pro cessor takes cont rol by writing the own bit (which redirects the bus through the cybus3384s and sets the busy bit notifying the other bus the sram is not avail- able). processor 1 owns the bus and may now ac cess the sram as needed. when finished, processor 1 resets the own bit releasing the sram. the sram access sequence is identical for processor 2. in this application, the cybus3384 saves 10 ns compared to using an f244 address buffer and an f245 data bus transceiver. this, in turn, allows the use of a slower, more available sram, resulting in lower system cost and power savings. selectable termination loads in some applications, it is desirable to vary the characteristic termination impe dance as the system c onfiguration changes. this is a common problem in automatic test equipment appli- cations. because of their low on resistance, miniature relays are often used to switch termination loads. a single cybus3384 can replace as many as 10 such relays resulting in faster switching operation, lower power, and significant cost savings. fast latch figures 8 and 9 show variations of a latch having a sub 1-ns propagational delay time using the cybus3384 in combina- tion with other components. this circuit has the advantage of being four to ten times faster than an equivalent implementa- tion using a 373 latchand with no added noise. figure 8 relies on the stray c apacitance of the bus to maintain data when the cybus3384 opens. assuming 50-pf stray c apaci- tance at room temper ature and a 1 microampere input leakage current, a 1 volt droop from the initial voltage level would take 50 micro secon ds. figure 9 shows the addit ion of a physical capacitor if t here is insufficient stray capacitance. figure 10 shows an active bus ter mination capable of s ustaining the pro- grammed logic for an indefinite period of time in the presence of v cc . document #: 38C00355 figure 7. high speed dual port ram cybus3384 processor 1 processor 2 arbiter cybus3384 be 1 /be 2 enables 1 address 1 enables 2 address 2 static ram addr/enables bus2 cybus3384 cybus3384 cybus3384 bus1 bus3384-9 figure 8. latch variation w ith spray capacitance figure 9. latch variation w ith physical capacitor figure 10. active bus termination ram or other logic cybus3384 bus3384-10 stray cap. (50pf) ram or other logic cybus3384 bus3384-11 c1 ram or other logic cybus3384 bus3384-12 fct244t 1k
cybus3384 cybus3l384 7 package diagrams 24-lead (300-mil) cerdip d14 milCstdC1835 dC 9 config.a 28-square leadless chip carrier l64 milCstdC1835 cC4 24-lead (300-mil) molded dip p13/p13a
cybus3384 cybus3l384 ? cypress s emiconduc tor corporation, 1996. the information contained herein is subject to change without noti ce. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. package diagrams (continued) 24-lead quarter size outline q13 24-lead (300-mil) molded soic s13
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