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edi4164mev-rp 1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product features n access time: 50, 60 and 70ns n 4 meg x 16 bit cmos dynamic ram n package: ? 50 pin plastic tsop n extended data out mode operation n single +3.3v ( 0.3v) supply operation n 4096 cycles refresh pin configuration a 0-11 address inputs lcas / column address ucas strobes ras row address strobe we write enable input oe output enable dq 1-16 data inputs/outputs v cc power (+3.3v 0.3v) v ss ground nc no connection v cc dq 1 dq 2 dq 3 dq 4 vcc dq 5 dq 6 dq 7 dq 8 nc v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 nc nc nc nc nc a 0 a 1 oe nc nc nc a 11 a 10 a 2 a 3 a 4 a 5 v cc a 9 a 8 a 7 a 6 v ss v cc we ras v ss lcas ucas 1 50 25 26 4mx16 edo (extended data out) dynamic ram 3.3v pin description top view september 1999 rev. 2 n ras - only, cas-before-ras, and hidden refresh capability n low operating power dissipation n low standby power n common i/o n all inputs/outputs ttl compatible n industrial (-40 c to +85 c) and military (-55 c to +125 c) temperature ranges
edi4164mev-rp 2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com absolute maximum ratings* recommended dc operating conditions (1) voltage on any pin relative to vss -0.5v to 4.6v operating temperature (industrial) -40 c to +85 c operating temperature (military) -55 c to +125 c storage temperature -55 c to +150 c power dissipation 1 watt output current 50 ma *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter sym min typ max units supply voltage v cc 3.0 3.3 3.6 v supply voltage v ss 00 0v input high voltage v ih 2 -- vcc +0.3 v input low voltage v il -0.3 -- 0.8 v notes: 1. all voltage values are with respect to v ss . block diagram control clocks refresh timer refresh control refresh counter row address buffer col. address buffer row decoder memory array 4096 x 1024 x 16 cells column decoder data in buffer data out buffer sense amps & io ras cas we a0-a11 dq1 to dq16 oe lcas ucas
edi4164mev-rp 3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com capacitance (f = 1.0mhz, t a = 25 c, v cc = 3.3v) parameter symbol max unit address input capacitance c in1 5pf input capacitance (cas, we, ras) c in2 7pf output capacitance (q) c dq 7pf electrical characteristics parameter symbol conditions min typ max units operating current i cc1 ras and ucas, lcas, 180 ma address cycling @t rc = min. standby current i cc2 ras = ucas = lcas = we = v ih 4ma ras-only-refresh current i cc3 ucas = lcas = v ih , ras, addressing 180 ma cycling @ t rc = min edo mode current i cc4 ras = v il , ucas or lcas 165 ma addressing cycling @ t rc = min. standby current i cc5 ras = ucas = lcas = we = v cc -0.2v 2 ma cas-before-ras refresh current i cc6 ras and ucas or lcas cycling @ t rc =min. 180 ma input leakage current i il 0v v in vcc +0.3v -5 5 m a all other input pins = 0v output leakage current i ol 0v v out vcc -5 5 m a output high voltage v oh i oh = -2.0ma 2.4 v output low voltage v ol i ol = 2.0ma 0.4 v notes: 3. i cc1 (av), i cc3 (av), i cc4 (av), and i cc6 are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4. i cc1 (av) and i cc4 (av) are dependent on output loading. specified values are obtained with the output open. truth table ras lcas ucas we oe dq1-8 dq9-16 state h x x x x high z high z standby l h h x x high z high z refresh l l h h l dq out high z byte read l h l h l high z dq out byte read l l l h l dq out dq out word read l l h l h dq in byte write l h l l h dq in byte write l l l l h dq in dq in word write l l l h h high z high z
edi4164mev-rp 4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com timing requirements ? read, write, read-modify-write, refresh, and page mode cycles (v cc = 3.3v 0.3v) notes 1, 2, 5 50ns 60ns 70ns parameter symbol min max min max min max unit notes random read or write cycle time t rc 90 110 130 ns read-modify-write cycletime t rwc 126 150 180 ns access time from cas t cac 13 15 20 ns 3,4,5 access time from ras t rac 50 60 70 ns 3,4,10 access time from column address t aa 25 30 35 ns 3,10 cas to output in low-z t clz 000ns6 output buffer turn-off delay t off 0 13 0 15 0 20 ns 6,14 transition time t t 250250250ns2 ras precharge time t rp 30 40 50 ns ras low pulse width t ras 50 10,000 60 10,000 70 10,000 ns ras hold time after cas low t rsh 13 15 20 ns cas hold time after ras low t csh 38 45 50 ns cas low pulse width t cas 8 10,000 10 10,000 15 10,000 ns ras to cas delay time t rcd 11 37 14 45 20 50 ns 4 column address delay from ras low t rad 9 251230 1535ns10 delay cas high to ras low t crp 555ns row address set up time t asr 000ns row address hold time t rah 91010ns column address set up time t asc 000ns column address hold time t cah 81015ns column address hold time referenced ras t ar 40 45 55 ns column address to ras setup t ral 25 30 35 ns read set up time before cas low t rcs 000ns read hold time after cas high t rch 000ns8 read hold time after ras high t rrh 000ns8 write hold time after cas low t wch 81015ns write command hold time referenced to ras t wcr 40 45 55 ns write pulse width t wp 71015ns ras hold time after write low t rwl 13 15 20 ns cas hold time after write low t cwl 81015ns data set up time t ds 000ns9 data hold time after cas low t dh 81015ns9 data hold time referenced to ras t dhr 40 45 55 ns refresh cycle (industrial) t ref 32 32 32 ms refresh cycle (military) t ref 16 16 16 ms write setup time before cas low t wcs 000ns7 cas low to we low delay t cwd 30 35 45 ns 7 ras low to we low delay t rwd 67 79 94 ns 7 column address setup to cas high t ach 15 15 15 ns oe low to output valid t oe 13 15 20 ns 13 cas low to dout t coh 333ns ras low to we low t wrh 10 10 10 ns write high to ras low t wrp 10 10 10 ns address to we low delay t awd 48 55 65 ns 7
edi4164mev-rp 5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com write cycle, early and delayed write (vcc = 3.3v 0.3v) notes 1,2,5 50ns 60ns 70ns parameter symbol min max min max min max unit notes cas setup for cas before ras refresh t csr 555ns cas hold for cas before ras refresh t chr 10 10 15 ns precharge to cas active t rpc 555ns access time from cas precharge t cpa 28 35 40 ns 3 edo page cycle time t pc 20 25 30 ns edo page read-modify-write cycle time t prwc 47 56 71 ns cas precharge time (edo cycle) t cp 81010ns ras pulse width (edo cycle) t rasp 50 125k 60 125k 70 125k ns output disable time after oe high t od 013015020ns6 write low to next oe low t oeh 81012ns oe low to cas high setup time t oes 455ns oe high hold from cas high t oehc 51010ns oe high pulse width t oep 71010ns oe setup prior to ras during t ord 000ns hidden refresh cycle oe delay from we t whz 010013015ns we pulse to disable at cas high t wpz 10 10 10 ns notes: 1. an initial pause of 200 m s is required after power-up followed by any 8 ror or cbr cycles before proper device operation is achieved, and must be repeat ed whenever t ref is exceeded. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 3ns for all inputs. 3. measured with a load equivalent to 1 ttl load and 100pf. 4. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd (max) 6. this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 7. t wcs , t rwd , t cwd and t awd are non restrictive operating parameters. they are included in the data sheet as electric characteristics only. if t wcs 3 t wcs (min), the cycle is an early write and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd > t rwd (min) and t awd > t awd (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. either t rch or t rrh must be satisfied for a read cycle. 9. these parameters are referenced to the cas leading edge in early write cycles and to the we falling edge in oe controlled wri te cycle and read-modify-write cycles. 10.operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa .
edi4164mev-rp 6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com read cycle notes : 1. although we is a "don't care" at ras time during an access cycle (read or write), the system designer should implement we hi gh for t wrp and t wrh . 2. t off is referenced from rising edge of ras or cas, whichever occurs last. t rcs ras cas a0-a11 row we dq t aa t rac t asc t rrh t rp t off t csh t rcd t cas t rsh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t rad t ral t ach t wrh t cah t rah t asr t crp t od t ras t rc row column t rch note 2 note 1 valid data t wrp t clz t cac t oe open open undefined don't care
edi4164mev-rp 7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com write cycle, early write read write cycle (late write and read-modify-write cycles) ras cas a0-a11 row we dq t wp t cwl t rwl t wcr t asc t rp t wcs t csh t rcd t ar t cas t rsh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t ral t ach t wrh t cah t rah t asr t crp t dh t ras t rc row column note 1 valid data t wrp t dhr t wch t ds undefined don't care ras cas a0-a11 row we dq t rwd t cwd t asc t rp t rcs t csh t rcd t ar t cas t rsh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t ral t ach t wrh t cah t rah t asr t crp t aa t ras t rwc row column note 1 t wrp t rac t awd t cac undefined don't care valid d out valid d in open open t cwl t rwl t wp t dh t ds t clz t oeh t oe t od
edi4164mev-rp 8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edo-page-mode early write cycle edo-page-mode read cycle ras cas a0-a11 row we dq t asc t rp t rcs t csh t rcd t pc t ar t ral t cas t rsh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t ach t wrh t cah t asc t ach t cah t asc t ach t cah t rah t asr t crp t aa t rasp row column column column note 1 t wrp t cpa t rac t cac t aa t cpa t cac undefined don't care valid data valid data valid data open open t cwl t rch t rrh t off t clz t coh t aa t cac t clz t od t oe t oes t od t oe t oes t cas t cas t cp t cp t cp t oehc t oep ras cas a0-a11 row we dq t asc t rp t wcs t wch t wcs t wch t csh t rcd t pc t ar t ral t cas t rsh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t ach t wrh t cah t asc t ach t cah t asc t ach t cah t rah t asr t crp t rasp row column column column note 1 t wrp t dhr t dh t rwl t dh t ds t ds undefined don't care valid data valid data valid data t cwl t wcr t dh t ds t cas t cas t cp t cp t cp t cwl t cwl t wp t wp t wcs t wch t wp
edi4164mev-rp 9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edo-page-mode read-write cycle edo-page-mode read-early-write cycle note : 1. tpc is for late write cycles only ras cas a0-a11 row we dq t asc t rp t rcs t csh t rcd t pc / t prwc t ar t cas t rsh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t wrh t cah t asc t ral t cah t asc t cah t rah t asr t crp t aa t rasp row column column column note 2 t wrp t cpa t rac t cac t aa t cpa undefined don't care valid d in open open valid d out valid d in valid d out valid d in valid d out t cwl t wp t cwl t wp t rwl t awd t dh t ds t dh t ds t ds t clz t cac t clz t aa t cac t clz t od t od t oe t cas t cas t cp t cp t cp t cwd note 1 t awd t cwd t cwl t wp t awd t rwd t cwd t od t oe t dh t oe t oeh ras cas a0-a11 row we dq t asc t rp t csh t rcd t pc t pc t ar t cas t rsh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t wrh t rcs t cah t asc t ach t ral t cah t asc t cah t rah t asr t crp t aa t rasp row column (a) column (b) column (n) note 1 t wrp t cpa t rac t cac t coh undefined don't care open valid data in valid data (b) valid data (a) t rch t dh t ds t aa t cas t cas t cp t cp t cp t cws t wch t oe t whz t cac
edi4164mev-rp 10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com read cycle with we controlled disable ras - only refresh cycle t rcs ras cas a0-a11 we dq t aa t rac t cp t whz t csh t rcd t cas v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il oe t ar t wrh t rah t rad t asr t cah t asc t asc t crp t od row column column t rch t wpz t rcs note 1 valid data t wrp t clz t clz t cac t oe open open undefined don't care ras cas a0-a11 dq t rp t rc t rpc t ras v ih v il v ih v il v ih v il v oh v ol v ih v il we t wrh t rah t asr t crp row row note 1 t wrp t wrh t wrp open undefined don't care (we and oe=don't care)
edi4164mev-rp 11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com cbr refresh cycle hidden refresh cycle (we=high, oe=low) note 1 note: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high (a0-a11 and oe=don't care) ras cas dq t rp t ras t rpc t rp t ras v ih v il v ih v il v oh v ol v ih v il we t wrh t rpc t cp t csr t chr t csr t chr note 1 t wrp t wrh t wrp open undefined don't care t aa ras cas a0-a11 dq t rac t chr t ras t rp t ras t rcd t rsh v ih v il v ih v il v ih v il v oh v ol v ih v il oe t rad t rc t ar t rah t asr t cah t asc t crp t od t off row column valid data t clz t cac t oe t ord open open undefined don't care
edi4164mev-rp 12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com 50 pin plastic tsop package no. 372 package description 0.006 0.002 0.024 0.016 detail a 0.008 0.005 0.830 0.820 0.405 0.395 0.471 0.047 max 0.032 typ 0.018 0.012 see detail a 0.455 all dimensions are in inches ordering information military (-55 c to +125 c) part no. speed (ns) package no. EDI4164MEV50SM 50 372 edi4164mev60sm 60 372 edi4164mev70sm 70 372 industrial (-40 c to +85 c) part no. speed (ns) package no. edi4164mev50si 50 372 edi4164mev60si 60 372 edi4164mev70si 70 372

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