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| comtech aha corporation 2345 ne hopkins court pullman wa 99163 tel: 509.334.1000 fax: 509.334.9000 www.aha.com a subsidiary of comtech te lecommunications corporation ps4525_0204 product specification AHA4525 ieee 802.16a compliant turbo product code encoder/decoder this product is covered by a turbo code patent license from france telecom - tdf - groupe des ecoles des telecommunications. this product is covered under multiple patents he ld or licensed by comtech aha corporation.
comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 document conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.0 data and configuration input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 configuration writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 configuration reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 configuration cycle format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 decoder status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 decoder status output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 encoder and decoder - synchronous i/o - full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 encoder and decoder synchronous - half duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 bus mode - half duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 decoder bus interface, encoder synchronous interface - full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.0 encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 crc encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 tpc encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 encoder code shortening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 helical interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 internal buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.4 encoder latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 channel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.1 channel input formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 tpc decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 helical deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.2 code configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.3 decoder code shortening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.4 corrections count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.5 descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.6 crc checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.7 decoder latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.8 code performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0 phase lock loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 general output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.0 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 configuration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 user data formatting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3.1 crc and scrambler configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 code configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4.1 tpc constituent code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4.2 block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.3 buffer configuration (encoder only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.4 shortening configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.4.5 feedback (decoder only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4.6 iterations (decoder only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 channel interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.5.1 quantization (decoder only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 comtech aha corporation ii a subsidiary of comtech te lecommunications corporation ps4525_0204 7.6 data input/output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.1 transfer word size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.7.1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.7.2 status and correction count (decoder only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 7.7.3 actual iterations (decoder only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.8 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.8.1 version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 system control and miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 unencoded data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.3 encoded data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4 channel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5 decoded data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.0 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.0 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.2 absolute maximum stress ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.0 ac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.1 sysclk clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2 u_clk, e_clk, c_clk, d_clk clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3 u_wr_n, e_rd_n, c_wr_n, d_rd_n strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.4 synchronous data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.5 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.6 reset_n timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.0 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.1 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.1 available parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.2 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.0 related technical publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 appendix a: vad recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation iii list of figures figure 1: pinout .............................................................................................................. .................................. 1 figure 2: AHA4525 func tional block diagram ..................................................................................... ............. 2 figure 3: configuration cycl e followed by block 1 .............................................................................. ............. 4 figure 4: fixed configuration mode ............................................................................................. ..................... 4 figure 5: configuration example for gaps between configuration writes ....................................................... 4 figure 6: full duplex conn ection diagram ....................................................................................... ................ 6 figure 7: synchronous data/con figuration communication timi ng - start of block ......................................... 8 figure 8: synchronous data/con figuration communication ti ming - end of block .......................................... 9 figure 9: half duplex connection di agram ....................................................................................... ................ 9 figure 10: half duplex connection diagram ...................................................................................... ................. 10 figure 11: bus interface data/configurati on communication timing - start of bl ock ......................................... 12 figure 12: full duplex conn ection diagram ...................................................................................... ................. 13 figure 13: encoder block diagram ........................... .................................................................... ...................... 14 figure 14: crc encoder ......................................................................................................... ............................ 14 figure 15: 2d tpc encoded block with crc ....................................................................................... .............. 15 figure 16: scrambler ........................................................................................................... ................................ 15 figure 17: structure of shortened code ......................................................................................... .................... 16 figure 18: input block ......................................................................................................... ................................ 17 figure 19: 2d interleaving ..................................................................................................... .............................. 17 figure 20: encoded/interleaved data output ..................................................................................... ................. 17 figure 21: c_data interface .................................... ................................................................ .......................... 18 figure 22: signal timing vs. output load ....................................................................................... .................... 39 figure 23: sysclk clock timing . .................... .................... .................... .................................... ...................... 40 figure 24: clock timing ................ ........................................................................................ .............................. 41 figure 25: strobe timing ....................................... ................................................................ .............................. 41 figure 26: encoder interface data in put timing ................................................................................. ................ 42 figure 27: decoder interface data in put timing ................................................................................. ................ 43 figure 28: encoder interface data outp ut timing using chip select .............................................................. ... 44 figure 29: encoder interface data ou tput timing ................................................................................ ............... 45 figure 30: decoder interface data outp ut timing using chip select ........... ................................................... ... 46 figure 31: decoder interface data ou tput timing ................................................................................ .............. 47 figure 32: encoder bus interface data input timing ............................................................................. ............. 48 figure 33: decoder bus interface data input timing ............................................................................. ............. 49 figure 34: encoder bus interface data output timing ............................................................................ ........... 50 figure 35: decoder bus interface data output timing .. .......................................................................... ........... 50 figure 36: reset_n timing ...................................................................................................... ......................... 51 figure 37: package dimensions - top view ................. ...................................................................... ................ 52 figure 38: package dimensions - cro ss section view ............................................................................. .......... 52 figure a1: example external circuit co mponent configuration .................................................................... ...... 55 comtech aha corporation iv a subsidiary of comtech te lecommunications corporation ps4525_0204 list of tables table 1: recommended crc poly nomials ........................................................................................... ................15 table 2: partial code list and decode r datapath latency ........................................................................ ...........21 table 3: partial code list and performance - synchronous interface ............................................................. .....21 table 4: partial code list and perfor mance - bus interface ..................................................................... ............22 table 5: register bits - alphabetic al .......................................................................................... ...........................23 table 6: summary of code sh ortening rules ...................................................................................... .................29 table 7: pinout - pin number order ............................................................................................. .........................37 table 8: sysclk clock timing with pl lbypass = 0 .................. ................ ........................ ...................... .........40 table 9: sysclk clock timing with pl lbypass = 1 .................. ................ ........................ ...................... .........40 table 10: clock timing ......................................................................................................... ..................................41 table 11: strobe timing with pllbypass = 0 ................. .................. ................... ............................... .................41 table 12: encoder interface data in put timing .................................................................................. ....................42 table 13: decoder interface data input timing ....... ........................................................................... ....................43 table 14: encoder interface data output timing using chip select ............................................................... .......44 table 15: encoder interface data output timing ................................................................................ ...................45 table 16: decoder interface data output timing using chip select ............................................................... .......46 table 17: decoder interface data outp ut timing ................................................................................. ..................47 table 18: encoder bus interface data input timing .............................................................................. .................48 table 19: decoder bus interface data input timing .............................................................................. .................49 table 20: encoder bus interface data output timing ............................................................................. ...............50 table 21: decoder bus interface data output timing ............................................................................. ...............50 table 22: reset_n timing ................. .................... .................... ................ .............................. .............................51 table 23: tqfp (thin quad flat pack) 7 x 7 mm package di mensions ............................................................... .53 comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 1 of 55 1.0 introduction the AHA4525 device is a single-chip turbo product code (tpc) fo rward error correction (fec) encoder/decoder. this device integrates independent tpc encoder and decoder functions, and can be configured for full or half duplex operation. the encoder and decoder accept data and configuration through a synchronous 3-wire dsp type interface or asynchronous data bus. encoder and decoder configuration registers are written and read through th e same interface as the data. configuration registers are accessible after a reset and before the chip is enabled for data transfers. the encode datapath, after configuration for any of the ieee 802.16a btc coding options, inputs data on udata, ca lculates and inserts error correction code (ecc) bits, and outputs the data on the edata interface. the decoder datapath is the reverse of the encoder datapath. the received data is input either serially or one soft metric per transfer at the cdata interface, decoded with ecc bits removed, then output in a serial bit stream on the ddata bus. the input/output data interfaces each have a separate clock input. this coupled with an on-chip pll for the 4x internal system clock allow flexibility in the system and lower on-board clock frequencies. this device implements the same code shortening schemes defined in the ieee 802.16a standard. removing x axis rows, y axis columns, and bits from the beginning of the original message are easily programmed configuration register parameters. 1.1 features performance: ? 60 mbit/sec channel rate and 50 mbit/sec payload data rate for (64,57)x (64,57) code with 3 iterations ? s upports all ieee 802.16a btc code configurations flexibility: ? code rates from 0.25 to 0.97 ? encoded block sizes from 64 bits to 4k bits ? programmable code shortening supports exact block sizes ? programmable decoder input quantization for up to 4 bit wide soft metrics ? programmable iterations up to 255 per block ? on chip pll allows low frequency system clock channel interface: ? synchronous 3-wire input and output ports designed to be compatib le with dsp serial ports ? bus mode input and output ports designed to be compatible with a dsp bus ? chip selects on encoder and decoder ports for full or half-duplex operation ? pin selectable interface control signal polarity ? decoder supports up to 4 bit parallel soft metric input data for fast decode operation system interface: ? configuration registers are accessed through the data ports electrical: ? 3.3v i/o, 1.8v core operation ? 5v tolerant inputs ? ttl signal compatible ? 64 pin tqfp package ? commercial or industrial temperature rating figure 1: pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 48 47 46 45 44 43 42 41 40 39 38 37 36 29 28 27 26 25 24 23 22 21 20 19 18 17 52 53 54 55 56 57 58 59 60 61 62 63 64 gnd e_rdy gnd vdd e_clk vddio gndio e_data e_fs gnd vdd e_cs_n scanmode d_cs_n vdd d_fs gnd d_data gndio vddio d_clk vdd gnd d_rdy d_gout d_mode testmode tristate_n gnd vdd pll_bypass vad agnd sysclk u_data vdd gnd u_fs u_clk c_acpt gndio vddio dparinput gnd c_clk vdd c_fs rdypolarity acptpolarity c_data[3] c_data[2] vdd AHA4525a 14 15 16 35 34 33 49 50 51 32 31 30 vdd gnd reset_n e_mode vdd e_gout gnd c_data[1] c_data[0] vddio gndio u_acpt 040 ptc llllllll note: yywwd = date code; llllllll = lot number yywwd comtech aha corporation page 2 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 1.2 glossary of terms block (tpc) ? a tpc error correction block, including user data bits, crc bits, and tpc error correction bits. channel rate - the bit rate output from the encoder, or input to the decoder, in cluding all user data bits, crc bits, and tp c error correction bits. data rate - the bit rate input to the encoder, or output from the decoder, including only user data bits. this is sometim es referred to as the payload data rate. 1.3 document conventions the following are fo rmatting examples for specific document elements. ? signal or pins - electrical connections available to the system. ? register bit - bit(s) within a register. when the same register exists in both the encoder and decoder, an ? x? is used to designate both register bits, as in ecrcenable and dcrcenable . ? hex values are represented with a prefix of ?0x,? such as register ?0x00.? binary values are represented with a prefix of ?0b?. ? active low signals have ? _n ? appended to the signal name, as in e_rd_n . ? signals labelled ?= 1? are tied to vddio. signals labelled ?= 0? are tied to ground. ? ?configuration header or footer bit? - configuration header control bits are listed in quotes, as in ?last? or ?rwn?. figure 2: AHA4525 functional block diagram c_data descrambler AHA4525 decoder crc verification d_data configuration registers helical deinterleaver u_data encoder e_data i/o formatter optional helical interleaver configuration registers optional i/o formatter crc scrambler optional optional optional optional tpc tpc encoder decoder comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 3 of 55 2.0 data and configuration input/output the input/output ports of the AHA4525 chip may be configured to operate in synchronous mode or bus mode. synchronous mode signals consist of a continuous port clock, a frame sync signal, and data. bus mode signals consist of a read or write strobe and data. bus mode is selected for the encoder when pin e_mode = 1 on the rising edge of reset_n , and is selected for the decoder when pin d_mode = 1 on the rising edge of reset_n . synchronous mode is selected for the encoder when pin e_mode = 0 and for the decoder when pin d_mode = 0. the interface modes are independent. the encoder is not required to use the same interface mode as the decoder. the input port cannot be configured to use a different mode than the output port within the encoder or decoder. the interfaces into and out of the encoder and out of the decoder are always serial in either mode. the soft decision channel data into the decoder may be input symbol per transfer, up to 4 bits parallel, in either mode. the parallel channel input is selected when pin dparinput = 1 on the rising edge of reset_n . when pin dparinput = 0, the channel data is input serially. a summary of the differences between synchronous and bus interface modes is: 1)synchronous mode requires a continuous - not gated - port clock. bus mode uses a data strobe. 2)synchronous mode requires a frame sync signal to assert 1 clock before data on each block. bus mode does not require a frame sync. 3)data input and output can be faster in the synchronous mode than in bus mode. the bus mode data strobe is limited to the sysclk frequency and the synchronous port clock allows an input clock rate of 1.9* sysclk (refer to section 11.2 u_clk, e_clk, c_clk, d_clk clock timing and section 11.3 u_wr_n, e_rd_n, c_wr_n, d_rd_n strobe timing ). with the exception of the 4 bit parallel channel input to the decoder, th e encoder interface is identical to the decoder interface. the following sections describe the interface in terms of the decoder, but all control descriptions and signal timing, except where explicitly stated, apply to the encoder signals. the encoder and decoder are shown on all connection diagrams. 2.1 configuration writes the AHA4525 configuration registers are split into 2 sets of register banks: one for the encoder datapath functions and one for the decoder datapath functions. all encoder configuration registers are written through the encoder unencoded data input port. all decoder configuration registers are written through the decoder channel data input port. the configuration registers can be written before the start of a block transfer - not during a block transfer. configuration data is written in a 16 bit configuration cycle format (refer to section 2.3 configuration cycle format ). when writing configuration data to the decoder and the decoder is configured for a parallel input by setting pin dparinput = 1, the configuration data must be input 4 bits per transfer. when writing the configuration in parallel, the first of 4 data transfers expects bit 15 to be input on cdata[3] down to bit 12 input on cdata[0] . all 4 cdata inputs are always used when writing configuration data in parallel. the configuration cycle starts with a ?rwn? bit to indicate whether the cu rrent configuration cycle is a read or write cycle and is followed by the ?last? bit to indicate that the current configuration cycle is the last configuration write cycle. configuration cycles are expected to continue until a cycle is received with the ?last? bit set. if the ?last? bit is set, the AHA4525 expects data to immediately follow the current configuration cycle unless the last configuration cycle writes a one to the noblock bit (see configuration section 7.7.1 control ). an example of the configuration cycle is shown in figure 3. comtech aha corporation page 4 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 figure 3: configuration cy cle followed by block 1 figure 4: fixed configuration mode figure 5: configuration example for gaps between configuration writes the ?last? bit is followed by a 6 bit address and then 8 bits of data to be written to the specified address. refer to section 7.0 register descriptions for configuration register functions and addresses. the AHA4525 is configured for a fixed configuration mode with only 1 block code. an example of this configuration mode is shown in figure 4. if system constraints make it necessary to allow for dead time in between configuration writes you may use the configuration timing shown in figure 5. cycle 1, 2, 3 are normal configuration writes followed by a register 0x26 write. register 0x26 must have the ? last ? bit set and the xnoblock bit set. the fixed configuration mode is selected during the initial configuration following reset_n . when a 1 is written to the xnoconfig bit in the control register (refer to section 7.7.1 control ), all data blocks are received as config 0. after the chip is configured, there is no access to the configuration registers until reset_n is asserted. 2.2 configuration reads all encoder configuration read requests are written through th e encoder unencoded data input port. all decoder configuration read requests are written through the decoder channel data input port. the encoder configurati on registers can only be read when the encoder datapath is empty. the decoder configuration registers can only be read when the decoder datapath is empty. the AHA4525 has a general output pin that may be used to monitor the datapath empty status (refer to section 7.7.1 control ). all encoder configuratio n registers are read from the encoder encoded data output port. all decoder configuration registers are read from the decoder decoded data output port. a configuration data read request is written in a 16 bit configuration cycle format (refer to section 2.3 configuration cycle format ). the configuration cycle starts with a ?rwn? bit to indicate whether the current configuration cycle is a read or write cycle. when the ?rwn? bit is set, the configuration cycle is a read request and it is by default the last configuratio n cycle. the ?last? bit is irrelevant in a configuration read because each read must wait for the read data to be output before a new read can be requested. data cannot directly follow a read configuration request. the ?last? bit is followed by a 6 bit address to specify which register to read. the 8 bits of data that follow the address field of the configuration read cycle are don?t cares, but they must be input to finish the configuration cycle (refer to section 7.0 register descriptions for configuration register functions and addresses). c_data, u_data c_fs, u_fs cycle 1 cycle 2 cycle 3 last cycle block 1 cycle 1 cycle 2 cycle 3 cycle 4 last c_data, u_data c_fs, u_fs block 1 block 2 block 3 c_acpt, v_acpt data fs cycle 2 reg 26 acpt cycle 1 reg 26 cycle 3 reg 26 last bit set no block set comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 5 of 55 2.3 configuration cycle format bit 15 is input first, bit 0 is input last. ?rwn? - read/write_not. when ?rwn? = 1, the configur ation cycle is a read cycle. when ?rwn? = 0, the configuration cycle is a write cycle. ?last? - last configuration cycle. when set, the cu rrent configuration cycle is the last configuration cycle before data begins. when cleared, the current configur ation cycle will be followed by another configuration cycle. ?a[5:0]? - configuration address. addres s of configuration read or write. ?d[7:0]? - configuration data. when ?rwn? = 0, this is the data to be written to the addressed configuration register. when ?rwn? = 1, th is data is a don?t care. 2.4 decoder status output the AHA4525 has the option to output status information with each decoded block. there is no option to output any status information with encoded blocks. the status of a decoded block is output as 16 bits at the end of every decoded block when the dstatus configuration bit is set to 1 (see section 7.7.1 control ). the structure of the status output is shown in section 2.5 decoder status output format . the status is output in serial, msb first. the status includes a parity error flag ?perr? which is asserted when the crc is enabled and the output block failed the crc verification. the last status information is the number of corrections ?c[11:0]?. this is a count of the number of bit errors corrected in the current block, including user data, inserted crc bits, and ecc bits. 2.5 decoder status output format bit 15 is output first, bit 0 is output last. ?perr? - parity error. asserted when crc is enabled and the output block failed the crc verification. ?c[11:0]? - correction count. the number of bit errors corre cted in the current block including user data, inserted crc bits, and ecc bits. bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rwn last a[5] a[4] a[3] a[2] a[1] a[0] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 res perr c[11] c[10] c[9] c[8] c[7] c[ 6] c[5] c[4] c[3] c[2] c[1] c[0] comtech aha corporation page 6 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 2.6 encoder and decoder - synchronous i/o - full duplex an AHA4525 synchronous interface full duplex connection diagram is shown in figure 6. data blocks and configura tion information are input through the u_data port when encoding or the c_data port when decoding. the soft decision channe l data into the decoder is serially input when dparinput = 0 on the rising edge of reset_n , which reduces the input rate by up to a factor of 4 when a 4 bit soft metric is used. the channel input port may be configured to allow 4 bit para llel input on c_data when dparinput = 1 on the rising edge of reset_n . when dparinput = 1, the c_data port is configured in parallel m ode and the configuration data is expected to be re ceived in 4 bit parallel. when dparinput = 0, the c_data port resets into serial mode and expects to receive configuration data serially. the synchronous interface timing for the decoder signals is shown in figures 7 and 8. the signal timing for the encoder is similar. a data or configuration write is started when c_fs is asserted for one c_clk cycle. the c_fs signal is a sync signal that is asserted once for every block when the dwordeqblk configuration bit is set to 1 or asserted once for every word when the dwordeqblk configuration bit is set to 0 (see section 7.6.1 transfer word size ). the word size is configured using the dwordsize[4:0] register also shown in section 7.6.1 transfer word size . the dwordsize[4:0] register resets to 16 bits per word. figure 27 shows the inpu t timing requirements for c_fs . figure 6: full duplex connection diagram AHA4525 e_cs_n u_data d_cs_n clkx dx fsx clkr dr fsr u_fs serial i/f u_clk (u_wr_n) e_data e_fs e_clk (e_rd_n) c_data c_fs c_clk (c_wr_n) d_data d_fs d_clk (d_rd_n) clkx dx fsx clkr dr fsr synchronous port 0 synchronous port 1 e_rdy d_rdy d_mode e_mode u_acpt c_acpt gnd gnd encoder decoder dparinput gnd comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 7 of 55 all AHA4525 configuration is done immediately following the first c_fs of a block and the interface remains in the configuration mode until a configuration cycle is input with the ?last? bit set. the structure of a configuration cycle is shown in section 2.3 configuration cycle format and in the timing diagram figure 7 in the c_data input data stream. in figure 7, a[3:0] and b[3:0] following the configuration cycle indicate the start of the data block where a is a 4 bit soft metric and b is a 4 bit soft metric. if the configuration cycle is a read request, the read data is available on d_data on the d_clk cycle following when the d_fs output signal is asserted for one d_clk cycle. data cannot follow a configuration read and decoder configuration reads are only allowed when the de coder datapath is empty. the read data must be read from the d_data port before another configuration cycle is started. the d_fs signal timing is shown in figures 7 and 8 and the electrical char acteristics are shown in figure 30. d_fs asserts to indicate that the block is finished processing and the output data will start on the next d_clk cycle. the d_fs signal is a sync signal that is asserted once for every block when the dwordeqblk configuration bit is set to 1 or asserted once for every word when the dwordeqblk configuration bit is set to 0 (see section 7.6.1 transfer word size ). the word size is configured using the dwordsize[4:0] register also shown in section 7.6.1 transfer word size . the dwordsize[4:0] register resets to 16 bits per word. the output data is read serially through the d_data port. d_rdy asserts with the d_fs at the start of a block and stays asserted until the last data, including block status, is clocked out of the decoder (see figures 7 and 8). note that the encoder does not output a block status footer. d_rdy is not required for systems where the receive port is set up to expect a certain output block size, but it may be used in systems that do not count the bits in the received block. c_acpt asserts when the input buffer is ready to accept a block and is deasserted after the data portion of the block transfer is started or a configuration read is started (see figures 7 and 8). this signal may be used to allow the decoder to process more than one block at a time. c_acpt is not required for systems that process one block at a time (i.e. the first block is input, processed, and output before a second block is input). the synchronous interfa ce requires continuous port clocks c_clk and d_clk . gated port clocks are not allowed. the continuous d_clk automatically fills any padding required by a serial receive port. the following timing diagrams figure 7 and figure 8 show a block input and output through the decoder in serial mode ( dparinput = 0). the c_fs and d_fs signals shown in the following diagrams are shown assuming dwordeqblk is set. comtech aha corporation page 8 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 figure 7: synchronous data/c onfiguration communication timing - start of block d_data (output) d_fs (output) d_clk (input) d_rdy (output) start of block c_data (input) c_fs (input) c_clk (input) c_acpt (output) d_data (output) d_fs (output) d_clk (input) d_rdy (output) start of block - configuration read configuration read configuration write a b c d e f g h i j k l m n o p q r s t u v w x rwn last a[5] rwn a[5] a[4] last a[4] a[3] a[2] a[1] a[0] r[1] r[7] a r[6] r[5] r[4] r[3] r[2] r[0] b c d e f g h xx c_data is a don?t care on read decoded start of block - output data (after decoder latency) output configuration read data xx xx xx xx xx xx xx decoded data next block data read data y a[3] i c_data (input) rwn last d[7] a[5] c_fs (input) a[3] a[2] a[0] b[3] b[1] b[0] b[2] c_clk (input) a[4] a[3] a[2] a[1] a[0] d[6] d[5] d[4] d[3] d[2] d[1] d[0] c_acpt (output) a[1] configuration cycle channel data c[3] comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 9 of 55 figure 8: synchronous data/c onfiguration communication timing - end of block 2.7 encoder and decoder sy nchronous - half duplex this interface is the same as the full duplex synchronous mode except the e_cs_n and d_cs_n inputs are used to switch between the encoder and decoder. figure 9: half duplex connection diagram c_data (input) c_fs (input) c_clk (input) c_acpt (output) d_data (output) d_fs (output) d_clk (input) d_rdy (output) end of block write z[3] a[3] a[2] a[1] b[3] b[2] b[1] z[2] z[1] z[0] xs[3] s[2] s[1] s[4] s[5] s[0] a b y z s[15] s[6] s[7] s[8] s[9] s[10] s[11] s[12] s[13] s[14] data end next block channel data block status data start data end decoded end of block output data next block c[3] c c[2] c[1] e_cs_n u_data u_acpt d_cs_n gout[1:0] clkx dx fsx clkr dr fsr u_fs u_clk (u_wr_n) e_data e_fs e_clk (e_rd_n) e_rdy c_data c_acpt c_fs c_clk (c_wr_n) d_data d_fs d_clk (d_rd_n) d_rdy synchronous port 0 AHA4525 encoder decoder d_mode e_mode gnd dparinput comtech aha corporation page 10 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 the differences in the communication timing between the full duplex and half duplex synchronous configuratio ns are the tristated d_fs and d_data outputs when the decoder d_cs_n is not asserted, and the tristated e_fs and e_data outputs when the encoder e_cs_n is not asserted. refer to the full duplex synchronous configuration section 2.6 encoder and decoder - synchronous i/ o - full duplex for communication timing diagrams. 2.8 bus mode - half duplex the AHA4525 bus interface half duplex connection diagram is shown in figure 10. the bus interface is selected for the encoder when e_mode = 1 and is selected for the decoder when d_mode = 1. data blocks and configuration information are in put through the u_data port when encoding or the c_data port when decoding. the bus mode interface allows a 4 bit parallel channel input through the c_data port to allow soft metrics to be written to the decoder at a rate of one symbol per transfer. the interfaces to d_data , u_data , and e_data are serial. when bus mode is selected at reset, the status of the dparinput pin determines if the c_data port is configured in serial or 4 bit parallel mode. when dparinput = 1 at reset, the c_data port is configured in 4 bit parallel mode and the first configuration cycle is expected to be received in 4 bit parallel. figure 10: half duplex connection diagram AHA4525 e_cs_n u_data u_acpt d_cs_n cs, addr data[3:0] wr_n rd_n u_fs bus i/f u_clk (u_wr_n) e_data e_fs e_clk (e_rd_n) e_rdy c_data[3:0] c_acpt c_fs c_clk (c_wr_n) d_data d_fs d_clk (d_rd_n) d_rdy int0 int1 d_mode e_mode int2 int3 vddio encoder decoder dparinput comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 11 of 55 the bus interface timing for the decoder signals is shown in figure 11. the signal timing for the encoder is typical. a data or configuration write cycle is started when c_wr_n is asserted low. there is no block start signal in bus mode. the c_wr_n signal is a write strobe signal, with data being registered on the rising edge (see figure 33). all configuration is done immediately following reset. the AHA4525 counts the number of input data bits and compares the input count to the dblocksize configuration setting (see section 7.4.2 block size ) to find the end of an input block. the interface remains in the configuration mode until a configuration cycle is input with the ?last? bit set. the structure of a configuration cycle is shown in section 2.3 configuration cycle format . the configuration cycle is shown as c[3:0] in figure 11 in the c_data input stream. note that the encoder does not have the parallel input option and all configuration bits mu st be input serially. the first 16 bits (4 writes) in the c_data stream are configuration write bits with bits (15:11) written first and bits (3:0) written last. the configuration starts with a ?rwn? (read/write_not) bit and is followed by a ?last? bit which indicates that the current configuration cycle is the last configuration cycle. the ?last? bit is followed by a 6 bit address a[5:0] and then the data d[ 7:0] to be written to the address. the AHA4525 expects data to immediately follow the last configuration write cycle unless the last configuration cycl e writes a one to the noblock bit (see configuration section 7.7.1 control ). a and b following the configurati on cycle indicate the start of the data block where a is a 4 bit soft metric and b is a 4 bit soft metric. if the configuration cycle is a read request, the read data is available on d_data when d_rdy is asserted. the configuration data is read when d_rd_n is asserted low and the data is valid until the d_rd_n rising edge (see figure 35). data cannot follow a configura tion read and decoder configuration reads are only allowed when the decoder datapath is empty. each configuration read is considered a last config uration cycle similar to a last configuration write cycle with the noblock bit set. the read data must be read from the d_data port before another configuration cycle is started. d_rdy asserts when valid data is available to be read at the output and stays asserted until the last data, including block status, is strobed out of the decoder (see figure 11). d_rdy can be monitored to know when to start an output read, or the output can be read after decoder block latency number of sysclk s. the decoder latency calculations are shown in section 4.2.7 decoder latency . any d_rd_n strobes beyond the end of a block are ignored until the d_rdy signal is asserted. c_acpt asserts when the input buffer is ready to accept a block and deasserts after the data portion of the block transfer is started or a configuration read is started (see figure 11). this signal may be used to allow the decoder to process more than one block at a time. c_acpt is not required for systems that process one block at a time (i.e. the first block is input, processed , and output before a second block is input). the status of the decoded block is output in 16 bits at the end of every decoded block when the dstatus configuration bit is set to 1 (see control section 7.7.1 control ). the structure of the status output is shown in section 2.5 decoder status output format and partially in the timing diagram figure 11 in the d_data output data stream as s[8:0] (s[15:9] are not shown). there is not an option to output status information at the end of encoded blocks. in bus mode, the AHA4525 is a slave to the system. the c_wr_n and d_rd_n signals are both inputs to AHA4525. blocks do not need to be read or written in a contin uous stream in bus mode. the signal differences between synchronous mode and bus mode are: a) the c_clk and u_clk inputs become c_wr_n and u_wr_n in bus mode, b) the d_clk and e_clk inputs become d_rd_n and e_rd_n inputs in bus mode, c) the d_data bus is tristated when d_rd_n is not asserted, and d) the e_data bus is tristated when e_rd_n is not asserted. comtech aha corporation page 12 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 figure 11: bus interface data /configuration communication timing - start of block start of block - configuration write start of block - configuration read configuration read data d_data (output) d_rd_n (input) d_rdy (output) c_data (input) c_wr_n (input) c_acpt (output) d_data (output) d_rd_n (input) d_rdy (output) c_data (input) c_wr_n (input) c_acpt (output) end of block write d_data (output) d_rd_n (input) d_rdy (output) a b c d e f g h i j k l c[3] c[2] c[1] c[0] c[3] c[2] c[1] r[7] r[6] r[5] r[4] r[3] r[2] r[1] r[0] a b c x z a y b s[7] s[6] s[5] s[4] s[3] s[2] s[1] s[0] a b s[8] decoded start of block output data (after decoder latency) output configuration read data decoded end of block output data decoded data configuration configuration next data block data end data status footer next block c c[0] d e f c[3] c[2] c[1] c[0] a b c d e f g configuration data h c_data (input) c_wr_n (input) c_acpt (output) comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 13 of 55 2.9 decoder bus interface, encode r synchronous interface - full duplex the full duplex connection diagram shown in figure 12 is used to sh ow the flexibility of the AHA4525 interface. the decoder uses the bus connection with a 4 bit pa rallel channel input while the encoder uses the synchronous port. in this configuration, the c_acpt output is used to signal that the c_data input is ready to accept data. the AHA4525 decoder resets into 4 bit parallel mode when dparinput = 1, so the first decoder configuration write must be done in 4 bit parallel. figure 12: full duplex connection diagram AHA4525 e_cs_n u_data u_acpt d_cs_n clkx dx fsx clkr dr fsr u_fs u_clk (u_wr_n) e_data e_fs e_clk (e_rd_n) c_data c_acpt c_fs c_clk (c_wr_n) d_data d_fs d_clk (d_rd_n) data[3:0] wr_n synchronous port 0 bus i/f e_rdy d_rdy cs, addr int0 int1 d_mode e_mode rd_n gnd vddio gnd encoder decoder dparinput comtech aha corporation page 14 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 3.0 encoder figure 13: encoder block diagram figure 13 shows a block diagram of the encode path. note that all of the blocks in the encode path except the helical interl eaver operate by only inserting or modifying data in the stream. therefore, the entire encode path has low latency. data is input serially through u_data . the crc engine computes a crc over each block of data which is inserted at the end of the uncoded data block. this data is scra mbled by exclusive-oring with the output of a pseudo random binary sequence (prbs) generator. the scrambler ensures adequate bit transitions in the data stream, which are often required to allow improved dc balance and to accelerate clock recovery in the demodulator. the scrambled data is input to a tpc encoder, which computes ecc bits and inserts them at the appropriate locations in the data stream. the helical interleaver improves burst error performance of the decoder. however, it adds a one block latency to the datapa th. the encoded block is serially output through e_data . 3.1 crc encoder the cyclic redundancy check (crc) encoder is a 32 bit linear feedback shift register with a programmable polynomial. figure 14 shows a diagram of the shift register. each tpc block has a separate crc encoded with the resultant crc bits appended to the block. the polynomial for th e crc encoder is written into the ecrcpoly register. the highest order of the polynomial (defined by ecrcsize ) is assumed to be a 1, and bit 0 of the polynomial register corresponds to the 0th or der of the polynomial, as shown in figure 14. the d esired size of the crc, in bits, is written into the ecrcsize register. table 1 gives a suggested list of polynomials for various length crcs. the poly column of table 1 gives the value to program into the ecrcpoly register. the detection ca pability column gives the probability that an incorrect block will be detected and flagged as incorrect by the crc decoder. figure 14: crc encoder crc encoder scrambler tpc user data u_data prbs helical interleaver encoder encoded data e_data user data ecrcpoly[0:ecrcsize-1] shift direction crc output comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 15 of 55 table 1: recommended crc polynomials notes: * the leading ?1? in these values is assumed by the device and should not be written to the register. ** this detection capability is the probability that an incorrect block is marked in error. the probability of an undetected block is computed by multiplying the block error rate by (1 - detection capability). the shift register is reset to all 0s at the beginning of each tpc block. data from the block is shifted into the circu it until the number of bits programmed into eblksize is reached. note that the value written into eblksize does not include the crc bits. after the entire tp c block is shifted into the crc encoder, the data in put and feedback of the crc shifter are disabled, an d the contents of the crc registers are shifted ou t and inserted into the data stream. figure 15 shows the location of the crc word inserted in a 2d tpc encoded block. d denotes data bits and e denotes computed error correction bits. figure 15: 2d tpc encoded block with crc 3.2 scrambler the scrambler is built with a 16 bit pseudo-random binary sequence generator with programmable polynomial, length, and ini tialization seed. figure 16 shows the configuration of the scrambler. the shift register is clocked once fo r each bit. as shown in figure 16, the output of the shift register is exclusive- ored with the data to be scrambled. figure 16 shows an example configuration for the generator polynomial sequence: this sequence is programmed into the escrampoly register as 0b0110000000000000. the seed for the shift register that is shown in the diagram is programmed into escramseed as 0b0000000010101001. every time the scrambler is reset it is initialized with this seed value. figure 16: scrambler crc size (bits) poly program value (hex)* detection capability** 4 4 1f 0.9375 8 8 1d5 0.99609 12 12 180f 0.999756 ansi 16 18005 0.999985 ccitt 16 11021 0.999985 sdlc 16 1a097 0.999985 24 24 1805101 0.9999999404 32a 32 1404098e2 0.99999999953 32b 32 104c11db7 0.99999999977 dd de e dd d ee dd e crc e ee 1 x 14 x 15 ++ 1 2 3 4 5 6 7 8 9 10111213141516 data input data output escrampoly[0:15] 10010 10100000000 escramseed[0:15] shift direction comtech aha corporation page 16 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 note that the length of th e generator is directly determined by the polynomial configuration. the sequence shown here is generated by a 15 stage shift register. since the highest order of the polynomial is 15, the 16th bit xor feedba ck will be disabled and only 15 bits of the shift register are used. also note that the 0th order of the polynomial is assumed to be 1. the scrambler is reset at the beginning of every tpc block. 3.3 tpc encoder the tpc encoder supports 2d codes with constituent code lengths of up to 64 bits and overall block size up to 4096 bits. the encoder supports both extended hamming and parity only constituent codes. see section 7.4.1 tpc constituent code for a description of supported codes and shortening configurations. 3.3.1 encoder code shortening there are two methods of shortening product codes. the first method is to remove an entire row or column from a 2d code. this is equivalent to shortening the constituent codes that make up the product code and is acco mplished by writing the amount to shorten into the xshortx and xshorty registers (see section 7.4.4 shortening configuration ). this method enables a coarse granularity on shortening and at the same time maintaining the highest code rate possible by removing both data and parity symbols. further shortening is obtained by removing individual bits from the first row of a 2d code (using xshortb ). the following examples discuss shortening in a 2d code. assume a 456 bit block size is required with code rate of approx imately 0.6. the base code chosen before shortening is the (32,26)x(32,26) code which has a data size of 676 bits. shortening all rows by 5 and all colu mns by 4 results in a (27,21)x(28,22) code with a data size of 462 bits. to get the exact block size, th e first row of the product is shortened by an addition 6 bits. the final code is a (750,456) code with a code rate of 0.608. figure 17 shows the structure of the resultant block. this shortening is programed in to the device by writing xshortx to 5, xshorty to 4, and xshortb to 6. figure 17: structure of shortened code 3.3.2 helical interleaver helical interleaving transmits data in a helical fashion. when the channel introduces a burst of errors, the helical deinterl eaver in the decoder will spread these errors across all axes of the code. the use of helical interleaving increases the burst error correcting capability of th e code and increases the block latency (refer to section 3.3.4 encoder latency ). the helical interleave r is enabled by setting ehelical to one (see section 7.4.1 tpc constituent code ). when helical interleaving is enabled, the eshortx and eshortb values must be set to 0 (see section 7.4.4 shortening configuration ). this constrains the shortening resolution to one row for 2d codes. all of the blocks in the encode datapath must be either interleaved or not interleaved. a mixture of interleaving blocks and non-interleaving blocks in the encoder data path at the same time is not allowed. helical interleaving is applied along a diagonal path through the encoded block. data is output along diagonal lines from the upper left to lower right corner. the first diagon al output starts with the bit row 1, column 1 followed by the diagonal starting at row 1, column 2. shorten 6 additional bits unshortened block data bits ecc bits 28 bits 6 bits 26 bits 27 bits 26 bits 6 bits comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 17 of 55 the example below shows how interleaving is applied for a 2d (64,57)x(64,57) code. figure 18: input block note: the number reflects the bit order including generated ecc bits. the encoded, interleaved data output is taken along diagonal lines starting with bit zero as shown below. the order of the in terleaving is noted for each diagonal line. figure 19: 2d interleaving for the (64,57)x(64,57) bl ock, the data output is: 0, 65, 130,..., 4095, 1, 66,..., 4031, 4032, 2, 67,...,..., 63, 64,..., 4094 for a total of 4096 bits output. the AHA4525 operating as a decoder deinterleaves the block to restore it to its original order. figure 20: encoded/interleaved data output data bits are output from the encoder in row order from left to right. 3.3.3 internal buffering an internal encoder buffer is used to allow data to stream into and out of AHA4525. the encoder buffer is always enabled because the data flow into the encoder is not throt tled by AHA4525 in either bus mode or synchronous mode. the logical size of the encoder input buffer is set via ebuffersize (refer to section 7.4.3 buffer configuration (encoder only) for an equation to calculate ebuffersize ). 3.3.4 encoder latency the encoder latency is defined as the time from wh en the first un-encoded bit is input until the e_rdy signal is asserted to indicate that a block is ready to be output. when helical in terleaving is disabled and e_mode = 0, the approximate encoder latency in sysclk s when pllbypass = 0 is: when helical interleaving is disabled and e_mode = 1, the approximate encoder latency in sysclk s is: the ebuffersize input buffer is used to guaran tee a streaming input and output. 0123 63 64 65 66 67 127 128 129 191 192 193 4032 4033 4095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 . . . . . . . . . 0123 63 64 65 66 67 127 128 129 1 191 192 193 4032 4033 4095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 . . . . . . . . . 24 126 127 3 0 65 130 . . . 4095 1 66 131 . . . 4032 267 4033 368 63 64 4094 4030 4029 . . . 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4031 . . . 3968 ebuffersize 16 () 31 + 2 ------------------------------------------------------------ 2 sysclk (mhz) u _clk (mhz) ----------------------------------------- - ?? ?? 2 sysclk (mhz) e_clk (mhz) ----------------------------------------- - ?? ?? + + ebuffersize 16 () 36 + 2 ------------------------------------------------------------ comtech aha corporation page 18 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 helical interleaving adds one block of latency. when helical interleaving is en abled, the encoder input buffer is not used. the worst case encoder latency in sysclk s when helical interl eaving is enabled and e_mode = 0 is: when helical interlea ving is enabled and e_mode = 1, the worst case encoder latency in sysclk s is: if the pll is bypassed ( pllbypass = 1), then the latency result in sysclk s must be multiplied by 4. 4.0 decoder the decode path of AHA4525 includes a counterpart for each encoder module. the encoder and decoder are isolated paths. this allows full duplex operation where the encoder and decoder may be operating with different code types and data rates. 4.1 channel interface the channel interface formats the channel data for decoding by the turbo product code decoder. for best decoder performance, soft metric information from the channel is necessary. 4.1.1 channel in put formatting when decoding, data may be input either serially or one quantization value per handshake on c_data[q-1:0] where q is the number of input quantization bits. the number of quantization bits is configurable based on the setting of qbit[1:0] within the quantization regi ster in section 7.5.1. the qmode[1:0] bits within the quantization register determine the type of input data. the input data may be 2?s complement, sign/magnitude, or unsigned. all unused c_data inputs are ignored except in configuration cycles. note that all c_data[3:0] inputs are used for configuration cycles in parallel mode. in parallel configuration cycles, configuration bits (15:11) are written first with configuration bit 15 input on c_data[3] . in parallel data cycles, the lsb of the soft metric value is input on c_data[0] and the msb is determined by qbits[1:0] . figure 21 shows example connections when qbits[1:0] = ?11? (3 input bits). figure 21: c_data interface 4.2 tpc decoder the turbo product code decoder supports block sizes up to 4096 encoded bits. the decoder supports iterative decoding of 2d codes built from extended hamming or par ity only constituent codes of length up to 64 bits. 4.2.1 helical deinterleaver the helical deinterleaver is enabled by setting dhelical to 1 in the configuration register shown in section 7.4.1 tpc constituent code . see section 3.3.2 for a description of helical interleaving. 4.2.2 code configuration turbo product codes are specified by the constituent codes of each ax is in the code. the code configuration registers in section 7.4.1 tpc constituent code specify the code type (extended hamming or parity) and length of each axis. to generate a specific block size, the product code is shortened. shorte ning is discussed in detail in section 4.2.3. the decoder can be configured to run a specific number of iterations by programming the number of iterations in the configuration register shown in section 7.4.6 iterations (decoder only) . the decoder can be set to detect when a block converges and stop iterating. this a llows the decoder to spend more time, up to the number of iterations specified in iterations , on difficult blocks and less time on 1 encoded block size sysclk (mhz) u_clk (mhz) ----------------------------------------- - ?? ?? 2 sysclk (mhz) u_clk (mhz) ----------------------------------------- - ?? ?? 24 2 sysclk (mhz) e_clk (mhz) ----------------------------------------- - ?? ?? ++ + 1 encoded block size sysclk (mhz) u_clk (mhz) ----------------------------------------- - ?? ?? 26 + for qbits = ?11? connect c_data as shown c_data[1] c_data[0] - lsb c_data[1] c_data[0] AHA4525 c_data[3] c_data[2] - msb c_data[2] comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 19 of 55 less difficult blocks. this feature is enabled by setting stopiter in the configuration register shown in section 7.4.5 feedback (decoder only) . 4.2.3 decoder code shortening refer to section 3.3.1 encoder code shortening . 4.2.4 corrections count in order to assist the system with estimation of channel bit error rates, the AHA4525 device reports the number of bits correct ed in each block decoded. the corrections register (see section 7.7.2 status and correction count (decoder only) ) contains the number of corrections between incoming (channel) data and outgoing (decoded) data. this corrections valu e is the corrections done on all bits in the tpc bl ock including user data, crc, and tpc ecc bits. the correction count is updated in the corrections register after each block is decoded and is also optio nally output at the end of every block as a status footer (see section 2.5 decoder status output format ). 4.2.5 descrambler the descrambler is built with a 16 bit pseudo- random binary sequence generator with programmable polynomial, length, and initialization seed. the de scrambler logic matches that of the scrambler shown in figure 16 (refer to section 3.2). the generator polynomial sequence is programmed into the dscrampoly register. the seed for the shift register shown in figure 16 is programmed into dscramseed . every time the descrambler is reset, it initializes to the dscramseed value. the descramb ler is reset at the start of every block. 4.2.6 crc checking the crc parity bits are checked after decoding. each packet has a separate crc with variable length up to 32 bits. th e crc comparator circuit matches that of the encoder shown in figure 14. the shift register is reset at the beginning of each tpc block. data from the tpc block is shifted into the circuit until the number of bits programmed into dblksize is reached. at this point, the contents of the crc shift register ar e examined. if all bits are 0, then the crc is corre ct. otherwise, a crc error is detected and the crcerr status flag is set in the decoder status footer (see section 2.5 decoder status output format ). the crcerr flag can also be read from the status register shown in section 7.7.2 status and correction count (decoder only) . comtech aha corporation page 20 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 4.2.7 decoder latency the decoder latency is defined as the time from when the last channel bit is input until the d_rdy signal is asserted to indicate that a block is re ady to be output. in th e following equations, dcodex is dcodex[2:0] , dcodey is dcodey[2:0] . the approximate decoder latency in sysclk s when pllbypass = 0 is: if dcodex is not 0, if dcodex = 0, x_latency = 0. if dcodey is not 0, if dcodey = 0, y_latency = 0. when d_mode = 1, when d_mode = 0, if the pll is bypassed ( pllbypass = 1), then the latency result in sysclk s must be multiplied by 4. table 2 gives an abridged list of possible codes supported by AHA4525, along with the latency in sysclk s for 4, 6, and 12 iterations with the crc di sabled. this table applies to a synchronous ( d_mode = 0) port configuration with the internal pll enabled ( pllbypass = 0) and assumes that the frequency of c_clk = sysclk . this is a very small subset of supporte d codes. comtech aha corporation (cac) can provide software to assist the code selection process. x_latency 2 dcodex 2 dcodey dshorty ? () 4 ------------------------------------------------------------------------------ =2 dcodex 16 ++ y _latency 2 dcodey 2 dcodex dshortx ? () 4 ------------------------------------------------------------------------------ =2 dcodey 16 ++ iter_clocks x_latency y_latency + () iterations = latency 29 iter_clocks 2 ------------------------- - dshortb 4 ---------------------- ++ = latency 2 sysclk (mhz) c_clk (mhz) --------------------------------------------------- 2 7 2 sysclk (mhz) d_clk (mhz) --------------------------------------------------- iter_clocks 2 ------------------------- - dshortb 4 ---------------------- ++ + + = comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 21 of 55 table 2: partial code list and decoder datapath latency * the number of sysclk s is assuming the pll is enabled (pllbypass=0) and is accurate to within 2%. if the pll is not enabled (pllbypass=1), then the late ncy in sysclks must be multiplied by 4. table 3: partial code list and performance - synchronous interface * the input and output rates assume a 50 mhz sysclk frequency when the pll is enabled or a 200 mhz sysclk frequency when the pll is bypassed. the port clocks c_clk and d_clk are assumed to be running at 95 mhz. code (x)x(y)x(z) block size (bits) data size (bits) 4 iterations (sysclks)* 6 iterations (sysclks)* 12 iterations (sysclks)* (64,63)x(64,63) 4096 3969 4445 6665 13277 (64,57)x(64,57) 4096 3249 4445 6653 13277 (32,31)x(32,31) 1024 961 1245 1853 3677 (32,26)(x(32,26) 1024 676 1245 1853 3677 (64,57)x(32,26) 2048 1482 2333 3485 6941 (64,57)x(64,63) 4096 3591 4445 6665 13277 (64,57)x(32,31) 2048 1767 2333 3485 6941 (32,26)x(16,11) 512 286 701 1037 2045 (32,26)x(16,15) 512 390 701 1037 2045 code (x)x(y)x(z) block size (bits) data size (bits) code rate 6 iter coding gain (db) 4 iter channel/ data* (avg mbit/sec) 6 iter channel/ data* (avg mbit/sec) 12 iter channel/ data* (avg mbit/sec) (64,63)x(64,63) 4096 3969 0.969 3.2 46.4/45.0 31.0/30.0 15.5/15.0 (64,57)x(64,57) 4096 3249 0.793 7.3 46.4/36.9 31.0/24.5 15.5/12.3 (32,31)x(32,31) 1024 961 0.938 3.2 42.3/39.6 28.1/26.4 14.1/13.3 (32,26)x(32,26) 1024 676 0.660 7.2 42.3/27.9 28.1/18.6 14.1/9.3 (64,57)(x(32,26) 2048 1482 0.724 7.2 44.5/32.3 29.6/21.5 14.9/10.8 (64,57)x(64,63) 4096 3591 0.877 5.4 46.4/40.8 31.0/27.1 15.5/13.6 (64,57)x(32,31) 2048 1767 0.863 5.4 44.5/38.4 29.6/25.6 14.9/12.8 (32,26)x(16,11) 512 286 0.559 6.8 38.4/21.4 25.5/14.3 12.8/7.1 (32,26)x(16,15) 512 390 0.762 5.4 38.4/29.3 25.5/19.5 12.8/9.8 comtech aha corporation page 22 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 table 4: partial code list a nd performance - bus interface * the input and output rates assume a 50 mhz sysclk fr equency when the pll is enabled or a 200 mhz sysclk frequency when the pll is bypassed. the read and write strobes c_wr_n and d_rd_n are assumed to be running at 50 mhz. 4.2.8 code performance tables 3 and 4 give code rate, coding gain, and maximum channel and user (decoded) data rates for the same abridged list of possible codes that was shown in table 2. the data rate calculations assume that the frequency of sysclk is 50 mhz. the coding gain is measured on a binary input additive white gaussian noise (awgn) channel at 10 -6 bit error rate (ber) and 6 it erations. cac can provide software to assist in code ber performance analysis. 5.0 phase lock loop the AHA4525 contains an internal pll which is used to multiply the input sysclk frequency by 4 for internal clocking. the internal pll has a minimum input sysclk frequency of 20 mhz and a maximum input sysclk frequency of 50 mhz (see section 11.1 sysclk clock timing ). the pll can not lock to fre quencies below 20 mhz. the internal pll is enabled when pin pllbypass = 0. if pllbypass = 1, the internal pll is bypassed and the input sysclk directly drives the internal logic. when the pll is bypassed, the latency and throughput are reduced by a factor of 4 given the same input sysclk frequency. the throughput and latency are identical when the pll is bypassed and a 4x sysclk frequency is used when compared to the throughput and latency when the pll is enabled and a 1x sysclk frequency is used (refer to section 3.3.4 encoder latency and section 4.2.7 decoder latency ). 6.0 general output signals the AHA4525 contains a general output signal for the encoder and a general output signal for the decoder that can be used to control external logic or for system debugging. the signals can be driven to a 1 or 0 or can be driven according to events within the device including lo ad complete, decode complete, empty, etc. (see section 7.7.1 for a complete list of available status outputs). code (x)x(y)x(z) block size (bits) data size (bits) code rate 6 iter coding gain (db) 4 iter channel/ data* (avg mbit/sec) 6 iter channel/ data* (avg mbit/sec) 12 iter channel/ data* (avg mbit/sec) (64,63)x(64,63) 4096 3969 0.969 3.2 44.3/43.0 29.6/28.6 14.9/14.4 (64,57)x(64,57) 4096 3249 0.793 7.3 44.3/35.3 29.6/23.4 14.9/11.8 (32,31)x(32,31) 1024 961 0.938 3.2 40.4/37.9 26.9/25.3 13.5/12.6 (32,26)x(32,26) 1024 676 0.660 7.2 40.0/26.3 26.9/17.8 13.5/8.9 (64,57)x(32,26) 2048 1482 0.724 7.2 42.5/30.8 28.3/20.5 14.3/10.3 (64,57)x(64,63) 4096 3591 0.877 5.4 44.3/38.9 29.6/25.9 14.9/13.0 (64,57)x(32,31) 2048 1767 0.863 5.4 42.5/36.6 28.3/24.5 14.3/12.1 (32,26)x(16,11) 512 286 0.559 6.8 36.6/20.4 24.4/13.6 12.1/6.8 (32,26)x(16,15) 512 390 0.762 5.4 36.6/28.0 24.4/18.6 12.1/9.3 comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 23 of 55 7.0 register descriptions 7.1 configuration sequence the following sequence should be followed when configuring the device. the encoder and decoder configuration sequences are identical. the following configuration se quence is described in terms of the decoder, bu t all descriptions, except where explicitly stated, apply to the encoder. the decoder is reset when reset_n = 0. after the rising edge of reset_n , the decoder is idle. the first write to the decoder is expected to start a configuration cycle. the order of configuration is not important. the last configuration cycle is specified by either the ?rwb? bit = 1 or ?last? bit = 1 (see section 2.3 configuration cycle format ). data is not expected to follow th e configuration cycles if the last configuration cycl e is a read or if the dnoblock bit was set (see section 7.7.1 control ). 7.2 register list there are 2 complete register sets in the AHA4525 device: one for the encoder and one for the decoder. registers used in both the encoder and decoder have the same address but are accessed through either the encoder or decoder data interface. in table 5, the register bit name does not include the e for encoder register or d for decoder register when the register is comm on to both the encoder and decoder. registers th at are specific to the encoder or decoder are labelled with the e for encoder or d for decoder. all register bits labelled as ? res ? are reserved and must be written to 0. reads from reserved registers re turn unpredictable values. table 5: register bits - alphabetical register bit name config address bit register section actualiterations[7:0] read only 0x3d 7:0 section 7.7.3 actual iterations (decoder only) blksize[11:8] 00x113:0 section 7.4.2 block size 10x117:4 20x123:0 30x127:4 blksize[7:0] 00x13 7:0 10x14 20x15 30x16 codex[3:0] 00x09 7:4 section 7.4.1 tpc constituent code 10x0b 20x0d 30x0f codey[3:0] 00x09 3:0 10x0b 20x0d 30x0f corrections[11:8] read only 0x3b 3:0 section 7.7.2 status and correction count (decoder only) corrections[7:0] read only 0x3c 7:0 crcenable all 0x00 5 section 7.3.1 crc and scrambler configuration crcerr read only 0x3b 4 section 7.7.2 status and correction count (decoder only) crcpoly[31:24] all 0x01 7:0 section 7.3.1 crc and scrambler configuration crcpoly[23:16] 0x02 crcpoly[15:8] 0x03 crcpoly[7:0] 0x04 crcsize[4:0] all 0x00 4:0 doutputecc all 0x0a 5 section 7.4.1 tpc constituent code dstatus all 0x26 6 section 7.7.1 control comtech aha corporation page 24 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 ebuffersize[8] 00x28 7:0 section 7.4.3 buffer configuration (encoder only) 10x29 20x2a 30x2b epassthrough all 0x0a 6 section 7.4.1 tpc constituent code feedbackx[4:0] 00x28 4:0 section 7.4.5 feedback (decoder only) 10x2a 20x2c 30x2e feedbacky[4:2] 00x28 7:5 10x2a 20x2c 30x2e feedbacky[1:0] 00x29 1:0 10x2b 20x2d 30x2f goutconfig[2:0] all 0x26 5:3 section 7.7.1 control helical 00x0a 7 section 7.4.1 tpc constituent code 10x0c 20x0e 30x10 iterations[7:0] 00x36 7:0 section 7.4.6 iterations (decoder only) 10x37 20x38 30x39 noblock all 0x26 2 section 7.7.1 control noconfig all 7 qbits[1:0] all 0x3a 3:2 section 7.5.1 quantization (decoder only) qmode[1:0] all 1:0 scramenable all 0x00 6 section 7.3.1 crc and scrambler configuration scrampoly[15:8] all 0x05 7:0 scrampoly[7:0] all 0x06 scramseed[15:8] all 0x07 scramseed[7:0] all 0x08 register bit name config address bit register section comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 25 of 55 shortb[5:2] 00x18 7:4 section 7.4.4 shortening configuration 10x1b 20x1e 30x21 shortb[1:0] 00x19 1:0 10x1c 20x1f 30x22 shortx[5:0] 00x17 5:0 10x1a 20x1d 30x20 shorty[5:4] 00x17 7:6 10x1a 20x1d 30x20 shorty[3:0] 00x18 3:0 10x1b 20x1e 30x21 stopiter 00x29 7 section 7.4.5 feedback (decoder only) 10x2b 20x2d 30x2f version[7:0] read only 0x3f 7:0 section 7.8.1 version wordeqblk all 0x27 5 section 7.6.1 transfer word size wordsize[4:0] all 0x27 4:0 section 7.6.1 transfer word size register bit name config address bit register section comtech aha corporation page 26 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 7.3 user data formatting registers 7.3.1 crc and scram bler configuration read/write reset value (hex) = 00 00 00 00 00 00 00 00 00 xcrcenable - crc enable. when set, the encoder will co mpute and insert crc bits and the decoder will compute, check and remove crc. xcrcsize[4:0] - crc size. a value of 0 represents 32 bits. this value must always be less than or equal to xblocksize[11:0] . xcrcpoly[31:0] - crc polynomial. refer to table 1 on page 15 for configuration of the polynomial. xscramenable - scrambler/descrambler enab le. when set, the scrambler or descrambler will scramble the data according to the polynomial. when cleare d, the scrambler or descrambler is disabled. xscrampoly[15:0] - scrambler/descrambler polynomial. for ea ch exponential term in the polynomial, x n , a binary one should be load ed at bit location n-1. x 0 is assumed to be a term in the polynomial. for example, the polynomial 1+x 3 +x 5 +x 8 is programmed as 0b0000000010010100. note that the length of the prbs is dete rmined by the most significant bit location containing a one in xscrampoly[15:0] . refer to figure 16 on page 15 for configuration of the polynomial. xscramseed[15:0] - seed for scrambler and descrambler. the prbs is reset to this seed at the beginning of every tpc block. refer to figure 16 on page 15 for configuration of the seed. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 res xscramenable xcrcenable xcrcsize[4:0] 0x01 xcrcpoly[31:24] 0x02 xcrcpoly[23:16] 0x03 xcrcpoly[15:8] 0x04 xcrcpoly[7:0] 0x05 xscrampoly[15:8] 0x06 xscrampoly[7:0] 0x07 xscramseed[15:8] 0x08 xscramseed[7:0] comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 27 of 55 7.4 code configuration registers 7.4.1 tpc constituent code read/write reset value (hex) = 00 00 00 00 00 00 00 00 xcodex[3:0] - x axis code. xcodex[3] determines whether the code is an extended hamming or parity only code. when set, the code is a parity only code , when cleared, it is an extended hamming code. xcodex[2:0] determines the size of the code, as follows: xcodey[3:0] - y axis code. defined the same as xcodex[3:0] . the maximum length for y-code is 64 bits. epassthru - encoder pass through. when set, the encoder does not add ecc bits. the block size is still configured by the code configuration, but the encoder simply passes bits through from the input to the output. this is a reserved bit in the decoder configuration register stack. doutputecc - decoder output ecc. when set, the decoder will output both the user data and the tpc ecc bits. descrambling and crc checking must be disabled when this bit is set. this is a reserved bit in the encoder configuration register stack. xhelical - helical interleaver/deinterleaver enable. s ee section 3.3.2 for a description of helical interleaving. the following rules must be followed when helical interleaving. the length of the x dimension vector ( xcodex - xshortx ) must be a multiple of 2. xshortb must be 0. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x09 xcodex[3:0] - config 0 xcodey[3:0] - config 0 0x0a xhelical - config 0 epass thru doutput ecc reserved reserved 0x0b reserved 0x0c reserved 0x0d reserved 0x0e reserved 0x0f reserved 0x10 reserved code[2:0] extended hamming parity only 0x2 n/a (4,3) 0x3 (8,4) (8,7) 0x4 (16,11) (16,15) 0x5 (32,26) (32,31) 0x6 (64,57) (64,63) comtech aha corporation page 28 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 7.4.2 block size read/write reset value (hex) = 00 00 00 00 00 00 xblocksize - block size. this is the number of input bits per block when encoding or decoding. when decoding, dblocksize includes the crc bits if they we re inserted by the encoder. when encoding, eblocksize does not include crc bits. eblocksize + ecrcsize must always be less than 4096 bits. when set to 0, xblocksize is 4096 bits. the minimum number of data bits in a block is 16 and the number of data bits must be greater than or equal to xcrcsize[4:0] . an example of (16,11) (16,11) with 16 bit crc gives d blocksize = 16 16 = 256 = 0 100 e blocksize = (11 11) - 16 = 105 = 0 069 when decoding, dblocksize is equal to the channel block for a maximum of 4096 bits.when encoding eblocksize is equal to the data block size minus crc bits. 7.4.3 buffer configurat ion (encoder only) read/write reset value (hex) = 00 00 00 00 ebuffersize[7:0] - encoder logical buffer size * 16. the encode r input buffer is used to allow data blocks to stream into and out of the tpc encoder. when set to 0, ebuffersize[7:0] is 256. ebuffersize[7:0] should be set according to the following equations: if the frequency of u_clk is greater than or equal to the frequency of e_clk , or if ehelical = 1, then if the frequency of e_clk is greater than the frequency of u_clk , and ehelical = 0, then in order to stream out a block continuously, where the codes ( n x , k x ), ( n y , k y ) refer to the shortened constituent codes and cr is the code rate of the input block. the code rate is the number of input bits divided by th e number of output bits including bits inserted by the crc encoder. if ebuffersize *16 is calculated to be greater than eblocksize , then address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x11 reserved xblocksize[11:8] - config 0 0x12 reserved 0x13 xblocksize[7:0] - config 0 0x14 reserved 0x15 reserved 0x16 reserved addressbit7bit6bit5bit4bit3bit2bit1bit0 0x28 ebuffersize[7:0] - config 0 0x29 reserved 0x2a reserved 0x2b reserved ebuffersize 1. = ebuffersize n x n y n x n y k y ? () n x k x ? + + [] cr 16 ----- - eclk () uclk () ? () = ebuffersize = eblocksize/16 comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 29 of 55 7.4.4 shortening configuration read/write reset value (hex) = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 xshortx[5:0] - number of bits to shorten from the x axis code . this value must be set to an even value when helical interleaving is enabled. the x axis must always contain at least 2 data bits. xshorty[5:0] - number of bits to sh orten from the y axis code. xshortb[5:0] - number of bits to shorten from the first ro w. this value must be set to 0 when helical interleaving is enabled. table 6: summary of code shortening rules address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x17 xshorty[5:4] - config 0 xshortx[5:0] - config 0 0x18 reserved xshorty[3:0] - config 0 0x19 reserved xshortb[1:0] - config 0 0x1a reserved 0x1b reserved 0x1c reserved 0x1d reserved 0x1e reserved 0x1f reserved 0x20 reserved 0x21 reserved 0x22 reserved 0x23 reserved 0x24 reserved code type shortx shor ty shortz shortb shortr 2d not allowed not allowed 2d helical even not allowed not allowed not allowed comtech aha corporation page 30 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 7.4.5 feedback (decoder only) read/write reset value (hex) = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 feedbackx[4:0] - feedback for the x axis. the output of the siso is multiplied by feedbackx[4:0] , then shifted by 5 (divided by 32) before being input to following iterations. feedbacky[4:0] - feedback for the y axis. stopiter - when set, decoder will stop iterating before reaching the maximum number of iterations specified in the iterations register if convergence is detected (see section 7.4.6 iterations (decoder only) ). when clear, the decoder will iterate the full number of iterations . 7.4.6 iterations (decoder only) read/write reset value (hex) = 00 00 00 00 iterations[7:0] - maximum number of iterations to perform. when set to 0, the decoder outputs the hard decision values for each bit with no corrections. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x28 feedbacky[4:2] - config 0 feedbackx[4:0] - config 0 0x29 stopiter - config 0 reserved feedbacky[1:0] - config 0 0x2a reserved 0x2b reserved 0x2c reserved 0x2d reserved 0x2e reserved 0x2f reserved 0x30 reserved 0x31 reserved 0x32 reserved 0x33 reserved 0x34 reserved 0x35 reserved address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x36 iterations[7:0] - config 0 0x37 reserved 0x38 reserved 0x39 reserved comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 31 of 55 7.5 channel interface registers 7.5.1 quantization (decoder only) read/write reset value (hex) = 00 qbits[1:0] - quantization bits. a value of 0 represents 4 bits. qbits = 01 is not valid unless qmode = 00. qmode[1:0] - quantization mode for soft inpu t data. when set to ?11,? input da ta is assumed to be in signed 2?s complement notation (mid-tread). when set to ?01,? data is assumed to be mid-riser sign/ magnitude notation. when set to ?00,? data is assumed to be mid-riser unsigned. when set to ?10,? data is assumed to be in ?half 2?s co mplement? mid-riser notation. the confidence mapping for each mode is shown be low with four bit quantization. 7.6 data input/output configuration 7.6.1 transfer word size read/write encoder reset value (hex) =e0 decoder reset value (hex) =e0 xwordeqblk - word size equals block size. only valid wh en port is configured as a synchronous port ( x_mode = 0). when set, the input port expects 1 x_fs per block and the output will generate 1 x_fs per block. when cleared, the input port expects 1 x_fs pulse for every xwordsize[4:0] input bits and the output port generates 1 x_fs pulse for every xwordsize[4:0] output bits. xwordsize[4:0] - word size. only valid when port is configured as a synchronous port ( x_mode = 0) and xwordeqblk is cleared. the input port expects 1 x_fs pulse for every xwordsize[4:0] input bits and the output port generates 1 x_fs pulse for every xwordsize[4:0] output bits. valid values for xwordsize[4:0] range from 2 to 32 b its. when set to 0, xwordsize[4:0] is 32 bits. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x3a res qbits[1:0] qmode[1:0] qmode[1:0] input data type hard decision 0 confidence range no confidence hard decision 1 confidence range max . . . min min . . . max 00 unsigned 0000 . . . 0111 n/a 1000 . . . 1111 01 sign/magnitude 0111 . . . 0000 n/a 1000 . . . 1111 10 half 2?s compl 1000 . . . 1111 n/a 0000 . . . 0111 11 2?s complement 1000 . . . 1111 0000 0001 . . . 0111 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x27 res xwordeqblk xwordsize[4:0] comtech aha corporation page 32 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 7.7 control and status 7.7.1 control read/write reset value (hex) = 00 xgoutconfig[2:0] - general output control. th ese registers control the state of the general output signals ( e_gout and d_gout ). the general outputs can be driven to a 1 or 0 or any one of six signals can be muxed to either of the general outp ut signals. this is used for system debugging or control of an external device. the fo llowing table shows the options for each gout signal. note that xgoutconfig[2] is only used in the decoder. * the datapath empty flags may assert between a configuration read request and the read data output. xnoblock - no block input following configuration. this bit is written to indicate that the configuration write cycle will not be followed by data. the xnoblock bit must be written to a 1 for each set of configuration cycles that is not finished with a configuration read or followed by a data block. the xnoblock bit is automatically cleared between blocks. reads of xnoblock will always return a 0. xnoconfig - no configuration cycl es. this bit is written after configurat ion 0 is programmed and no further configuration is needed. th e configuration cycle with xnoconfig set must be the last configuration cycle. the AHA4525 expects data to follow this configuration cycle unless xnoblock is set. dstatus - decoder status. when this bit is asserted, a status footer is attached at the end of every decoded block. the status footer contains the corrections count and the crcerr flag. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x26 xnoconfig dstatus xgoutcon fig[2:0] xnoblock reserved dgout config[2:0] selected output signal 0drive d_gout to 0 (low). 1drive d_gout to 1 (high). 2 drive decoder load complete event. d_out will change state each time the decoder completes loading one block of data. 3 drive decode complete event. d_gout will change state each time the decoder completes decoding one block of data. 4 drive unload co mplete event. d_gout will change state each time the decoder completes unloading one block of data. 5* drive d_gout to 1 when the decoder datapath is empty, 0 when not empty. egout config[1:0] selected output signal 0drive e_gout to 0 (low). 1drive e_gout to 1 (high). 2 drive encoder load complete event. e_gout will change state each time the encoder completes loading one block of da ta. this is only valid when helical interleaving is enabled. 3* drive e_out to 1 when the encoder datapath is empty and not processing a block, 0 when not empty or processing a block. comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 33 of 55 7.7.2 status and correctio n count (decoder only) read only reset value (hex) = 00 00 corrections[11:0] - corrections per block. the total number of bits corrected by the tpc decoder in the previous block. this value is output as a footer at the end of the tpc block when dstatus is set. the corrections value applies to the last decoded block. writes to these bits have no effect. crcerr - crc verification error. this decoder signal is asserted when the data block did not pass the crc verification. this value is output as a fo oter at the end of the tpc block when dstatus is set. the crcerr status is updated with the last read of a bl ock and is valid until the last read of the next block. a write to this bit has no effect. 7.7.3 actual iterations (decoder only) read only reset value (hex) = 00 actualiterations[7:0] - iterations per block. this is the actual number of iteratio ns performed on the previous block. this number will always equal iterations when stopiter is not asserted. the actualiterations count value can only be read when the decoder datapath is empty. the actualiterations value applies to the last decoded block. actualiterations may be used as a tool to tune the iterations setting for specific nois e levels. writes to these bits have no effect. 7.8 miscellaneous 7.8.1 version read only reset value (hex) = 2b xversion[7:0] - version number of the device. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x3b res crcerr corrections[11:8] 0x3c corrections[7:0] addressbit7bit6bit5bit4bit3bit2bit1bit0 0x3d actualiterations[7:0] addressbit7bit6bit5bit4bit3bit2bit1bit0 0x3f xversion[7:0] comtech aha corporation page 34 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 8.0 signal descriptions this section contains descriptions for all the pins. e ach signal has a type code associated with it. the type codes are described in the following table. 8.1 system control and miscellaneous type code description i input only pin o output only pin signal type description reset_n i refer to section 11.6 reset_n timing for reset_n timing rules. tristate_n i when low, all outputs are tristated. tie high for normal operation. testmode i test mode input signal. ti e low for normal operation. scanmode i scan mode input signal. tie low for normal operation. dparinput i decoder parallel input. when dparinput = 1 on the reset_n rising edge, c_data[3:0] is configured as a 4 bit input bus. when dparinput = 0 on the reset_n rising edge, c_data[0] is configured as a serial input. pll_bypass i pll bypass input signal. ti e low for normal operation. e_mode i encoder interface mode. when e_mode = 0 on the reset_n rising edge, the encoder interface is configured as a synchronous port. when e_mode = 1 on the reset_n rising edge, the encoder inte rface is configured as a bus interface. d_mode i decoder interface mode. when d_mode = 0 on the reset_n rising edge, the decoder interface is configured as a synchronous port. when d_mode = 1 on the reset_n rising edge, the decoder inte rface is configured as a bus interface. e_cs_n i encoder chip select, active low. when deasserted, e_data and e_fs are tristated. d_cs_n i decoder chip select, active low. when deasserted, d_data and d_fs are tristated. sysclk i system clock. e_gout o encoder general output signal . the functionality of this signal is configured in section 7.7.1 control .this signal is driven from an internal clock domain. there is no timing relationship betwee n the external clocks and the gout signals. d_gout o decoder general output signal. the functio nality of this signal is configured in section 7.7.1 control . this signal is driven from an internal clock domain. there is no timing relationship betwee n the external clocks and the gout signals. rdypolarity i ready polarity signal. when rdypolarity = 1, e_rdy and d_rdy are active high. when rdypolarity = 0, e_rdy and d_rdy are active low. this can only change when reset_n is asserted. acptpolarity i accept polarity signal. when acptpolarity = 1, u_acpt and c_acpt are active high. when acptpolarity = 0, u_acpt and c_acpt are active low. this in put can only change when reset_n is asserted. comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 35 of 55 8.2 unencoded data interface 8.3 encoded data interface signal type description u_clk or u_wr_n i unencoded data clock. refer to section 11.2 u_clk, e_clk, c_clk, d_clk clock timing for timing rules. u_data i unencoded input data. when e_mode = 0, u_data is synchronous to u_clk . data is transferred into the device on the rising edge of u_clk . when e_mode = 1, u_data is latched on the rising edge of u_wr_n . u_fs i unencoded frame sync . only used when e_mode = 0, u_fs is synchronous to u_clk . indicates to the device th at data will be transferred on the next rising edge of u_clk . u_acpt o unencoded data accept. indicates that the device can accept u_data . the polarity of this signal is selected with the acptpolarity pin. signal type description e_clk or e_rd_n i encoded data clock. refer to section 11.2 u_clk, e_clk, c_clk, d_clk clock timing for timing rules. e_data o encoded output data. when e_mode = 0, e_data is synchronous to e_clk . data is transferred into the device on the rising edge of e_clk . when e_mode = 1, e_data is transferred on the rising edge of e_rd_n . e_fs o encoded frame sync. only used when e_mode = 0, e_fs is synchronous to e_clk . indicates to the device that data will be transferred on the next rising edge of e_clk . e_rdy o encoded data ready. indicates that the de vice has data ready to be transferred across e_data . the polarity of this sign al is selected with the rdypolarity pin. comtech aha corporation page 36 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 8.4 channel data interface 8.5 decoded data interface signal type description c_clk or c_wr_n i channel data clock. refer to section 11.2 u_clk, e_clk, c_clk, d_clk clock timing for timing rules. c_data[3:0] i channel input data. when d_mode = 0, c_data[3:0] is synchronous to c_clk . data is transferred into the device on the rising edge of c_clk . when d_mode = 1, c_data[3:0] is latched on the rising edge of c_wr_n . if dparinput = 1 on the rising edge of reset_n , data is received in parallel on c_data[3:0] . if dparinput = 0 on the rising edge of reset_n , data is received serially on c_data[0] . c_fs i channel frame sync. only used when d_mode = 0, c_fs is synchronous to c_clk . indicates to the device that data will be transferred on the next rising edge of c_clk . c_acpt o channel data accept. indicates that the device can accept c_data . the polarity of this signal is selected with the acptpolarity pin. signal type description d_clk or d_rd_n i decoded data clock. refer to section 11.2 u_clk, e_clk, c_clk, d_clk clock timing for timing rules. d_data o decoded output data. when d_mode = 0, d_data is synchronous to d_clk . data is transferred into the device on the rising edge of d_clk . when d_mode = 1, d_data is transferred on the rising edge of d_rd_n . d_fs o decoded frame sync. only used when d_mode = 0, d_fs is synchronous to d_clk . indicates to the device that data will be transferred on the next rising edge of d_clk . d_rdy o decoded data ready. indicates that the device has data ready to be transferred across d_data . the polarity of this signal is selected with the rdypolarity pin. comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 37 of 55 9.0 pinout table 7: pinout - pin number order pin signal pin signal 1 c_acpt 33 u_acpt 2 gndio 34 gndio 3 vddio 35 vddio 4 dparinput 36 u_clk 5 gnd 37 u_fs 6 c_clk 38 gnd 7 vdd 39 vdd 8 c_fs 40 u_data 9 rdypolarity 41 sysclk 10 acptpolarity 42 agnd 11 c_data[3] 43 vad 12 c_data[2] 44 pll_bypass 13 vdd 45 vdd 14 gnd 46 gnd 15 c_data[1] 47 tristate_n 16 c_data[0] 48 testmode 17 scanmode 49 vdd 18 e_cs_n 50 gnd 19 vdd 51 reset_n 20 gnd 52 d_cs_n 21 e_fs 53 vdd 22 e_data 54 d_fs 23 gndio 55 gnd 24 vddio 56 d_data 25 e_clk 57 gndio 26 vdd 58 vddio 27 gnd 59 d_clk 28 e_rdy 60 vdd 29 gnd 61 gnd 30 e_gout 62 d_rdy 31 vdd 63 d_gout 32 e_mode 64 d_mode comtech aha corporation page 38 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 10.0 dc electrical specifications information in this section represent s design goals. while every effort w ill be made to meet these goals, values presented should be considered targets until characteriza tion is complete. please consult with comtech aha corporation for the most up-to-date values. 10.1 operating conditions notes: 1) timings referenced to this load. 2) may require external heat sink. 3) see appendix a for vad recommendations. 4) measured at 0v and vddio nominal. 5) at maximum sysclk frequency, nominal vdd and vddio, and full duplex operation. 6) at maximum sysclk frequency, nominal vdd and vddio, and encode operation. 7) during power on sequencing, vdd must reach 1. 7v concurrent or before vddio reaches 1.7v. 10.2 absolute maximum stress ratings symbol parameter min max units notes vdd core supply voltage (1.8v nominal) 1.7 1.9 v 7 vddio input/output supply voltage (3.3v nominal) 3.0 3.6 v 7 vad analog pll supply voltage (1.8v nominal) 1.7 1.9 v 3 idd supply current (static) 1 ma iddio input/output supply current (static) 0.6 ma idd supply current (active) 110 ma 5 iddio input/output supply current (active) 10.3 5 idd supply current (active) 90 ma 6 iddio input/output supply current (active) 8 ma 6 ta ambient temperature 0 70 c2 vil input low voltage -0.3 0.8 v vih input high voltage 2.0 5.5 v iin input leakage current -5 5 ua 4 vol output low voltage (iol=-2ma) 0.4 v voh output high voltage (ioh=2ma) 2.4 v iol output low current 8 ma ioh output high current 8 ma ioz output leakage current during tristate -5 5 ua cin input capacitance 10 pf cio input/output capacitance 10 pf cout output load capacitance 30 pf 1 symbol parameter min max units notes tstg storage temperature -50 150 c vsupply supply voltage -0.5 4.6 v vpin voltage applied to any signal pin 6.0 v comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 39 of 55 10.3 test conditions * the timing diagrams for these signals assume a capacitive load of 30pf. the specified signal timings must be derated by the factor shown in figure 22 when operating at loads other than 30pf. figure 22: signal timing vs. output load *production test conditions parameter value ac timing reference 1.4 v 10 50 0.86 1.15 load capacitance (pf) multiplication factor 20 30 40 load capacitance multiplication factor 10 pf 0.86 20 pf 0.92 30 pf 1.00 40 pf 1.07 50 pf* 1.15 comtech aha corporation page 40 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 11.0 ac electrical specifications 11.1 sysclk clock timing figure 23: sysclk clock timing table 8: sysclk clock timi ng with pllbypass = 0 table 9: sysclk clock timi ng with pllbypass = 1 number parameter min max units 1 sysclk rise time 1ns 2 sysclk fall time 1ns 3 sysclk high time 8ns 4 sysclk low time 8ns 5 sysclk period (t cp ) 20 ns sysclk frequency 20 50 mhz cycle to cycle jitter -125 125 ps long term jitter -200 200 ps number parameter min max units 1 sysclk rise time 1ns 2 sysclk fall time 1ns 3 sysclk high time 2.0 ns 4 sysclk low time 2.0 ns 5 sysclk period (t cp ) 5.0 ns sysclk frequency 200 mhz cycle to cycle jitter -125 125 ps long term jitter -200 200 ps sysclk 1 34 5 2 2.0v 1.4v 0.8v comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 41 of 55 11.2 u_clk, e_clk, c_clk, d_clk clock timing figure 24: clock timing table 10: clock timing 11.3 u_wr_n, e_rd_n, c_wr_n, d_rd_n strobe timing figure 25: strobe timing table 11: strobe timing with pllbypass = 0 number parameter min max units 1 u_clk, e_clk, c_clk, d_clk rise time 1ns 2 u_clk, e_clk, c_clk, d_clk fall time 1ns 3 u_clk, e_clk, c_clk, d_clk high time 4ns 4 u_clk, e_clk, c_clk, d_clk low time 4ns 5 u_clk, e_clk, c_clk, d_clk frequency with pllbypass = 0. 1.9* sysclk mhz 5 u_clk, e_clk, c_clk, d_clk frequency with pllbypass = 1. sysclk/ 2.1 mhz number parameter min max units 1 u_wr_, e_rd_n, c_wr_n, d_rd_n rise time. 1ns 2 u_wr_, e_rd_n, c_wr_n, d_rd_n fall time. 1ns 3 u_wr_, e_rd_n, c_wr_n, d_rd_n high time. 8ns 4 u_wr_, e_rd_n, c_wr_n, d_rd_n low time. 8ns 5 u_wr_, e_rd_n, c_wr_n, d_rd_n frequency with pllbypass = 0. sysclk mhz 5 u_wr_, e_rd_n, c_wr_n, d_rd_n frequency with pllbypass = 1. sysclk /4 mhz x_clk 1 34 5 2 2.0v 1.4v 0.8v x_wr_n, x_rd_n 1 34 5 2 2.0v 1.4v 0.8v comtech aha corporation page 42 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 11.4 synchronous data interface figure 26: encoder interf ace data input timing table 12: encoder interf ace data input timing notes: 1) u_acpt is driven from an internal clock domain. there is no timing relationship between u_clk and u_acpt. the function of u_acpt is to indicate that the encoder can accept a block of data. u_acpt deasserts following the first data transfer or after a configuration read is started. 2) there is no timing relationship between u_clk and sysclk. number parameter min max units notes t 1 u_fs setup to u_clk .5ns t 2 u_fs hold from u_clk .3ns t 3 u_data setup to u_clk .5ns t 4 u_data hold from u_clk .3ns t 5 e_cs_n setup to u_clk rising edge that u_fs is asserted. 9ns u_clk u_data (input) (input) t 1 t 2 u_fs (input) t 3 t 4 u_acpt (output) e_cs_n (input) t 5 configuration data comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 43 of 55 figure 27: decoder interf ace data input timing table 13: decoder interf ace data input timing notes: 1) c_acpt is driven from an internal clock domain. there is no timing relationship between c_clk and c_acpt. the function of c_acpt is to indicate that the encode r can accept a block of data. c_acpt deasserts following the first data transfer or after a configuration read is started. 2) there is no timing relationship between c_clk and sysclk. number parameter min max units notes t 1 c_fs setup to c_clk . 5ns t 2 c_fs hold from c_clk . 3ns t 3 c_data[0] setup to c_clk . 5ns t 4 c_data[0] hold from c_clk . 3ns t 5 d_cs_n setup to c_clk rising edge that c_fs is asserted. 9ns c_clk c_data[0] (input) (input) t 1 t 2 c_fs (input) t 3 t 4 c_acpt (output) d_cs_n (input) t 5 configuration data comtech aha corporation page 44 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 figure 28: encoder interface data output timing using chip select table 14: encoder interface data output timing using chip select notes: 1) it is valid for e_cs_n to always be asserted. 2) there is no timing relationship between e_clk and sysclk. number parameter min max units notes t 1 e_fs, e_data delay from e_clk . 8ns t 1 e_fs, e_data valid from e_clk following e_cs_n asserted. 8ns1 t 2 e_fs, e_data hold from e_clk . 1ns t 3 e_rdy delay from e_clk . 8ns t 4 e_cs_n setup to e_clk. 9ns t 5 last e_data read to e_cs_n deasserted. 5 sysclk 1 t 6 e_cs_n asserted to e_fs, e_data valid. 8ns t 7 e_cs_n deasserted to e_fs , e_data tristate. 8ns e_clk e_data (input) (output) t 6 t 1 e_fs (output) t 3 e_rdy (output) t 2 high-z first typical last high-z t 2 t 1 t 7 t 5 t 4 e_cs_n (input) high-z high-z comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 45 of 55 figure 29: encoder interf ace data output timing table 15: encoder interf ace data output timing notes: 1) it is valid for e_cs_n to always be asserted. 2) there is no timing relationship between e_clk and sysclk. number parameter min max units notes t 1 e_fs, e_rdy, e_data delay from e_clk . 8ns t 1 e_fs, e_rdy, e_data valid from e_clk following e_cs_n asserted. 8ns1 t 2 e_fs, e_data hold from e_clk . 1ns t 3 e_rdy delay from e_clk . 8ns e_clk e_data (input) (output) t 1 e_fs (output) t 1 e_rdy (output) t 2 first typical last t 2 t 1 e_cs_n (input) comtech aha corporation page 46 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 figure 30: decoder interf ace data output timing using chip select table 16: decoder interface data output timing using chip select notes: 1) it is valid for d_cs_n to always be asserted. 2) there is no timing relationship between d_clk and sysclk. number parameter min max units notes t 1 d_fs, d_data delay from d_clk . 8ns t 1 d_fs, d_data valid from d_clk following d_cs_n asserted. 8ns1 t 2 d_fs, d_data hold from d_clk . 1ns t 3 d_rdy delay from d_clk . 8ns t 4 d_cs_n setup to d_clk . 9ns t 5 last d_data read to d_cs_n deasserted. 5 sysclk 1 t 6 d_cs_n asserted to d_fs, d_data valid. 8ns t 7 d_cs_n deasserted to d_fs , d_data tristate. 8ns d_clk d_data (input) (output) t 6 t 1 d_fs (output) t 3 d_rdy (output) t 2 high-z first typical last high-z t 2 t 1 t 7 t 5 t 4 d_cs_n (input) high-z high-z comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 47 of 55 figure 31: decoder interface data output timing table 17: decoder interface data output timing notes: 1) it is valid for d_cs_n to always be asserted. 2) there is no timing relationship between d_clk and sysclk. number parameter min max units notes t 1 d_fs, d_rdy, d_data delay from d_clk . 8ns t 1 d_fs, d_rdy, d_data valid from d_clk following d_cs_n asserted. 8ns1 t 2 d_fs, d_data hold from d_clk . 1ns t 3 d_rdy delay from d_clk . 8ns d_clk d_data (input) (output) t 1 d_fs (output) t 1 d_rdy (output) t 2 first typical last t 2 t 1 d_cs_n (input) comtech aha corporation page 48 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 11.5 bus interface figure 32: encoder bus interface data input timing table 18: encoder bus interface data input timing notes: 1) u_acpt is driven from an internal clock domain. there is no timing relationship between u_wr_n and u_acpt. the function of u_acpt is to indicate that the encoder can accept a block of data. u_acpt deasserts following the first data transfer or after a configuration read is started. 2) there is no timing relationship between u_wr_n and sysclk. 3) u_wr_n is used internally as a clock. u_wr_n must not glitch. number parameter min max units notes t 1 u_wr_n frequency with pllbypass = 0. sysclk mhz 2, 3 t 1 u_wr_n frequency with pllbypass = 1. sysclk /4 mhz 2, 3 t 2 u_data setup to u_wr_n rising edge. 5 ns t 3 u_data hold from u_wr_n rising edge. 3 ns t 4 e_cs_n valid before u_wr_n strobe rising edge. 9ns u_wr_n u_acpt (input) (output) t 1 u_data (input) t 2 t 3 e_cs_n (input) t 4 configuration data comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 49 of 55 figure 33: decoder bus interface data input timing table 19: decoder bus interface data input timing notes: 1) c_acpt is driven from an internal clock domain. there is no timing relationship between c_clk and c_acpt. the function of c_acpt is to indicate that the encode r can accept a block of data. c_acpt deasserts following the first data transfer or after a configuration read is started. 2) there is no timing relationship between c_wr_n and sysclk. 3) c_wr_n is used internally as a clock. c_wr_n must not glitch. number parameter min max units notes t 1 c_wr_n frequency with pllbypass = 0. sysclk mhz 2, 3 t 1 c_wr_n frequency with pllbypass = 1. sysclk /4 mhz 2, 3 t 2 c_data setup to c_wr_n rising edge. 5 ns t 3 c_data hold from c_wr_n rising edge. 3 ns t 4 d_cs_n valid before c_wr_n strobe rising edge. 9 ns c_wr_n c_acpt (input) (output) t 1 c_data (input) t 2 t 3 d_cs_n (input) t 4 configuration data comtech aha corporation page 50 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 figure 34: encoder bus interface data output timing table 20: encoder bus interf ace data output timing notes: 1) there is no timing relationship between e_rd_n and sysclk. 2) e_rd_n is used internally as a clock. e_rd_n must not glitch. figure 35: decoder bus interf ace data output timing table 21: decoder bus interf ace data output timing notes: 1) there is no timing relationship between d_rd_n and sysclk. 2) d_rd_n is used internally as a clock. d_rd_n must not glitch. number parameter min max units notes t 1 e_rd_n frequency with pllbypass = 0. sysclk mhz 1, 2 t 1 e_rd_n frequency with pllbypass = 1. sysclk /4 mhz 1, 2 t 2 e_data valid from e_rd_n falling edge. 8 ns t 3 e_data hold from e_rd_n rising edge. 1 5 ns t 4 e_rdy delay from e_rd_n rising edge. 8 ns t 5 e_cs_n setup to e_rd_n rising edge. 9 ns number parameter min max units notes t 1 d_rd_n frequency with pllbypass = 0. sysclk mhz 1, 2 t 1 d_rd_n frequency with pllbypass = 1. sysclk /4 mhz 1, 2 t 2 d_data valid from d_rd_n falling edge. 8 ns t 3 d_data hold from d_rd_n rising edge. 1 5 ns t 4 d_rdy delay from d_rd_n rising edge. 8 ns t 5 d_cs_n setup to d_rd_n rising edge. 9 ns e_rd_n e_rdy (input) (output) e_data (output) t 3 t 4 high-z e_cs_n (input) t 5 t 2 t 1 d_rd_n d_rdy (input) (output) d_data (output) t 3 t 4 high-z d_cs_n (input) t 5 t 2 t 1 comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 51 of 55 11.6 reset_n timing figure 36: reset_n timing table 22: reset_n timing notes: 1) if e_mode = 0 and pllbypass = 0, t xclk is the period of the lowest frequency of u_clk, e_clk and sysclk. 2) if e_mode = 0 and pllbypass = 1, t xclk is the period of the lowest frequency of u_clk, e_clk and sysclk/ 4. 3) if d_mode = 0 and pllbypass=0, t xclk is the period of the lowest frequency of c_clk, d_clk and sysclk. 4) if d_mode = 0 and pllbypass=1, t xclk is the period of the lowest frequency of c_clk, d_clk and sysclk/4. 5) sysclk must be running for 10us to lock the internal pll before reset_n is asserted. number parameter min max units notes t 1 reset_n pulsewidth with e_mode = 1, d_mode = 1, and pllbypass = 0. 10 sysclk t 1 reset_n pulsewidth with e_mode = 1, d_mode = 1, and pllbypass = 1. 40 sysclk t 1 reset_n pulsewidth with e_mode = 0 or d_mode = 0. 10 t xclk 1,2,3,4 t 2 pll lock time 10 us 5 vdd x_clk reset_n t 1 t 2 comtech aha corporation page 52 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 12.0 package specifications 12.1 package dimensions figure 37: package dimensions - top view figure 38: package dimensi ons - cross section view AHA4525a 15 16 49 50 63 64 p b d d1 (lca) (lcb) e1 e 040 ptc llllllll note: yywwd = date code; llllllll = lot number yywwd l a a2 a1 a comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 53 of 55 table 23: tqfp (thin quad flat pa ck) 7 x 7 mm package dimensions notes: all dimensions are in millimeters. more detailed mechanical information is available upon request. 13.0 ordering information 13.1 available parts 13.2 part numbering device number: AHA4525 revision letter: a package material: p plastic package type: t thin quad flat pack temperature specifications: c commercial 0 c to +70 c i industrial -40 c to +85 c (all dimensions are in mm) symbol number of pin and spe cification dimension 64 min nom max (lca) 16 (lcb) 16 a1.11.2 a1 0.05 0.1 0.15 a2 0.95 1.0 1.05 d9.0 d1 7.0 e9.0 e1 7.0 l 0.45 0.60 0.75 p0.40 b 0.13 0.18 0.23 part number description AHA4525a-040 ptc ieee 802.16a compliant turbo product code encoder/decoder AHA4525a-040 pti ieee 802.16a compliant turbo product code encoder/decoder - industrial temp aha 4525 a- 040 p t c, i manufacturer device number revision level internal reference package material package type temperature specification comtech aha corporation page 54 of 55 a subsidiary of comtech te lecommunications corporation ps4525_0204 14.0 related technical publications document # description pb4524evb product brief - aha4524 tpc evaluation board pb4525 product brief - AHA4525 ieee 802.16 a compliant turbo product code encoder/decoder pbgalaxy-evsw product brief - aha gala xy tpc windows evaluation software antpc01 application note ? primer: turbo product codes antpc02 application note ? use and perform ance of shortened codes with the aha4501 tpc encoder/decoder) antpc03 application note ? turbo product code encoder/decoder with quadrature amplitude modulation (qam) antpc04 application note ? use and perfo rmance of the aha4501 tpc encoder/ decoder with differential phase shift keying (dpsk) antpc06 application note ? aha turbo produc t codes frequently asked questions (faq) antpc07 application note ? turbo product codes for lmds antpc09 application note ? tpc code selection and parameter determination tpceval evaluation software ? turbo prod uct codes - windows evaluation software comtech aha corporation ps4525_0204 a subsidiary of comtech te lecommunications corporation page 55 of 55 appendix a: vad recommendations analog power supply filter for pll usage the analog power supply for the internal pll (vad) ideally comes from an analog power supply having low pass filter char acteristics of -3db at < 1khz and < -70db in the absorption band. actual component selection will limit the -3db point and good board layout is vital to achieving good high frequency absorption. an r-c or r-l-c filter can be used with the ?c? being composed of multiple devices to achieve a wide spectrum of noise absorption. for dc reasons the series resistance of this filter should be limited. ther e should be considerably less than 5% voltage drop across the resistor under worst-case conditions. high quality series inductors should be used with a series resistor to prevent a high gain series resonator from being created. for the low-frequency cu toff an electrolytic capacitor should be used in the filter design. the filter also needs to sustain its attenuation into high frequencies (i.e. > 100 mhz) so additional non- electrolytic capacitance shou ld be added in parallel. all leads of the high frequency capacitor(s) should be kept short. this includes the board wires, vias, and component le ads, and within the component package (so select the comp onent carefully). board layout around the high -frequency capacitance and the path from there to the pads is critical. it is vital that the quiet ground and power are treated like analog signals. the power (vad) path must be a single trace from the ic package pin to the high frequency capacitance, then to the low frequency capacitance, then through the series element (e.g. resistor), then to board power (vdd). the distance from the ic pin to the high frequency cap should be kept as short as possible. the ground (agnd) path should be from the ic pin to the high frequency capacitance to the low frequency capacitance with the distances being very short. the pll has the dc ground connection made on chip, so the external gnd pin must not be connected to pcb ground, but only to the power supply filter. the power and ground traces should be run close and parallel as far as possible with large spacing between adjacent traces. this will help minimize noise, especially non common-mode noise. the power loop consisting of the high frequency capacitor, vad and gnd traces to the ic, and the ic itself must be designed to keep area and impedance to a minimum. layout the board to enable the total analog power circuit to be small with short and adjacent wire traces. no extra connections should be made to board power planes; only connect as described above. care should be exer cised in component selection to insure that there are no resonant absorptions or resonant non-absorptions throughout the attenuating frequency range,. this means that the series element will either be a resistor or a very poor (i.e. resistive) inductor. for a series element with high impedance (i.e. 100 ohms), the electrolytic is often chosen as the biggest capacitance tantalum available which fits reasonably on the board (i .e. 25uf). similarly, the other capacitor is typically the largest value high frequency capacitor available in a small package (i.e. 100nf). example schematic this schematic represents an example of both the circuit and the device placement. actual component values may be different. figure a1: example external circ uit component configuration board chip vdd vad agnd 100nf 25 f 100 ? |
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