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description the gmm26417233atg is a 16m x 64bits synchronous dynamic ram module which is assembled 8 pieces of 16m x 8bits synchronous drams in 54 pin tsop ii package and one 2048 bit eeprom in 8pin tssop package mounted on a 168 pin printed circuit board with decoupling capacitors. the gmm26417233atg is optimized for application to the systems which are required high density and large capacity such as main memory of the computers and an image memory systems, and to the others which are requested compact size. the gmm26417233atg provides common data inputs and outputs. gmm26417233atg (single side) features pin name ck0, 1, 2, 3 cke0 s0, 2 ras cas we a0 ~ a11 ba0,1 dq0 ~ 63 dqmb0 ~ 7 v cc v ss nc v ref sda scl sa0 ~ 2 du clock input clock enable chip select row address strobe column address strobe write enable address input bank address input data input / output data input / output mask power for internal circuit ground for internal circuit no connect power supply for reference serial data input/ output serial clock address in eeprom don't use * pc100/pc66 compatible -8(125mhz) -7k(pc100,2-2-2)/-7j(pc100,3-2-2)/-10k(pc66) * 3.3v +/- 0.3v power supply * maximum clock frequency 100 / 125 mhz * lvttl interface * burst read/write operation and burst read/ single write operation capability * programmable burst length ; 1, 2, 4, 8, full page * programmable burst sequence sequential / interleave * full page burst length capability sequential burst burst stop capability * programmable cas latency ; 2, 3 * cke power down mode * input / output data masking * 4096 refresh cycles / 64ms * auto refresh / self refresh capability * serial presence detect with eeprom (-7 k/7j) single side (-10 k) double side 16 mx64 bits pc100 sdram unbuffered dimm based on 16mx8 sdram with lvttl, 4 banks & 4k refresh gmm26417233atg this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 1.1/dec.99 ? 1999 hyundai microelectronics
gmm26417233atg rev. 1.1/dec.99 2 pin symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pin configuration pin symbol pin symbol pin symbol pin symbol pin symbol 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 v ss dq32 dq33 dq34 dq35 v cc dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 v cc dq46 dq47 *cb4 *cb5 v ss nc nc v cc cas dqmb4 dq18 dq19 v cc dq20 nc *v ref , nc *cke1 v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 v cc dq28 dq29 dq30 dq31 v ss ck2 nc wp sda scl v cc dqmb1 s0 du v ss a0 a2 a4 a6 a8 a10/ap ba1 v cc v cc ck0 v ss du s2 dqmb2 dqmb3 du v cc nc nc *cb2 *cb3 v ss dq16 dq17 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 dqmb5 *s1 ras v ss a1 a3 a5 a7 a9 ba0 a11 v cc ck1 *a12 v ss cke0 *s3 dqmb6 dqmb7 *a13 v cc nc nc *cb6 *cb7 v ss dq48 dq49 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 dq50 dq51 v cc dq52 nc *v ref , nc nc v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 v cc dq60 dq61 dq62 dq63 v ss ck3 nc sa0 sa1 sa2 v cc v ss dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 v cc dq14 dq15 *cb0 *cb1 v ss nc nc v cc we dqmb0 * these pins are not used in this module
gmm26417233atg rev. 1.1/dec.99 3 dqm0 dqm u0 cs s0 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm1 dqm u1 cs dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm2 dqm u2 cs dq 16 dq17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm3 dqm u3 cs dq 24 dq25 dq26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm4 dqm u4 cs dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm5 dqm u5 cs dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm6 dqm u6 cs dq 48 dq 49 dq 50 dq 51 dq 52 dq53 dq 54 dq 55 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm7 dqm u7 cs dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 s2 a0 ~ a11, ba0,1 ras v cc v ss capacitor one 0.33uf and one 0.1uf per each sdram u0 - u7 u0 - u7 u0 - u7 cas cke0 we u0 - u7 u0 - u7 a0 a1 a2 serial pd sda scl u0 ~ u7 u0 ~ u7 ck0,2 4 sdrams ck1, 3 10 pf vss 3.3 pf wp 47 kohm 10 ohm sa0 sa1 sa2 10 ohm block diagram (-7k/-7j)
gmm26417233atg rev. 1.1/dec.99 4 dqm0 dqm u0 cs s0 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm1 dqm u1 cs dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm2 dqm u2 cs dq 16 dq17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm3 dqm u3 cs dq 24 dq25 dq26 dq 27 dq 28 dq 29 dq 30 dq 31 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm4 dqm u4 cs dq 32 dq 33 dq 34 dq 35 dq 36 dq 37 dq 38 dq 39 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm5 dqm u5 cs dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm6 dqm u6 cs dq 48 dq 49 dq 50 dq 51 dq 52 dq53 dq 54 dq 55 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dqm7 dqm u7 cs dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 s2 a0 ~ a11, ba0,1 ras v cc v ss capacitor two 0.33uf per each sdram u0 - u7 u0 - u7 u0 - u7 cas cke0 we u0 - u7 u0 - u7 a0 a1 a2 serial pd sda scl u0 ~ u7 u0 ~ u7 ck0,1 4 sdrams ck2,3 10 pf 10 ohm sa0 sa1 sa2 10 ohm block diagram (-10k)
gmm26417233atg rev. 1.1/dec.99 5 pin description pin name description ck0, 1, 2, 3 (input pins) ck is the master clock input to this pin. the other input signals are referred at ck rising edge. cke0 (input pin) this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down and clock suspend modes. when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. s0, 2 (input pins) although these pin names are the same as those of conventional drams , they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. ras, cas and we (input pins) a0 ~ a11 (input pins) row address (ax0 to ax11) is determined by a0 to a11 level at the bank active command cycle ck rising edge. column address is determined by a0 to a9 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, both banks are precharged . but when a10 = low at the precharge command cycle, only the bank that is selected by ba0 is precharged . ba0,1 (input pin) ba0,1 are bank select signal. if ba0 is low and ba1 is high, bank 0 is selected. if ba0 is high and ba1 is low, bank 1 is selected. if ba0 is low and ba1 is high, bank 2 is selected. if ba0 is high and ba1 is high, bank 3 is selected. dq0 ~ dq63 (i/o pins) data is input and output from these pins. these pins are the same as those of a conventional drams . dqmb0 ~ dqmb7 (input pins) dqmb controls input/output buffers. *read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z. *write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written. v cc (power supply pins) 3.3 v is applied. (v cc is for the internal circuit) v ss (power supply pins) ground is connected. (v ss is for the internal circuit) nc no connection pins.
gmm26417233atg rev. 1.1/dec.99 6 absolute maximum ratings notes : 1. respect to v ss symbol value unit note parameter v t -0.5 to vcc +0.5 (<= 4.6 (max)) v 1 voltage on any pin relative to v ss v cc -0.5 to +4.6 v 1 supply voltage relative to v ss i out 50 ma short circuit output current p t 1.0 w power dissipation topr 0 to +70 c operating temperature tstg -55 to +125 c storage temperature notes : 1. all voltage referred to v ss . 2. v ih (max) = 5.6v for pulse width <= 3ns 3. v il (min) = -2.0v for pulse width <= 3ns recommended dc operating conditions ( ta = 0 to + 70c) symbol min unit note v cc , v ccq v 1 v ss , v ssq v input high voltage v ih v 1, 2 input low voltage v il v 1, 3 supply voltage parameter max 3.0 3.6 0 0 2.0 vcc + 0.3 -0.3 0.8
gmm26417233atg rev. 1.1/dec.99 7 dc characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) parameter symbol unit test conditions notes operating current standby current in power down i cc2p self refresh current i cc6 ma v ih >=v cc - 0.2 v il <=0.2v 7 burst length= 1 t rc = min 1, 2, 3 cke = v il , t ck = 12 ns 5 i cc1 ma ma standby current in power down (input signal stable) i cc2ps cke=v il , t ck = infinity 6 ma standby current in non power down (cas latency=2) i cc2n cke,cs = v ih , t ck = 12ns 4 ma standby current in non power down (input signal stable) i cc2ns cke,cs = v ih , t ck = infinity 4 ma active standby current in power down i cc3p cke = v il , t ck = 12 ns , dq = high-z ma active standby current in power down (input signal stable) i cc3ps cke = v il , t ck = infinity 2,6 ma active standby current in non power down i cc3n cke,cs = v ih , t ck = 12 ns , dq = high-z 1,2,4 ma active standby current in non power down (input signal stable) i cc3ns cke,cs = v ih , t ck = infinity 2,8 ma burst operating current i cc4 t ck = min bl = 4 1,2,3 ma ( cl= 2 ) i cc4 ma ( cl= 3 ) refresh current t rc = min 3 i cc5 ma 1,2,5 16 16 8 120 110 35 240 200 40 - 8 max - 10 k max 700 - 7 k max - 7 j 750 max 900 800 1000 900 1500 1400 800 900 1500 900 900 1500
gmm26417233atg rev. 1.1/dec.99 8 notes : 1. i cc depends on output load condition when the device is selected. i cc ( max) is specified at the output open condition. 2. one bank operation. 3. addresses are changed once per one cycle. 4. addresses are changed once per two cycles. 5. after power down mode, clk operating current. 6. after power down mode, no clk operating current. 7. after self refresh mode set, self refresh current. 8. input signals are v ih or v il fixed. capacitance ( ta = 25c, v cc , v ccq = 3.3v +/- 0.3v) 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. dqmb = vih to disable dout . 3. this parameter is sampled and not 100% tested. 60 60 45 40 20 20 note : symbol parameter min max unit notes c i1 input capacitance (a0 ~ a11, ba0,1) - pf 1, 3 c i2 input capacitance (ras, cas, we,cke) - pf c i3 input capacitance (ck0~ck3) - pf c i4 input capacitance (s0, s2) - pf c i5 input capacitance (dqmb0 ~ dqmb7) - pf c i/o i/o capacitance (dq0 ~ 63) - pf 1, 3 1, 3 1, 3 1, 3 1, 2 ,3 dc characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/-0.3 v, v ss , v ssq = 0 v) input leakage current i li ua 0<= vin<=v cc output leakage current i lo ua 0<= vout <=v cc dq = disable output high voltage v oh v i oh = -2 ma output low voltage v ol v i ol =2 ma -1 1 -1.5 1.5 2.4 - - 0.4 parameter symbol unit test conditions notes - 8, - 7 k, - 7j, -10k min max
gmm26417233atg rev. 1.1/dec.99 9 ac characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) symbol unit notes t ck t ck parameter system clock cycle time ( cl=2) ( cl=3) ns 1 t ckh ns 1 clk high pulse width t ckl ns 1 clk low pulse width t ac t ac access time from clk ( cl=2) ( cl=3) ns 1, 2 t oh ns 1, 2 data-out hold time t lz ns 1, 2, 3 clk to data-out low impedance t hz clk to data-out high impedance ( cl = 2,3 ) ns 1, 4 t ds ns 1 data-in setup time t dh ns 1 data-in hold time t as ns 1 address setup time t ah ns 1 address hold time t ces ns 1, 5 cke setup time t cesp ns 1 cke setup time for power down exit t ceh ns 1 cke hold time t cs ns 1 command (cs, ras, cas, we, dqm) setup time t rc ns 1 ref/active to ref/active command period t ch ns 1 command (cs, ras, cas, we, dqm) hold time t ras ns 1 active to precharge command period t rcd ns 1 active command to column command (same bank) t rp ns 1 precharge to active command period - 8 min max 8 - 12 - - 10 k min max 10 - 15 - 3 - 3 - 3 - 3 - - 6 - 6 - 8 - 9 3 - 3 - 2 - 2 - - 6 - 7 2 - 2 - 1 - 1 - 2 - 2 - 1 - 1 - 2 - 2 - 2 - 2 - 1 - 1 - 2 - 2 - 68 - 90 - 1 - 1 - 48 120000 60 120000 20 - 30 - 20 - 30 - - 7 k min max 10 - 10 - 3 - 3 - - 6 - 6 3 - 2 - - 6 2 - 1 - 2 - 1 - 2 - 2 - 1 - 2 - 70 - 1 - 50 120000 20 - 20 - - 7 j min max 10 - 15 - 3 - 3 - - 6 - 8 3 - 2 - - 6 2 - 1 - 2 - 1 - 2 - 2 - 1 - 2 - 70 - 1 - 50 120000 20 - 20 -
gmm26417233atg rev. 1.1/dec.99 10 ac characteristics ( ta = 0 to 70c, v cc , v ccq = 3.3 v +/- 0.3 v, v ss , v ssq = 0 v) (continued) test condition ? input and output-timing reference levels: 1.4v ? input waveform and output load: see following figures 20% t t t t 0.4 v 2.4 v i/o 80% open input c l notes : 1. ac measurement assumes t t = 1ns. reference level for timing of input signals is 1.40v. if t t is longer than 1ns,transition time compensation should be considered. 2. access time is measured at 1.40v. load condition is c l = 50pf without termination. 3. t lz (min)defines the time at which the outputs achieves the low impedance state. 4. t hz (max)defines the time at which the outputs achieves the high impedance state. 5. t ces define cke setup time to cke rising edge except power down exit command. symbol notes parameter 1 t rrd 1 active (a) to active (b) command period t ref refresh period t rwl write recovery or data-in to precharge lead time unit ns ns ms - 7 k min max 10 - 20 - - 64 - 7 j min max 10 - 20 - - 64 - 10 k min max 15 - 20 - - 64 - 8 min max 8 - 16 - - 64
gmm26417233atg rev. 1.1/dec.99 11 relationship between frequency and minimum latency notes l rcd 1 active command to column command (same bank) l rc = [ l ras + l rp ], 1 active command to active command (same bank) l ras active command to precharge command (same bank) l rp 1 precharge command to active command (same bank) l rwl 1 write recovery or last data-in to precharge command (same bank) l rrd 1 active command to active command (different bank) l srex self refresh exit time l apw = [ l rwl + l rp ], 1 last data in to active command (auto precharge , same bank) l sec = [ l rc ] self refresh exit to command input l hzp precharge command to high impedance l hzp ( cl=2) ( cl=3) l apr last data out to active command (auto precharge ) (same bank) l ep last data out to precharge (early precharge ) l ep ( cl=2) ( cl=3) l ccd column command to column command l wcd write command to data in latency l did dqm to data in l dod dqm to data out l pec power down exit to command input l cle cke to clk disable l rsa register set to active command l cdd parameter t ck ( ns ) frequency(mhz) 1 cs to command disable symbol -7 j 100 2 7 5 10 2 1 2 1 3 7 - 3 1 - - 2 1 0 0 2 1 1 1 0 -8 125 3 9 6 8 3 1 2 1 4 9 - 3 1 - -2 1 0 0 2 1 1 1 0 83 2 6 4 12 2 1 2 2 3 6 2 3 1 -1 -2 1 0 0 2 1 1 1 0 66 2 6 4 15 2 1 2 2 3 6 2 3 1 -1 - 2 1 0 0 2 1 1 1 0 100 2 7 5 10 2 1 2 1 3 7 2 3 1 - 1 - 2 1 0 0 2 1 1 1 0 -7 k 100 2 7 5 10 2 1 2 1 3 7 2 3 1 - 1 - 2 1 0 0 2 1 1 1 0 -10 k 100 3 9 6 10 3 1 2 2 5 9 - 3 1 - - 2 1 0 0 2 1 1 1 0 66 2 6 4 15 2 1 2 2 3 6 2 3 1 -1 - 2 1 0 0 2 1 1 1 0
gmm26417233atg rev. 1.1/dec.99 12 relationship between frequency and minimum latency notes : 1. l rcd to l rrd are recommended value. symbol notes l bsr burst stop to output valid data hold l bsr ( cl=2) ( cl=3) l bsh burst stop to output high impedance l bsh ( cl=2) ( cl=3) l bsw burst stop to write data ignore parameter t ck ( ns ) frequency(mhz) - 7 k - 7 j - 8 125 8 - 2 - 3 0 83 12 1 2 2 3 0 100 10 - 2 - 3 0 66 15 1 2 2 3 0 100 10 1 2 2 3 0 100 10 1 2 2 3 0 - 10 k 100 10 - 2 - 3 0 66 15 1 2 2 3 0
gmm26417233atg rev. 1.1/dec.99 13 package dimension(-7k/-7j) note : 1. tolerances on all dimensions +/-5 (0.127) unless otherwise specified. 2. thickness includes plating and / or metallization . 85 168 1 84 5250(133.35) 5013.78(127.35) 1700(43.18) 1450(36.83) 2150(54.61) 450(11.43) 250(6.35) 700(17.78) 157.48(4.0) 1375(34.9255) " c" " b" " a" 4550(115.57) detail "b" detail "a" 5.9(0.15) 100(2.54) min. 39.37(1.0) 50(1.27) 78.74(2.0) 39.37(1.0) detail "c" 78.74(2.0) 122.83(3.12) 39.37(1.0) 125(3.175) 125(3.175) unit: mil (mm) * (1 mil = 1/1000 inches) r78.74 (2.0) r78.74 (2.0) ( front side) ( rear side) 50(1.27) 157.48(4.0) min. 170.47(4.33) max.
gmm26417233atg rev. 1.1/dec.99 14 package dimension (-10k) note : 1. tolerances on all dimensions +/-5 (0.127) unless otherwise specified. 2. thickness includes plating and / or metallization . 85 168 1 84 5250(133.35) 5013.78(127.35) 1700(43.18) 1450(36.83) 2150(54.61) 450(11.43) 250(6.35) 700(17.78) 157.48(4.0) 1000(25.4) " c" " b" " a" 4550(115.57) detail "b" detail "a" 5.9(0.15) 100(2.54) min. 39.37(1.0) 50(1.27) 78.74(2.0) 39.37(1.0) detail "c" 78.74(2.0) 122.83(3.12) 39.37(1.0) 125(3.175) 125(3.175) unit: mil (mm) * (1 mil = 1/1000 inches) r78.74 (2.0) r78.74 (2.0) ( front side) ( rear side) 50(1.27) 157.48(4.0) min. 157.48(4.0) max.
sdram memory module eeprom data information GMM26417233ATG-7K 00.05.09 byte function described function support hex code dec code bin code note 0 define # bytes written into serial memory at module mfgr 128 bytes 80 128 10000000 1 total # bytes of spd memory device 256 bytes 08 008 00001000 2 fundamental memory type (fpm, edo, sdram...) from appendix a sdram 04 004 00000100 3 # row addresses on this assembly 12 0c 012 00001100 4 # column addresses on this assembly 10 0a 010 00001010 5 # module banks on this assembly 1 01 001 00000001 6 data width of this assembly... 64 bit 40 064 01000000 7 ...data width continuation n/a 00 000 00000000 8 voltage interface standard of this assembly lvttl 01 001 00000001 9 sdram cycletime 10.0 ns a0 160 10100000 10 sdram access from clock 6.0 ns 60 096 01100000 11 dimm configuration type (non-parity, parity, ecc) none 00 000 00000000 12 refresh rate/type normal(15.625us) 80 128 10000000 13 dram/sdram width, primary dram/sdram x8 08 008 00001000 14 error checking sdram data width n/a 00 000 00000000 15 minimum clock delay, back to back random column address(tccd) 1 ns 01 001 00000001 16 burst lengths supported full page supported 8f 143 10001111 17 # banks on each sdram device 4 banks 04 004 00000100 18 cas # latency 2&3 06 006 00000110 19 cs # latency 0 01 001 00000001 20 write latency 0 01 001 00000001 21 sdram module attributes unbuffer 00 000 00000000 22 sdram device attributes : general support all(vcc:10%) 0f 015 00001111 23 minimum clock cycle time at cl x-1 10.0 ns a0 160 10100000 24 maximum data access time from clock at cl x-1 6.0 ns 60 096 01100000 25 minimum clock cycle time at cl x-2 n/a 00 000 00000000 26 maximum data access time from clock at cl x-2 n/a 00 000 00000000 27 minimum row precharge time(trp) 20 ns 14 020 00010100 28 minimum row active to row active delay(trrd) 20 ns 14 020 00010100 29 minimum ras to cas delay(trcd) 20 ns 14 020 00010100 30 minimum ras pulse width(tras) 50 ns 32 050 00110010 31 module bank density 128 mbytes 20 032 00100000 32 command and address signal input setup time(tas) 2.0 ns 20 032 00100000 33 command and address signal input hold time(tah) 1.0 ns 10 016 00010000 34 data signal input setup time(tds) 2.0 ns 20 032 00100000 35 data signal input hold time(tdh) 1.0 ns 10 016 00010000 36-61 superset information (may be used in future) tbd 00 000 00000000 62 spd revision rev 1.2 12 018 00010010 63 checksum for bytes 0-62 17 023 10111 64 manufacturers jedec id code per jep-106f hme e0 224 11100000 1st group 65-71 ?.. continuation manufacturers jedec id code 00 000 00000000 72 manufacturing location korea 52 082 01010010 82d(free) 73 manufacturer's part number GMM26417233ATG-7K 47 071 01000111 g 74 === allowed characters include 0-9, a-z and 'space' === 4d 077 01001101 m 75 4d 077 01001101 m 76 32 050 00110010 2 77 36 054 00110110 6 78 34 052 00110100 4 79 31 049 00110001 1 80 37 055 00110111 7 81 32 050 00110010 2 82 33 051 00110011 3 83 33 051 00110011 3 84 41 065 01000001 a 85 54 084 01010100 t 86 47 071 01000111 g 87 2d 045 00101101 - 88 37 055 00110111 7 89 4b 075 01001011 k 90 20 32 00100000 blank 91 revision code rev 0 00 000 00000000 92 revision code 00 000 00000000 93 date code ww 14 020 00010100 20 ww 94 yy 00 000 00000000 0 year 95-98 assembly serial number binary incremental 00 000 00000000 98byte start 99-125 manufacturer specific data n/a 00 000 00000000 126 intel specification for frequency 100 mhz 64 100 01100100 127 intel specfication details for 100mhz support ck0_2_cl2 af 175 10101111 128-135 system integrator's id 00 000 00000000 136-150 system integrator's p/n 00 000 00000000 151-152 system integrator's d/c 00 000 00000000 153-165 system integrator's s/n 00 000 00000000 166 checksum for bytes 128-165 00 000 00000000 167-189 top level system serial no. 00 000 00000000 190-221 open 00 000 00000000 222 checksum for bytes 167-221 00 000 00000000 223-253 open 00 000 00000000 254 checksum for bytes 223-253 00 000 00000000 255 checksum for bytes 0-128 00 000 00000000 source : intel rev. 1.2b
sdram memory module eeprom data information gmm26417233atg-7j 00.05.09 byte function described function support hex code dec code bin code note 0 define # bytes written into serial memory at module mfgr 128 bytes 80 128 10000000 1 total # bytes of spd memory device 256 bytes 08 008 00001000 2 fundamental memory type (fpm, edo, sdram...) from appendix a sdram 04 004 00000100 3 # row addresses on this assembly 12 0c 012 00001100 4 # column addresses on this assembly 10 0a 010 00001010 5 # module banks on this assembly 1 01 001 00000001 6 data width of this assembly... 64 bit 40 064 01000000 7 ...data width continuation n/a 00 000 00000000 8 voltage interface standard of this assembly lvttl 01 001 00000001 9 sdram cycletime 10.0 ns a0 160 10100000 10 sdram access from clock 6.0 ns 60 096 01100000 11 dimm configuration type (non-parity, parity, ecc) none 00 000 00000000 12 refresh rate/type normal(15.625us) 80 128 10000000 13 dram/sdram width, primary dram/sdram x8 08 008 00001000 14 error checking sdram data width n/a 00 000 00000000 15 minimum clock delay, back to back random column address(tccd) 1 ns 01 001 00000001 16 burst lengths supported full page supported 8f 143 10001111 17 # banks on each sdram device 4 banks 04 004 00000100 18 cas # latency 2&3 06 006 00000110 19 cs # latency 0 01 001 00000001 20 write latency 0 01 001 00000001 21 sdram module attributes unbuffer 00 000 00000000 22 sdram device attributes : general support all(vcc:10%) 0f 015 00001111 23 minimum clock cycle time at cl x-1 15.0 ns f0 240 11110000 24 maximum data access time from clock at cl x-1 8.0 ns 80 128 10000000 25 minimum clock cycle time at cl x-2 n/a 00 000 00000000 26 maximum data access time from clock at cl x-2 n/a 00 000 00000000 27 minimum row precharge time(trp) 20 ns 14 020 00010100 28 minimum row active to row active delay(trrd) 20 ns 14 020 00010100 29 minimum ras to cas delay(trcd) 20 ns 14 020 00010100 30 minimum ras pulse width(tras) 50 ns 32 050 00110010 31 module bank density 128 mbytes 20 032 00100000 32 command and address signal input setup time(tas) 2.0 ns 20 032 00100000 33 command and address signal input hold time(tah) 1.0 ns 10 016 00010000 34 data signal input setup time(tds) 2.0 ns 20 032 00100000 35 data signal input hold time(tdh) 1.0 ns 10 016 00010000 36-61 superset information (may be used in future) tbd 00 000 00000000 62 spd revision rev 1.2 12 018 00010010 63 checksum for bytes 0-62 87 135 10000111 64 manufacturers jedec id code per jep-106f hme e0 224 11100000 1st group 65-71 ?.. continuation manufacturers jedec id code 00 000 00000000 72 manufacturing location korea 52 082 01010010 82d(free) 73 manufacturer's part number gmm26417233atg-7j 47 071 01000111 g 74 === allowed characters include 0-9, a-z and 'space' === 4d 077 01001101 m 75 4d 077 01001101 m 76 32 050 00110010 2 77 36 054 00110110 6 78 34 052 00110100 4 79 31 049 00110001 1 80 37 055 00110111 7 81 32 050 00110010 2 82 33 051 00110011 3 83 33 051 00110011 3 84 41 065 01000001 a 85 54 084 01010100 t 86 47 071 01000111 g 87 2d 045 00101101 - 88 37 055 00110111 7 89 4a 074 01001010 j 90 20 32 00100000 blank 91 revision code rev 0 00 000 00000000 92 revision code 00 000 00000000 93 date code ww 14 020 00010100 20 ww 94 yy 00 000 00000000 0 year 95-98 assembly serial number binary incremental 00 000 00000000 98byte start 99-125 manufacturer specific data n/a 00 000 00000000 126 intel specification for frequency 100 mhz 64 100 01100100 127 intel specfication details for 100mhz support ck0_2_cl3 ad 173 10101101 128-135 system integrator's id 00 000 00000000 136-150 system integrator's p/n 00 000 00000000 151-152 system integrator's d/c 00 000 00000000 153-165 system integrator's s/n 00 000 00000000 166 checksum for bytes 128-165 00 000 00000000 167-189 top level system serial no. 00 000 00000000 190-221 open 00 000 00000000 222 checksum for bytes 167-221 00 000 00000000 223-253 open 00 000 00000000 254 checksum for bytes 223-253 00 000 00000000 255 checksum for bytes 0-128 00 000 00000000 source : intel rev. 1.2b

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