features ? supports all fibre channel topologies; arbitrated loop (fc-al) and n_port fabric attachment ? supports class 3 and class 2 (via software) ? 66 mhz, 32/64-bit pci interface ? 1 gigabit/second fibre channel rate ? full duplex support with parallel inbound and outbound processing ? complete hardware handling of entire scsi i/o via fcp on-chip assists ? full initiator and target mode functionality applications ? motherboard integration ? host-based adapters ? storage subsystems ?i 2 o designs description the HPFC-5166A, tachyon ts, is a second-generation controller that leverages extensive experience in fibre channel, established with the original tachyon controller. tachyon ts carries forward the assurance of interoperability and true fibre channel performance. HPFC-5166A tachyon ts 66 mhz pci to fibre channel controller technical data tachyon ts focuses on mass storage applications for any topology that require class 3 and class 2 (via software), and scsi upper layer protocol handling. coupled with a high performance 66 mhz, 32/64-bit pci bus inter- face, tachyon ts provides a cost- effective, high-performance mass storage solution. tachyon architecture tachyon ts continues with the tachyon architecture, a complete hardware-based state machine design. this architecture does not require an additional on- board microprocessor and there- fore avoids reduced performance issues relating to processor cycles per second and access time to firmware. rather, the tachyon architecture is designed to be a single chip fibre channel solution. tachyon ts provides the highest levels of concurrency via numerous independent functional blocks providing parallel processing of data, control, and commands. in addition, these blocks process at hardware speeds versus firmware speeds, and automate the entire scsi i/o in hardware. the result is minimized latency and i/o overhead, coupled with the highest levels of parallel- ism to provide maximum i/o rates and bandwidth. fc-al features in addition to the high-perfor- mance architecture, tachyon ts builds on the tachyon tl with public loop, multiple i/os in the same loop arbitration cycle, loop map, loop broadcast, and loop directed reset while offering 66 mhz pci connectivity. these features allow the designer to achieve higher performance in an arbitrated loop topology. physical layer the physical layer interface is the popular 10-bit wide specification that allows interfacing to a low- cost serializer/deserializer (serdes) ic. the stable, demon- strated performance of the serdes with ber>10 -14 avoids the random occurrences and configuration dependent limita- tions introduced by current integrated implementations that exhibit degraded signal integrity and jitter tolerance.
2 HPFC-5166A block diagram. host data structures scsi
exchange
state table single
frame
queue inbound
message
queue exchange
request
queue inbound
data outbound
data pci local bus dma arbiter multiplexer slave
registers completion
message
manager single
frame
manager exchange
request
manager scsi exchange
manager,
outbound sest
link fetch
manager scsi exchange
manager,
inbound fibre
channel
services inbound
data
manager outbound
sequence
manager os processor/
crc checker elastic
store 10b / 8b
decoder os / crc
generator 8b / 10b
encoder inbound
fifo
manager outbound
fifo
manager frame manager 10-bit interface exchange
memory
interface
3 fibre channel operation fibre channel rate 1 gbit/sec, 100 m bytes/sec, each direction with full duplex support frame payload size up to 1024 bytes topology arbitrated loop, public & private, and n_port fabric attachment classes of operation class 3 and class 2 (via software) upper layer protocol fcp C on-chip automation for complete scsi i/o loop initialization completely hardware-based for high availability arbitrated loop capabilities loop map, loop-directed reset, loop broadcast, loop port bypass buffer-to-buffer credit four via on-chip buffers physical layer interface 10-bit interface link diagnostics link status indicators, internal/external loopback, user-definable signal pins compliance fc-ph, fc-al, fc-al2, fc-plda, fc-fla, fcp , 10-bit profile fibre channel protocol (fcp) for scsi features scsi i/o complete hardware-based management and processing of entire i/o on chip, including multiple data phases initiator and target mode yes, simultaneously maximum # of concurrent i/os 32,768 i/o request queue up to 8,000 commands interrupts per i/o 1 or less arbitration avoidance techniques status and chained commands to the sample al_pa sent in same loop tenancy error recovery simplified error notification and recovery addressability byte-level addressability on all data buffers, inbound and outbound pci dma channels 6 width and rate 32- or 64-bit selectable; 16 to 66 mhz burst transfer rate 528 mbytes/second, guaranteed for length of frame, inbound and outbound (at 64-bit, 66 mhz) dual address cycle support yes voltage 3.3 v, 5 v tolerant external subsystem id support yes additional pci features zero wait state multiple cache line bursting capable up to full frame size, configurable latency timer, 32-byte cache line, boot bios capable advanced configuration and power interface yes, d0 and d3 power management states supported tachyon ts architectural features complete hardware-based design numerous independent functional blocks concurrently processing inbound data, outbound data, control and commands in hardware six dma channels automation of complete i/o on-chip in hardware results in lowest latency and i/o overhead and highest levels of parallelism tachyon ts specifications
command & data management context switching 16-entry on-chip cache for low latency context save and restore, as well as extensive pipelining techniques reduced pci control overhead through the use of local memory option full duplex support yes, independent inbound and outbound fifos with automatic hardware management of buffer-to-buffer credit full scatter/gather list support yes, with support for local and extended scatter/gather lists for unlimited chaining of length/address pairs dma channels 6 to optimize concurrency and pci utilization parity protection all data paths at byte level optional external memory interface interface 32-bit at 66 mhz for 264 mbytes/second memory supported 128 k or 256 k bytes of synchronous static ram for optional low latency control access flash and rom support for boot bios and subsystem vendor id parity protection no test & debug jtag yes full internal scan yes, ieee standard 1149.1 boundary scan hardware debug capability yes link status indicators yes user definable signal pins link up/down, low-speed serial interface or custom packaging package 388-pin plastic ball grid array (pbga). note: heatsink is required for most 66mhz applications. tachyon ts specifications , continued www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies, inc. 5968-5304e (11/99)
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