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dram module KMM364C213CK/cs performance range speed t rac t cac t rc t pc -5 50ns 18ns 90ns 35ns -6 60ns 20ns 110ns 40ns KMM364C213CK/cs fast page mode 2m x 64 dram dimm using 2mx8, 2k refresh , 5v the samsung kmm364c213c is a 2mx64bits dynamic ram high density memory module. the samsung kmm364c213c consists of eight cmos 2mx8bits drams in soj/tsop-ii 300mil package, and two 16bits driver ic in 48pin tssop package mounted on a 168-pin glass-epoxy substrate. a 0.1 or 0.22uf decoupling capacitor is mounted on the printed cir- cuit board for each dram. the kmm364c213c is a dual in- line memory module and is intended for mounting into 168 pin edge connector sockets. general description pd note : pd & id terminals must each be pulled up through a resister to v cc at the next higher level assembly. pds will be either open (nc) or driven to v ss via on-board buffer circuits. id note : ids will be either open (nc) or connected directly to v ss without a buffer. ? part identification - KMM364C213CK (2048 cycles/32ms ref. 300mil soj) - kmm364c213cs (2048 cycles/32ms ref. 300mil tsop) ? fast page mode operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? ttl compatible inputs and outputs ? single 5v 10% power supply ? jedec standard pinout & buffered pdpin ? buffered input except ras and dq ? pcb : height(1000mil), single sided component pin names pins marked * are not used in this module. pin names function a0, b0, a1 - a10 address input (2k ref.) dq0 - dq71 data in/out w0 , w2 read/write enable oe0 , oe2 output enable ras0 , ras2 row address strobe cas0 ~ cas7 column address strobe v cc power(+5v) v ss ground nc no connection pde presence detect enable pd1 - 8 presence detect id0 - 1 id bit rsvd reserved use rfu reserved for future use pd & id table pd : 0 for vol of drive ic & 1 for n.c id : 0 for vss & 1 for n.c pin 50ns 60ns pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 1 0 0 1 0 0 0 1 1 0 0 1 0 1 1 1 id0 id1 0 0 0 0 pin configurations pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 front v ss dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 *dq8 v ss dq9 dq10 dq11 dq12 dq13 v cc dq14 dq15 dq16 *dq17 v ss rsvd rsvd v cc w0 cas0 pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 front cas2 ras0 oe0 v ss a0 a2 a4 a6 a8 a10 *a12 v cc rfu rfu v ss oe2 ras2 cas4 cas6 w2 v cc rsvd rsvd dq18 dq19 v ss dq20 dq21 pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 front dq22 dq23 v cc dq24 rfu rfu rfu rfu dq25 *dq26 dq27 v ss dq28 dq29 dq30 dq31 v cc dq32 dq33 dq34 *dq35 v ss pd1 pd3 pd5 pd7 id0 v cc pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 back v ss dq36 dq37 dq38 dq39 v cc dq40 dq41 dq42 dq43 *dq44 v ss dq45 dq46 dq47 dq48 dq49 v cc dq50 dq51 dq52 *dq53 v ss rsvd rsvd v cc rfu cas1 pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 back cas3 * ras1 rfu v ss a1 a3 a5 a7 a9 *a11 *a13 v cc rfu b0 v ss rfu * ras3 cas5 cas7 pde v cc rsvd rsvd dq54 dq55 v ss dq56 dq57 pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 back dq58 dq59 v cc dq60 rfu rfu rfu rfu dq61 *dq62 dq63 v ss dq64 dq65 dq66 dq67 v cc dq68 dq69 dq70 *dq71 v ss pd2 pd4 pd6 pd8 id1 v cc features
dram module KMM364C213CK/cs functional block diagram vcc vss 0.1 or 0.22uf capacitor under each dram to all drams a0 b0 a1-an w 0, 2 oe 0, 2 u0-u3 u4-u7 a1-an : u0-u7 ras0 w0 oe0 a0 u0 a1-a10 ras2 w2 oe2 b0 a1-a10 cas1 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 u1 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 cas2 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 u2 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 cas3 dq27 dq28 dq29 dq30 dq31 dq32 dq33 dq34 u3 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 u4 cas5 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 u5 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 cas6 dq54 dq55 dq56 dq57 dq58 dq59 dq62 dq61 u6 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 cas7 dq63 dq64 dq65 dq66 dq67 dq68 dq69 dq70 u7 dq0 dq1 dq2 dq3 dq4 dd5 dq6 dq7 cas0 cas4
dram module KMM364C213CK/cs i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one page mode cycle, t pc . * note : dc and operating characteristics (recommended operating conditions unless otherwise noted) i cc1 * i cc2 i cc3 * i cc4 * i cc5 i cc6 * i i(l) i o(l) v oh v ol symbol speed KMM364C213CK/cs unit min max i cc1 -5 -6 - - 880 800 ma ma i cc2 don t care - 100 ma i cc3 -5 -6 - - 880 800 ma ma i cc4 -5 -6 - - 720 640 ma ma i cc5 don t care - 30 ma i cc6 -5 -6 - - 880 800 ma ma i i(l) i o(l) don t care -40 -5 40 5 ua ua v oh v ol don t care 2.4 - - 0.4 v v : operating current * ( ras , cas , address cycling @ t rc =min) : standby current ( ras = cas = w =v ih ) : ras only refresh current * ( cas =v ih , ras cycling @ t rc =min) : fast page mode current * ( ras =v il , cas cycling : t pc =min) : standby current ( ras = cas = w =vcc-0.2v) : cas -before- ras refresh current * ( ras and cas cycling @ t rc =min) : input leakage current (any input 0 v in vcc+0.5v, all other pins not under test=0 v) : output leakage current(data out is disabled, 0v v out vcc) : output high voltage level (i oh = -5ma) : output low voltage level (i ol = 4.2ma) recommended operating conditions (voltage referenced to v ss , t a = 0 to 70 c) *1 : v cc +2.0v/ 20ns, pulse width is measured at v cc . *2 : -2.0v/ 20ns, pulse width is measured at v ss . item symbol min typ max unit supply voltage ground input high voltage input low voltage v cc v ss v ih v il 4.5 0 2.4 -1.0 *2 5.0 0 - - 5.5 0 v cc +1 *1 0.8 v v v v absolute maximum ratings * * permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for in tended periods may affect device reliability. item symbol rating unit voltage on any pin relative v ss voltage on v cc supply relative to v ss storage temperature power dissipation short circuit output current v in , v out v cc t stg p d i os -1 to +7.0 -1 to +7.0 -55 to +125 8 50 v v c w ma
dram module KMM364C213CK/cs capacitance (t a = 25 c, vcc=5v, f = 1mhz) item symbol min max unit input capacitance[a0-a10, b0] input capacitance[ w0 , w2 , oe0 , oe2 ] input capacitance[ ras0 , ras2 ] input capacitance[ cas0 ~ cas7 ] input/output capacitance[dq0 - 71] c in1 c in2 c in3 c in4 c dq1 - - - - - 15 17 38 17 17 pf pf pf pf pf ac characteristics (0 c t a 70 c, v cc =5.0v 10% . see notes 1,2.) test condition : v ih /v il =2.4/0.8v, v oh /v ol =2.4/0.4v, output loading cl=100pf parameter symbol -5 -6 unit note min max min max random read or write cycle time t rc 90 110 ns read-modify-write cycle time t rwc 133 155 ns access time from ras t rac 50 60 ns 3,4 access time from cas t cac 18 20 ns 3,4,5,11 access time from column address t aa 30 35 ns 3,10,11 cas to output in low-z t clz 5 5 ns 3,11 output buffer turn-off delay t off 5 18 5 20 ns 6,11 transition time(rise and fall) t t 2 50 2 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 18 20 ns 11 cas hold time t csh 48 58 ns 11 cas pulse width t cas 13 10k 15 10k ns ras to cas delay time t rcd 18 32 18 40 ns 4,11 ras to column address delay time t rad 13 20 13 25 ns 10,11 cas to ras precharge time t crp 10 10 ns 11 row address set-up time t asr 5 5 ns 11 row address hold time t rah 8 8 ns 11 column address set-up time t asc 0 0 ns column address hold time t cah 10 10 ns column address to ras lead time t ral 30 35 ns 11 read command set-up time t rcs 0 0 ns read command hold referenced to cas t rch 0 0 ns 8 read command hold referenced to ras t rrh -2 -2 ns 8,11 write command hold time t wch 10 10 ns write command pulse width t wp 10 10 ns write command to ras lead time t rwl 18 20 ns 11 write command to cas lead time t cwl 13 15 ns data set-up time t ds -2 -2 ns 9,11 data hold time t dh 15 20 ns 9,11 refresh period (2k refresh) t ref 32 32 ms write command set-up time t wcs 0 0 ns 7 cas to w delay time t cwd 36 40 ns 7 column address to w delay time t awd 48 55 ns 7 cas precharge to w delay time t cpwd 53 60 ns 7
dram module KMM364C213CK/cs test condition : v ih /v il =2.4/0.8v, v oh /v ol =2.4/0.4v, output loading cl=100pf parameter symbol -5 -6 unit note min max min max ras to w delay time t rwd 71 83 ns 7,11 cas setup time( cas -before- ras refresh) t csr 10 10 ns 11 cas hold time( cas -before- ras refresh) t chr 8 8 ns 11 ras precharge to cas hold time t rpc 3 3 ns 11 access time from cas precharge t cpa 35 40 ns 3,11 fast page mode cycle time t pc 35 40 ns fast page mode read-modify-write cycle time t prwc 75 80 ns cas precharge time(fast page cycle) t cp 10 10 ns ras pulse width (fast page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 35 40 ns 11 w to ras precharge time ( c -b- r refresh) t wrp 15 15 ns 11 w to ras hold time ( c -b- r refresh) t wrh 8 8 ns 11 oe access time t oea 18 20 ns 11 oe to data delay t oed 18 20 ns 11 output buffer turn off delay time from oe t oez 5 5 20 ns 11 oe command hold time t oeh 13 15 ns pde to valid pd bit t pd 10 10 ns pde to pd bit inactive t pdoff 2 7 2 7 ns present detect read cycle ac characteristics (0 c t a 70 c, v cc =5.0v 10% . see notes 1,2.)
dram module KMM364C213CK/cs notes an initial pause of 200us is required after power-up followed by any 8 ras -only or cas -before- ras refresh cycles before proper device operation is achieved. input voltage levels are vih/vil. v ih (min) and v il (max) are ref- erence levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 2 ttl loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs is not restrictive operating parameter. it included in the data sheet as electrical characteristic only. if t wcs 3 t wcs (min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to the cas leading edge in early write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . the timing skew from the dram to the dimm resulted from the addition of buffers. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
dram module KMM364C213CK/cs t crp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq read cycle column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open data-out t oez t rrh t rch don t care undefined t rcs t off
dram module KMM364C213CK/cs t wcs write cycle ( early write ) note : d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp t ds t dh t wch t cwl t rwl don t care data-in undefined
dram module KMM364C213CK/cs t oed ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp data-in t wp don t care write cycle ( oe controlled write ) note : d out = open t cwl t rwl t ds t dh t oeh undefined
dram module KMM364C213CK/cs ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care read - modify - wrtie cycle t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address
dram module KMM364C213CK/cs t rch t oez t clz ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq column address row addr t rhcp t rasp t cas t asc t rad t asr t rah t asc t cah t crp valid don t care fast page read cycle t oez t rrh data-out undefined valid data-out note : d out = open column address column address t rsh t cas t rcd t pc ? t csh t cah t asc t cah ? ? ? t rch ? t rcs t rcs t rcs t oea t cac t oea t cac t oea t cac valid data-out t clz t off t aa t off t aa t clz t off t oez t rac t aa ? ? t cp t cas t rp t cp
dram module KMM364C213CK/cs t asc t cah ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row addr t rhcp t rasp t cas t rad t asr t rah t asc t crp valid don t care fast page write cycle ( early write ) data-in undefined valid data-in t ds note : d out = open column address column address t rsh t cas t rcd t pc ? t csh t cah t asc t cah ? ? ? t wcs t wch t wcs valid data-in ? ? t wp t cwl t wp t wch t wp t wcs t wch t cwl t rwl t cwl t dh t ds t dh t ds t dh ? ? ? t rp t cp t cp t cas t pc
dram module KMM364C213CK/cs t cac t asc t asc ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq row addr t csh t rasp t asr valid don t care fast page read - modify - write cycle data-out undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t cah t ral t prwc t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed valid data-in valid data-out valid data-in t clz t ds t oea t aa t dh t ds t oez t oed t rwl t rp t rsh t rah
dram module KMM364C213CK/cs ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t ras t rc t rp t asr t rah t crp don t care ras - only refresh cycle undefined note : w , oe , d in = don t care d out = open t rpc t crp cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t wrp t rpc t rp t cp t chr t csr w v ih - v il - t wrh t off t rpc v oh - v ol - dq open
dram module KMM364C213CK/cs t wrh t off ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq hidden refresh cycle ( read ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp t rcs t aa t oea t cac t clz t rac open t rrh don t care t rsh t oez t wrp undefined t rc data-out t rp t rp t ras
dram module KMM364C213CK/cs ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq hidden refresh cycle ( write ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp don t care t rsh data-in t wrp t wrh undefined t rc note : d out = open t wch t wp t dh t rp t rp t ras t ds t wcs
dram module KMM364C213CK/cs cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - data-out dq t off t clz write cycle v ih - v il - data-in dq t dh t ds w v ih - v il - t wp t cwd t cwl t rwl read-modify-write t awd v ih - v il - oe t oea t aa t cac t ds t dh valid data-out v i/oh - v i/ol - dq don t care undefined v ih - v il - oe t oea t oez oe v ih - v il - t rcs t clz t oez t oed t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl t wrp t wrh valid data-in note : this timing diagram is applied to all devices besides 16m dram 4th & 64m dram.
dram module KMM364C213CK/cs don t care undefined cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rass t rps t rpc t wrp t chs t rp t cp t csr w v ih - v il - t wrh t off t rpc open v oh - v ol - dq test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t ras t rc t rp t rpc t wts t rpc t rp t cp t chr t csr w v ih - v il - t wth t off open v oh - v ol - dq
dram module KMM364C213CK/cs package dimensions units : inches (millimeters) 5.250 5.014 0.050 0.039 .002 0.010max (0.250 max) 0.100max (2.54max ) 0.050 0.0039 (1.270 0.10) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 7 0 0 ( 1 7 . 7 8 0 ) (1.000 . 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c .118dia .004 (3.000dia .100) (8.890) a b c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100 ) 0.054 (1.372) (127.350) (133.350) 1 . 0 0 0 ( 2 5 . 4 0 ) 0.118 (3.000) 0.250 (6.350 ) detail a 0.123 .005 (3.125 .125) 0.250 (6.350 ) detail b 0.123 .005 (3.125 .125) 0.079 .004 (2.000 .100) 0.079 .004 (2.000 .100) 0 . 1 1 8 ( 3 . 0 0 0 ) 0 . 2 0 0 m i n ( 5 . 0 8 m i n ) ( back view ) ( front view ) (tsop ) 0.200max (5.08max ) (soj ) tolerances : .005(.13) unless otherwise specified the used device is 2mx8 dram with fast page mode, soj or tsop ii (forward). dram part no. : KMM364C213CK - km48c2100ck kmm364c213cs - km48c2100cs

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