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lh5481 LH5491 features fastest 64 8/9 cascadable fifo 35/25/15 mhz expandable in word width and fifo depth almost-full/almost-empty and half-full flags fully independent asynchronous inputs and outputs lh5481 output enable forces data outputs to high-impedance state pin-compatible replacements for cypress cy7c408a/09a or logic devices l8c408/09 fifos industry standard pinout packages: 28-pin, 300-mil dip 28-pin plcc functional description the lh5481 and LH5491 are high-performance, asyn- chronous first-in, first-out (fifo) memories organized 64 words deep by eight or nine bits wide. the eight-bit lh5481 has an output enable ( oe) function, which can be used to force the eight data outputs (do) to a high-im- pedance state. the LH5491 has nine data outputs. these fifos accept eight or nine- bit data at the data inputs (di). a shift in (si) signal writes the di data into the fifo. a shift out (so) signal s hifts stored data to the data outputs (do). the output ready (or) signal indicates when valid data is present on the do outputs. if the fifo is full and unable to accept more di data, input ready (ir) will not ret urn high, and si pulses will be ignored. if the fifo is empty and unable to shift data to the do outputs, or will not return high, and so pulses will be ignored. the almost-full/almost-empty (afe) flag is asserted (high) when the fifo is almost-full (56 words or more) or almost- empty (eight words or less). the half-full ( hf) flag is asserted (high) when the fifo contains 32 words or more. reading and writing operations may be asynchronous, allowing these fifos to be used as buffers between digital machines of different operating frequencies. the high speed makes these fifos ideal for high perform- ance communication and controller applications. pin connections 5481-1d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 afe hf ir si di 0 di 1 v ss di 2 di 3 di 4 di 5 di 6 di 7 nc/di 8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc mr so or do 0 do 1 v ss do 2 do 3 do 4 do 5 do 6 do 7 oe/do 8 28-pin pdip top view figure 1. pin connections for dip package 5481-2d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 di 0 di 1 di 2 di 3 di 4 di 5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 or do 0 do 1 do 2 do 3 do 4 si ir hf afe v cc mr so di 6 di 7 nc/di 8 oe/do 8 do 7 do 6 do 5 28-pin plcc top view v ss v ss figure 2. pin connections for plcc package cascadable 64 8 fifo cascadable 64 9 fifo 1
pin descriptions pin pin type * description di 0 C di 7 i data inputs, lh5481 do 0 C do 7 o/z data outputs, lh5481 di 0 C di 8 i data inputs, LH5491 do 0 C do 8 o data outputs, LH5491 si i shift in so i shift out ir o input ready or o output ready * i = input, o = output, z = hi gh-impedance, v = power voltage level pin pin type * description hf o half- full flag afe o almost-full / almost- empty mr i master reset oe i output enable (lh5481 only) v cc v positive power supply v ss v ground 5481-3 write pointer write multiplexer memory array read multiplexer read pointer input control logic data in master reset si ir (LH5491) di 0 - di 8 (lh5481) di 0 - di 7 mr almost-full/ almost-empty half-full data out output control logic afe hf do 0 do 7 or so do 8 (LH5491) oe (lh5481) . . . . . . figure 3. lh5481/91 block diagram lh5481/91 64 8 / 64 9 fifo 2
absolute maximum ratings 1,2 parameter ra ting vcc range C 0.5 v to 7 v input voltage range C0.5 v to vcc + 0.5 v (not to exceed 7 v) dc output current 3 40 ma storage temperature C65 o c to 150 o c dc voltage applied to outputs in high-z state C 0.5 v to vcc + 0.5 v (not to exceed 7 v) static discharge volt age 4 > 2000 v power dissipation (package limit) 1.0 w notes: 1. all voltages are me asured with respect to vss. 2. stresses greater than th ose li sted under absol ute max imum rati ngs may ca use permanent damage to the device. this is a stress rating for t ransient conditions only. functional operation of the device at these or any other cond itions above those indicated in the operating range of this spe cification is not impli ed. exposure to absolute maximum rating conditions for extended peri ods may affect device reliability. 3. outputs should not be shorted for more than 30 seconds. no more than one output should be shorted at any time. 4. sample tested only. operating range 1 parameter description min max unit t a temperature, ambient 0.0 70 o c v cc supply voltage 4.5 5.5 v vss ground 0.0 0.0 v v il input low voltage (logic 0) 2 C 0.5 0.8 v v ih input high voltage ( logic 1) 2.0 vcc + 0.5 v notes: 1. all voltages are me asured with respect to vss. 2. fifo inputs are able to withstand a C 1.5 v undersh oot for less than 10 ns per cycle. dc electrical characteristics 1 (over operating range unless otherwise noted) parameter description test con ditions min max unit i li input leakage current v cc = 5.5 v, v in = 0 v to v cc C10 10 m a i lo output leakage current (high-z) v cc = 5.5 v, v out = 0 v to v cc C10 10 m a v oh output high voltage v cc = 4.5 v, i oh = C4 ma 2.4 v v ol output low voltage v cc = 4.5 v, i ol = 8.0 ma 0.4 v i ccq power supply quiescent current v cc = 5.5 v, i out = 0 ma v in v il, v in 3 v ih 25 ma i cc power supply current 2 fsi = 35 mhz, fso = 35 mhz 45 ma notes: 1. all voltages are me asured with respect to vss. 2. icc is d epend ent u pon actual output loading and cycle rates. specified values are with outputs open. 64 8 / 64 9 fifo lh5481/91 3
ac test conditions 1 parameter rating input pulse levels 0 to 3 v input rise and fall times (10% / 90%) figure 4a input timing reference levels 1.5 v output timing reference levels 1.5 v output load for ac timing tests figure 4b note: 1. all voltages are measured with respect to vss. capacitance 1,2 parameter description test con ditions rating c in input capacitance t a = 25 c, f = 1 mhz, v cc = 4.5 v 5 pf c out output capacitance t a = 25 o c, f = 1 mhz, vcc = 4.5 v 7 pf notes: 1. all voltages are measured with respect to vss. 2. sample tested only. 167 w 1.73 v device under test cl = 30 pf * 5481-4 * includes jig and scope capacitances figure 4b. output load circuit gnd 10% 10% 90% 90% 5 ns 5 ns 5481-18 3.0 v figure 4a. input rise and fall times lh5481/91 64 8 / 64 9 fifo 4
ac electrical c haract eristics 1 (over operating range) symbol parameter 15mhz 25mhz 35mhz units min max min max min max f o operating frequency 2 15 25 35 mhz t phsi si high time 3,8 15 11 9 ns t plsi si low time 3,8 20 18 17 ns t ssi data setup to si 4 C1 C1 C1 ns t hsi data hold from si 4 14 12 10 ns t dlir delay, si high to ir low 20 18 16 ns t dhir delay, si low to ir high 24 20 18 ns t phso so high time 3 15 11 9 ns t plso so low time 3 20 18 17 ns t dlor delay, so high to or low 20 18 16 ns t dhor delay, so low to or high 24 20 18 ns t sor data setup to or high C1 C1 C1 ns t hso data hold from so low 0 0 0 ns t ft fallthrough time 36 34 30 ns t bt bubblethrough time 28 26 25 ns t sir data setup to ir 5 555ns t hir data hold from ir 5 555ns t pir input ready pulse high 8 777ns t por output ready pulse high 8 777ns t dlzoe oe low to low z (lh5481) 6,9 35 30 25 ns t dhzoe oe high to high z (lh5481) 6,9 35 30 25 ns t dhhf si low to hf high 40 40 36 ns t dlhf so low to hf low 40 40 36 ns t dlafe so or si low to afe low 40 40 36 ns t dhafe so or si low to afe high 40 40 36 ns t pmr mr pulse width 35 35 35 ns t dsi mr high to si high 25 25 22 ns t dor mr low to or low 7 25 25 20 ns t dir mr low to ir high 7 25 25 20 ns t lxmr mr low to output low 7 25 25 20 ns t afe mr low to afe high 30 30 30 ns t hf mr low to hf low 30 30 30 ns t od so low to next data out valid 26 22 20 ns notes: 1. all time measurements performed at ac test c onditio ns. 2. f o = f si = f so . 3. t phsi + t plsi = t phso + t plso = i/f o . 4t ssi and t hsi apply when memory is not full. 5. t sir and t hir apply when memory is full and si is high. 6. high-z transitions are referenced to the steady-state v oh C 500 mv and v ol + 500 mv levels on the output. 7. after reset goes low, all data outputs will be at low level, ir goes high and or goes low. 8. common dash number devices are guaranteed by design to function properly in a casc aded configuration. 64 8 / 64 9 fifo lh5481/91 5
operational description unlike earlier versions of fifos, the lh5481 and LH5491 use dual-port random-access-memory, write and read pointers, and special control logic. the write pointer is incremented by the falling edge of the shift in (si) signal, while the read pointer is incremented by the falling edge of the shift out (so) signal. the input ready (ir) signal enables data writing to the fifo. the output ready (or) signal indicates valid read information is available on the data output (do) pins. resetting the fifo the fifo must be reset, upon power-up, using the master reset ( mr) signal. this causes the fifo to enter an empty state, indicated by the output ready (or) being low and input ready (ir) being high. all data output (do) pins will be low in this state. the afe flag w ill be high, and the hf flag will be low. if shift in (si) is high, when the master reset ( mr) signal is ended, then the data on the data input (di) pins will be written into the fifo, and input ready (ir) will return low until shift in (si) is brought low. if shift in (si) is low when the master reset ( mr) is deasserted, then input ready (ir) goes high, but the data on the data input (di) pins does not enter the fifo until shift in (si) goes high. shifting data in data input (di) is shifted into the fifo on the rising edge of shift in (si). this loads input data into the fifo, and causes input re ady (ir) to go low. when a falling edge of shift in (si) occurs,the write pointer increments to the next word position, and input ready (ir) goes high, indicating that the fifo is ready to accept new data. when the fifo is full, input ready (ir) remains low after the negative edge of shift in (si) signal; shift out (so) action is required to unload a word of data and bring input ready (ir) high. (see bubblethrough con- dition des cription.) shifting data out data is shifted out of the fifo on the falling edge of shift out (so). the read pointer increments to the next word location; fifo data, if present, appears on the data output (do) pins; and the output ready (or) signal goes high. if fifo data is not present, output ready (or) stays low, indicating that the fifo is empty; in this case, the last valid data read from the fifo re mains on the data output (do) pins. w hen the fifo is not empty, output ready (or) goes low after the rising edge of shift out (so). the previous data remains on the data output (do) pins until a falling edge of shift out (so). fallthrough condition when the fifo is empty, a data word entering through the shift in (si) action follows one of two seq uences. if shift out (so) is low, the data propagates to the data output (do) pins; and output ready (or) goes high and stays high until the next rising edge of shift out (so). if shift out (so) is held high while data is shifted into an empty fifo as occurs in depth cascading of fifos, data propagates to the data output (do) pins, and output ready (or) pulses high for a minimum time duration specified by t por and then goes back low again. the stored word remains on the data output (do) pins. if more words are written into the fifo, they line up behind the first word, and do not appear on the data output (do) pins until shift out (so) has returned low. bubblethrough condition when the fifo is full, shift out (so) action initiates one of the following two sequences: if shift in (si) is low, input ready (ir) goes high and stays high until the next rising edge of shift in (si). if shift in (si) is held high while data is shifted out of a full fifo, as occurs in depth cascading of fifos, input ready (ir) pulses high for a minimum time duration specified by t pir , and then goes back low again. special data input (di) setup and hold times (t sir and t hir , respectively) are defined for this condition. lh5481/91 64 8 / 64 9 fifo 6
timing diagrams 5481-5 shift in input ready data in afe hf 1/fo 1/fo t phsi t plsi t dhir t hsi t dlafe t ssi (low) * t dlir * note: fifo contains 8 words figure 5. data in timing 5481-6 shift out output ready data out afe hf 1/fo 1/fo t phso t plso t dhor t hso (low) ** t dlor t sor t dhafe ** note: fifo contains 9 words t od figure 6. data out timing 64 8 / 64 9 fifo lh5481/91 7
timing diagrams (contd) 5481-7 shift in input ready data in afe hf 1/fo 1/fo t phsi t plsi t dhir t ssi (low) *** t dlir t dhhf t hsi *** note: fifo contains 31 words figure 7. data in timing 5481-8 shift out output ready data out hf afe 1/fo 1/fo t phso t plso t dhor t hso t dlhf (low) **** t dlor t sor **** note: fifo contains 32 words t od figure 8. data out timing lh5481/91 64 8 / 64 9 fifo 8
timing diagrams (contd) 5481-9 shift in input ready data in hf afe 1/fo 1/fo t phsi t plsi t dhir t ssi (high) ***** t dlir t dhafe t hsi ***** note: fifo contains 55 words figure 9. data in timing 5481-10 shift out output ready data out 1/fo 1/fo t phso t plso t dhor t hso t dlafe (high) ****** t dlor t sor afe hf ****** note: fifo contains 56 words t od figure 10. data out timing 64 8 / 64 9 fifo lh5481/91 9
timing diagrams (contd) 5481-11 shift out shift in input ready t pir data in t hir t sir t bt figure 11. bubblethrough timing (reading a full fifo) 5481-12 shift out shift in output ready t por data out t ft t sor figure 12. fallthrough timing (writing an empty fifo) lh5481/91 64 8 / 64 9 fifo 10
timing diagrams (contd) 5481-13 master reset input ready output ready shift in t dir t pmr t dor t lxmr t dhf t dafe t dsi data out hf afe figure 13. master reset timing 64 8 / 64 9 fifo lh5481/91 11
timing diagrams (contd) 5481-14 shift in . . . . . . . . . . . . empty hf afe 2 1 8 9 10 31 32 33 55 56 57 64 full figure 14. shifting words in 5481-15 shift out . . . . . . . . . . . . empty hf afe 1 31 32 30 full 7 8 9 54 55 56 63 64 figure 15. shifting words out lh5481/91 64 8 / 64 9 fifo 12
fifo expansion 5481-16 ir si di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 so or do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 256 x 8/9 mr ir si di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 so or do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 64 x 8/9 mr ir si di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 so or do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 256 x 8/9 mr ir si di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 so or do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 64 x 8/9 mr ir si di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 so or do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 256 x 8/9 mr ir si di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 so or do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 64 x 8/9 mr hf/afe hf/afe shift out mr shift in composite input ready composite output ready figure 16. 320 24/27 conf iguration using 64 8/9 (lh5481/91) & 256 8/9 (lh5485/95) fifos 64 8 / 64 9 fifo lh5481/91 13
fifo expansion (contd) fifos are expandable in depth and width. however, in forming wider words, external logic is required to gen- erate composite input ready and output ready flags. this is due to the variation of delays of the fifos. for example, the circuit of figure 16 uses simple and gates as the external ir and or generators. more complex logic may be required if fallthrough and bubblethrough pulses are needed by the external system. fifos can be easily cascaded to any desired depth, as illustrated in figure 17. the handshaking and associ- ated timing between the fifos are handled by the inher- ent timing of the devices. notes: 1. when the memory is empty, the last word read remains on the out- puts until master reset is strobed, or a new data word bubbles through to the output. however, or remains low, indic ating that the data word at the output is not valid. 2. when the output data word cha nges as a result of a pulse on so, the or signal always goes low before the output data word changes and st ays low until a new data word has appeared at the outputs. anytime or is high, there is valid stable data on the outputs. 3. all sharp fifos can be cascaded with other sharp fifos of the same architecture (i. e., 64 8/9 with 64 8/9). however, they may not cascade w ith fifos from other manufacturers. 5481-17 si ir di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 or so do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 256 x 8/9 mr si ir di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 di 8 or so do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 do 8 64 x 8/9 mr hf/afe shift in input ready data in output ready shift out data out mr hf/afe figure 17. 128 8/9 configuration lh5481/91 64 8 / 64 9 fifo 14
package diagrams 28sk-dip (dip028-p-0300) dimensions in mm [inches] maximum limit minimum limit 114 15 28 28dip-1 7.05 [0.278] 6.65 [0.262] 0.51 [0.020] min. 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] typ. 0.56 [0.022] 0.36 [0.014] 0.35 [0.014] 0.15 [0.006] detail 35.00 [1.378] 34.40 [1.354] 0 to 15 3.65 [0.144] 3.25 [0.128] 7.62 [0.300] typ. 28-pin, 300-mil pdip 28plcc maximum limit minimum limit dimensions in mm [inches] 28plcc (plcc28-p-s450) 1.27 [0.050] basic non-accum 12.57 [0.495] 12.32 [0.485] 0.10 [0.004] 1.22 [0.048] 1.07 [0.042] x 45 12.57 [0.495] 12.32 [0.485] 0.51 [0.020] min. 10.92 [0.430] 9.91 [0.390] detail 11.56 [0.455] 11.43 [0.450] 11.56 [0.455] 11.43 [0.450] 0.81 [0.032] 0.66 [0.026] 2.79 [0.110] 2.52 [0.099] 0.53 [0.021] 0.33 [0.013] 4.57 [0.180] 4.19 [0.165] 28-pin, 450-mil plcc 64 8 / 64 9 fifo lh5481/91 15
ordering information lh#### device type x package - ## speed examples: lh5481d-25 (64 x 8 fifo, 28-pin, 300-mil pdip, 25 mhz) LH5491u-35 (64 x 9 fifo, 28-pin plcc, 35 mhz) 5481md d 28-pin, 300-mil pdip (dip028-p-0300) u 28-pin plastic leaded chip carrier (plcc28-p-s450) 5481 64 x 8 fifo 5491 64 x 9 fifo 15 25 frequency (mhz) 35 lh5481/91 64 8 / 64 9 fifo 16

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