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tl/dd12869 cop8acc7 8-bit one time programmable (otp) microcontroller with high resolution a/d conversion preliminary october 1996 cop8acc7 8-bit one time programmable (otp) microcontroller with high resolution a/d conversion general description the cop8acc7 otp microcontroller is a member of the cop8 tm feature family using an 8-bit core architecture. it is pin and software compatible to the mask rom cop8acc5 product family. (continued) key features y analog function block for high resolution a/d including e analog comparator with seven input muxes e constant current source and v cc/2 reference e 16-bit capture timer (upcounter) clocked from cki with auto reset on timer startup y quiet design (reduced radiated emissions) y 4096 bytes on-board otp eprom with security feature y 128 bytes on-board ram additional peripheral features y idle timer y one 16-bit timer with two 16-bit registers supporting: e processor independent pwm mode e external event counter mode e input capture mode y multi-input wake-up (miwu) with optional interrupts (4) y watchdog tm and clock monitor logic y microwire/plus tm serial i/o with programmable shift clock-polarity i/o features y memory mapped i/o y software selectable i/o options (tri-state output, push-pull output, weak pull-up input, high impedance input) y high current outputs y schmitt trigger inputs on ports g and l y packages: 28 dip/so with 24 i/o pins 20 so with 16 i/o pins cpu/instruction set features y 1 m s instruction cycle time y eight multi-source vectored interrupt servicing e external interrupt e idle timer t0 e timer t1 associated interrupts e microwire/plus e multi-input wake up e software trap e default vis e a/d (capture timer) y versatile and easy to use instruction set y 8-bit stack pointer (sp)estack in ram y two 8-bit registers indirect data memory pointers (b and x) fully static cmos y low current drain (typically k 5 m a) y two power saving modes: halt and idle y single supply operation: 2.7v to 5.5v y temperature ranges: 0 cto a 70 c, b 40 cto a 85 c, development system y emulation device for cop8acc5 y real time emulation and full program debug offered by metalink development system applications y battery chargers y appliances y data acquisition systems tri-state is a registered trademark of national semiconductor corporation. microwire/plus tm , cop8 tm , microwire tm and watchdog tm are trademarks of national semiconductor corporation. ibm ,pc , and pc-xt are registered trademarks of international business machines corporation. icemaster tm is a trademark of metalink corporation. c 1996 national semiconductor corporation rrd-b30m116/printed in u. s. a. http://www.national.com
block diagram tl/dd/12869 1 figure 1. block diagram http://www.national.com 2
general description (continued) the device provides up to 6 channels of a/d performing a measurement with 12 bits of resolution in less than 0.5 ms at a clock-rate of 10 mhz. there is only an external capaci- tor required to complete the measurement setup and estab- lishing low cost, high-resolution (up to 16 bits) and accurate a/d. this device is a complete microcomputer containing all sys- tem timing, interrupt logic, rom, ram, and i/o necessary to implement dedicated control functions in a variety of ap- plications. features include an 8-bit memory mapped archi- tecture, microwire/plus serial i/o, one 16-bit pwm-tim- er with two autoreload registers, multi-sourced interrupts an analog function block and an idle timer watchdog. each i/o pin has software selectable options to adapt the device to the specific application. the device operates over a volt- age range of 2.7v to 5.5v. high throughput is achieved with an efficient, regular instruction set operating at a minimum of 2 ms per instruction cycle. connection diagrams tl/dd/12869 2 top view order number cop8acc728n9, cop8acc728n8 or cop8acc728n6 see ns molded package number n28a order number cop8acc728m9, cop8acc728m8 or cop8acc728m6 see ns molded package number m28b tl/dd/12869 3 top view order number cop8acc720m9, cop8acc720n8 or cop8acc720m6 see ns molded package number m20b figure 2. connection diagrams http://www.national.com 3
connection diagrams (continued) pinouts for 28-pin, 20-pin packages port type alt. fun alt. fun 28-pin 20-pin dip/so so l4 i/o miwu ext. int. 4 l5 i/o miwu ext. int. 5 l6 i/o miwu ext. int. 6 l7 i/o miwu ext. int. 7 g0 i/o int 23 15 g1 wdout 24 16 g2 i/o t1b 25 17 g3 i/o t1a 26 18 g4 i/o so 27 19 g5 i/o sk 28 20 g6 i si 1 1 g7 i/cko halt restart 2 2 d0 o 11 7 d1 o 12 8 d2 o 13 9 d3 o 14 i0 i analog ch1 15 10 i1 i i src 16 11 i2 i analog ch2 17 12 i3 i analog ch3 18 13 i4 i analog ch4 19 14 i5 i analog ch5 20 i6 i analog ch6 21 i7 i c out 22 v cc 95 gnd 8 4 cki 3 3 reset 10 6 http://www.national.com 4
absolute maximum ratings if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. supply voltage (v cc )7v voltage at any pin b 0.3v to v cc a 0.3v total current into v cc pin (source) 100 ma total current out of gnd pin (sink) 110 ma storage temperature range b 65 cto a 140 c note: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings. dc electrical characteristics 0 c s t a s a 70 c unless otherwise specified parameter conditions min typ max units operating voltage peak-to-peak 2.7 5.5 v power supply ripple (note 1) 0.1 v cc v supply current (note 2) cki e 4 mhz v cc e 5.5v, t c e 2.5 m s 9.5 ma cki e 4 mhz v cc e 4v, t c e 2.5 m s 6.5 ma cki e 1 mhz v cc e 4v, t c e 10 m s 5.4 ma halt current (note 3) v cc e 5.5v, cki e 0 mhz k 510 m a v cc e 4v, cki e 0 mhz k 36 m a idle current cki e 4 mhz v cc e 5.5v, t c e 2.5 m s 1.5 ma cki e 1 mhz v cc e 4v, t c e 10 m s 0.5 ma input levels (v ih ,v il ) reset logic high 0.8 v cc v logic low 0.2 v cc v cki, all other inputs logic high 0.7 v cc v logic low 0.2 v cc v hi-z input leakage v cc e 5.5v 1 1 m a input pullup current v cc e 5.5v, v in e 0v b 40 b 250 m a g and l port input hysteresis (note 5) 0.35 v cc v output current levels d outputs source v cc e 4v, v oh e 3.3v b 0.4 ma v cc e 2.7v, v oh e 1.8v b 0.2 ma sink v cc e 4v, v ol e 1v 10 ma v cc e 2.7v, v ol e 0.4v 2.0 ma all others source (weak pull-up mode) v cc e 4v, v oh e 2.7v b 10 b 110 m a v cc e 2.7v, v oh e 1.8v b 2.5 b 33 m a source (push-pull mode) v cc e 4v, v oh e 3.3v b 0.4 ma v cc e 2.7v, v oh e 1.8v b 0.2 ma sink (push-pull mode) v cc e 4v, v ol e 0.4v 1.6 ma v cc e 2.7v, v ol e 0.4v 0.7 ma tri-state leakage v cc e 5.5v 1 1 m a allowable sink/source current per pin d outputs (sink) 15 ma all others 3ma maximum input current room temp g 200 ma without latchup (note 4) ram retention voltage, v r 500 ns rise and fall time (min) 2 v input capacitance (note 5) 7 pf load capacitance on d2 (note 5) 1000 pf http://www.national.com 5
ac electrical characteristics 0 c s t a s a 70 c unless otherwise specified parameter conditions min typ max units instruction cycle time (t c ) crystal, resonator 2.7v s v cc s 4v 2.5 dc m s 4v s v cc s 5.5v 1.0 dc m s r/c oscillator 2.7v s v cc s 4v 7.5 dc m s 4v s v cc s 5.5v 3.0 dc m s inputs t setup 4v s v cc s 5.5v 200 ns 2.7v s v cc s 4v 500 ns t hold 4v s v cc s 5.5v 60 ns 2.7v s v cc s 4v 150 ns output propagation delay (note 5) r l e 2.2k, c l e 100 pf t pd1 ,t pd0 so, sk 4v s v cc s 5.5v 0.7 m s 2.7v s v cc s 4v 1.75 m s all others 4v s v cc s 5.5v 1 m s 2.7v s v cc s 4v 2.5 m s microwire setup time (t uws ) (note 5) v cc t 4v 20 ns microwire hold time (t uwh ) (note 5) v cc t 4v 56 ns microwire output propagation delay (t upd )v cc t 4v 220 ns input pulse width (note 6) interrupt input high time 1 t c interrupt input low time 1 t c timer 1, 2, 3 input high time 1 t c timer 1, 2, 3 input low time 1 t c reset pulse width 1 m s note 1: maximum rate of voltage change must be k 0.5v/ms. note 2: supply current is measured after running 2000 cycles with a square wave cki input, cko open, inputs at rails and outputs open. note 3: the halt mode will stop cki from oscillating in the rc and the crystal configurations. measurement of i dd halt is done with device neither sourcing or sinking current; with l, c, and g0g5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to v cc ; clock monitor and comparator disabled. parameter refers to halt mode entered via setting bit 7 of the g port data register. part will pull up cki during halt in crystal clock mode. note 4: pins g6 and reset are designed with a high voltage input network. these pins allow input voltages l v cc and the pins will have sink current to v cc when biased at voltages l v cc (the pins do not have source current when biased at a voltage below v cc ). the effective resistance to v cc is 750 x (typical). these two pins will not latch up. the voltage at the pins must be limited to less than 14v. warning: voltages in excess of 14v will cause damage to the pins. this warning excludes esd transients. note 5: the output propagation delay is referenced to the end of the instruction cycle where the output change occurs. note 6: parameter characterized but not tested. note 7: t c e instruction cycle time. http://www.national.com 6
absolute maximum ratings if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. supply voltage (v cc )7v voltage at any pin b 0.3v to v cc a 0.3v total current into v cc pin (source) 100 ma total current out of gnd pin (sink) 110 ma storage temperature range b 65 cto a 140 c note: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings. dc electrical characteristics b 40 c s t a s a 85 c unless otherwise specified parameter conditions min typ max units operating voltage 2.7 5.5 v power supply ripple (note 1) peak-to-peak 0.1 v cc v supply current (note 2) cki e 4 mhz v cc e 5.5v, t c e 2.5 m s 9.5 ma cki e 4 mhz v cc e 4v, t c e 2.5 m s 6.5 ma cki e 1 mhz v cc e 4v, t c e 10 m s 5.4 ma halt current (note 3) v cc e 5.5v, cki e 0 mhz k 512 m a v cc e 4v, cki e 0 mhz k 38 m a idle current cki e 4 mhz v cc e 5.5v, t c e 2.5 m s 1.5 ma cki e 1 mhz v cc e 4v, t c e 10 m s 0.5 ma input levels (v ih ,v il ) reset logic high 0.8 v cc v logic low 0.2 v cc v cki, all other inputs logic high 0.7 v cc v logic low 0.2 v cc v hi-z input leakage v cc e 5.5v b 2 a 2 m a input pullup current v cc e 5.5v, v in e 0v b 40 b 250 m a g and l port input hysteresis (note 5) 0.35 v cc v output current levels d outputs source v cc e 4v, v oh e 3.3v b 0.4 ma v cc e 2.7v, v oh e 1.8v b 0.2 ma sink v cc e 4v, v ol e 1v 10 ma v cc e 2.7v, v ol e 0.4v 2.0 ma all others source (weak pull-up mode) v cc e 4v, v oh e 2.7v b 10 b 110 m a v cc e 2.7v, v oh e 1.8v b 2.5 b 33 m a source (push-pull mode) v cc e 4v, v oh e 3.3v b 0.4 ma v cc e 2.7v, v oh e 1.8v b 0.2 ma sink (push-pull mode) v cc e 4v, v ol e 0.4v 1.6 ma v cc e 2.7v, v ol e 0.4v 0.7 ma tri-state leakage v cc e 5.5v b 2 a 2 m a allowable sink/source current per pin d outputs (sink) 15 ma all others 3ma maximum input current room temp g 200 ma without latchup (note 4) ram retention voltage, v r 500 ns rise and fall time (min) 2 v input capacitance (note 5) 7 pf load capacitance on d2 (note 5) 1000 pf http://www.national.com 7
ac electrical characteristics b 40 c s t a s a 85 c unless otherwise specified parameter conditions min typ max units instruction cycle time (t c ) crystal, resonator 2.7v s v cc k 4v 2.5 dc m s 4v s v cc s 5.5v 1.0 dc m s r/c oscillator 2.7v s v cc k 4v 7.5 dc m s 4v s v cc k 5.5v 3.0 dc m s inputs t setup 4v s v cc s 5.5v 200 ns 2.7v s v cc k 4v 500 ns t hold 4v s v cc s 5.5v 60 ns 2.7v s v cc k 4v 150 ns output propagation delay (note 5) r l e 2.2k, c l e 100 pf t pd1 ,t pd0 so, sk 4v s v cc s 5.5v 0.7 m s 2.7v s v cc k 4v 1.75 m s all others 4v s v cc s 5.5v 1 m s 2.7v s v cc k 4v 2.5 m s microwire setup time (t uws ) (note 5) v cc t 4v 20 ns microwire hold time (t uwh ) (note 5) v cc t 4v 56 ns microwire output propagation delay (t upd )v cc t 4v 220 ns input pulse width (note 6) interrupt input high time 1 t c interrupt input low time 1 t c timer 1, 2, 3 input high time 1 t c timer 1, 2, 3 input low time 1 t c reset pulse width 1 m s note 1: maximum rate of voltage change must be k 0.5 v/ms. note 2: supply current is measured after running 2000 cycles with a square wave cki input, cko open, inputs at rails and outputs open. note 3: the halt mode will stop cki from oscillating in the rc and the crystal configurations. measurement of i dd halt is done with device neither sourcing or sinking current; with l, c, and g0g5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to v cc ; clock monitor and comparator disabled. parameter refers to halt mode entered via setting bit 7 of the g port data register. part will pull up cki during halt in crystal clock mode. note 4: pins g6 and reset are designed with a high voltage input network. these pins allow input voltages l v cc and the pins will have sink current to v cc when biased at voltages greater than v cc (the pins do not have source current when biased at a voltage below v cc ). the effective resistance to v cc is 750 x (typical). these two pins will not latch up. the voltage at the pins must be limited to less than 14v. warning: voltages in excess of 14v will cause damage to the pins. this warning excludes esd transients. note 5: the output propagation delay is referenced to the end of the instruction cycle where the output change occurs. note 6: parameter characterized but not tested. note 7: t c e instruction cycle time. http://www.national.com 8
comparator ac and dc characteristics v cc e 5v, b 40 c s t a s a 85 c parameter conditions min typ max units input offset voltage 0.4v k v in k v cc b 1.5v 10 25 mv input common mode voltage range (note 8) 0.4 v cc b 1.5 v voltage gain 300k v/v v cc /2 reference 4.0v k v cc k 5.5v 0.5 v cc b 0.04 0.5v cc 0.5v cc a 0.04 v dc supply current v cc e 5.5v 250 m a for comparator (when enabled) dc supply current v cc 5.5v 50 80 m a for v cc /2 reference (when enabled) dc supply current v cc e 5.5v 200 m a for constant current source (when enabled) constant current source 4.0v k v cc k 5.5v 10 20 40 m a current source variation 4.0v k v cc k 5.5v 2 m a temp e constant current source enable time 1.5 2 m s comparator response time 10 mv overdrive, 1 m s 100 pf load note 8: the device is capable of operating over a common mode voltage range of 0 to v cc b 1.5v, however increased offset voltage will be observed between 0v and 0.4v. tl/dd/12869 4 figure 2. microwire/plus timing http://www.national.com 9
pin descriptions v cc and gnd are the power supply pins. all v cc and gnd pins must be connected. cki is the clock input. this can come from an r/c generat- ed oscillator, or a crystal oscillator (in conjunction with cko). see oscillator description section. reset is the master reset input. see reset description section. the device contains two bidirectional (one 8-bit, one 4-bit) i/o ports (g and l), where each individual bit may be inde- pendently configured as an input (schmitt trigger inputs on ports l and g), output or tri-state under program control. three data memory address locations are allocated for each of these i/o ports. each i/o port has two associated 8-bit memory mapped registers, the configuration reg- ister and the output data register. a memory mapped ad- dress is also reserved for the input pins of each i/o port. (see the memory map for the various addresses associated with the i/o ports.) figure 3 shows the i/o port configura- tions. the data and configuration registers allow for each port bit to be individually configured under software control as shown below: port l is a 4-bit i/o port. all l-pins have schmitt triggers on the inputs. the port l supports multi-input wake up on all four pins. the port l has the following alternate features: l4 miwu or external interrupt l5 miwu or external interrupt l6 miwu or external interrupt l7 miwu or external interrupt tl/dd/12869 5 figure 3. i/p port configurations configuration data port set-up register register 0 0 hi-z input (tri-state output) 0 1 input with weak pull-up 1 0 push-pull zero output 1 1 push-pull one output please note: the lower 4 l-bits read all ones (l0:l3). this is independant from the states of the associated bits in the l-port data- and configuration register. the lower 4 bits in the l-port data- and configuration register can be used as general purpose status indicators (flags). port g is an 8-bit port with 5 i/o pins (g0, g2 g5), an input pin (g6), and a dedicated output pin (g7). pins g0 and g2 g6 all have schmitt triggers on their inputs. pin g1 serves as the dedicated wdout watchdog output, while pin g7 is either input or output depending on the oscillator mask option selected. with the crystal oscillator option selected, g7 serves as the dedicated output pin for the cko clock output. with the single-pin r/c oscillator mask option se- lected, g7 serves as a general purpose input pin but is also used to bring the device out of halt mode with a low to high transition on g7. there are two registers associated with the g port, a data register and a configuration register. therefore, each of the 5 i/o bits (g0, g2 g5) can be indi- vidually configured under software control. since g6 is an input only pin and g7 is the dedicated cko clock output pin (crystal clock option) or general purpose input (r/c clock option), the associated bits in the data and configuration registers for g6 and g7 are used for special purpose functions as outlined below. reading the g6 and g7 data bits will return zeros. note that the chip will be placed in the halt mode by writ- ing a ``1'' to bit 7 of the port g data register. similarly the chip will be placed in the idle mode by writing a ``1'' to bit 6 of the port g data register. writing a ``1'' to bit 6 of the port g configuration register enables the microwire/plus to operate with the alter- nate phase of the sk clock. the g7 configuration bit, if set high, enables the clock start up delay after halt when the r/c clock configuration is used. config reg. data reg. g7 clkdly halt g6 alternate sk idle port g has the following alternate features: g0 intr (external interrupt input) g2 t1b (timer t1 capture input) g3 t1a (timer t1 i/o) g4 so (microwire serial data output) g5 sk (microwire serial clock) g6 si (microwire serial data input) port g has the following dedicated functions: g1 wdout watchdog and/or clock monitor dedicated output. g7 cko oscillator dedicated output or general purpose input port i is an eight-bit hi-z input port. port i0 i7 are used for the analog function block. the port i has the following alternate features: i0 compin1 a (comparator positive input 1) i1 compin b (comparator negative input/current source out) i2 compin0 a (comparator positive input 0) http://www.national.com 10
pin descriptions (continued) i3 compout/compin2 a (comparator output/compar- ator positive input 2) i4 compin3 a (comparator positive input 3) i5 compin4 a (comparator positive input 4) i6 compin5 a (comparator positive input 5) i7 compout (comparator output) port d is a 4-bit output port that is preset high when reset goes low. the user can tie two or more d port outputs (ex- cept d2) together in order to get a higher drive. functional description the architecture of the device is a modified harvard archi- tecture. with the harvard architecture, the control store pro- gram memory (rom) is separated from the data store mem- ory (ram). both rom and ram have their own separate addressing space with separate address buses. the archi- tecture, though based on the harvard architecture, permits transfer of data from rom to ram. cpu registers the cpu can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t c ) cycle time. there are six cpu registers: a is the 8-bit accumulator register pc is the 15-bit program counter register pu is the upper 7 bits of the program counter (pc) pl is the lower 8 bits of the program counter (pc) b is an 8-bit ram address pointer, which can be optionally post auto incremented or decremented. x is an 8-bit alternate ram address pointer, which can be optionally post auto incremented or decremented. sp is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in ram). the sp is initialized to ram ad- dress 06f with reset. all the cpu registers are memory mapped with the excep- tion of the accumulator (a) and the program counter (pc). program memory the program memory consists of 4096 bytes of otp ep- rom. these bytes may hold program instructions or con- stant data (data tables for the laid instruction, jump vectors for the jid instruction, and interrupt vectors for the vis in- struction). the program memory is addressed by the 15-bit program counter (pc). all interrupts in the device vector to program memory location 0ff hex. the device can be configured to inhibit external reads of the program memory. this is done by programming the security byte. security feature the program memory array has an associate security byte that is located outside of the program address range. this byte can be addressed only from programming mode by a programmer tool. security is an optional feature and can only be asserted after the memory array has been programmed and verified. a secured part will read all 00(hex) by a programmer. the part will fail blank check and will fail verify operations. a read operation will fill the programmer's memory with 00(hex). the security byte itself is always readable with val- ue of 00(hex) if unsecure and ff(hex) if secure. data memory the data memory address space includes the on-chip ram and data registers, the i/o registers (configuration, data and pin), the control registers, the microwire/plus sio shift register, and the various registers, and counters asso- ciated with the timers (with the exception of the idle timer). data memory is addressed directly by the instruction or indi- rectly by the b, x, sp pointers and s register. the data memory consists of 128 bytes of ram. sixteen bytes of ram are mapped as ``registers'' at addresses 0f0 to 0ff hex. these registers can be loaded immediately, and also decremented and tested with the drsz (decre- ment register and skip if zero) instruction. the memory pointer registers x, b and sp are memory mapped into this space at address locations 0fc to 0ff hex respectively, with the other registers being available for general usage. the instruction set permits any bit in memory to be set, reset or tested. all i/o and registers (except a and pc) are memory mapped; therefore, i/o bits and register bits can be directly and individually set, reset and tested. the accumu- lator (a) bits can also be directly and individually tested. note: ram contents are undefined upon power-up. reset the reset input when pulled low initializes the microcon- troller. initialization will occur whenever the reset input is pulled low. upon initialization, the data and configuration registers for ports l and g are cleared, resulting in these ports being initialized to the tri-state mode. pin g1 of the g port is an exception (as noted below) since pin g1 is dedicated as the watchdog and/or clock monitor error output pin. port d is set high. the pc, psw, icntrl and cntrl-control registers are cleared. the comparator se- lect register is cleared. the s register is initialized to zero. the multi-input wakeup registers wken and wkedg are cleared. wakeup register wkpnd is unknown. the stack pointer, sp, is initialized to 6f hex. the device comes out of reset with both the watchdog logic and the clock monitor detector armed, with the watchdog service window bits set and the clock monitor bit set. the watchdog and clock monitor circuits are in- hibited during reset. the watchdog service window bits being initialized high default to the maximum watchdog service window of 64k t c clock cycles. the clock monitor bit being initialized high will cause a clock monitor error follow- ing reset if the clock has not reached the minimum specified frequency at the termination of reset. a clock monitor error will cause an active low error output on pin g1. this error output will continue until 16 t c -32 t c clock cycles following the clock frequency reaching the minimum specified value, at which time the g1 output will enter the tri-state mode. the external rc network shown in figure 4 should be used to ensure that the reset pin is held low until the power supply to the chip stabilizes. oscillator circuits the chip can be driven by a clock input on the cki input pin which can be between dc and 10 mhz. the cko output clock is on pin g7 (crystal configuration). the cki input fre- quency is divided down by 10 to produce the instruction cycle clock (t c ). http://www.national.com 11
oscillator circuits (continued) tl/dd/12869 6 rc l 5 x power supply rise time figure 4. recommended reset circuit figure 5 shows the crystal and r/c oscillator diagrams. crystal oscillator cki and cko can be connected to make a closed loop crystal (or resonator) controlled oscillator. table i shows the component values required for various standard crystal values. table i. crystal oscillator configuration, t a e 25 c r1 r2 c1 c2 cki freq conditions (k x )(m x ) (pf) (pf) (mhz) 0 1 30 30 36 10 v cc e 5v 0 1 30 30 36 4 v cc e 5v 0 1 200 100 150 0.455 v cc e 5v r/c oscillator by selecting cki as a single pin oscillator input, a single pin r/c oscillator circuit can be connected to it. cko is avail- able as a general purpose input, and/or halt restart input. note: use of the r/c oscillator option will result in higher electromagnetic emissions. table ii shows the variation in the oscillator frequencies as functions of the component (r and c) values. table ii. rc oscillator configuration, t a e 25 c r c cki freq instr. cycle conditions (k x ) (pf) (mhz) ( m s) 3.3 82 2.2 to 2.7 3.7 to 4.6 v cc e 5v 5.6 100 1.1 to 1.3 7.4 to 9.0 v cc e 5v 6.8 100 0.9 to 1.1 8.8 to 10.8 v cc e 5v note: 3k s r s 200k 50 pf s c s 200 pf control registers cntrl register (address x'00ee) the timer1 (t1) and microwire/plus control register contains the following bits: sl1 and sl0 select the microwire/plus clock divide by (00 e 2, 01 e 4, 1x e 8) iedg external interrupt edge polarity select (0 e rising edge, 1 e falling edge) msel selects g5 and g4 as microwire/plus signals sk and so respectively t1c0 timer t1 start/stop control in timer modes 1 and 2. t1 underflow interrupt pending flag in timer mode 3 t1c1 timer t1 mode control bit t1c2 timer t1 mode control bit t1c3 timer t1 mode control bit t1c3 t1c2 t1c1 t1c0 msel iedg sl1 sl0 bit 7 bit 0 psw register (address x'00ef) the psw register contains the following select bits: gie global interrupt enable (enables interrupts) exen enable external interrupt busy microwire/plus busy shifting flag expnd external interrupt pending t1ena timer t1 interrupt enable for timer underflow or t1a input capture edge t1pnda timer t1 interrupt pending flag (autoreload ra in mode 1, t1 underflow in mode 2, t1a cap- ture edge in mode 3) c carry flag hc half carry flag hc c t1pnda t1ena expnd busy exen gie bit 7 bit 0 the half-carry flag is also affected by all the instructions that affect the carry flag. the sc (set carry) and rc (reset carry) instructions will respectively set or clear both the car- ry flags. in addition to the sc and rc instructions, adc, subc, rrc and rlc instructions affect the carry and half carry flags. tl/dd/12869 7 tl/dd/12869 8 figure 5. crystal and r/c oscillator diagrams http://www.national.com 12
control registers (continued) icntrl register (address x'00e8) the icntrl register contains the following bits: t1enb timer t1 interrupt enable for t1b input capture edge t1pndb timer t1 interrupt pending flag for t1b capture edge m wen enable microwire/plus interrupt m wpnd microwire/plus interrupt pending t0en timer t0 interrupt enable (bit 12 toggle) t0pnd timer t0 interrupt pending lpen l port interrupt enable (multi-input wakeup/in- terrupt) bit 7 could be used as a flag unused lpen t0pnd t0en wpnd wen t1pndb t1enb bit 7 bit 0 capcntl register (address x'00) the capcntl register contains the following bits: capien capture interrupts enable cappnd capture pending capovl capture timer overflow caprun capture timer run capmod reset timer unused capmod caprun capovl cappnd capien bit 7 bit 0 timers the device contains a very versatile set of timers (t0 and t1). all timers and associated autoreload/capture registers power up containing random data. timer t0 (idle timer) the device supports applications that require maintaining real time and low power with the idle mode. this idle mode support is furnished by the idle timer t0, which is a 16-bit timer. the timer t0 runs continuously at the fixed rate of the instruction cycle clock, t c . the user cannot read or write to the idle timer t0, which is a count down timer. the timer t0 supports the following functions: # exit out of the idle mode (see idle mode description) # watchdog logic (see watchdog description) # start up delay out of the halt mode figure 6 is a functional block diagram showing the structure of the idle timer and its associated interrupt logic. bits 11 through 15 of the itmr register can be selected for triggering the idle timer interrupt. each time the selected bit underflows (every 4k, 8k, 16k, 32k or 64k instruction cy- cles), the idle timer interrupt pending bit t0pnd is set, thus generating an interrupt (if enabled), and bit 6 of the port g data register is reset, thus causing an exit from the idle mode if the device is in that mode. in order for an interrupt to be generated, the idle timer interrupt enable bit t0en must be set, and the gie (global interrupt enable) bit must also be set. the t0pnd flag and t0en bit are bits 5 and 4 of the icntrl register, respective- ly. the interrupt can be used for any purpose. typically, it is used to perform a task upon exit from the idle mode. for more information on the idle mode, refer to the power save modes section. the idle timer period is selected by bits 0 2 of the itmr register bits 3 7 of the itmr register are reserved and should not be used as software flags. table iii. idle timer window length itsel2 itsel1 itsel0 idle timer period (instruction cycles) 0 0 0 4,096 0 0 1 8,192 0 1 0 16,384 0 1 1 32,768 1 x x 65,536 the itmr register is cleared on reset and the idle timer period is reset to 4,096 instruction cycles. itmr register (address x'0xcf) reserved itsel2 itsel1 itsel0 bit 7 bit 0 any time the idle timer period is changed there is the pos- sibility of generating a spurious idle timer interrupt by set- ting the t0pnd bit. the user is advised to disable idle timer interrupts prior to changing the value of the itsel bits of the itmr register and then clear the t0pnd bit before attempting to synchronize operation to the idle timer. http://www.national.com 13
timers (continued) tl/dd/12869 9 figure 6. functional block diagram for idle timer t0 timer t1 the device has a powerful timer/counter block. the timer consists of a 16-bit timer, t1, and two supporting 16-bit au- toreload/capture registers, r1a and r1b. the timer block has two pins associated with it, t1a and t1b. the pin t1a supports i/o required by the timer block, while the pin t1b is an input to the timer block. the powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. the timer block has three operating modes: processor independent pwm mode, ex- ternal event counter mode, and input capture mode. the control bits t1c3, t1c2, and t1c1 allow selection of the different modes of operation. mode 1. processor independent pwm mode as the name suggests, this mode allows the device to gen- erate a pwm signal with very minimal user intervention. the user only has to define the parameters of the pwm signal (on time and off time). once begun, the timer block will continuously generate the pwm signal completely indepen- dent of the microcontroller. the user software services the timer block only when the pwm parameters require updat- ing. in this mode the timer t1 counts down at a fixed rate of t c . upon every underflow the timer is alternately reloaded with the contents of supporting registers, r1a and r1b. the very first underflow of the timer causes the timer to reload from the register r1a. subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register r1b. the t1 timer control bits, t1c3, t1c2 and t1c1 set up the timer for pwm mode operation. figure 7 shows a block diagram of the timer in pwm mode. the underflows can be programmed to toggle the t1a out- put pin. the underflows can also be programmed to gener- ate interrupts. underflows from the timer are alternately latched into two pending flags, t1pnda and t1pndb. the user must reset these pending flags under software control. two control en- able flags, t1ena and t1enb, allow the interrupts from the timer underflow to be enabled or disabled. setting the timer enable flag t1ena will cause an interrupt when a timer un- derflow causes the r1a register to be reloaded into the timer. setting the timer enable flag t1enb will cause an interrupt when a timer underflow causes the r1b register to be reloaded into the timer. resetting the timer enable flags will disable the associated interrupts. either or both of the timer underflow interrupts may be en- abled. this gives the user the flexibility of interrupting once per pwm period on either the rising or falling edge of the pwm output. alternatively, the user may choose to interrupt on both edges of the pwm output. http://www.national.com 14
timers (continued) mode 2. external event counter mode this mode is quite similar to the processor independent pwm mode previously described. the main difference is that the timer, t1, is clocked by the input signal from the t1a pin. the t1 timer control bits, t1c3, t1c2 and t1c1 allow the timer to be clocked either on a positive or negative edge from the t1a pin. underflows from the timer are latched into the t1pnda pending flag. setting the t1ena control flag will cause an interrupt when the timer under- flows. in this mode the input pin t1b can be used as an indepen- dent positive edge sensitive interrupt input if the t1enb control flag is set. the occurrence of a positive edge on the t1b input pin is latched into the t1pndb flag. figure 8 shows a block diagram of the timer in external event counter mode. note: the pwm output is not available in this mode since the t1a pin is being used as the counter input clock. mode 3. input capture mode the device can precisely measure external frequencies or time external events by placing the timer block, t1, in the input capture mode. in this mode, the timer t1 is constantly running at the fixed t c rate. the two registers, r1a and r1b, act as capture registers. each register acts in conjunction with a pin. the register r1a acts in conjunction with the t1a pin and the register r1b acts in conjunction with the t1b pin. the timer value gets copied over into the register when a trigger event occurs on its corresponding pin. control bits, t1c3, t1c2 and t1c1, allow the trigger events to be speci- fied either as a positive or a negative edge. the trigger con- dition for each input pin can be specified independently. tl/dd/12869 10 figure 7. timer in pwm mode the trigger conditions can also be programmed to generate interrupts. the occurrence of the specified trigger condition on the t1a and t1b pins will be respectively latched into the pending flags, t1pnda and t1pndb. the control flag t1ena allows the interrupt on t1a to be either enabled or disabled. setting the t1ena flag enables interrupts to be generated when the selected trigger condition occurs on the t1a pin. similarly, the flag t1enb controls the interrupts from the t1b pin. underflows from the timer can also be programmed to gen- erate interrupts. underflows are latched into the timer t1c0 pending flag (the t1c0 control bit serves as the timer under- flow interrupt pending flag in the input capture mode). con- sequently, the t1c0 control bit should be reset when enter- ing the input capture mode. the timer underflow interrupt is enabled with the t1ena control flag. when a t1a interrupt occurs in the input capture mode, the user must check both the t1pnda and t1c0 pending flags in order to determine whether a t1a input capture or a timer underflow (or both) caused the interrupt. tl/dd/12869 11 figure 8. timer in external event counter mode http://www.national.com 15
timers (continued) tl/dd/12869 12 figure 9. timer in input capture mode figure 9 shows a block diagram of the timer in input capture mode. timer control flags the timer t1 control bits and their functions are summa- rized below. t1c0 timer start/stop control in modes 1 and 2 (processor independent pwm and external event counter), where 1 e start, 0 e stop tim- er underflow interrupt pending flag in mode 3 (input capture) t1pnda timer interrupt pending flag t1pndb timer interrupt pending flag t1ena timer interrupt enable flag t1enb timer interrupt enable flag 1 e timer interrupt enabled 0 e timer interrupt disabled t1c3 timer mode control t1c2 timer mode control t1c1 timer mode control high speed capture timer the device provides a 16-bit high-speed capture timer. the timer consists of a 16-bit up-counter that is clocked with the device clock input frequency (cki) and an 8-bit control reg- ister. the 16-bit counter is mapped as two read/write 8-bit registers. this timer is specifically designed to be used in conjunction with the analog function block (comparator, analog multiplexer, constant current source) to implement a low-cost, high-resolution, single-slope a/d. the timer is automatically stopped in the event of a capture to allow the software to read the timer value. coming out of reset the counter is disabled (stopped) and reads all ``0''. setting the capture timer run bit caprun bit in the cap- ture control register (capcntl) will start the counter. the counter will count up until a capture event (negative edge) is received. upon a capture the counter will be stopped, the capture pending bit (cappnd) is set, and the caprun bit is automatically reset. if capture interrupts are enabled (capien e 1), the capture event will generate an interrupt. setting the caprun bit again by software will start a new counting cycle. if the capture mode bit is reset (capmod e 0) the capture timer will be automatically initial- ized to all ``0'' with each setting of the caprun bit. if capmod e 1 the timer will not be cleared when setting the caprun bit, thus allowing the user's software to pre-load the timer registers with any desired value. this mode can be used in conjunction with the timer's overflow to implement for example a programmable delay counter. http://www.national.com 16
timers (continued) the timer mode control bits (t1c3, t1c2 and t1c1) are detailed below: table iv. timer mode control t1c3 t1c2 t1c1 timer mode interrupt a interrupt b timer source source counts on 0 0 0 mode 2 (external event counter) timer underflow pos. t1b edge t1a pos. edge 0 0 1 mode 2 (external event counter) timer underflow pos. t1b edge t1a neg. edge 1 0 1 mode 1 (pwm) t1a toggle autoreload ra autoreload rb t c 1 0 0 mode 1 (pwm) no t1a toggle autoreload ra autoreload rb t c 0 1 0 mode 3 (capture) captures: pos. t1a edge pos. t1b edge t c t1a pos. edge timer underflow t1b pos. edge 1 1 0 mode 3 (capture) captures: pos. t1a edge or neg. t1b edge t c t1a pos. edge timer underflow t1b neg. edge 0 1 1 mode 3 (capture) captures: neg. t1a edge or pos. t1b edge t c t1a neg. edge timer underflow t1b pos. edge 1 1 1 mode 3 (capture) captures: neg. t1a edge or neg. t1b edge t c t1a neg. edge timer underflow t1b neg. edge ``capture mode'' is only active when the caprun bit is set, i.e. any capture events received while the timer is stopped (caprun e 0) will be ignored and will not cause the cappnd bit to be set. the capture counter can also be stopped (frozen) by the user's software resetting the caprun bit. if the user program tries to set the caprun bit at the same time that the hardware gets a capture event and tries to reset the caprun bit, the hardware will have precedence. should the counter overflow before a capture condition oc- curs, the capture overflow bit (capovl) bit in the capcntl register will be set. if capture interrupts are en- abled (capien e 1) an overflow will generate an interrupt. the user software should reset this bit before the next over- flow occurs, otherwise subsequent overflow conditions can- not be detected. capture overflow interrupt and capture pending interrupt share the same interrupt vector. power save modes the device offers the user two power save modes of opera- tion: halt and idle. in the halt mode, all microcontroller activities are stopped. in the idle mode, the on-board oscil- lator circuitry and timer t0 are active but all other microcon- troller activities are stopped. in either mode, all on-board ram, registers, i/o states, and timers (with the exception of t0) are unaltered. halt mode the device can be placed in the halt mode by writing a ``1'' to the halt flag (g7 data bit). all microcontroller activi- ties, including the clock and timers, are stopped. the watchdog logic on the device is disabled during the halt mode. however, the clock monitor circuitry, if en- abled, remains active and will cause the watchdog out- put pin (wdout) to go low. if the halt mode is used and the user does not want to activate the wdout pin, the clock monitor should be disabled after the device comes out of reset (resetting the clock monitor control bit with the first write to the wdsvr register). in the halt mode, the power requirements of the device are minimal and the ap- plied voltage (v cc ) may be decreased to v r (v r e 2.0v) without altering the state of the machine. the device supports three different ways of exiting the halt mode. the first method of exiting the halt mode is with the multi-input wakeup feature on the port l. the second method is with a low to high transition on the cko (g7) pin. this method precludes the use of the crystal clock configuration (since cko becomes a dedicated out- put), and so may only be used with an rc clock configura- tion. the third method of exiting the halt mode is by pull- ing the reset pin low. since a crystal or ceramic resonator may be selected as the oscillator, the wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full ampli- http://www.national.com 17
power save modes (continued) tude and frequency stability. the idle timer is used to gen- erate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. in this case, upon detecting a valid wakeup signal, only the oscillator circuitry is enabled. the idle timer is loaded with a value of 256 and is clocked with the t c instruction cycle clock. the t c clock is derived by dividing the oscillator clock down by a factor of 10. the schmitt trigger following the cki inverter on the chip ensures that the idle timer is clocked only when the oscillator has a sufficiently large amplitude to meet the schmitt trigger specifications. this schmitt trigger is not part of the oscillator closed loop. the startup timeout from the idle timer enables the clock signals to be routed to the rest of the chip. if an rc clock option is being used, the fixed delay is intro- duced optionally. a control bit, clkdly, mapped as config- uration bit g7, controls whether the delay is to be intro- duced or not. the delay is included if clkdly is set, and excluded if clkdly is reset. the clkdly bit is cleared on reset. the device has two mask options associated with the halt mode. the first mask option enables the halt mode fea- ture, while the second mask option disables the halt mode. with the halt mode enable mask option, the device will enter and exit the halt mode as described above. with the halt disable mask option, the device cannot be placed in the halt mode (writing a ``1'' to the halt flag will have no effect, the halt flag will remain ``0''). idle mode the device is placed in the idle mode by writing a ``1'' to the idle flag (g6 data bit). in this mode, all activities, except the associated on-board oscillator circuitry and the idle timer t0, are stopped. as with the halt mode, the device can be returned to nor- mal operation with a reset, or with a multi-input wakeup from the l port. alternately, the microcontroller resumes normal operation from the idle mode when the thirteenth bit (representing 4.096 ms at internal clock frequency of 10 mhz, t c e 1 m s) of the idle timer toggles. this toggle condition of the thirteenth bit of the idle timer t0 is latched into the t0pnd pending flag. the user has the option of being interrupted with a transition on the thirteenth bit of the idle timer t0. the interrupt can be enabled or disabled via the t0en control bit. setting the t0en flag enables the interrupt and vice versa. the user can enter the idle mode with the timer t0 inter- rupt enabled. in this case, when the t0pnd bit gets set, the device will first execute the timer t0 interrupt service rou- tine and then return to the instruction following the ``enter idle mode'' instruction. alternatively, the user can enter the idle mode with the idle timer t0 interrupt disabled. in this case, the device will resume normal operation with the instruction immediate- ly following the ``enter idle mode'' instruction. note: it is necessary to program two nop instructions following both the set halt mode and set idle mode instructions. these nop instruc- tions are necessary to allow clock resynchronization following the halt or idle modes. multi-input wakeup the multi-input wakeup feature is used to return (wakeup) the device from either the halt or idle modes. alternately multi-input wakeup/interrupt feature may also be used to generate up to 4 edge selectable external interrupts. figure 10 shows the multi-input wakeup logic. the multi-input wakeup feature utilizes the l port. the user selects which particular l port bit (or combination of l port bits) will cause the device to exit the halt or idle modes. the selection is done through the register wken. the regis- ter wken is an 8-bit read/write register, which contains a control bit for every l port bit. setting a particular wken bit enables a wakeup from the associated l port pin. the user can select whether the trigger condition on the selected l port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). this selection is made via the register wkedg, which is an 8-bit control register with a bit assigned to each l port pin. setting the control bit will select the trigger condition to be a negative edge on that particular l port pin. resetting the bit selects the trigger condition to be a positive edge. changing an edge select entails several steps in order to avoid a wakeup condition as a result of the edge change. first, the associated wken bit should be reset, followed by the edge select change in wkedg. next, the associated wkpnd bit should be cleared, followed by the associated wken bit being re-enabled. an example may serve to clarify this procedure. suppose we wish to change the edge select from positive (low going high) to negative (high going low) for l port bit 5, where bit 5 has previously been enabled for an input interrupt. the pro- gram would be as follows: rbit 5, wken sbit 5, wkedg rbit 5, wkpnd sbit 5, wken if the l port bits have been used as outputs and then changed to inputs with multi-input wakeup/interrupt, a safe- ty procedure should also be followed to avoid wakeup con- ditions. after the selected l port bits have been changed from output to input but before the associated wken bits are enabled, the associated edge select bits in wkedg should be set or reset for the desired edge selects, followed by the associated wkpnd bits being cleared. this same procedure should be used following reset, since the l port inputs are left floating as a result of reset. the occurrence of the selected trigger condition for multi-in- put wakeup is latched into a pending register called wkpnd. the respective bits of the wkpnd register will be set on the occurrence of the selected trigger edge on the corresponding port l pin. the user has the responsibility of clearing these pending flags. since wkpnd is a pending register for the occurrence of selected wakeup conditions, the device will not enter the halt mode if any wakeup bit is both enabled and pending. consequently, the user must clear the pending flags before attempting to enter the halt mode. wken, wkpnd and wkedg are all read/write registers, and are cleared at reset. http://www.national.com 18
multi-input wakeup (continued) tl/dd/12869 13 figure 10. multi-input wake up logic port l interrupts port l provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service subroutine. the interrupt from port l shares logic with the wake up cir- cuitry. the register wken allows interrupts from port l to be individually enabled or disabled. the register wkedg specifies the trigger condition to be either a positive or a negative edge. finally, the register wkpnd latches in the pending trigger conditions. the gie (global interrupt enable) bit enables the interrupt function. a control flag, lpen, functions as a global interrupt enable for port l interrupts. setting the lpen flag will enable inter- rupts and vice versa. a separate global pending flag is not needed since the register wkpnd is adequate. since port l is also used for waking the device out of the halt or idle modes, the user can elect to exit the halt or idle modes either with or without the interrupt enabled. if he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the in- struction that placed the microcontroller in the halt or idle modes. in the other case, the device will first execute the interrupt service routine and then revert to normal oper- ation. (see halt mode for clock option wakeup informa- tion.) http://www.national.com 19
analog function block this device contains an analog function block with the in- tent to provide a function which allows for single slope, low cost, a/d conversion of up to 6 channels. cmpsl register (address x'00b7) the cmpsl register contains the following bits: cmpneg will drive i1 to a low level. this bit can be used to discharge an external capacitor. this bit is disabled if the comparator is not enabled (cmpen e 0). cmpen enable the comparator (``1'' e enable) csen enables the internal constant current source. this current source provides a nominal 20 m a constant current at the i1 pin. this current can be used to ensure a linear charging rate on an external capaci- tor. this bit has no affect and the current source is disabled if the comparator is not enabled (cmpen e 0). cmpoe enables the comparator output to either pin i3 or pin i7 (``1'' e enable) depending on the value of cmpisel0/1/2. cmpisel0/1/2 will select one of seven possible sources (i0/i2/i3/i4/i5/i6/internal reference) as a positive input to the comparator (see table v for more information.) cmpt2b selects the timer t2b input to be driven directly by the comparator output. if the comparator is disabled (cmpen e 0), this function is disabled, i.e. the t2b input is connected to port l5. cmpt2b cmpisel2 cmpisel1 cmpisel0 cmpoe csen cmpen cmpneg bit 7 bit 0 the comparator select register is cleared on reset (the comparator is disabled). to save power the program should also disable the comparator before the m c enters the halt/idle modes. disabling the comparator will turn off the constant current source and the v cc /2 reference, dis- connect the comparator output from the t2b input and pin i3 or i7 and remove the low on i1 caused by cmpneg. it is often useful for the user's program to read the result of a comparator operation. since i1 is always selected to be compinewhen the comparator is enabled (cmpen e 1), the comparator output can be read internally by reading bit 1 (cmprd) of register porti (ram address 0xd7). the following table lists the comparator inputs and outputs versus the value of the cmpisel0/1/2 bits. the output will only be driven if the cmpoe bit is set to 1. tl/dd/12869 14 figure 11. cop884ct analog function block http://www.national.com 20
analog function block (continued) table v. comparator input selection control bit comparator comparator output input source cmpisel2 cmpisel1 cmpisel0 neg. pos. input input 0 0 0 i1 i2 i3 0 0 1 i1 i2 i7 0 1 0 i1 i3 i7 0 1 1 i1 i0 i7 1 0 0 i1 i4 i7 1 0 1 i1 i5 i7 1 1 0 i1 i6 i7 111i1v cc /2 i7 ref. reset the state of the comparator block immediately after reset is as follows: 1. the cmpsl register is set to all zeros 2. the comparator is disabled 3. the constant current source is disabled 4. cmpneg is turned off 5. the port i inputs are electrically isolated from the com- parator 6. the t2b input is as normally selected by the t2cntrl register 7. cmpisel0 cmpisel2 are set to zero 8. all port i inputs are selected to the default digital input mode the comparator outputs have the same specification as ports l and g except that the rise and fall times are sym- metrical. interrupts the device supports a vectored interrupt scheme. it sup- ports a total of twelve interrupt sources. the following table lists all the possible device interrupt sources, their arbitra- tion rankings and the memory locations reserved for the interrupt vector for each source. two bytes of program memory space are reserved for each interrupt source. all interrupt sources except the software interrupt are maskable. each of the maskable interrupts have an enable bit and one or more pending bits. a maska- ble interrupt is active if its associated enable and pending bits are set. if gie e 1 and an interrupt is active, then the processor will be interrupted as soon as it is ready to start executing an instruction except if the above conditions hap- pen during the software trap service routine. this excep- tion is described in the software trap sub-section. the interruption process is accomplished with the intr in- struction (opcode 00), which is jammed inside the instruc- tion register and replaces the opcode about to be execut- ed. the following steps are performed for every interrupt: 1. the gie (global interrupt enable) bit is reset. 2. the address of the instruction about to be executed is pushed into the stack. 3. the pc (program counter) branches to address 00ff. this procedure takes 7 t c cycles to execute. table vi. interrupt vector table arbitration source vector * ranking description address (hi-low byte) (1) highest software intr instruction 0yfe 0yff (2) reserved 0yfc 0yfd (3) external g0 0yfa 0yfb (4) timer t0 idle timer 0yf8 0yf9 (5) timer t1 t1a/underflow 0yf6 0yf7 (6) timer t1 t1b 0yf4 0yf5 (7) microwire/plus busy low 0yf2 0yf3 (8) reserved 0yf0 0yf1 (9) reserved 0yee 0yef (10) reserved 0yec 0yed (11) high speed capture timer capture overflow/ 0yea 0yeb capture pending (12) reserved 0ye8 0ye9 (13) reserved 0ye6 0ye7 (14) reserved 0ye4 0ye5 (15) port l/wakeup port l edge 0ye2 0ye3 (16) lowest default vis reserved 0ye0 0ye1 * y is a variable which represents the vis block. vis and the vector table must be located in the same 256-byte block except if vis is located at the last address of a block. in this case, the table must be in the next block. http://www.national.com 21
interrupts (continued) at this time, since gie e 0, other maskable interrupts are disabled. the user is now free to do whatever context switching is required by saving the context of the machine in the stack with push instructions. the user would then pro- gram a vis (vector interrupt select) instruction in order to branch to the interrupt service routine of the highest priority interrupt enabled and pending at the time of the vis. note that this is not necessarily the interrupt that caused the branch to address location 00ff hex prior to the context switching. thus, if an interrupt with a higher rank than the one which caused the interruption becomes active before the decision of which interrupt to service is made by the vis, then the interrupt with the higher rank will override any lower ones and will be acknowledged. the lower priority interrupt(s) are still pending, however, and will cause another interrupt im- mediately following the completion of the interrupt service routine associated with the higher priority interrupt just serv- iced. this lower priority interrupt will occur immediately fol- lowing the reti (return from interrupt) instruction at the end of the interrupt service routine just completed. inside the interrupt service routine, the associated pending bit has to be cleared by software. the reti (return from interrupt) instruction at the end of the interrupt service rou- tine will set the gie (global interrupt enable) bit, allowing the processor to be interrupted again if another interrupt is active and pending. the vis instruction looks at all the active interrupts at the time it is executed and performs an indirect jump to the beginning of the service routine of the one with the highest rank. the addresses of the different interrupt service routines, called vectors, are chosen by the user and stored in rom in a table starting at 01e0 (assuming that vis is located be- tween 00ff and 01df). the vectors are 15-bit wide and therefore occupy 2 rom locations. vis and the vector table must be located in the same 256- byte block (0y00 to 0yff) except if vis is located at the last address of a block. in this case, the table must be in the next block. the vector table cannot be inserted in the first 256-byte block (y i 0). tl/dd/12869 15 figure 12. interrupt block diagram http://www.national.com 22
interrupts (continued) the vector of the maskable interrupt with the lowest rank is located at 0ye0 (hi-order byte) and 0ye1 (lo-order byte) and so forth in increasing rank number. the vector of the maskable interrupt with the highest rank is located at 0yfa (hi-order byte) and 0yfb (lo-order byte). the software trap has the highest rank and its vector is located at 0yfe and 0yff. if, by accident, a vis gets executed and no interrupt is ac- tive, then the pc (program counter) will branch to a vector located at 0ye0-0ye1. warning a default vis interrupt handler routine must be present. as a minimum, this handler should confirm that the gie bit is cleared (this indicates that the interrupt sequence has been taken), take care of any required housekeeping, restore context and return. some sort of warm restart procedure should be implemented. these events can occur without any error on the part of the system designer or programmer. note: there is always the possibility of an interrupt occurring during an instruction which is attempting to reset the gie bit or any other inter- rupt enable bit. if this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. this is because interrupt pro- cessing is started at the same time as the interrupt bit is being reset. to avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits. figure 12 shows the interrupt block diagram. software trap the software trap (st) is a special kind of non-maskable interrupt which occurs when the intr instruction (used to acknowledge interrupts) is fetched from rom and placed inside the instruction register. this may happen when the pc is pointing beyond the available rom address space or when the stack is over-popped. when an st occurs, the user can re-initialize the stack pointer and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization pro- cedures) before restarting. the occurrence of an st is latched into the st pending bit. the gie bit is not affected and the st pending bit ( not accessible by the user ) is used to inhibit other interrupts and to direct the program to the st service routine with the vis instruction. the rpnd instruction is used to clear the software interrupt pending bit. this pending bit is also cleared on reset. the st has the highest rank among all interrupts. nothing (except another st) can interrupt an st being serviced. watchdog the devices contain a watchdog and clock monitor. the watchdog is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or ``runaway'' programs. the clock monitor is used to detect the absence of a clock or a very slow clock below a speci- fied rate on the cki pin. the watchdog consists of two independent logic blocks: wd upper and wd lower. wd upper establishes the upper limit on the service window and wd lower defines the lower limit of the service window. servicing the watchdog consists of writing a specific val- ue to a watchdog service register named wdsvr which is memory mapped in the ram. this value is com- posed of three fields, consisting of a 2-bit window select, a 5-bit key data field, and the 1-bit clock monitor select field. table vii shows the wdsvr register. table vii. watchdog service register (wdsvr) window key data clock select monitor x x 01100 y 7 6 54321 0 the lower limit of the service window is fixed at 2048 in- struction cycles. bits 7 and 6 of the wdsvr register allow the user to pick an upper limit of the service window. table viii shows the four possible combinations of lower and upper limits for the watchdog service window. this flexibility in choosing the watchdog service window pre- vents any undue burden on the user software. bits 5, 4, 3, 2 and 1 of the wdsvr register represent the 5-bit key data field. the key data is fixed at 01100. bit 0 of the wdsvr register is the clock monitor select bit. table viii. watchdog service window select wdsvr wdsvr service window bit 7 bit 6 (lower-upper limits) 0 0 2k8k t c cycles 0 1 2k 16k t c cycles 1 0 2k 32k t c cycles 1 1 2k 64k t c cycles clock monitor the clock monitor aboard the device can be selected or deselected under program control. the clock monitor is guaranteed not to reject the clock if the instruction cycle clock (1/t c ) is greater or equal to 10 khz. this equates to a clock input rate on cki of greater or equal to 100 khz. watchdog operation the watchdog and clock monitor are disabled during reset. the device comes out of reset with the watchdog armed, the watchdog window select bits (bits 6, 7 of the wdsvr register) set, and the clock monitor bit (bit 0 of the wdsvr register) enabled. thus, a clock monitor error will occur after coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value, in- cluding the case where the oscillator fails to start. the wdsvr register can be written to only once after reset and the key data (bits 5 through 1 of the wdsvr register) must match to be a valid write. this write to the wdsvr register involves two irrevocable choices: (i) the selection of http://www.national.com 23
watchdog operation (continued) the watchdog service window (ii) enabling or disabling of the clock monitor. hence, the first write to wdsvr register involves selecting or deselecting the clock monitor, select the watchdog service window and match the watch- dog key data. subsequent writes to the wdsvr register will compare the value being written by the user to the watchdog service window value and the key data (bits 7 through 1) in the wdsvr register. table ix shows the se- quence of events that can occur. the user must service the watchdog at least once be- fore the upper limit of the service window expires. the watchdog may not be serviced more than once in every lower limit of the service window. the user may service the watchdog as many times as wished in the time period between the lower and upper limits of the service window. the first write to the wdsvr register is also counted as a watchdog service. the watchdog has an output pin associated with it. this is the wdout pin, on pin 1 of the port g. wdout is active low. the wdout pin is in the high impedance state in the inactive state. upon triggering the watchdog, the logic will pull the wdout (g1) pin low for an additional 16 t c 32 t c cycles after the signal level on wdout pin goes below the lower schmitt trigger threshold. after this delay, the device will stop forcing the wdout output low. the watchdog service window will restart when the wdout pin goes high. it is recommended that the user tie the wdout pin back to v cc through a resistor in order to pull wdout high. a watchdog service while the wdout signal is active will be ignored. the state of the wdout pin is not guaran- teed on reset, but if it powers up low then the watchdog will time out and wdout will enter high impedance state. the clock monitor forces the g1 pin low upon detecting a clock frequency error. the clock monitor error will continue until the clock frequency has reached the minimum speci- fied value, after which the g1 output will enter the high im- pedance tri-state mode following 16 t c 32 t c clock cy- cles. the clock monitor generates a continual clock moni- tor error if the oscillator fails to start, or fails to reach the minimum specified frequency. the specification for the clock monitor is as follows: 1/t c l 10 khzeno clock rejection. 1/t c k 10 hzeguaranteed clock rejection. watchdog and clock monitor summary the following salient points regarding the watchdog and clock monitor should be noted: # both the watchdog and clock monitor detector circuits are inhibited during reset. # following reset, the watchdog and clock moni- tor are both enabled, with the watchdog having the maximum service window selected. # the watchdog service window and clock moni- tor enable/disable option can only be changed once, during the initial watchdog service following reset. # the initial watchdog service must match the key data value in the watchdog service register wdsvr in or- der to avoid a watchdog error. # subsequent watchdog services must match all three data fields in wdsvr in order to avoid watchdog er- rors. # the correct key data value cannot be read from the watchdog service register wdsvr. any attempt to read this key data value of 01100 from wdsvr will read as key data value of all 0's. # the watchdog detector circuit is inhibited during both the halt and idle modes. # the clock monitor detector circuit is active during both the halt and idle modes. consequently, the de- vice inadvertently entering the halt mode will be detect- ed as a clock monitor error (provided that the clock monitor enable option has been selected by the program). # with the single-pin r/c oscillator mask option selected and the clkdly bit reset, the watchdog service win- dow will resume following halt mode from where it left off before entering the halt mode. # with the crystal oscillator mask option selected, or with the single-pin r/c oscillator mask option selected and the clkdly bit set, the watchdog service window will be set to its selected value from wdsvr following halt. consequently, the watchdog should not be serviced for at least 2048 instruction cycles following halt, but must be serviced within the selected window to avoid a watchdog error. # the idle timer t0 is not initialized with reset. # the user can sync in to the idle counter cycle with an idle counter (t0) interrupt or by monitoring the t0pnd flag. the t0pnd flag is set whenever the thirteenth bit of the idle counter toggles (every 4096 instruction cycles). the user is responsible for resetting the t0pnd flag. # a hardware watchdog service occurs just as the de- vice exits the idle mode. consequently, the watch- dog should not be serviced for at least 2048 instruction cycles following idle, but must be serviced within the selected window to avoid a watchdog error. # following reset, the initial watchdog service (where the service window and the clock monitor enable/ disable must be selected) may be programmed any- where within the maximum service window (65,536 in- struction cycles) initialized by reset. note that this ini- tial watchdog service may be programmed within the initial 2048 instruction cycles without causing a watch- dog error. table ix. watchdog service actions key data window data clock monitor action match match match valid service: restart service window don't care mismatch don't care error: generate watchdog output mismatch don't care don't care error: generate watchdog output don't care don't care mismatch error: generate watchdog output http://www.national.com 24
detection of illegal conditions the device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. reading of undefined rom gets zeros. the opcode for soft- ware interrupt is 00. if the program fetches instructions from undefined rom, this will force a software interrupt, thus sig- naling that an illegal condition has occurred. the subroutine stack grows down for each call (jump to subroutine), interrupt, or push, and grows up for each re- turn or pop. the stack pointer is initialized to ram location 06f hex during reset. consequently, if there are more re- turns than calls, the stack pointer will point to addresses 070 and 071 hex (which are undefined ram). undefined ram from addresses 070 to 07f (segment 0), and all other segments (i.e., segments 4... etc.) is read as all 1's, which in turn will cause the program to return to address 7fff hex. this is an undefined rom location and the instruction fetched (all 0's) from this location will generate a software interrupt signaling an illegal condition. thus, the chip can detect the following illegal conditions: 1. executing from undefined rom 2. over ``pop''ing the stack by having more returns than calls. when the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before re- starting (this recovery program is probably similar to that following reset, but might not contain the same program initialization procedures). the recovery program should re- set the software interrupt pending bit using the rpnd in- struction. microwire/plus microwire/plus is a serial synchronous communica- tions interface. the microwire/plus capability enables the device to interface with any of national semiconductor's microwire peripherals (i.e. a/d converters, display driv- ers, e2proms etc.) and with other microcontrollers which support the microwire interface. it consists of an 8-bit serial shift register (sio) with serial data input (si), serial data output (so) and serial shift clock (sk). figure 13 shows a block diagram of the microwire/plus logic. the shift clock can be selected from either an internal source or an external source. operating the microwire/ plus arrangement with the internal clock source is called the master mode of operation. similarly, operating the mi- crowire/plus arrangement with an external shift clock is called the slave mode of operation. the cntrl register is used to configure and control the microwire/plus mode. to use the microwire/plus, the msel bit in the cntrl register is set to one. in the master mode, the sk clock rate is selected by the two bits, sl0 and sl1, in the cntrl register. table x details the different clock rates that may be selected. table x. microwire/plus master mode clock select sl1 sl0 sk period 0 0 2xt c 0 1 4xt c 1 x 8xt c where t c is the instruction cycle clock microwire/plus operation setting the busy bit in the psw register causes the mi- crowire/plus to start shifting the data. it gets reset when eight data bits have been shifted. the user may reset the busy bit by software to allow less than 8 bits to shift. if enabled, an interrupt is generated when eight data bits have been shifted. the device may enter the microwire/plus mode either as a master or as a slave. figure 14 shows how two devices, microcontrollers and several peripherals may be interconnected using the microwire/plus ar- rangements. tl/dd/12869 16 figure 13. microwire/plus block diagram http://www.national.com 25
microwire/plus (continued) warning the sio register should only be loaded when the sk clock is low. loading the sio register while the sk clock is high will result in undefined data in the sio register. sk clock is normally low when not shifting. setting the busy flag when the input sk clock is high in the microwire/plus slave mode may cause the current sk clock for the sio shift register to be narrow. for safety, the busy flag should only be set when the input sk clock is low. microwire/plus master mode operation in the microwire/plus master mode of operation the shift clock (sk) is generated internally. the microwire master always initiates all data exchanges. the msel bit in the cntrl register must be set to enable the so and sk functions onto the g port. the so and sk pins must also be selected as outputs by setting appropriate bits in the port g configuration register. table xi summarizes the bit settings required for master mode of operation. microwire/plus slave mode operation in the microwire/plus slave mode of operation the sk clock is generated by an external source. setting the msel bit in the cntrl register enables the so and sk functions onto the g port. the sk pin must be selected as an input and the so pin is selected as an output pin by setting and resetting the appropriate bits in the port g configuration reg- ister. table xi summarizes the settings required to enter the slave mode of operation. the user must set the busy flag immediately upon entering the slave mode. this will ensure that all data bits sent by the master will be shifted properly. after eight clock pulses the busy flag will be cleared and the sequence may be repeated. table xi. microwire mode settings g4 (so) g5 (sk) g4 g5 operation config. bit config. bit fun. fun.4 1 1 so int. microwire/plus sk master 0 1 tri- int. microwire/plus state sk master 1 0 so ext. microwire/plus sk slave 0 0 tri- ext. microwire/plus state sk slave this table assumes that the control flag msel is set. alternate sk phase operation the device allows either the normal sk clock or an alternate phase sk clock to shift data in and out of the sio register. in both the modes the sk is normally low. in the normal mode data is shifted in on the rising edge of the sk clock and the data is shifted out on the falling edge of the sk clock. the sio register is shifted on each falling edge of the sk clock. in the alternate sk phase operation, data is shift- ed in on the falling edge of the sk clock and shifted out on the rising edge of the sk clock. a control flag, sksel, allows either the normal sk clock or the alternate sk clock to be selected. resetting sksel causes the microwire/plus logic to be clocked from the normal sk signal. setting the sksel flag selects the alter- nate sk clock. the sksel is mapped into the g6 configura- tion bit. the sksel flag will power up in the reset condition, selecting the normal sk signal. tl/dd/12869 17 figure 14. microwire/plus application http://www.national.com 26
memory map all ram, ports and registers (except a and pc) are mapped into data memory address space. address contents s/add reg 0000 to 006f on-chip ram bytes (112 bytes) 0070 to 007f unused ram address space (reads as all ones) xx80 to xxaf unused ram address space (reads undefined data) xxb0 reserved xxb1 reserved xxb2 reserved xxb3 reserved xxb4 reserved xxb5 reserved xxb6 reserved xxb7 comparator select register (cmpsl) xxb8 to xxbf reserved xxc0 reserved xxc1 reserved xxc2 reserved xxc3 reserved xxc4 reserved xxc5 reserved xxc6 reserved xxc7 watchdog service register (reg:wdsvr) xxc8 miwu edge select register (reg:wkedg) xxc9 miwu enable register (reg:wken) xxca miwu pending register (reg:wkpnd) xxcb reserved xxcc captlo (capture timer low-byte) xxcd capthi (capture timer high-byte) xxce capcntl (capture timer control register) xxcf idle timer control register xxd0 port l data register xxd1 port l configuration register xxd2 port l input pins (read only) xxd3 reserved xxd4 port g data register xxd5 port g configuration register xxd6 port g input pins (read only) xxd7 port i input pins (read only) xxd8 reserved xxd9 reserved address contents s/add reg xxda reserved xxdb reserved xxdc port d xxdd to df reserved xxe0 to xxe5 reserved xxe6 timer t1 autoload register t1rb lower byte xxe7 timer t1 autoload register t1rb upper byte xxe8 icntrl register xxe9 microwire/plus shift register xxea timer t1 lower byte xxeb timer t1 upper byte xxec timer t1 autoload register t1ra lower byte xxed timer t1 autoload register t1ra upper byte xxee cntrl control register xxef psw register xxf0 to fb on-chip ram mapped as registers xxfc x register xxfd sp register xxfe b register xxff reserved 0100-017f reserved reading memory locations 0070h-007fh (segment 0) will return all ones. reading unused memory locations 0080h- 00afh (segment 0) will return undefined data. reading memory locations from other segments (i.e., segment 2, segment 3, . . . etc.) will return all ones. http://www.national.com 27
addressing modes there are ten addressing modes, six for operand address- ing and four for transfer of control. operand addressing modes register indirect this is the ``normal'' addressing mode. the operand is the data memory addressed by the b pointer or x pointer. register indirect (with auto post increment or decre- ment of pointer) this addressing mode is used with the ld and x instruc- tions. the operand is the data memory addressed by the b pointer or x pointer. this is a register indirect mode that automatically post increments or decrements the b or x reg- ister after executing the instruction. direct the instruction contains an 8-bit address field that directly points to the data memory for the operand. immediate the instruction contains an 8-bit immediate field as the op- erand. short immediate this addressing mode is used with the load b immediate instruction. the instruction contains a 4-bit immediate field as the operand. indirect this addressing mode is used with the laid instruction. the contents of the accumulator are used as a partial address (lower 8 bits of pc) for accessing a data operand from the program memory. transfer of control addressing modes relative this mode is used for the jp instruction, with the instruction field being added to the program counter to get the new program location. jp has a range from b 31 to a 32 to allow a 1-byte relative jump (jp a 1 is implemented by a nop instruction). there are no ``pages'' when using jp, since all 15 bits of pc are used. absolute this mode is used with the jmp and jsr instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (pc). this allows jumping to any loca- tion in the current 4k program memory segment. absolute long this mode is used with the jmpl and jsrl instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (pc). this allows jumping to any location up to 32k in the program memory space. indirect this mode is used with the jid instruction. the contents of the accumulator are used as a partial address (lower 8 bits of pc) for accessing a location in the program memory. the contents of this program memory location serve as a partial address (lower 8 bits of pc) for the jump to the next instruc- tion. note: the vis is a special case of the indirect transfer of control address- ing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (pc) in order to jump to the associated interrupt service routine. instruction set register and symbol definition registers a 8-bit accumulator register b 8-bit address register x 8-bit address register sp 8-bit stack pointer register pc 15-bit program counter register pu upper 7 bits of pc pl lower 8 bits of pc c 1-bit of psw register for carry hc 1-bit of psw register for half carry gie 1-bit of psw register for global interrupt enable vu interrupt vector upper byte vl interrupt vector lower byte symbols [ b ] memory indirectly addressed by b register [ x ] memory indirectly addressed by x register md direct addressed memory mem direct addressed memory or [ b ] meml direct addressed memory or [ b ] or immediate data imm 8-bit immediate data reg register memory: addresses f0 to ff (includes b, x and sp) bit bit number (0 to 7) w loaded with y exchanged with http://www.national.com 28
instruction set add a,meml add a w a a meml adc a,meml add with carry a w a a meml a c, c w carry, hc w half carry subc a,meml subtract with carry a w a b memi a c, c w carry, hc w half carry and a,meml logical and a w a and meml andsz a,imm logical and immed., skip if zero skip next if (a and imm) e 0 or a,meml logical or a w a or meml xor a,meml logical exclusive or a w a xor meml ifeq md,imm if equal compare md and imm, do next if md e imm ifeq a,meml if equal compare a and meml, do next if a e meml ifne a,meml if not equal compare a and meml, do next if a i meml ifgt a,meml if greater than compare a and meml, do next if a l meml ifbne y if b not equal do next if lower 4 bits of b i imm drsz reg decrement reg., skip if zero reg w reg b 1, skip if reg e 0 sbit y ,mem set bit 1 to bit, mem (bit e 0 to 7 immediate) rbit y ,mem reset bit 0 to bit, mem ifbit y ,mem if bit if bit y ,a or mem is true do next instruction rpnd reset pending flag reset software interrupt pending flag x a,mem exchange a with memory a y mem xa, [ x ] exchange a with memory [ x ] a y [ x ] ld a,meml load a with memory a w meml ld a, [ x ] load a with memory [ x ] a w [ x ] ld b,imm load b with immed. b w imm ld mem,imm load memory immed mem w imm ld reg,imm load register memory immed. reg w imm xa, [ b g ] exchange a with memory [ b ] a y [ b ] ,(b w b g 1) xa, [ x g ] exchange a with memory [ x ] a y [ x ] ,(x w x g 1) ld a, [ b g ] load a with memory [ b ] a w [ b ] ,(b w b g 1) ld a, [ x g ] load a with memory [ x ] a w [ x ] ,(x w x g 1) ld [ b g ] ,imm load memory [ b ] immed. [ b ] w imm, (b w b g 1) clr a clear a a w 0 inc a increment a a w a a 1 dec a decrement a a w a b 1 laid load a indirect from rom a w rom (pu,a) dcor a decimal correct a a w bcd correction of a (follows adc, subc) rrc a rotate a right thru c c x a7 x ... x a0 x c rlc a rotate a left thru c c w a7 w ... w a0 w c swap a swap nibbles of a a7...a4 y a3...a0 sc set c c w 1, hc w 1 rc reset c c w 0, hc w 0 ifc if c if c is true, do next instruction ifnc if not c if c is not true, do next instruction pop a pop the stack into a sp w sp a 1, a w [ sp ] push a push a onto the stack [ sp ] w a, sp w sp b 1 vis vector to interrupt service routine pu w [ vu ] ,pl w [ vl ] jmpl addr. jump absolute long pc w ii (ii e 15 bits, 0 to 32k) jmp addr. jump absolute pc9...0 w i(i e 12 bits) jp disp. jump relative short pc w pc a r(ris b 31 to a 32, except 1) jsrl addr. jump subroutine long [ sp ] w pl, [ sp-1 ] w pu,sp-2, pc w ii jsr addr jump subroutine [ sp ] w pl, [ sp-1 ] w pu,sp-2, pc9...0 w i jid jump indirect pl w rom (pu,a) ret return from subroutine sp a 2, pl w [ sp ] ,pu w [ sp-1 ] retsk return and skip sp a 2, pl w [ sp ] ,pu w [ sp-1 ] , skip next instruction reti return from interrupt sp a 2, pl w [ sp ] ,pu w [ sp-1 ] ,gie w 1 intr generate an interrupt [ sp ] w pl, [ sp-1 ] w pu, sp-2, pc w 0ff nop no operation pc w pc a 1 http://www.national.com 29
instruction execution time most instructions are single byte (with immediate address- ing mode instructions taking two bytes). most single byte instructions take one cycle time to execute. skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. see the bytes and cycles per instruction table for details. bytes and cycles per instruction the following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. arithmetic and logic instructions [ b ] direct immed add 1/1 3/4 2/2 adc 1/1 3/4 2/2 subc 1/1 3/4 2/2 and 1/1 3/4 2/2 or 1/1 3/4 2/2 xor 1/1 3/4 2/2 ifeq 1/1 3/4 2/2 ifgt 1/1 3/4 2/2 ifbne 1/1 drsz 1/1 1/3 sbit 1/1 3/4 rbit 1/1 3/4 ifbit 1/1 3/4 rpnd 1/1 instructions using a and c clra 1/1 inca 1/1 deca 1/1 laid 1/3 dcora 1/1 rrca 1/1 rlca 1/1 swapa 1/1 sc 1/1 rc 1/1 ifc 1/1 ifnc 1/1 pusha 1/3 popa 1/3 andsz 2/2 transfer of control instructions jmpl 3/4 jmp 2/3 jp 1/3 jsrl 3/5 jsr 2/5 jid 1/3 vis 1/5 ret 1/5 retsk 1/5 reti 1/5 intr 1/7 nop 1/1 memory transfer instructions register direct immed. register indirect indirect auto incr and decr [ b ][ x ][ b a ,b b ][ x a ,x b ] xa, * 1/1 1/3 2/3 1/2 1/3 ld a, * 1/1 1/3 2/3 2/2 1/2 1/3 ld b,imm 1/1 (if b k 16) ld b,imm 2/2 (if b l 15) ld mem,imm 2/2 3/3 2/2 ld reg,imm 2/3 ifeq md,imm 3/3 * memory location addressed by b or x or directly. http://www.national.com 30
lower nibble opcode table upper nibble fe d c b a 9 8 76 5 4 3 2 1 0 jp b 15 jp b 31 ld 0f0, y i drsz 0f0 rrca rc adc a, y i adc a, [ b ] ifbit andsz ld b, y 0f ifbne 0 jsr jmp jp a 17 intr 0 0, [ b ] a, y i x000 x0ff x000 x0ff jp b 14 jp b 30 ld 0f1, y i drsz 0f1 * sc subc subc a, [ b ] ifbit * ld b, y 0e ifbne 1 jsr jmp jp a 18 jp a 21 a, y i1, [ b ] x100 x1ff x100 x1ff jp b 13 jp b 29 ld 0f2, y i drsz 0f2 x a, x a, ifeq a, ifeq a, [ b ] ifbit * ld b, y 0d ifbne 2 jsr jmp jp a 19 jp a 32 [ x a ][ b a ] y i2, [ b ] x200 x2ff x200 x2ff jp b 12 jp b 28 ld 0f3, y i drsz 0f3 x a, x a, ifgt a, ifgt a, [ b ] ifbit * ld b, y 0c ifbne 3 jsr jmp jp a 20 jp a 43 [ x b ][ b b ] y i3, [ b ] x300 x3ff x300 x3ff jp b 11 jp b 27 ld 0f4, y i drsz 0f4 vis laid add a, add a, [ b ] ifbit clra ld b, y 0b ifbne 4 jsr jmp jp a 21 jp a 54 y i4, [ b ] x400 x4ff x400 x4ff jp b 10 jp b 26 ld 0f5, y i drsz 0f5 rpnd jid and a, and a, [ b ] ifbit swapa ld b, y 0a ifbne 5 jsr jmp jp a 22 jp a 65 y i5, [ b ] x500 x5ff x500 x5ff jp b 9jp b 25 ld 0f6, y i drsz 0f6 x a, [ x ] xa, [ b ] xor a, xor a, [ b ] ifbit dcora ld b, y 09 ifbne 6 jsr jmp jp a 23 jp a 76 y i6, [ b ] x600 x6ff x600 x6ff jp b 8jp b 24 ld 0f7, y i drsz 0f7 ** or a, y iora, [ b ] ifbit pusha ld b, y 08 ifbne 7 jsr jmp jp a 24 jp a 87 7, [ b ] x700 x7ff x700 x7ff jp b 7jp b 23 ld 0f8, y i drsz 0f8 nop rlca ld a, y i ifc sbit rbit ld b, y 07 ifbne 8 jsr jmp jp a 25 jp a 98 0, [ b ] 0, [ b ] x800 x8ff x800 x8ff jp b 6jp b 22 ld 0f9, y i drsz 0f9 ifne ifeq ifne ifnc sbit rbit ld b, y 06 ifbne 9 jsr jmp jp a 26 jp a 10 9 a, [ b ] md, y ia, y i1, [ b ] 1, [ b ] x900 x9ff x900 x9ff jp b 5jp b 21 ld 0fa, y i drsz 0fa ld a, ld a, ld [ b a ] , inca sbit rbit ld b, y 05 ifbne 0a jsr jmp jp a 27 jp a 11 a [ x a ][ b a ] y i2, [ b ] 2, [ b ] xa00 xaff xa00 xaff jp b 4jp b 20 ld 0fb, y i drsz 0fb ld a, ld a, ld [ b b ] , deca sbit rbit ld b, y 04 ifbne 0b jsr jmp jp a 28 jp a 12 b [ x b ][ b b ] y i3, [ b ] 3, [ b ] xb00 xbff xb00 xbff jp b 3jp b 19 ld 0fc, y i drsz 0fc ld md, y i jmpl x a,md popa sbit rbit ld b, y 03 ifbne 0c jsr jmp jp a 29 jp a 13 c 4, [ b ] 4, [ b ] xc00 xcff xc00 xcff jp b 2jp b 18 ld 0fd, y i drsz 0fd dir jsrl ld a,md retsk sbit rbit ld b, y 02 ifbne 0d jsr jmp jp a 30 jp a 14 d 5, [ b ] 5, [ b ] xd00 xdff xd00 xdff jp b 1jp b 17 ld 0fe, y i drsz 0fe ld a, [ x ] ld a, [ b ] ld [ b ] , y i ret sbit rbit ld b, y 01 ifbne 0e jsr jmp jp a 31 jp a 15 e 6, [ b ] 6, [ b ] xe00 xeff xe00 xeff jp b 0jp b 16 ld 0ff, y i drsz 0ff ** ld b, y i reti sbit rbit ld b, y 00 ifbne 0f jsr jmp jp a 32 jp a 16 f 7, [ b ] 7, [ b ] xf00 xfff xf00 xfff where, i is the immediate data md is a directly addressed memory location * is an unused opcode note: the opcode 60 hex is also the opcode for ifbit y i,a http://www.national.com 31
development support summary # icemaster: im-cop8/400efull feature in-circuit emu- lation for all cop8 products. a full set of cop8 basic and feature family device and package specific probes are available. # cop8 debug module: moderate cost in-circuit emulation and development programming unit. # assembler: cop8-dev-ibma. a dos installable cross development assembler, linker, librarian and utility software development tool kit. # c compiler: cop8c. a dos installable cross develop- ment software tool kit. # otp/eprom programmer support: covering needs from engineering prototype, pilot production to full pro- duction environments. icemaster (im) in-circuit emulation the icemaster im-cop8/400 is a full feature, pc based, in-circuit emulation tool developed and marketed by metalink corporation to support the whole cop8 family of products. national is a resale vendor for these products. see figure 15 for configuration. the icemaster im-cop8/400 with its device specific cop8 probe provides a rich feature set for developing, test- ing and maintaining product: # real-time in-circuit emulation; full 2.4v 5.5v operation range, full dc-10 mhz clock. chip options are program- mable or jumper selectable. # direct connection to application board by package com- patible socket or surface mount assembly. # full 32 kbyte of loadable programming space that over- lays (replaces) the on-chip rom or eprom. on-chip ram and i/o blocks are used directly or recreated on the probe as necessary. # full 4k frame synchronous trace memory. address, in- struction, and eight unspecified, circuit connectable trace lines. display can be hll source (e.g., c source), assem- bly or mixed. # a full 64k hardware configurable break, trace on, trace off control, and pass count increment events. # tool set integrated interactive symbolic debuggeresup- ports both assembler (coff) and c compiler (.cod) linked object formats. # real time performance profiling analysis; selectable bucket definition. # watch windows, content updated automatically at each execution break. # instruction by instruction memory/register changes dis- played on source window when in single step operation. # single base unit and debugger software reconfigurable to support the entire cop8 family; only the probe personali- ty needs to change. debugger software is processor cus- tomized, and reconfigured from a master model file. # processor specific symbolic display of registers and bit level assignments, configured from master model file. # halt/idle mode notification. # on-line help customized to specific processor using master model file. # includes a copy of cop8-dev-ibma assembler and link- er sdk. im order information base unit im-cop8/400-1 icemaster base unit, 110v power supply im-cop8/400-2 icemaster base unit, 220v power supply icemaster probe cop8ac-im28n 28 dip cop8ac-im20n 20 dip surface mount adapter mhw-soic28 28 so mhw-soic20 20 so tl/dd/12869 18 figure 15. cop8 icemaster environment http://www.national.com 32
development support (continued) icemaster debug module (dm) the icemaster debug module is a pc based, combination in-circuit emulation tool and cop8 based otp/eprom pro- gramming tool developed and marketed by metalink corpo- ration to support the whole cop8 family of products. nation- al is a resale vendor for these products. see figure 16 for configuration. the icemaster debug module is a moderate cost devel- opment tool. it has the capability of in-circuit emulation for a specific cop8 microcontroller and in addition serves as a programming tool for cop8 otp and eprom product fami- lies. summary of features is as follows: # real-time in-circuit emulation; full operating voltage range operation, full dc-10 mhz clock. # all processor i/o pins can be cabled to an application development board with package compatible cable to socket and surface mount assembly. # full 32 kbyte of loadable programming space that over- lays (replaces) the on-chip rom or eprom. on-chip ram and i/o blocks are used directly or recreated as necessary. # 100 frames of synchronous trace memory. the display can be hll source (c source), assembly or mixed. the most recent history prior to a break is available in the trace memory. # configured break points; uses intr instruction which is modestly intrusive. # softwareeonly supported features are selectable. # tool set integrated interactive symbolic debuggeresup- ports both assembler (coff) and c compiler (.cod) sdk linked object formats. # instruction by instruction memory/register changes dis- played when in single step operation. # debugger software is processor customized, and recon- figured from a master model file. # processor specific symbolic display of registers and bit level assignments, configured from master model file. # halt/idle mode notification. # programming menu supports full product line of program- mable otp and eprom cop8 products. program data is taken directly from the overlay ram. # programming of 44plcc and 68plcc parts requires ex- ternal programming adapters. # includes wallmount power supply. # on-board v pp generator from 5v input or connection to external supply supported. requires v pp level adjust- ment per the family programming specification (correct level is provided on an on-screen pop-down display). # on-line help customized to specific processor using master model file. # includes a copy of cop8-dev-ibma assembler and link- er sdk. dm order information debug module unit cop8ac-dm cable adapters dm-cop8/28d 28 dip dm-cop8/20d 20 dip surface mount adapters dm-cop8/28d-so 28 dip to so dm-cop8/20d-so 20 dip to so tl/dd/12869 19 figure 16. cop-dm environment http://www.national.com 33
development support (continued) cop8 assembler/linker software development tool kit national semiconductor offers a relocatable cop8 macro cross assembler, linker, librarian and utility software devel- opment tool kit. features are summarized as follows: # basic and feature family instruction set by ``device'' type. # nested macro capability. # extensive set of assembler directives. # supported on pc/dos platform. # generates national standard coff output files. # integrated linker and librarian. # integrated utilities to generate rom code file outputs. # dumpcoff utility. this product is integrated as a part of metalink tools as a development kit, fully supported by the metalink debugger. it may be ordered separately or it is bundled with the meta- link products at no additional cost. order information assembler sdk: cop8-dev-ibma assembler sdk on installable 3.5 pc/dos floppy disk drive format. periodic upgrades and most recent version is available on national's bbs and internet. cop8 c compiler a c compiler is developed and marketed by byte craft lim- ited. the cop8c compiler is a fully integrated development tool specifically designed to support the compact embed- ded configuration of the cop8 family of products. features are summarized as follows: # ansi c with some restrictions and extensions that opti- mize development for the cop8 embedded application. # bits data type extension. register declaration y pragma with direct bit level definitions. # c language support for interrupt routines. # expert system, rule based code generation and optimiza- tion. # performs consistency checks against the architectural definitions of the target cop8 device. # generates program memory code. # supports linking of compiled object or cop8 assembled object formats. # global optimization of linked code. # symbolic debug load format fully source level supported by the metalink debugger. single chip otp/emulator support the cop8 family is supported by single chip otp emula- tors. for detailed information refer to the emulator specific datasheet and the emulator selection table below: otp emulator ordering information device number clock package emulates option cop8acc720mx crystal 20 so cop8acc720mx cop8acc728nx crystal 20 dip cop8acc728nx cop8acc728mx crystal 20 so cop8acc728mx x e temp. range (6, 7, 8) industry wide otp/eprom programming support programming support, in addition to the metalink develop- ment tools, is provided by a full range of independent ap- proved vendors to meet the needs from the engineering laboratory to full production. approved list: manufacturer north europe asia america bp (800) 225-2102 a 49-8152-4183 a 852-234-16611 microsystems (713) 688-4600 a 49-8856-932616 a 852-2710-8121 fax: (713) 688-0920 data i/o (800) 426-1045 a 44-0734-440011 call (206) 881-6444 north america fax: (206) 882-1043 hi lo (510) 623-8860 call asia a 886-2-764-0215 fax: a 886-2-756-6403 ice (800) 624-8949 a 44-1226-767404 technology (919) 430-7915 fax: 0-1226-370-434 metalink (800) 638-2423 a 49-80 9156 96-0 a 852-737-1800 (602) 926-0797 fax: a 49-80 9123 86 fax: (602) 693-0681 systems (408) 263-6667 a 41-1-9450300 a 886-2-917-3005 general fax: a 886-2-911-1283 needhams (916) 924-8037 fax: (916) 924-8065 http://www.national.com 34
development support (continued) available literature for more information, please see the cop8 basic family user's manual, literature number 620895, cop8 feature family user's manual, literature number 620897 and na- tional's family of 8-bit microcontrollers cop8 selection guide, literature number 630009. dial-a-helper service dial-a-helper is a service provided by the microcontroller applications group. the dial-a-helper is an electronic infor- mation system that may be accessed as a bulletin board system (bbs) via data modem, as an ftp site on the inter- net via standard ftp client application or as an ftp site on the internet using a standard internet browser such as net- scape or mosaic. the dial-a-helper system provides access to an automated information storage and retrieval system. the system capa- bilities include a message section (electronic mail, when accessed as a bbs) for communications to and from the microcontroller applications group and a file sec- tion which consists of several file areas where valuable application software and utilities could be found. dial-a-helper bbs via a standard modem modem: canada/u.s.: (800) nsc-micro (800) 672-6427 europe: ( a 49) 0-814-135 13 32 baud: 14.4k set-up: length: 8-bit parity: none stop bit: 1 operation: 24 hours, 7 days dial-a-helper via ftp ftp nscmicro.nsc.com user: anonymous password: username @ yourhost.site.domain dial-a-helper via a worldwide web browser ftp://nscmicro.nsc.com national semiconductor on the worldwide web see us on the worldwide web at: http://www.national.com customer response center complete product information and technical support is avail- able from national's customer response centers. canada/u.s.: tel: (800) 272-9959 email: support @ tevm2.nsc.com europe: email: europe.support @ nsc.com deutsch tel: a 49 (0) 180-530 85 85 english tel: a 49 (0) 180-532 78 32 fran 3 ais tel: a 49 (0) 180-532 93 58 italiano tel: a 49 (0) 180-534 16 80 japan: tel: a 81-043-299-2309 s.e. asia: beijing tel: ( a 86) 10-6856-8601 shanghai tel: ( a 86) 21-6415-4092 hong kong tel: ( a 852) 2737-1600 korea tel: ( a 82) 2-3771-6909 malaysia tel: ( a 60-4) 644-9061 singapore tel: ( a 65) 255-2226 taiwan tel: a 886-2-521-3288 australia: tel: ( a 61) 3-9558-9999 india: tel: ( a 91) 80-559-9467 http://www.national.com 35
physical dimensions inches (millimeters) unless otherwise noted order number cop8acc728n9, cop8acc728n8 or cop8acc728n6 ns molded package number n28b http://www.national.com 36
physical dimensions inches (millimeters) unless otherwise noted (continued) order number cop8acc728m9, cop8acc728m8 or cop8acc728m6 ns molded package number m28b http://www.national.com 37
cop8acc7 8-bit one time programmable (otp) microcontroller with high resolution a/d conversion physical dimensions inches (millimeters) unless otherwise noted (continued) order number cop8acc720m9, cop8acc720m8 or cop8acc720m6 ns molded package number m20b life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or 2. a critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: a 49 (0) 180-530 85 86 13th floor, straight block, tel: 81-043-299-2308 arlington, tx 76017 email: europe.support @ nsc.com ocean centre, 5 canton rd. fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch tel: a 49 (0) 180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english tel: a 49 (0) 180-532 78 32 hong kong fran 3 ais tel: a 49 (0) 180-532 93 58 tel: (852) 2737-1600 http://www.national.com italiano tel: a 49 (0) 180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications.

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