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data s heet 8-bit single-chip microcontrollers mos integrated circuits m m m m pd78f9136a document no. u14690ej1v0ds00 (1st edition) date published february 2000 ns cp(k) printed in japan 2000 the m pd78f9136a is a m pd789134a subseries product of the 78k/0s series. the m pd78f9136a replaces the internal masked rom of the m pd789131a,789132a and 789134a with flash memory, which enables the writing/erasing of a program while the device is mounted on the board. because the device can be programmed by the user, it is ideally suited to the evaluation stages of system development, the manufacture of small batches of multiple products, and the rapid development of new products. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m m m m pd789104a, 789114a, 789124a, 789134a subseries users manual: to be prepared 78k/0s series user's manual instruction: u11047e features pin-compatible with masked rom version (excluding v pp pin) flash memory: 16k bytes internal high-speed ram: 256 bytes built-in rc oscillator on-chip multiplier: 8 bits 8 bits = 16 bits minimum instruction execution time can be changed from high-speed (0.5 m s) to low-speed (2.0 m s) (@ 4.0-mhz operation with system clock) i/o ports: 20 serial interface: 1 channel: switchable between 3-wire serial i/o and uart modes 10-bit resolution a/d converter: 4 channels timers: 3 channels 16-bit timer: 1 channel 8-bit timer/event counter: 1 channel watchdog timer: 1 channel power supply voltage: v dd = 1.8 to 5.5 v applications cleaners, washing machines, refrigerators and battery-charger ordering information part number package m pd78f9136amc-5a4 30-pin plastic ssop (7.62mm (300)) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet u14690ej1v0ds00 2 m m m m pd 78 f 9136 a 78k/0s series lineup the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 78k/0s series small, general-purpose small, general-purpose + a/d for inverter control for driving lcd for assp 44 pins 44 pins 42/44 pins 28 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins 44 pins products under mass production products under development y subseries supports smb. pd789014 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins 44 pins 44 pins 20 pins 20 pins m pd789026 m pd789046 pd789026 with subsystem clock added pd789014 with timer reinforced and rom and ram expanded uart. low-voltage (1.8-v) operation pd789167 with improved a/d pd789104a with improved timer pd789146 with improved a/d pd789104a with eeprom added pd789124a with improved a/d rc oscillation model of pd789104a pd789104a with improved a/d pd789026 with a/d and multiplier added pd789407a with improved a/d pd789456 with improved i/o pd789446 with improved a/d pd789426 with improved display output pd789426 with improved a/d pd789306 with a/d added rc oscillation model of pd789306 basic subseries for driving lcd for pc keyboard. internal usb function for key pad. internal poc rc oscillation model of pd789860 for keyless entry. internal poc and key return circuit internal inverter control circuit and uart m pd789104a m pd789114a m pd789842 m pd789124a m pd789134a m pd789146 m pd789156 m pd789167 m pd789177 m pd789306 m pd789316 m pd789426 m pd789436 m pd789860 m pd789861 m pd789840 m pd789800 m pd789446 m pd789456 m pd789167y m pd789177y m m m m m m m m m m m m m m m m m m m pd789407a m pd789417a m 88 pins segment: 40 pins, common: 16 pins pd789830 m 144 pins segment/common output: 96 pins pd789835 m for driving dot lcd 52 pins 52 pins for remote controller. internal lcd controller/driver pd789327 m pd789467 m pd789327 with a/d added m
data sheet u14690ej1v0ds00 3 m m m m pd 78 f 9136 a the major differences between subseries are shown below. timer rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o v dd min value remark m pd789046 16 k 1 ch m pd789026 4 k-16 k 1 ch 1 ch 34 pins small, general- purpose m pd789014 2 k-4 k 2 ch - - 1 ch -- 1 ch (uart:1 ch) 22 pins 1.8 v - m pd789177 - 8 ch m pd789167 16 k-24 k 3 ch 1 ch 8 ch - 31 pins - m pd789156 - 4 ch m pd789146 8 k-16 k 4 ch - internal eeprom m pd789134a 4 ch m pd789124a 4 ch - rc oscillation version m pd789114a - 4 ch small, general- purpose + a/d m pd789104a 2 k-8 k 1 ch 1 ch - 1 ch 4 ch - 1 ch (uart: 1 ch) 20 pins 1.8 v - for inverter control m pd789842 8 k-16 k 3 ch note 1 ch 1 ch 8 ch - 1 ch (uart: 1 ch) 30 pins 4.0 v - m pd789417a 7 ch m pd789407a 12 k-24 k 3 ch 7 ch - 43 pins m pd789456 - 6 ch m pd789446 6 ch - 30 pins m pd789436 - 6 ch m pd789426 12 k-16 k 6 ch 1 ch (uart: 1 ch) 40 pins - m pd789316 rc oscillation version for lcd driving m pd789306 8 k to 16k 2 ch 1 ch 1 ch 1 ch - - 2 ch (uart: 1 ch) 23 pins 1.8 v - m pd789835 24 k-60 k 6 ch - 2 ch 1 ch 27 pins 1.8 v for dot lcd driving m pd789830 24 k 1 ch 1 ch 1 ch 1 ch - - 1 ch (uart: 1 ch) 30 pins 2.7 v - m pd789467 1 ch - 18 pins m pd789327 4 k-24 k 2 ch - 1 ch 1 ch - 1 ch 21 pins 1.8 v internal lcd m pd789800 - 2 ch (usb: 1 ch) 31 pins 4.0 v m pd789840 8 k 1 ch 4 ch 1 ch 29 pins 2.8 v - m pd789861 rc oscillation version, internal eeprom assp m pd789860 4 k 2 ch - - 1 ch - - - 14 pins 1.8 v internal eeprom note 10-bit timer: 1 channel function subseries name
data sheet u14690ej1v0ds00 4 m m m m pd 78 f 9136 a overview of functions item function flash memory 16 kbytes internal memory high-speed ram 256 bytes oscillator rc oscillator minimum instruction execution time 0.5/2.0 m s (@ 4.0-mhz operation with system clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 20 cmos input: 4 cmos i/o: 12 n-ch open-drain (12-v withstand voltage): 4 a/d converters 10-bit resolution 4 channels serial interface switchable between 3-wire serial i/o and uart modes timer 16-bit timer: 1 channel 8-bit timer/event counter: 1 channel watchdog timer: 1 channel timer output 1 output (16-bit/8-bit timer alternate function) maskable internal: 6, external: 3 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to + 85c package 30-pin plastic ssop (7.62 mm (300))
data sheet u14690ej1v0ds00 5 m m m m pd 78 f 9136 a contents 1. pin configuration (top view).............................................................................................. 6 2. block diagram ............................................................................................................... ............ 7 3. differences between m m m m pd78f9136a and masked rom version .................................. 8 4. pin functions ............................................................................................................... ............... 9 4.1 port pins................................................................................................................... ............................... 9 4.2 non-port pins............................................................................................................... ........................... 10 4.3 pin i/o circuits and recommended connection of unused pins...................................................... 11 5. memory space................................................................................................................ ............. 13 6. flash memory programming ................................................................................................. 14 6.1 selecting communication mode ................................................................................................ ........... 14 6.2 function of flash memory programming ........................................................................................ .... 15 6.3 flashpro iii connection..................................................................................................... ..................... 15 6.4 example of settings for flashpro iii (pg-fp3) ............................................................................... ...... 17 7. instruction set overview ................................................................................................... .18 7.1 conventions................................................................................................................. ........................... 18 7.2 operations .................................................................................................................. ............................ 20 8. electrical specifications ................................................................................................... .25 9. example of rc oscillator frequency characteristics (reference values)............................................................................................................ ..... 37 10. package drawing............................................................................................................ .......... 39 11. recommended soldering conditions .............................................................................. 40 appendix a development tools .............................................................................................. 4 1 appendix b related documents.............................................................................................. 4 3
data sheet u14690ej1v0ds00 6 m m m m pd 78 f 9136 a 1. pin configuration (top view) 30-pin plastic ssop (7.62 mm (300)) m pd78f9136amc-5a4 p23/intp0/cpt20/ss20 p24/intp1/to80/to20 p25/intp2/ti80 av dd p60/ani0 p61/ani1 p62/ani2 p63/ani3 av ss p50 ic0 p51 p52 p53 p00 28 27 26 30 29 25 24 23 22 21 20 19 18 16 p22/si20/r x d20 p21/so20/t x d20 p20/sck20/asck20 p11 p10 v dd v ss cl1 cl2 v pp ic0 reset p03 p02 p01 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 cautions 1. connect the ic0 (internally connected) pin directly to v ss . 2. connect the v pp pin directry to v ss in normal operation mode. 3. connect the av dd pin to v dd . 4. connect the av ss pin to v ss . ani0 to ani3: analog input reset: reset asck20: asynchronous serial input r x d20: receive data av dd : analog power supply sck20: serial clock input/output av ss : analog ground si20: serial data input cl1,cl2: rc oscillator so20: serial data output cpt20: capture trigger input ss20: chip select input ic0: internally connected ti80: timer input intp0 to intp2: interrupt from peripherals to20, to80: timer output p00 to p03: port0 t x d20: transmit data p10, p11: port1 v dd : power supply p20 to p25: port2 v pp : programing power supply p50 to p53: port5 v ss : ground p60 to p63: port6
data sheet u14690ej1v0ds00 7 m m m m pd 78 f 9136 a 2. block diagram 78k/0s cpu core flash memory ram v dd v ss ic0 ti80/intp2/p25 8-bit timer/ event counter 80 to80/to20 /intp1/p24 p00 to p03 port 0 p10, p11 port 1 p20 to p25 port 2 p50 to p53 port 5 p60 to p63 port 6 system control to20/to80 /intp1/p24 cpt20/intp0 /ss20/p23 16-bit timer 20 watchdog timer serial interface 20 sck20/asck20 /p20 si20/rxd20/p22 so20/txd20/p21 ss20/intp0 /cpt20/p23 a/d converter ani0/p60 to ani3/p63 av dd av ss reset cl1 cl2 interrupt control intp0/cpt20 /p23/ss20 intp1/to80 /to20/p24 intp2/ti80/p25 v pp
data sheet u14690ej1v0ds00 8 m m m m pd 78 f 9136 a 3. differences between m m m m pd78f9136a and masked rom version the m pd78f9136a is a product that substitutes flash memory for the internal rom of the masked rom version. the differences between the m pd78f9136a and the masked rom versions are shown in table 3-1. table 3-1. types of pin input/output circuits flash memory version masked rom version item m pd78f9136a m pd789131a m pd789132a m pd789134a rom 16kbytes (flash memory) 2 kbytes 4 kbytes 8 kbytes internal memory high-speed ram 256 bytes pull-up resistor 12 ( software control only ) 16 ( software control : 12, mask option specification : 4 ) v pp pin provided not provided electric characteristics see the relevant data sheet caution there are differences in the amount of noise tolerance and noise radiation between flash memory versions and masked rom versions. when considering changing from a flash memory version to a masked rom version during process from experimental manufacturing to mass production, make sure to sufficiently evaluate the masked rom versions using commercial samples (cs) (not engineering samples (es)).
data sheet u14690ej1v0ds00 9 m m m m pd 78 f 9136 a 4. pin functions 4.1 port pins pin name i/o function after reset alternate function p00 to p03 i/o port 0 4-bit input/output port input/output can be specified in 1-bit units when used as an input port, an on-chip pull-up resistor can be specified by means of software. input C p10, p11 i/o port 1 2-bit input/output port input/output can be specified in 1-bit units when used as an input port, an on-chip pull-up resistor can be specified by means of software. input C p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 intp0/cpt20 /ss20 p24 intp1/to80/to20 p25 i/o port 2 6-bit input/output port input/output can be specified in 1-bit units when used as an input port, an on-chip pull-up resistor can be specified by means of software. input intp2/ti80 p50 to p53 i/o port 5 4-bit n-ch open-drain input/output port input/output can be specified in 1-bit units an on-chip pull-up resistor can be specified by the mask option. input C p60 to p63 input port 6 4-bit input-only port input ani0 to ani3
data sheet u14690ej1v0ds00 10 m m m m pd 78 f 9136 a 4.2 non-port pins pin name i/o function after reset alternate function intp0 p23/cpt20/ss20 intp1 p24/to80/to20 intp2 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p25/ti80 si20 input serial interface serial data input input p22/rxd20 so20 output serial interface serial data output input p21/txd20 sck20 i/o serial interface serial clock input/output input p20/asck20 asck20 input serial clock input for asynchronous serial interface input p20/sck20 ss20 input chip select input for serial interface input p23/cpt20/intp0 rxd20 input serial data input for asynchronous serial interface input p22/si20 txd20 output serial data output for asynchronous serial interface input p21/so20 ti80 input external count clock input to 8-bit timer/event counter 80 input p25/intp2 to80 output 8-bit timer/event counter 80 output input p24/intp1/to20 to20 output 16-bit timer 20 output input p24/intp1/to80 cpt20 input capture edge input input p23/intp0/ss20 ani0 to ani3 input a/d converter analog input input p60 to p63 av dd - a/d converter analog power supply C C av ss - a/d converter ground potential C C cl1 input CC cl2 - connected to resistor (r) or capacitor (c) CC reset input system reset input input C v dd - positive power supply C C v ss - ground potential C C v pp - sets flash memory programming mode. applies high voltage when a program is written or verified. connect directly to v ss in normal operation mode. CC ic0 - internally connected. connect directly to v ss .CC
data sheet u14690ej1v0ds00 11 m m m m pd 78 f 9136 a 4.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 4-1. for the input/output circuit configuration of each type, refer to figure 4-1. table 4-1. types of pin input/output circuits pin name input/output circuit type i/o recommended connection of unused pins p00 to p03 p10, p11 5-a p20/sck20/asck20 p21/so20/t x d20 p22/si20/r x d20 input: independently connect to v dd or v ss via a resistor. output: leave open p23/intp0/cpt20/ss20 p24/intp1/to80/to20 p25/intp2/ti80 8-a input: independently connect to v ss via a resistor. output: leave open p50 to p53 13-v i/o input: independently connect to v dd via a resistor. output: leave open p60/ani0 to p63/ani3 9-c input connect directly to v dd or v ss . av dd connect to v dd . av ss CC connect to v ss . reset 2 input C v pp ic0 C C connect directly to v ss .
data sheet u14690ej1v0ds00 12 m m m m pd 78 f 9136 a figure 4-1. pin input/output circuits schmitt-triggered input with hysteresis characteristics type 2 in type 5-a pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n-ch type 13-v v ss v ss type 8-a pull-up enable data output disable v dd p-ch v dd p-ch in/out n-ch v ss type 9-c in comparator + C v ref (threshold voltage) av ss p-ch n-ch input enable output data output disable in/out n-ch middle-voltage input buffer input enable
data sheet u14690ej1v0ds00 13 m m m m pd 78 f 9136 a 5. memory space figure 5-1 shows the memory map of the m pd78f9136a. figure 5-1. memory map special function registers 256 8 bits internal high-speed ram 256 8 bits reserved program memory space data memory space program area program area callt table area vector table area flash memory 16384 8 bits ffffh ff00h feffh fe00h fdffh 3fffh 0080h 007fh 0040h 003fh 0016h 0015h 0000h 0000h 3fffh 4000h
data sheet u14690ej1v0ds00 14 m m m m pd 78 f 9136 a 6. flash memory programming the on-chip program memory in the m pd78f9136a is a flash memory. the flash memory can be written with the m pd78f9136a mounted on the target system (on-board). connect the dedicated flash programmer (flashpro iii (model number: fl-pr3, pg-fp3)) to the host machine and target system to write the flash memory. remark fl-pr3 is made by naito densei machida mfg. co., ltd.. 6.1 selecting communication mode the flash memory is written by using flashpro iii and by means of serial communication. select a communication mode from those listed in table 6-1. to select a communication mode, the format shown in figure 6-1 is used. each communication mode is selected by the number of v pp pulses shown in table 6-1. table 6-1. communication mode list communication mode pins used number of v pp pulses 3-wired serial i/o mode sck20/asck20/p20 so20/txd20/p21 si20/rxd20/p22 0 uart txd20/so20/p21 rxd/si20/p22 8 pseudo 3-wire mode note p00 (serial clock input) p01 (serial data output) p02 (serial data input) 12 note serial transfer is performed by controlling a port by software. caution be sure to select a communication mode depending on the v pp pulse number shown in table 6-1. figure 6-1. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n
data sheet u14690ej1v0ds00 15 m m m m pd 78 f 9136 a 6.2 function of flash memory programming by transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. table 6-2 shows the major functions of flash memory programming. table 6-2. functions of flash memory programming function description batch erase erases all contents of memory batch blank check checks erased state of entire memory data write write to flash memory based on write start address and number of data written (number of bytes) batch verify compares all contents of memory with input data 6.3 flashpro iii connection how the flashpro iii is connected to the m pd78f9136a differs depending on the communication mode (3-wired serial i/o or pseudo 3-wire mode). figures 6-2 to 6-4 show the connection in the respective mode. figure 6-2. flashpro iii connection in 3-wired serial i/o mode v pp n note v dd reset sck so si gnd v pp v dd , av dd reset clk p03 sck20 si20 so20 v ss , av ss flashpro iii pd78f9136a m note n = 1, 2
data sheet u14690ej1v0ds00 16 m m m m pd 78 f 9136 a figure 6-3. flashpro iii connection in uart mode v pp n note v dd reset so si gnd v pp v dd , av dd reset clk p03 rxd20 txd20 v ss , av ss flashpro iii pd78f9136a m note n= 1, 2 figure 6-4. flashpro iii connection in pseudo 3-wire mode (when port 0 is used) v pp n note v dd reset sck so si gnd v pp v dd , av dd reset clk p03 p00 (serial clock) p02 (serial input) p01 (serial output) v ss , av ss flashpro iii pd78f9136a m note n= 1, 2
data sheet u14690ej1v0ds00 17 m m m m pd 78 f 9136 a 6.4 example of settings for flashpro iii (pg-fp3) set as follows when writing to flash memory using the flashpro iii (pg-fp3). <1> download the parameter file. <2> select the serial mode and the serial clock using the type command. <3> the following is a setting example using the pg-fp3. table 6-3. example using pg-fp3 communication mode setting example using pg-fp3 number of v pp pulses note1 comm port sio ch-0 on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz 3-wired serial i/o mode sio clk 1.0 mhz 0 comm port uart-ch0 on target board cpu clk in flashpro on target board 4.1943 mhz uart uart bps 9600 bps note2 8 comm port port b on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1 khz in flashpro 4.0 mhz pseudo 3-wire mode sio clk 1 khz 12 notes 1. the number of v pp pulses supplied from the flashpro iii during serial communication initialization. the pins to be used in communication are determined by this number of pulses. 2. select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. remark comm port: selection of serial port sio clk : selection of serial clock frequency cpu clk : selection of cpu clock source to be input
data sheet u14690ej1v0ds00 18 m m m m pd 78 f 9136 a 7. instruction set overview the instruction set for the m pd78f9136a is listed later. 7.1 conventions 7.1.1 operand identifiers and description methods operands are described in the operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords and must be described as they are. each symbol has the following meaning. #: immediate data specification $: relative address specification !: absolute address specification [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #,!, $, or [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 7-1. operand identifiers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or label fe20h to ff1fh immediate data or label (even address only) addr16 addr5 0000h to ffffh immediate data or label (only even addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or label (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
data sheet u14690ej1v0ds00 19 m m m m pd78f9136a 7.1.2 descriptions of the operation field a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive or : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 7.1.3 description of the flag operation field (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
data sheet u14690ej1v0ds00 20 m m m m pd 78 f 9136 a 7.2 operations flag mnemonic operand byte clock operation zaccy r, #byte 3 6 r ? byte saddr , #byte 3 6 (addr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) mov [hl + byte], a 2 6 (hl + byte) ? a a, x 1 4 a ? x a, r note 2 26a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl + byte] 2 8 a ? (hl + byte) rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp movw rp, ax note 3 14rp ? ax xchw ax, rp note 3 1 8 ax ? rp notes 1. except r = a 2. except r = a or x 3. only when rp = bc, de, hl remark one instruction clock cycle is one cycle of the cpu clock (f cpu ), selected by the processor clock control register (pcc).
data sheet u14690ej1v0ds00 21 m m m m pd78f9136a flag mnemonic operand byte clock operation zaccy a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a ,cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) add a, [hl + byte] 2 6 a, cy ? a + (hl + byte) a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a + (saddr) + cy a, !addr16 3 8 a, cy ? a + (addr16) + cy a, [hl] 1 6 a, cy ? a + (hl) + cy addc a, [hl + byte] 2 6 a, cy ? a + (hl + byte) + cy a, #byte 2 4 a, cy ? a C byte saddr, #byte 3 6 (saddr), cy ? (saddr) C byte a, r 2 4 a, cy ? a C r a, saddr 2 4 a, cy ? a C (saddr) a, !addr16 3 8 a, cy ? a C (addr16) a, [hl] 1 6 a, cy ? a C (hl) sub a, [hl + byte] 2 6 a, cy ? a C (hl + byte) a, #byte 2 4 a, cy ? a C byte C cy saddr, #byte 3 6 (saddr), cy ? (saddr) C byte C cy a, r 2 4 a, cy ? a C r C cy a, saddr 2 4 a, cy ? a C (saddr) C cy a, !addr16 3 8 a, cy ? a C (addr16) C cy a, [hl] 1 6 a, cy ? a C (hl) C cy subc a, [hl + byte] 2 6 a, cy ? a C (hl + byte) C cy a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) and a, [hl + byte] 2 6 a ? a (hl + byte) remark one instruction clock cycle is one cycle of the cpu clock (f cpu ), selected by the processor clock control register (pcc).
data sheet u14690ej1v0ds00 22 m m m m pd 78 f 9136 a flag mnemonic operand byte clock operation zaccy a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) or a, [hl + byte] 2 6 a ? a (hl + byte) a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) xor a, [hl + byte] 2 6 a ? a (hl + byte) a, #byte 2 4 a C byte saddr, #byte 3 6 (saddr) C byte a, r 2 4 a C r a, saddr 2 4 a C (saddr) a, !addr16 3 8 a C (addr16) a, [hl] 1 6 a C (hl) cmp a, [hl + byte] 2 6 a C (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax C word cmpw ax, #word 3 6 ax C word r24r ? r + 1 inc saddr 2 4 (saddr) ? (saddr) + 1 r24r ? r C 1 dec saddr 2 4 (saddr) ? (saddr) C 1 incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp C 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m C 1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m + 1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m C 1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m + 1 ? a m ) 1 remark one instruction clock cycle is one cycle of the cpu clock (f cpu ), selected by the processor clock control register (pcc).
data sheet u14690ej1v0ds00 23 m m m m pd78f9136a flag mnemonic operand byte clock operation zaccy saddr. bit 3 6 (saddr. bit) ? 1 sfr. bit 3 6 sfr. bit ? 1 a. bit 2 4 a. bit ? 1 psw. bit 3 6 psw. bit ? 1 set1 [hl]. bit 2 10 (hl) . bit ? 1 saddr. bit 3 6 (saddr. bit) ? 0 sfr. bit 3 6 sfr. bit ? 0 a. bit 2 4 a. bit ? 0 psw. bit 3 6 psw. bit ? 0 clr1 [hl]. bit 2 10 (hl) . bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (sp C 1) ? (pc + 3) h ,(sp C 2) ? (pc + 3) l , pc ? addr16, sp ? sp C 2 callt [addr5] 1 8 (sp C 1) ? (pc + 1) h ,(sp C 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp C 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr psw 1 2 (sp C 1) ? psw, sp ? sp C 1 push rp 1 4 (sp C 1) ? rp h , (sp C 2) ? rp l , sp ? sp C 2 psw 1 4 psw ? (sp), sp ? sp + 1 r r r pop rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 sp, ax 2 8 sp ? ax movw ax, sp 2 6 ax ? sp !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 br ax 1 6 pc h ? a, pc l ? x remark one instruction clock cycle is one cycle of the cpu clock (f cpu ), selected by the processor clock control register (pcc).
data sheet u14690ej1v0ds00 24 m m m m pd 78 f 9136 a flag mnemonic operand byte clock operation zaccy bc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 1 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 1 a. bit , $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 1 bt psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 1 saddr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 0 sfr. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 0 a. bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 0 bf psw. bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 0 b, $addr16 2 6 b ? b C 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c C 1, then pc ? pc + 2 + jdisp8 if c 1 0 dbnz saddr, $addr16 3 8 (saddr) ? (saddr) C 1, then pc ? pc + 3 + jdisp8 if(saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1(enable interrupt) di 3 6 ie ? 0(disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cycle of the cpu clock (f cpu ), selected by the processor clock control register (pcc).
data sheet u14690ej1v0ds00 25 m m m m pd 78 f 9136 a 8. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd , av dd v dd = av dd C0.3 to +6.5 v supply voltage v pp C0.3 to +10.5 v v i1 pins other than p50 to p53 C0.3 to v dd + 0.3 v input voltage v i2 p50 to p53 with n-ch open drain C0.3 to +13 v output voltage v o C0.3 to v dd + 0.3 v per pin C10 ma output current, high i oh total for all pins C30 ma per pin 30 ma output current, low i ol total for all pins 160 ma in normal operation mode C40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg C40 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u14690ej1v0ds00 26 m m m m pd 78 f 9136 a system clock oscillator characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit rc resonator cl2 cl1 oscillation frequency (f cc ) note 1 v dd = oscillation voltage range 2.0 4.0 mhz cl1 input frequency (f cc ) note 1 1.0 5.0 mhz cl1 cl2 cl1 input high-/low-level width (t xh , t xl ) 85 500 ns cl1 input frequency (f cc ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock cl1 cl2 open cl1 input high-/low-level width (t xh , t xl ) 85 500 ns note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. rc oscillator frequency characteristics (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit f cc1 v dd = 2.7 to 5.5 v 1.5 2.0 2.5 mhz f cc2 v dd = 1.8 to 3.6 v 0.5 2.0 2.5 mhz f cc3 r = 11.0 k w , c = 22 pf target : 2 mhz v dd = 1.8 to 5.5 v 0.5 2.0 2.5 mhz f cc4 v dd = 2.7 to 5.5 v 2.5 3.0 3.5 mhz f cc5 v dd = 1.8 to 3.6 v 0.75 3.0 3.5 mhz f cc6 r = 6.8 k w , c = 22 pf target : 3 mhz v dd = 1.8 to 5.5 v 0.75 3.0 3.5 mhz f cc7 v dd = 2.7 to 5.5 v 3.5 4.0 4.7 mhz f cc8 v dd = 1.8 to 3.6 v 1.0 4.0 4.7 mhz oscillator frequency f cc9 r = 4.7 k w , c = 22 pf target : 4 mhz v dd = 1.8 to 5.5 v 1.0 4.0 4.7 mhz remark so that the typ. spec is satisfied between 2.0 to 4.0 mhz, set one of the above nine patterns for r and c.
data sheet u14690ej1v0ds00 27 m m m m pd 78 f 9136 a dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin C1 ma output current, high i oh total for all pins C15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v dd = 2.7 to 5.5 v 0.7 v dd v dd v v ih1 pins other than described below 0.9 v dd v dd v v dd = 2.7 to 5.5 v 0.7 v dd 12 v v ih2 p50 to p53 n-ch open drain v dd = 1.8 to 5.5 v t a = 25 to 85 c 0.9 v dd 12 v v dd = 2.7 to 5.5 v 0.8 v dd v dd v v ih3 reset, p20 to p25 0.9 v dd v dd v v dd = 4.5 to 5.5 v v dd C0.5 v dd v input voltage, high v ih4 cl1, cl2 v dd C0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3 v dd v v il1 pins other than described below 0 0.1 v dd v v il2 p50 to p53 v dd = 2.7 to 5.5 v 0 0.3 v dd v v dd = 2.7 to 5.5 v 0 0.2 v dd v v il3 reset, p20 to p25 0 0.1 v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 cl1, cl2 00.1v v oh1 v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C1.0 v output voltage, high v oh2 v dd = 1.8 to 5.5 v, i oh = C100 m av dd C0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 m a0.5v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u14690ej1v0ds00 28 m m m m pd 78 f 9136 a dc characteristics (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 pins other than cl1, cl2, or p50 to p53 3 m a i lih2 cl1, cl2 v in = v dd 20 m a input leakage current, high i lih3 p50 to p53 (n-ch open drain) v in = 12 v 20 m a i lil1 pins other than cl1, cl2, or p50 to p53 C3 m a i lil2 cl1, cl2 C20 m a input leakage current, low i lil3 p50 to p53 (n-ch open drain) v in = 0 v C3 note 1 m a output leakage current, high i loh v out = v dd 3 m a output leakage current, low i lol v out = 0 v C3 m a software pull-up resistor r 1 v in = 0 v, for pins other than p50 to p53 50 100 200 k w v dd = 5.0 v 10% note 4 5.0 15.0 ma v dd = 3.0 v 10% note 5 1.9 4.9 ma i dd1 note 2 4.0-mhz rc oscillation operating mode (r = 4.7 k w , c = 22pf) v dd = 2.0 v 10% note 5 1.5 3.0 ma v dd = 5.0 v 10% note 4 2.5 5.0 ma v dd = 3.0 v 10% note 5 1.0 2.0 ma i dd2 note 2 4.0-mhz rc oscillation halt mode (r = 4.7 k w , c = 22pf) v dd = 2.0 v 10% note 5 0.75 1.5 ma v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a i dd3 note 2 stop mode v dd = 2.0 v 10% 0.05 10 m a v dd = 5.0 v 10% note 4 6.2 17.3 ma v dd = 3.0 v 10% note 5 3.1 7.2 ma power supply current i dd4 note 3 4.0-mhz rc oscillation a/d operating mode (r = 4.7 k w , c = 22pf) v dd = 2.0 v 10% note 5 2.5 5.0 ma notes 1. when port 5 is in input mode, a low-level input leakage current of C60 m a (max.) flows only for 1 cycle time after a read instruction has been executed to port 5. 2. the current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and av dd current are not included. 3. the current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not included. 4. high-speed mode operation (when processor clock control register (pcc) is set to 00h.) 5. low-speed mode operation (when pcc is set to 02h). remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u14690ej1v0ds00 29 m m m m pd 78 f 9136 a flash memory write/delete characteristics (t a = 10 c to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (in 5.0-mhz operation mode) 18 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 22.5 ma delete current (v dd pin) note i dde when v pp supply voltage = v pp1 (in 5.0-mhz operation mode) 18 ma delete current (v pp pin) note i ppe when v pp supply voltage = v pp1 115 ma unit delete time t er 0.511s total delete time t era 20 s write count delete/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and av dd current are not included.
data sheet u14690ej1v0ds00 30 m m m m pd 78 f 9136 a ac characteristics (1) basic operation (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 m s cycle time (minimum instruction execution time) t cy 1.6 8 m s v dd = 2.7 to 5.5 v 0.1 m s ti80 input high-/low- level width t tih , t til 1.8 m s v dd = 2.7 to 5.5 v 0 4 mhz ti80 input frequency f ti 0 275 khz interrupt input high- /low-level width t inth , t intl intp0 to intp2 10 m s reset low-level width t rsl 10 m s cpt20 input high- /low-level width t cph , t cpl 10 m s t cy vs v dd supply voltage v dd [v] 123456 0.1 0.4 0.5 1.0 2.0 10 60 cycle time t cy [ s] guaranteed operation range m
data sheet u14690ej1v0ds00 31 m m m m pd 78 f 9136 a (2) serial interface (t a = ?40 to +85 c, v dd = 1.8 to 5.5 v) (i) 3-wire serial i/o mode (sck20...internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 C 50 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 C 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 - ) t sik1 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 - ) t ksi1 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k w , c = 100 pf note 0 1000 ns note r and c are the load resistance and load capacitance of the so output line. (ii) 3-wire serial i/o mode (sck20...external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy2 3200 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 - ) t sik2 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 - ) t ksi2 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k w , c = 100 pf note 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (for ss20 when ss20 is used) t kas2 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (for ss20 - when ss20 is used) t kds2 800 ns note r and c are the load resistance and load capacitance of the so output line. (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate 19531 bps
data sheet u14690ej1v0ds00 32 m m m m pd 78 f 9136 a (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns asck20 cycle time t kcy3 3200 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate 9766 bps asck20 rise/fall time t r , t f 1 m s
data sheet u14690ej1v0ds00 33 m m m m pd 78 f 9136 a ac timing test points (excluding cl1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points clock timing 1/f cc t xl t xh cl1 input v ih4 (min.) v il4 (max.) ti timing ti80 t til t tih 1/f ti interrupt input timing intp0 to intp2 t intl t inth reset input timing reset t rsl
data sheet u14690ej1v0ds00 34 m m m m pd 78 f 9136 a serial transfer timing 3-wire serial i/o mode: sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 m = 1, 2 3-wire serial i/o mode (when ss20 is used): t kas2 so20 ss20 output data t kds2 uart mode (external clock input): asck20 t r t f t kl3 t kcy3 t kh3
data sheet u14690ej1v0ds00 35 m m m m pd 78 f 9136 a 10-bit a/d converter characteristics (t a = - - - - 40 to +85c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.5 v v dd 5.5 v 0.2 0.4 %fsr 2.7 v v dd < 4.5 v 0.4 0.6 %fsr overall error note1,2 1.8 v v dd < 2.7 v 0.8 1.2 %fsr 2.7 v v dd 5.5 v 14 100 m s conversion time t conv 1.8 v v dd < 2.7 v 28 100 m s 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr zero-scale error note1,2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 0.4 %fsr 2.7 v v dd < 4.5 v 0.6 %fsr full-scale error note1,2 1.8 v v dd < 2.7 v 1.2 %fsr 4.5 v v dd 5.5 v 2.5 lsb 2.7 v v dd < 4.5 v 4.5 lsb integral linearity error note1 ile 1.8 v v dd < 2.7 v 8.5 lsb 4.5 v v dd 5.5 v 1.5 lsb 2.7 v v dd < 4.5 v 2.0 lsb differential linearity error note1 dle 1.8 v v dd < 2.7 v 3.5 lsb analog input voltage v ian 0av dd v notes 1. excludes quantization error ( 0.05%fsr). 2. it is indicated as a ratio to the full-scale value (%fsr).
data sheet u14690ej1v0ds00 36 m m m m pd 78 f 9136 a data memory stop mode low supply voltage data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 m s release by reset 2 7 /f cc ms oscillation stabilization wait time note t wait release by interrupt request 2 7 /f cc ms note the oscillation stabilization wait time is the period during which the cpu operation is stopped to avoid unstable operation at the beginning of oscillation. remark f cc : system clock oscillation frequency data retention timing (stop mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
data sheet u14690ej1v0ds00 37 m m m m pd 78 f 9136 a 9. example of rc oscillator frequency characteristics (reference values) f cc vs v dd (rc oscillation, r = 11 k w w w w , c = 22 pf) 23 456 supply voltage v dd [v] 1.4 1.6 1.8 2.0 2.2 2.4 2.6 system clock frequency f cc [mhz] (t a =?0 c) sample a sample b sample c cl2 cl1 11 k w 22 pf 1.4 1.6 1.8 2.0 2.2 2.4 2.6 23 456 supply voltage v dd [v] system clock frequency f cc [mhz] (t a =25 c) cl2 cl1 11 k w 22 pf sample a sample b sample c 1.4 1.6 1.8 2.0 2.2 2.4 2.6 system clock frequency f cc [mhz] 23 456 supply voltage v dd [v] (t a =85 c) sample a sample b sample c cl2 cl1 11 k w 22 pf
data sheet u14690ej1v0ds00 38 m m m m pd 78 f 9136 a f cc vs v dd (rc oscillation, r = 4.7 k w w w w , c = 22 pf) (t a =C40 c) 23 456 supply voltage v dd [v] 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] sample a sample b sample c cl2 cl1 4.7 k w 22 pf (t a =25 c) 23 456 supply voltage v dd [v] 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] sample a sample b sample c cl2 cl1 4.7 k w 22 pf 3.4 3.6 3.8 4.0 4.2 4.4 4.6 system clock frequency f cc [mhz] 23 456 supply voltage v dd [v] (t a =85 c) sample a sample b sample c cl2 cl1 4.7 k w 22 pf
data sheet u14690ej1v0ds00 39 m m m m pd 78 f 9136 a 10. package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 - 0.07 1.0 0.2 3 + 5 - 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2
data sheet u14690ej1v0ds00 40 m m m m pd 78 f 9136 a 11. recommended soldering conditions the m pd78f9136a should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 10-1. surface mounting type soldering conditions m pd78f9136amc-5a4: 30-pin plastic ssop (7.62 mm (300)) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, reflow time: 30 seconds or below (at 210c or higher), number of reflow processes : 3 max., exposure limit : 7days note (after that, prebaking is necessary at 125 c for 10 hours) ir35-107-3 vps package peak temperature: 215c, reflow time: 40 seconds or below (at 200c or higher), number of reflow processes : 3 max., exposure limit : 7days note (after that, prebaking is necessary at 125 c for 10 hours) vp15-107-3 wave soldering solder bath temperature: 260c or below, flow time: 10 seconds or below, number of flow processes: 1 preheating temperature: 120c or below (package surface temperature), exposure limit : 7days note (after that, prebaking is necessary at 125 c for 10 hours) ws60-107-1 partial heating pin temperature: 300c max., time: 3 sec. max. (per pin row) C note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
data sheet u14690ej1v0ds00 41 m m m m pd 78 f 9136 a appendix a development tools the following development tools are available for system development using the m pd78f9116a. language processing software ra78k0s notes 1, 2, 3 assembler package common to 78k/0s series cc78k0s notes 1, 2, 3 c compiler package common to 78k/0s series df789136 notes 1, 2, 3 device file for m pd78f9136a flash memory writing tools flashpro lil (model number: fl-pr3 note 4 , pg-fp3) dedicated flash programmer for on-chip flash memory fa-30mc note 4 flash memory writing adapter debugging tools (1/2) ie-78k0s-ns in-circuit emulator in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0s series product. it supports the id78k0s-ns integrated debugger. used in combination with an ac adapter, emulation probe, and interface adapter connecting to the host machine. ie-70000-mc-ps-b ac adapter adapter used to supply power from a power outlet of 100 v ac to 240 v ac. ie-70000-98-if-c interface adapter adapter when pc-9800 series pc (except notebook type) is used as the ie-78k0s-ns host machine (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable when notebook pc is used as the ie-78k0s-ns host machine (pcmcia socket supported). ie-70000-pc-if-c interface adapter adapter when using an ibm pc/at? or compatible as the ie-78k0s-ns host machine. ie-70000-pci-if interface adapter adapter when using pc that includes a pci bus as the ie-78k0s-ns host machine. ie-789136-ns-em1 emulation board board for emulation of the peripheral hardware peculiar to a device. used in combination with an in-circuit emulator. np-36gs note 4 board used to connect the in-circuit emulator to the target system. for a 30-pin plastic ssop (mc-5a4 type), used in combination with ngs-30. ngs-30 note 4 conversion socket conversion socket used to connect the np-36gs to the target system board designed to mount a 30-pin plastic ssop (mc-5a4 type). notes 1. pc-9800 series (japanese windows?) based 2. ibm pc/at or compatibles (japanese/english windows) based 3. hp9000 series 700? (hp-ux?), sparcstation? (sunos?, solaris?), or news? (news-os?) based. 4. products made by naito densei machida mfg. co., ltd. (phone: +81-44-822-3813). remark ra78k0s, cc78k0s, and sm78k0s are used in combination with the df789136.
data sheet u14690ej1v0ds00 42 m m m m pd 78 f 9136 a debugging tools (2/2) sm78k0s notes 1, 2 system simulator common to 78k/0s series id78k0s-ns notes 1, 2 integrated debugger common to 78k/0s series df789136 notes 1, 2 device file for m pd78f9136a real-time os mx78k0s notes 1, 2 os for 78k/0s series notes 1. pc-9800 series (japanese windows) based. 2. ibm pc/at or compatibles (japanese/english windows) based.
data sheet u14690ej1v0ds00 43 m m m m pd 78 f 9136 a appendix b related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document no. document name japanese english m pd789121a, 122a, 124a, 131a, 132a, 134a, 121a(a), 122a(a), 124a(a), 131a(a), 132a(a), 134a(a) data sheet u14678j u14678e m pd78f9136a data sheet u14690j this manual m pd789104a, 789114a, 789124a, 789134a subseries users manual u14643j to be prepared 78k/0s series users manual instruction u11047j u11047e 78k/0, 78k/0s series application note flash memory write u14458j u14458e documents related to development tools (users manuals) document no. document name japanese english operation u11622j u11622e assembly language u11599j u11599e ra78k0s assembler package structured assembly language u11623j u11623e operation u11816j u11816e cc78k0s c compiler language u11817j u11817e sm78k0s system simulator windows based reference u11489j u11489e sm78k series system simulator external parts user open interface specifications u10092j u10092e id78k0s-ns integrated debugger windows based reference u12901j u12901e ie-78k0s-ns in-circuit emulator u13549j u13549e ie-789136-ns-em1 emulation board u14363j u14363e documents related to embedded software (users manuals) document no. document name japanese english 78k/0s series os mx78k0s fundamental u12938j u12938e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u14690ej1v0ds00 44 m m m m pd 78 f 9136 a other related documents document no. document name japanese english semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to microcomputer-related products by third party u11416j - caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u14690ej1v0ds00 45 m m m m pd 78 f 9136 a [ memo ]
data sheet u14690ej1v0ds00 46 m m m m pd 78 f 9136 a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. eeprom is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
data sheet u14690ej1v0ds00 47 m m m m pd 78 f 9136 a regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m m m m pd78f9136a the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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