View UT54ACS164245SUCC_2991534.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ut54acs164245s radhard schmitt cmos 16-bit bidirectional multipurpose transceiver datasheet january 17 , 2001 features voltage translation - 5v bus to 3.3v bus - 3.3v bus to 5v bus cold sparing - 1m w minimum input impedance power-off 0.6m m commercial radhard tm cmos - total dose: 100k rad ( si) - single event latchup immune high speed, low power consumption schmitt trigger inputs to filter noisy signals available qml q or v processes standard microcircuit drawing 5962-98580 package: - 48-lead flatpack, 25 mil pitch (.390 x .640) description the 16-bit wide ut54acs164245s multipurpose transceiver is built using utmc?s commercial radhard tm epitaxial cmos technology and is ideal for space applications. this high speed, low power ut54acs164245s transceiver is designed to perform multiple functions including: asynchronous two-way communication, signal buffering, voltage translation, and cold sparing. with v dd equal to zero volts, the ut54acs164245s outputs and inputs present a minimum impedance of 1m w mak- ing it ideal for "cold spare" applications. balanced outputs and low "on" output impedance make the ut54acs164245s well suited for driving high capacitance loads and low impedance backplanes. the ut54acs164245s enables system designers to interface 3.3 volt cmos compatible components with 5 volt cmos components. for voltage translation, the a port inter- faces with the 3.3 volt bus; the b port interfaces with the 5 volt bus. the direction control (dirx) controls the direction of data flow. the output enable ( oe x) overrides the direction control and disables both ports. these signals can be driven from either port a or b. the direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. logic symbol pin description function table pin names description oe x output enable input (active low) dirx direction control inputs xax side a inputs or 3-state outputs (3.3v port) xbx side b inputs or 3-state outputs (5v port) enable oe x direction dirx operation l l b data to a bus l h a data to b bus h x isolation (48) oe 1 g2 (47) 1a1 (46) 1a2 (44) (2) 1b1 (5) (3) 1b2 1a3 (43) 1a4 (41) 1a5 (40) 1a6 1b3 (9) 1b6 (8) 1b5 (6) 1b4 (38) 1a7 (37) 1a8 (12) 1b8 (11) 1b7 (1) dir1 1en1 (ba) 1en2 (ab) 11 12 (25) oe 2 g1 (24) dir2 21 22 (36) 2a1 2b1 (13) (35) 2a2 (33) 2a3 (32) 2a4 (30) 2a5 (29) 2a6 (27) 2a7 (26) 2a8 (16) 2b2 2b3 (20) 2b6 (19) 2b5 (17) 2b4 (23) 2b8 (22) 2b7 (14) 2en1 (ba) 2en2 (ab)
2 pinouts power table 1 note: 1. v dd2 cannot be tied to v ss while power is applied to v dd1 . control signals dirx and oex are 5 volt tolerant inputs. when v dd2 is at 3.3 volts, either 3.3 or 5 volt cmos logic levels can be applied to all control inputs. for proper operation connect power to all v dd and ground all v ss pins (i.e., no floating v dd or v ss input pins). if v dd1 and v dd2 are not powered up to- gether, then v dd2 should be powered up first for proper con- trol of oe and dir. until v dd2 reaches 2.75v + 5%, control of the outputs by oe and dir cannot be guaranteed. tie unused inputs to v ss . always insure v dd1 > v dd2 during operation of the part. 1 2 3 4 5 7 6 48 47 46 45 44 42 43 dir1 1b1 1b2 v ss 1b3 1b4 vdd1 oe 1 1a1 1a2 v ss 1a3 vdd2 8 41 1b5 1a5 1a4 9 40 1b6 1a6 10 39 v ss v ss 48-lead flatpack top view 1b7 1b8 2b1 2b2 v ss 2b3 2b4 vdd1 2b5 2b6 11 12 13 14 15 17 16 18 19 20 v ss 2b7 2b8 dir2 21 22 23 24 38 37 36 35 34 32 33 1a7 1a8 2a1 2a2 v ss 2a4 31 vdd2 2a3 30 2a5 29 2a6 28 v ss 27 2a7 26 2a8 25 oe 2 port b port a operation 5 volts 3.3 volts voltage translator 5 volts 5 volts non translating 3.3 volts 3.3 volts non translating v ss v ss cold spare v ss 3.3v or 5v port b cold spare
3 logic diagram 1a1 1a2 1a3 1a4 1a5 1a6 1a7 1a8 dir1 (1) (47) (48) (2) (46) (3) (44) (5) (43) (6) (41) (8) (40) (9) (38) (11) (37) (12) 1b1 1b2 1b3 1b6 1b5 1b4 1b8 1b7 oe 1 2a1 2a2 2a3 2a4 2a5 2a6 2a7 2a8 dir2 (24) (36) (25) (13) (35) (14) (33) (16) (32) (17) (30) (19) (29) (20) (27) (22) (26) (23) 2b1 2b2 2b3 2b6 2b5 2b4 2b8 2b7 oe 2 3 . 3 v p o r t 5 v p o r t 3 . 3 v p o r t 5 v p o r t
4 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. not tested, inherent of cmos technology. absolute maximum ratings 1 note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability and performance . dual supply operating conditions parameter limit units total dose 1.0e5 rad ( si) sel latchup >120 mev-cm 2 /mg neutron fluence 2 1.0e14 n/cm 2 symbol parameter limit (mil only) units v i/o voltage any pin -.3 to v dd1 +.3 v v dd1 supply voltage -0.3 to 6.0 v v dd2 supply voltage -0.3 to 6.0 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c q jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd1 supply voltage 3.0 to 3.6 or 4.5 to 5.5 v v dd2 supply voltage 3. 0 t o 3.6 or 4.5 to 5.5 v v in input voltage any pin 0 to v dd1 v t c temperature range -55 to + 125 c
5 dc electrical characteristics 1 ( -55 c < t c < +125 c) symbol parameter condition min max unit v t + schmitt trigger, positive going threshold 2 v dd from 3. 00 t o 5.5 .7v dd v v t - schmitt trigger, negative going threshold 2 v dd from 3. 00 t o 5.5 .3v dd v v h1 schmitt trigger range of hysteresis 10 v dd from 4.5 to 5.5 0.6 v v h2 schmitt trigger range of hysteresis 10 v dd from 3. 00 t o 3.6 0.4 v i i n input l eakage current 10 v dd from 3. 6 t o 5.5 v in = v dd or v ss - 1 3 m a i oz three-state o utput leakage current 10 v dd from 3.6 t o 5.5 v in = v dd or v ss - 1 3 m a i cs cold sparing l eakage current 3 v in = 5 .5 v dd = v ss - 1 5 m a i os1 short-circuit output current 6, 11 v o = v dd or v ss v dd from 4.5 to 5.5 -200 200 ma i os2 short-circuit output current 6, 11 v o = v dd or v ss v dd from 3. 00 t o 3.6 -100 100 ma v ol1 low-level output voltage 4, 10 i ol = 8ma i ol = 100 m a v dd = 4 .5 0.4 0.2 v v ol2 low-level output voltage 4, 10 i ol = 8ma i ol = 100 m a v dd = 3 . 00 0.5 0.2 v v oh1 high-level output voltage 4, 10 i oh = -8ma i oh = -100 m a v dd = 4 .5 v dd - 0.7 v dd - 0.2 v v oh2 high-level output voltage 4, 10 i oh = -8ma i oh = -100 m a v dd = 3 . 00 v dd - 0.9 v dd - 0.2 v
6 notes: 1. all specifications valid for radiation dose 1e5 rad ( si) per mil-std-883, method 1019. 2. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within th e above specified range, but are guaranteed to v ih (min) and v il (max). 3. all combinations of oe x and dirx 4. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pf-mhz. 5. guaranteed by characterization. 6. not more than one output may be shorted at a time for maximum duration of one second. 7. power does not include power contribution of any cmos output sink current. 8. power dissipation specified per switching output. 9. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 1 0. guaranteed; tested on a sample of pins per device. 11. supplied as a design limit, but not guaranteed or tested. . p total1 power dissipation 5,7, 8 c l = 50pf v dd from 4.5 t o 5.5 2.0 mw/ mhz p total2 power dissipation 5, 7, 8 c l = 50pf v dd from 3. 00 t o 3.6 1.5 mw/ mhz i dd standby supply current v d d1 o r v dd2 pre-rad 25 o c pre-rad -55 o c to +125 o c p ost-rad 25 o c v in = v dd or v ss v dd = 5 .5 oe =v dd oe =v d d o e =v dd 10 100 5 00 m a m a m a c in input capacitance 9 | = 1mhz @ 0v v dd from 3. 00 t o 5.5 15 pf c out output capacitance 9 | = 1mhz @ 0v v dd from 3. 00 t o 5.5 15 pf
7 ac electrical characteristics 1 (port b = 5 volt, port a = 3.3 volt) (v dd1 = 5v 10%; v dd2 = 3. 00v to 3.6v, -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose 1e5 rad ( si) per mil-std-883, method 1019. 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested. symbol parameter minimum maximum unit t plh propagation delay data to bus 1 20 ns t phl propagation delay data to bus 1 20 ns t pzl output enable time oe x to bus 1 18 ns t pzh output enable time oe x to bus 1 18 ns t plz output disable time oe x to bus high impedance 1 20 ns t phz output disable time oe x to bus high impedance 1 20 ns t pzl 2 output enable time dirx to bus 1 18 ns t pzh 2 output enable time dirx to bus 1 18 ns t plz 2 output disable time dirx to bus high impedance 1 20 ns t phz 2 output disable time dirx to bus high impedance 1 20 ns t plz t pzh t pzl t phl t phz propagation delay i nput output v dd v dd /2 0v t plh v oh v ol v dd /2 control input 5v o utput normally low enable disable times 5v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8 v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .8 v dd - .2v t plz t pzh t pzl t phz 3.3v o utput normally low 3.3v output normally high v dd /2 v dd /2 .7 v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .7 v dd - .2v
8 ac electrical characteristics 1 (port a = port b, 5 volt operation) (v dd1 = 5v 10%; v dd2 = 5.0v + 10%, -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose 1e5 rad ( si) per mil-std-883, method 1019. 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested symbol parameter minimum maximum unit t plh propagation delay data to bus 1 15 ns t phl propagation delay data to bus 1 15 ns t pzl output enable time oe x to bus 1 12 ns t pzh output enable time oe x to bus 1 12 ns t plz output disable time oe x to bus high impedance 1 15 ns t phz output disable time oe x to bus high impedance 1 15 ns t pzl 2 output enable time dirx to bus 1 12 ns t pzh 2 output enable time dirx to bus 1 12 ns t plz 2 output disable time dirx to bus high impedance 1 15 ns t phz 2 output disable time dirx to bus high impedance 1 15 ns t plz t pzh t pzl t phz control input 5v o utput normally low enable disable times 5v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8 v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .8 v dd - .2v t phl propagation delay i nput output v dd v dd /2 0v t plh v oh v ol v dd /2
9 ac electrical characteristics 1 (port a = port b, 3.3 volt operation) (v dd1 = 3. 00v to 3.6v; v dd2 = 3. 00v to 3.6v, -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose 1e5 rad ( si) per mil-std-883, method 1019 . 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested. symbol parameter minimum maximum unit t plh propagation delay data to bus 1 20 ns t phl propagation delay data to bus 1 20 ns t pzl output enable time oe x to bus 1 18 ns t pzh output enable time oe x to bus 1 18 ns t plz output disable time oe x to bus high impedance 1 20 ns t phz output disable time oe x to bus high impedance 1 20 ns t pzl 2 output enable time dirx to bus 1 18 ns t pzh 2 output enable time dirx to bus 1 18 ns t plz 2 output disable time dirx to bus high impedance 1 20 ns t phz 2 output disable time dirx to bus high impedance 1 20 ns t plz t pzh t pzl t phl t phz propagation delay i nput output v dd v dd /2 0v t plh v oh v ol v dd /2 control input 3.3v o utput normally low enable disable times 3.3v output normally high v dd v dd /2 0v v dd /2 v dd /2 .7v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .7v dd - .2v
10 package figure 1. 48-lead flatpack 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance with mil-prf-38535. 4. lead position and colanarity are not measured. 5. id mark symbol is vendor option. 6. with solder, increase maximum by 0.003. 6 4 5 6
11 ordering information ut54acs164245s: smd lead finish: (c) = gold case outline: (x) = 48 lead bb fp (gold only) class designator: (q) = class q (v) = class v device type (01) = 16-bit multipurpose transceiver (3.13v - 5.5v) (02) = 16-bit multipurpose transceiver (3.0v - 5.5v) d rawing number: 98580 total dose: (r) = 1e5 rad ( si) federal stock class designator: no options 5962 r 98580 ** * * * notes: 1. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
12 ut54acs164245s ut54 *** ****** * * * lead finish: (c) = gold screening: (c) = mil temp (p) = prototype package type: (u) = 48-lead bb fp (gold only) part number: (164245s) = 16-bit multipurpose transceiver i/o type: (acs) = cmos compatible i/o level utmc core part number notes: 1. military temperature range flow per utmc manufacturing flows document. devices are tested -55c, room temp, and 125c. radiation n either tested nor guaranteed. 2. prototype flow per utmc manufacturing flows document tested at 25c only. lead finish is gold only.

▲Up To Search▲

Price & Availability of UT54ACS164245SUCC

	To Download UT54ACS164245SUCC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .