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| 1 features ? avr ? microcontroller clock generator provides cpu rates up to 24 mhz programmable uart with 16-byte fifos at the receiver side (1), with a maximum rate of 921k baud programmable spi interface full-speed usb function controller 2k bytes of sram for data, stack and program variables 2k bytes of dual-port ram, shared among the usb, uart and avr 8k x 16-bit sram for program execution internal rom for the bootstrap loader one usb control endpoint six usb programmable endpoints (up to 64 bytes) with double-buffered fifos for back-to-back transfers one 8-bit timer/counter one 16-bit timer/counter external and internal interrupt sources programmable watchdog timer independent uart brg oscillator 64-lead tqfp package and bga package 3.3v operation pin configuration (tqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rst pb0_t0 pb1_t1 pb2_icp pb3 pb4_ss pb5_mosi pb6_miso pb7_sck vcc lft gnd xtal1 xtal2 test1 psdin p_rx p_tx gnd vcc pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 vcc gnd test2 eck 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 tck tp lc vcc gnd dp dm susp gnd vcc pm0 pm1 pc0 pc1 pc2 pc3 nc vcc gnd pd7_int1 pd6_int0 pd5 pd4 pd3 pd2 pd1_sout pd0_sin uxtal0 uxtal1 gnd lftu vcc avr ? -based bridge between full-speed usb and fast serial asynchronous interfaces at76c711 rev. 1643c?usb?10/02
2 at76c711 1643c?usb?10/02 description the atmel at76c711 is a compound usb device designed to provide a high-speed usb interface to devices that need to communicate with a host through fast serial links, like uarts and irda interfaces. it is based on the avr-enhanced risc architecture and consists of a usb function interface with a devoted dma controller for fast data transfers between the buffers of the usb endpoints and a shared dpram of 2k bytes, 2k bytes sram for data, stack and program variables, a synchronous peripheral inter- face (spi), a uart supporting a maximum rate of 921k baud with dma channels for data transfers to/from the dpram and an 8k x 16-bit sram for microcode execution. an irda controller is also provided, attached to a second uart module, and is able to communicate with an irda transceiver with a maximum rate of 1.2 mbps. an internal rom contains the bootstrap loader which reads the instructions from an external serial dataflash ? of atmel at45 series and stores them into the on-chip program sram. alternatively, microcode can be stored in the program sram using the slave program mode while the chip is in the reset state. the usb hardware block consists of a usb transceiver, the sie, endpoint controllers and an interface to the microcontroller. the usb hardware interfaces to the usb host at the packet level. the microcontroller firmware handles the higher-level usb protocol layers that are not processed by the usb hardware and in addition, it performs the peripheral control functions. the device is suitable for applications where minimization of power dissipation is required, since there are no power-consumable transactions with external parallel devices. block diagram usb dpram dma controller uart0 spi sram osc timers wd program memory controller address decoder clock generator avr core uart 1 irda 1.0 encdec general-purpose i/o 3 at76c711 1643c?usb?10/02 applications the at76c711 can be used in applications where peripherals supporting fast serial asynchronous or synchronous transfer of data have to communicate with a host or other peripherals through a high-speed serial link, like usb. a typical application of at76c711 and its functional diagram are shown in figures 1 and 2. typical areas of at76c711 usage are: connection of network interface cards (nics) to a host system wireless communications bridging of microcontrollers with different types of serial interfaces usb to uart bridge usbtoirdabridge irda to uart bridge packet adaptation of network protocol packets to usb requirements figure 1. typical at76c711 application figure 2. functional diagram desktop system usb at76c 711 network adaptor uart rf tr s c printer rf tr s c network adaptor lft xtal2 xtal1 uxtalo pb0/t0 pb1/t1 pb2/int0 pb3/int1 pb4/ss pb5/mosi pb6/miso pb7/sck pd0/sin0 pd1/sout0 pd2/rts0 pd3/cts0 pd4/dsr0 pd5/dtr0 pd6 pd7 pc0-3 uxtali usb dpram 2k x 8-bit dma controller usart 0 spi sram data port registers - port direction registers - drivers/buffers uart osc clock osc dp susp rst timers wd dm program bus / debug rom 16k x 16-bit sram program memory controller s/u data txrdy rxrdy uint address decoder tdmac, rdmac, uint clock generator address & control bus for avr register file programming interrupt lines avr core ram address bus & bi-directional data bus lftu usclk uart 1 irda 1.0 encdec pa0/sin1/irrx pa1/sout1/ir t pa2 pa3 pa4 pa5 pa6 pa7 2k x 8-bit 4 at76c711 1643c?usb?10/02 notes: 1. (*) gnd - tgfp: 12, 21, 25, 35, 46, 51, 62. 2. (**) vcc - tqfp: 10, 20, 24, 36, 45, 49, 63. 3. (***) gnd - bga: b3, c6, c7, e3, f6, h5, g4 4. (****)vcc-bga:a2,a8,c8,f7,f4,g3,d3 pin summary ? pin assignment in alphabetical order type: i = input, o = output, od = output, open drain, b = bi-directional, v = power supply, ground pin # tqfp pin # bga signal type pin # tqfp pin # bga signal type pin # tqfp pin # bga signal type 23 h4 dm b 44 d6 pa7 b 58 c5 pd4 b 22 h3 dp b 2 b1 pb0_t0 b 59 b4 pd5 b 33 h8 eck i 3 c3 pb1_t1 b 60 c4 pd6_int0 b 19 f3 lc i 4 c2 pb2_icp b 61 a3 pd7_int1 b 14 e2 lft i 5 d2 pb3 b 16 g2 psdin i 50 a7 lftu i 6 c1 pb4_ss b1a1rst i * *** gnd v 7 d1 pb5_mosi b 27, 28 g5, f5 pm0, pm1 i 64 b2 nc 8 d4 pb6_miso b 24 e4 susp o 48 b7 p_irx i 9 e1 pb7_sck b 17 h1 tck i 47 b8 p_itx o 29 h6 pc0 b 15 g1 test1 i 37 e7 pa0 b 30 g6 pc1 b 34 g8 test2 i 38 f8 pa1 b 31 h7 pc2 b 18 h2 tp i 39 e8 pa2 b 32 g7 pc3 b ** **** vcc v 40 e5 pa3 b 54 a6 pd0_sin b 51 b6 uxtali i 41 d8 pa4 b 55 a5 pd1_sout b 52 b5 uxtalo o 42 e6 pa5 b 56 d5 pd2 b 11 f1 xtal1 i 43 d7 pa6 b 57 a4 pd3 b 12 f2 xtal2 o 5 at76c711 1643c?usb?10/02 pin summary ? pin assignment in numerical order pin # tqfp pin # bga signal type pin # tqfp pin # bga signal type pin # tqfp pin # bga signal type 1a1rst i23h4dm b45c8vccv 2 b1 pb0_t0 b 24 e4 susp o46c7gndv 3 c3 pb1_t1 b 25 h5 gnd v 47 b8 p_itx o 4 c2 pb2_icp b 26 f4 vcc v 48 b7 p_irx i 5 d2 pb3 b 27 g5 pm0 i 49 a8 vcc v 6 c1 pb4_ss b 28f5pm1 i 50a7lftu i 7 d1 pb5_mosi b 29 h6 pc0 b 51 c6 gnd v 8 d4 pb6_miso b 30 g6 pc1 b 52 b6 uxtali i 9 e1 pb7_sck b 31 h7 pc2 b 53 b5 uxtalo o 10 d3 vcc v 32 g7 pc3 b 54 a6 pd0_sin b 11 e2 lft i 33 h8 eck i 55 a5 pd1_sout b 12 e3 gnd v 34 g8 test2 i56d5pd2b 13 f1 xtal1 i 35 f6 gnd v 57 a4 pd3 b 14 f2 xtal2 o 36 f7 vcc v 58 c5 pd4 b 15 g1 test1 i37e7pa0b59b4pd5b 16 g2 psdin i 38 f8 pa1 b 60 c4 pd6_int0 b 17 h1 tck i 39 e8 pa2 b 61 a3 pd7_int1 b 18 h2 tp i 40 e5 pa3 b 62 b3 gnd v 19 f3 lc i 41 d8 pa4 b 63 a2 vcc v 20 g3 vcc v 42 e6 pa5 b 64 b2 nc v 21 g4 gnd v 43 d7 pa6 b 22 h3 dp b 44 d6 pa7 b 6 at76c711 1643c?usb?10/02 signal description (1) type: i = input, o = output, od = output, open drain, b = bi-directional, v = power supply, ground name type description program memory controller signals pm0, pm1 i configuration pins ? see figure 3 psdin i program serial data-in: in slave program mode, this signal carries the serial program data that are samples with the positive edge of tck. tp i when rst is active (low), a high level of this signal, for at least two tck pulses, forces the program address generator. lc i load complete: a transition from low to high denotes the completion of program data transfer from the external device. the avr will start executing instructions from the internal sram as soon as the rst goes high. tck i a clock signal for sampling psdin input. port signals pa[0:7] b port a, pa0 through pa7 ? 8-bit bi-directional port. pa[0:7] b port b, pb0 through pb7 ? 8-bit bi-directional port. pb0, pb1, pb2, pb4 through pb7 are dual- function as shown below: port alternate function pb0 timer/counter0 clock input pb1 timer/counter1 clock input pb2 (icp) input capture pin for timer/counter1 pb4 (ss ) spi slave port select input pb5 (mosi) spi slave port select input pb6 (miso) spi master data-in, slave data-out pb7 (sck) spi master clock out, slave clock in pc[0:3] b port c, pc0 through pc3 ? 4-bit output port. pd[0:7] b port d, pd0 through pd7 ? 8-bit bi-directional i/o port. pd0, pd1 also serve as the data lines for the asynchronous serial port as listed below: port alternate function pd0 (sin) serial data-in (i): this pin provides the serial receive data input to 16550 uart. the sin signal will be a logic ?1? during reset, idle (no data). during the local loopback mode, the sin input pin is disabled and sout data is internally connected to the uart sin input. pd1 (sout) serial data out (o): this pin provides the serial transmit data from the 16550 uart. the sout signal will be a logic ?1? during reset, idle (no data). pd6 (int0) external interrupt0 source pd7 (int1) external interrupt1 source usb serial interface dp b upstream plus usb i/o ? dp and dm form the differential signal pin pair connected to the host controller or an upstream hub. dm b upstream minus usb i/o susp o suspend: this output pin is deactivated (high) during normal operation. it is used to signal the host microcontroller that at76c711 has received usb suspend signaling. this pin will stay asserted while at76c711 is in the suspend mode. this pin is deactivated whenever a usb resume signaling is detected on dp and dm. 7 at76c711 1643c?usb?10/02 note: 1. any signal with an overline indicates that it is an active low signal. test signals test1 i test signal for clocks (used in production phase only ? normally tied to high) test2 i test signal for monitoring internal signal levels using the four data ports (used in production phase only ? normally tied to high) eck i clock pulse for activating various test modes when test2 is active irda interface p_itx o infrared data out: this pin provides the serial transmit data from the irda codec to external ir data transceiver. this function is activated when the irda interface is enabled from periphen i/o register. p_irx i infrared data-in: this pin provides the serial receive data input from the external ir data transceiver to irda codec. this function is activated when the irda interface is enabled from periphen i/o register. other signals gnd v ground vcc v 3.3v power supply rst i reset: a low on this pin for two machine cycles, while the oscillator is running, resets the device. xtal1 i oscillator input: input to the inverting oscillating amplifier. a 12 mhz clock oscillator should be applied. xtal2 o oscillator output: output of the inverting oscillator amplifier. lft i master clock pll lft pin uxtali i uart brg oscillator input. input to the uart oscillator amplifier. uxtalo o uart brg oscillator output. output of the uart oscillator amplifier. lftu i uart clock pll lft pin signal description (continued) (1) type: i = input, o = output, od = output, open drain, b = bi-directional, v = power supply, ground name type description 8 at76c711 1643c?usb?10/02 functional description bootstrap rom and program modes the at76c711 offers a variety of program modes that allow the user not only to upload the microcode to internal program sram but also to upgrade the system firmware that is contained in a serial at45db011 (or larger) flash. at76c711 supports one slave and three master program modes. slave program mode the chip enters the slave program mode while in the reset state (rst active low) when it detects a positive edge transition of tp signal. the timing diagram of the procedure is depicted in figure 3. figure 3. slave program mode timing diagram master program modes on power-up or after a system reset, the bootstrap code traces the value of the pm0, pm1 signals and executes the respective task according to figure 3. after the execution of any of the following tasks, the chip enters the normal mode and starts running the code loaded in the internal program sram. note: 1. this mode is not supported in the current version of the chip. rst psdin tp tck lp pm0 pm1 task 1 x spi program mode: the internal program sram is loaded from the external serial flash through the spi. 0 0 usb program mode: the host downloads the code to the internal program sram using the dfu protocol. (1) 0 1 usb program mode with firmware upgrade: the host downloads pages of code to the internal program sram, which are then stored to the external spi flash. (1) 9 at76c711 1643c?usb?10/02 usb hardware block usb function interface the usb function interface consists of a serial interface engine (sie), a serial bus controller (sbc) and a system interface (si). the sie performs the clock/data separa- tion, nrzi encoding and decoding, bit insertion and deletion, crc generation and checking and the serial-parallel data conversion. the sbc consists of a protocol engine and a usb device with one control endpoint (ep0), four programmable endpoints, each with one 2 x 64-byte dedicated double-buffered fifo and one programmable endpoint with one 2 x 16-byte double-buffered fifo. each ep can be programmed as isochro- nous, bulk or interrupt and can be configured either as in or out. a pair endpoint address scheme is also supported for the first four programmable endpoints. according to this scheme, two endpoints may have the same address, provided one of them has been configured as in and the other as out. the sbc manages the device address, monitors the status of the transactions, manages the fifos and communicates to the microcontroller through a set of status and control registers. the si connects the sbc to the microcontroller and provides a dma mechanism for transferring data between the dpram and the endpoint buffers. usb function controller the function controller is implemented in the microcontroller?s firmware. usb interrupt handling all interrupt signals from the usb functions are consolidated into a single interrupt line, which is input to the interrupt controller of the avr. the following sections describe all the interrupt sources of the usb controller. all interrupts are masked through the interrupt enable registers that exist in the usb controller. the external resume and received resume interrupts are cleared when the firmware clears the interrupt bit (the suspend interrupt is automatically cleared when activity is detected). all other interrupts are cleared when the processor sets a corre- sponding bit in an interrupt acknowledge register in the usb macro cell. there is only one bit for each interrupt source. interrupt description function ep0 interrupt see ?control transfers at function ep0? for details. function ep1 interrupt for an out endpoint, it indicates that function endpoint1 has received a valid out packet and that the data is in the fifo. for an in endpoint, it means that the endpoint has received an in token, sent out the data stored in the fifo andreceivedanackfromthehost.thefifoisnowreadytobewrittenby new data from the processor. function ep2 interrupt see function ep1 interrupt function ep3 interrupt see function ep1 interrupt function ep4 interrupt see function ep1 interrupt function ep5 interrupt see function ep1 interrupt function ep6 interrupt see function ep1 interrupt sof received whenever usb hardware decodes a valid start of frame ext rsm the usb hardware has received a remote wake-up request. rcvd rsm the usb hardware has received resume signaling. the processor?s firmware should take the function out of the suspended state. susp the usb hardware has detected a suspend condition and is preparing to enter the suspend mode. the processor?s firmware should place the embedded function in the suspend mode. 10 at76c711 1643c?usb?10/02 interrupt priority the usb macro interrupt priority is defined below. endpoint interrupt endpoint interrupts are triggered by setting or clearing one or more bits in the control and status registers of an endpoint. these interrupts are caused by events during packet transactions and are different for control and non-control endpoints. the inter- rupts are described below, with respect to the control and status register bit definitions. please refer to the ?endpoint control and status register? definition on page 59. interrupt for non-control endpoints 1. rx out packet set (0 -> 1) 2. tx packet ready clear (1 -> 0) interrupt for control endpoints 1. rx out packet set (0 -> 1) 2. rx setup set (0 -> 1) 3. tx packet ready clear (1 -> 0) 4. tx complete set (0 -> 1) serial interface engine the sie performs the following functions: nrzi data encoding and decoding bit stuffing and unstuffing crc generation and checking acks and nacks identifying the type of a token address checking clock generation (via dpll) function interface unit the function interface unit (fiu) provides the interface between the processor and the sie. it manages transactions at the packet level with minimal intervention from the pro- cessor and contains the endpoints? buffers. the fiu is designed to operate in single-packet mode and to manage the usb packet protocol layer. to operate the fiu, the firmware must first enable the endpoints of the fiu, and select direction and ping-pong capability. after being enabled, the endpoints are in receive mode by default. the fiu notifies the processor when a valid token has been received. the data contained in the data packet will be supplied in the fifo. the processor transfers the data to and from the host by interacting with each end- point?s fifo and control and status registers. for example, when transmitting an in packet, the fiu assembles the data of the end- point?s fifo in a usb packet, transmits the packet and will signal the processor after the host receives and acknowledges the packet. the fiu performs automatic data packet retransmission and data0/data1 pid toggling. for setup tokens, the processor must parse the device request and then respond appropriately. after a setup token, there may be zero (0) or more data in or data out packets for which the processor must either supply or receive the data. priority level interrupt name 2 (high level) sof received 1: same level (low level) function ep0 to ep6 11 at76c711 1643c?usb?10/02 control transfers at function ep0 legend: data1/data0 = data packet with data1 or data0 pid data 1 (0) = zero length data1 packet host usb macro microcontroller setup stage 1. [sync]-[setup] 2. [sync]-[data0] 3. data are put in fifo 4. if crc ok, send [sync]-[ack] 5. if crc ok, set rx_setup bit 6. interrupt 7. read uisr (bit 0 is set) 8. read fcsr0 (rx_setup bit) 9. read fbyte_cnt0 10. read fifo0 11. parse data if set control direction fill fifo with data set tx_packet_ready if control write phase: clear control direction if no data stage phase: clear control direction set data_end bit if unsupported command: set force_stall bit 12. clear rx_setup bit 13. set uiar (ep0 inta) status stage, no data stage 1. [sync]-[in] 2. send data1(0) 3. if crc ok, send [sync]-[ack] 4. set tx_complete bit 5. interrupt 6. read uisr 7. read csr 8. if set_address, write to faddr 9. clear tx_complete bit 12 at76c711 1643c?usb?10/02 10. clear data_end bit 11. set force_stall bit 12. set uiar (ep0 inta) data stage, control read 1. [sync]-[in] 2. if tx_packet_ready = 1 send data0/data1 else send stall 3. if crc ok, send [sync]-[ack] 4. clear tx_packet_ready 5. set tx_complete bit 6. interrupt 7. read uisr 8. read csr 9. clear tx_complete bit 10. if more data fill fifo with data set tx_packet_ready else set set_force_stall 11. set uiar (ep0 inta) status/early status stage with read data stage 1. [sync]-[out] 2. [sync]-[data1(0)] 3. if tx_complete = 0 send [sync]-[ack] set rx_out else send [sync]-[nack] 4. interrupt 5. read uisr 6. read csr 7. clear rx_out 8. set data_end control transfers at function ep0 (continued) legend: data1/data0 = data packet with data1 or data0 pid data 1 (0) = zero length data1 packet host usb macro microcontroller 13 at76c711 1643c?usb?10/02 9. set force_stall comment: a setup token will clear data end. not cleared by firware in case host retries 1 through 3. 10. set uiar (ep0 inta) data stage, control write 1. [sync]-[out] 2. [sync]-[data1/data0] 3. data are put in fifo 4. if crc ok, send [sync]-[ack] 5. if crc ok, set rx_out 6. interrupt 7. read uisr 8. read csr 9. read fifo 10. clear rx_out if last packet, set data_end set force_stall 11. set uiar (ep0 inta) status stage with write data stage 1. [sync]-[in] 2. send data1(0) 3. if crc ok, send [sync]-[ack] 4. set tx_complete bit 5. interrupt 6. read uisr 7. read csr 8. clear tx_complete bit 9. clear data_end bit 10. set force_stall bit 11. set uiar (ep0 inta) control transfers at function ep0 (continued) legend: data1/data0 = data packet with data1 or data0 pid data 1 (0) = zero length data1 packet host usb macro microcontroller 14 at76c711 1643c?usb?10/02 interrupt and bulk in transfers 1. the usb hardware automatically starts the endpoint in receive mode and naks all in tokens as long as bit csr[tx packet ready] is cleared. 2. the processor checks bit csr[tx packet ready]. if it is ?0?, writes the data into the fifo, then sets csr[tx packet ready]. 3. at the next in token, the usb hardware sends the packet out and waits for an ack. until an ack is received, the usb hardware will retransmit the packet. after receiving an ack, the usb hardware clears bit csr[tx packet ready], signaling a successful completion to the processor. figure 4. in token with and without ping-pong interrupt and bulk out transfers the usb hardware automatically starts the endpoint in receive mode. when an out token is received and if csr[rx out packet] is cleared, it stores the data in the fifo. it acks the host if the data received are not corrupted, and then interrupts the proces- sor. if csr[rx out packet] is set, the usb hardware responds with a nak to the incoming out token: the processor checks csr[rx out packet] and if it is ?1?, it reads the data from the fifo and clears csr[rx out packet ready]. figure 5. out token with and without ping-pong in token without ping-pong in token with ping-pong host reads usb fifo in token uc fills usb fifo host reads last data in token uc fills data uc pooling tx_complete ack tx_pkt_rdy = 1 tx_complete = 1 ack tx_complete = 1 tx_pkt_rdy = 0 tx_pkt_rdy = 1 host reads usb fifo in token ack tx_complete = 1 tx_pkt_rdy = 0 tx_complete = 0 tx_complete = 0 host reads last data in token uc fills data uc pooling tx_complete ack tx_pkt_rdy = 1 tx_complete = 1 tx_complete = 0 out token without ping-pong out token with ping-pong host fills usb fifo out token uc reads fifo rx_out = 1 rx_out = 0 ack out token host fills usb fifo out token uc reads fifo rx_out = 1 host fills usb fifo out token uc reads last data uc pooling rx_out rx_out = 1 rx_out = 0 ack host fills usb fifo out token uc reads last data uc pooling rx_out rx_out = 1 rx_out = 0 ack 15 at76c711 1643c?usb?10/02 interrupt and isochronous transfers isochronous transfers use the same protocol with bulk transfers except that error correc- tion and data packet retransmission are not supported: noacktoken nonaktoken data pid is always zero interrupt and interrupt in transfers interrupt transfers use the same protocol with bulk in transfers (interrupt out is not supported in usb spec 1.0). suspend a usb device enters the suspend mode only when requested by the usb host through bus inactivity for at least 3 ms. the usb hardware detects this request, sets the susp bit of the suspend/resume register (sprsr), and interrupts the processor if the inter- rupt is enabled. the processor should shutdown any peripheral activity, enter power- down mode and signal the usb hardware that it can now enter the suspend mode by writing ?1? to the ?sleep mode? usb_macro input pin. at this moment, the ?suspend2sie? output pin is activated and the oscillator, pll and other peripherals should be disabled. resume resume is signaled by a j- to k-state transition at the usb port. the usb hardware enables the oscillator/pll and sets the rsm bit of the sprsr, which generates an interrupt. the processor starts executing where it left off and services the interrupt. then the firmware clears the rcvd rsm bit. remote wake-up while the usb peripheral is in suspend mode, resuming is also possible through the remote wake-up feature. remote wake-up is invoked due to an external event (such as the detection of a key pressing in a keyboard) and is denoted by the ?ext_int? usb_macro pins (active high). this action, in turn, enables the oscillator and the usb hardware. the usb hardware sets the associated flag of uisr and the ext rsm bit of sprsr. these generate two interrupts to the processor: ext_int and rsm_int. the pro- cessor starts executing where it left off and services the interrupt. then the firmware clears the ext rsm bit and ext[0-3] bit. if the remote wake-up feature is enabled and the usb bus remains idle for a period of 5 ms (already 3 ms in the suspend mode), the resume signal is sent to the host during the next 10 ms and the rsminpr bit of the global state register is set. 16 at76c711 1643c?usb?10/02 avr microcontroller the at76c711 is based on the avr architecture and includes many of the features of the avr at90s8515 microcontroller. all peripherals, apart from spi and timers, are memory mapped to the data address space. interrupt handling the interrupt vector table of at76c711 is shown below. oscillator and clock generator at76c711 has two on-chip crystal oscillators. the first one is the main oscillator and is used to generate the clocks of the avr cpu and the 48 mhz clock of the usb core. the nominal value of this oscillator should be 12 mhz. after the initial reset, the default cpu rate is 24 mhz. dividing the 48 mhz clock appropriately, an internal clock of 14.746 mhz is produced, which can be used for generating standard modem baud rates with a deviation of 1.6 percent. alternatively, if a strict baud rate is required, a dedicated oscillator for the uart block is provided. the clock tree circuit is shown in figure 6. the output pins of the crystal oscillators are not designed to drive any external circuits. instead of using crystals, either oscillator?s input pin can also be driven by an external clock signal. ta ble 1. at76c711 interrupt vectors vector # program address source interrupt definition 1 $0000 reset hardware pin and watchdog reset 2 $0002 susp/resm usb suspend and resume 3 $0004 int0 external interrupt request 0 4 $0006 timer1 capt timer/counter1 capture event 5 $0008 timer1 compa timer/counter1 compare match a 6 $000a timer1 compb timer/counter1 compare match b 7 $000c timer1 ovf timer/counter1 overflow 8 $000e timer0 ovf timer/counter0 overflow 9 $0010 spi, stc spi serial transfer complete 10 $0012 tdmac tx dma termination 11 $0014 uart0 int uart0 interrupt request 12 $0016 rdmac rx dma termination 13 $0018 usb hardware usb hardware interrupt 14 $001a uart1 int uart1 interrupt request 15 $001c int1 external interrupt request 1 17 at76c711 1643c?usb?10/02 figure 6. clock tree circuit uart0 the main features of uart0 are: programmable baud rate generator 16-byte fifo at the receiver side parity, framing and overrun error detection line break generation and detection automatic echo, local loopback and remote loopback channel modes interrupt generation two dedicated controller channels 5-, 6-, 7- and 8-bit character length maximum rate 921.6k baud interface to a dma controller for fast data transfers to/from the dpram the input to the baud rate generator is selectable between a 14.746 mhz clock (derived from the internal clock generator) or the dedicated uart oscillator. both the dma con- troller and the avr processor can have access to the uart registers. the arbitration of the uart memory bus is implemented internally to the dma controller. receiver the uart detects the start of a received character by sampling the rxd signal until it detects a valid start bit. a low level (space) on rxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space that is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the rxd at the theoretical midpoint of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1 bit period) so the sampling point is 8 cycles (0.5 bit periods) after the beginning of the bit. therefore, the first sampling point is sampled 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. each subsequent bit is sam- pled 16 cycles (1 bit period) after the previous one. pll x8 pll x2 div 4 or 5 div 2 div 4 div 5 div 13/8 (gobbling) div 2 irda 19.2 mhz 96 mhz cp1, cp2 24 or 19.2 mhz 14.7456 mhz uart0 12 mhz xtal 14.7456 mhz (optional) uxtal uart1 div 4 (dpll) 48 mhz 12 mhz 18 at76c711 1643c?usb?10/02 receive fifo operation the 16-byte receive data fifo is enabled by the (us_fcr) bit 0. the user can set the receiver trigger level. the receiver fifo section includes a timeout function to ensure data is delivered to the external cpu. an interrupt is generated whenever the receive holding register (us_rhr) has not been read after the loading of a character or if the trigger level has been reached. timeout this function allows an idle condition on the rxd line to be detected. the maximum delay for which the uart should wait for a new character to arrive while the rxd line is inactive (high level) is programmed in us_rto (receiver timeout). when this register is set to ?0?, no timeout is detected. otherwise, the receiver waits for a first character and then initializes a counter, which decrements at each bit period and is reloaded at each byte reception. when the counter reaches ?0?, the timeout bit (bit 6) in us_csr is set. the user can restart waiting for a first character by setting the start timeout bit (bit 4) of us_cr register. the timeout duration is: duration=valuex_4_x_bitperiod receive break the break condition is detected by the receiver when all data, parity and stop bits are low. at the moment of the low stop bit detection, the receiver asserts receive break (bit 2) in us_csr. the end of receive break is detected by a high level for at least 2/16 of the bit period. receive break (bit 2) is also set after the end of break has been detected. transmitter the start bit, data bits, parity bit and stop bits are serially shifted, with the least signifi- cant bit first, on the falling edge of the serial clock. the number of data bits is selected in the character length field, (bits 7 and 6) in us_pmr. the parity bit is set according to the parity type bit 1 field in us_pmr. the number of stop bits is selected in the number of stop (bits 4, 5) field in us_mr. when a character is written to us_thr (transmit hold- ing), it is transferred to the shift register as soon as it is empty. when the transfer occurs, the transmit ready (bit 1) in us_csr is set until a new character is written to us_thr. if the transmit shift register and us_thr are both empty, the transmitter empty (bit 7) in us_csr is set. time-guard the time-guard function allows the transmitter to insert an idle state on the txd line between two characters. the duration of the idle state is programmed in us _ttg (transmitter time-guard). when this register is set to ?0?, no time-guard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in us_ttg. transmit break the transmitter can generate a break condition on the txd line when the start break command (bit 0) is set in us_cr (control register). in this case, the characters present in us_thr and in the transmit shift register are completed before the line is held low. to remove this break condition on the txd line, the stop break command (bit 1) in us_cr must be set. the uart generates minimum break duration of one character length. the txd line then returns to high level (idle state) for at least 12-bit periods to ensure that the end of break is correctly detected. then the transmitter resumes normal operation. interrupt generation each status bit in us_csr has a corresponding bit in us_ier (interrupt enable) that controls the generation of interrupts by asserting the uart interrupt line. any of the par- ity, framing or overrun error condition generate a line? error interrupt. interrupt sources are given in the register description section. 19 at76c711 1643c?usb?10/02 channel modes the uart can be programmed to operate in three different test modes using the field channel mode (bits 6 and 7) in us_mr. automatic echo mode allows bit-by-bit retrans- mission. when a bit is received on the rxd line, it is sent to the txd line. programming the transmitter has no effect. the local loopback mode allows the transmitted characters to be received. txd and rxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the rxd pin level has no effect and the txd pin is held high, as in theidlestate. the remote loopback mode directly connects the rxd pin to the txd pin. the transmit- ter and the receiver are disabled and have no effect. this mode allows bit-by-bit retransmission. uart1 ? irda codec the irda codec provides an irda 1.0 standard interface. it is connected to the sin and sout of uart1. the irdamod register of the i/o register set selects the operation mode of the irda codec. the en bit activates the module. when it is deactivated, the uart signals are con- nected directly to the external interface, bypassing the irda codec block. otherwise, it encodes the outgoing and decodes the incoming data from and to the uart1 respec- tively, according to the irda 1.0 standard (3/16 modulation). the mode bit gives the user the capability to change the modulation scheme from 3/16 pulse width to 4/16. the uart settings should be half-duplex to avoid signal interference. the uart1 reg- ister set is similar to that of uart0: its base address is 2030/hex. the irda codec transmits a 3/16 pulse width on zeros (0) and nothing on ones (1). in receive operations, it extends the incoming zeros to 16/16 pulse and feeds them reversed to the uart1 sin (see ?irda serial infrared physical layer specification? at www.irda.org/standards). an internally generated clock of 19.2 mhz makes it possible to use the irda module for up to 1.2 mbps transfer rates (much higher than the typical 115.2 kbps). this capability offers a simple solution for high-speed infrared communications. the input to the baud rate generator of uart1 is selectable between the 19.2 mhz clock and the clock of the dedicated oscillator for standard modem rates. a typical application of the at76c711 connection to an external ir data transceiver when the irda module is enabled is shown in figure 7. the gpo is a general-purpose output (can be provided from the data ports). 20 at76c711 1643c?usb?10/02 figure 7. at76c711 connection to external ir data transceiver, irda module enabled dma controller the dma controller is able, under firmware control, to transfer data between the dpram and the uart, without the intervention of the processor. the dma controller will interrupt the processor as soon as it transfers the processor-preprogrammed num- ber of bytes. during data transfers from the dma controller, the transmit and receive dma status registers are updated with possible errors indicated by the uart. these status registers can be read by the processor, after the dma controller?s interrupt at the end of a block transfer, to report if the block transfer was error free or not. the dma controller is programmed by the processor to transfer blocks of data between the dpram and the uart core. in addition, the uart can be accessed by the proces- sor only through the dma controller module. thus, data transfers between the processor and other memory devices are not interrupted when dma transfers occur. segmentation and reassembly of the transmitted/received packets through the uart are also executed with the aid of the dma controller, under firmware control. reassem- bly of network packets is implemented by storing the usb packets from a certain endpoint in successive address spaces. the dma controller is then programmed to con- secutively transfer the bytes of the reassembled packet that has been formed. on the other hand, during packet reception from the uart, the processor can program the dma controller to read a certain number of bytes from the uart?s fifo and store them at a given target address, depending on the packet header. after the end of the dma transfer, an interrupt is issued by the dma controller to signal the processor to check for possible errors during this transfer and forward the packet to the eps of the usb interface. the dma controller is programmed with the characteristics of a dma transfer before it is enabled. the only information that is required is the dpram target address and the packet length, because it is already aware of the segment boundaries in order to per- form wraparound inside the corresponding segment. in addition, status registers provide information related to errors encountered during a dma transfer. two of the above sets of registers are implemented, one for each direction. ir data transceiver irda 1.0 codec usart1 clock gen. en gpo sd/mode tx rx rx tx 16x clk at76c711 mode 21 at76c711 1643c?usb?10/02 transmit and receive dmas are performed by polling the txrdy and rxrdy signals of the uart. a dma operation consists of reading the uart status registers and access- ing the data hold register. transmit and receive dma operations can take place simultaneously. whenever a receive dma operation is terminated, either normally or by a receive char- acter timeout interrupt from the uart or forced by the firmware, an internal rdmac interrupt signal from dma is issued to the processor. after that, the firmware should read rxtpll and rxtplm to be informed about the exact number of the received bytes, possible errors during dma and the reason for the dma termination. after a transmit dma termination, either normally or forced by firmware, an internal tdmac interrupt signal from the dma is issued to the processor. after that, the firm- ware should read txtpll and txtplm to be informed about the exact number of the transmitted bytes and the reason for dma termination. dpram organization dpram organization is related to the length of the packets transferred through uart. the programmer can define segments in the dpram address space from dporg reg- ister of the dma controller. memory segmentation facilitates wraparound during dma transfers. according to the number of segments, the dma controller can determine the end and start address of each segment so it doesn?t need to be informed about the segment boundaries each time a transfer is enabled. the default state is the dpram being unsegmented. details of the possible dpram segmentation schemes are given at the description of the dporg register of the dma controller. mapping allocations the avr uses a 16-bit address bus to have access to 64-kbyte memory locations. in at76c711 design this memory is shared among the various peripherals as shown in figure 8. address space size module 0000 - 07ff 2048 bytes sram 0800 - 0fff 2048 bytes reserved 1000 - 1fff 4096 bytes usb (not all of the locations are used) 2000 - 201f 32 bytes dma controller 2020 - 202f 16 bytes uart0 2030 - 203f 16 bytes uart1 2040 1 byte program memory control bit 2041 - 2fff 4031 bytes reserved 3000 - 37ff 2048 bytes dpram 3800 - 7fff 18432 bytes reserved 8000 - 7fff 16384 bytes program sram 7fff - ffff 16384 bytes reserved 22 at76c711 1643c?usb?10/02 figure 8. memory allocation for on-chip resources note: 1. these register blocks are mapped to any 256-byte boundary (x00) in address space 2000 - 2fff/h. 0000/h ffff/h 64-kbyte address space sram (0-7ff, rest reserved) 0fff/h 1000/h 1fff/h 2000/h usb register set 2fff/h 3000/h x00 x1f x20 x2f 16-byte addresses for 12 registers of uart0 32 bytes dma controller (1) 37ff/h 3800/h 7fff/h 8000/h program sram* x50 x5f 16-byte addresses for 12 registers of uart1 reserved *program for avr is stored in the 8k x 16-bit program sram (reset vector is kept in address| ? 0000 ?). the program memory can be read using the lpm instruction. however, in order to modify that, it is mapped to the peripheral memory address space as follows: least significant byte of address ? 0000 ? corresponds to byte address 8000/h of the peripheral memory address space. most significant byte of address ? 0000 ? corresponds to byte address 8001/h of the peripheral memory address space and so on. dpram 23 at76c711 1643c?usb?10/02 i/o memory the i/o space definition of at76c711 is shown in table 2. this space is defined in the area $00 - $3f and can be directly accessed by in and out instructions or by ordinary sram accesses in the area $20 - $5f. the notation used will be followed in the rest of this document. a more detailed description of the i/o memory space is given in the sec- tions that follow. ta ble 2. at76c711 i/o space i/o address (sram address) name function $3f($5f) sreg status register $3e($5e) sph stack pointer high $3d($5d) spl stack pointer low $39($59) eimsk external interrupt mask register $37($57) timsk timer interrupt mask register $36($56) tifr timer interrupt flag register $35($55) mcucr mcu general control register $34($54) mcusr mcu status register $33($53) tccr0 timer0 control register $32($52) tcnt0 timer0 (8 bits) $31($51) preld pre-load register $2f($4f) tccr1a timer1 control register a $2e($4e) tccr1b timer1 control register b $2d($4d) tcnt1h timer1 high byte $2c($4c) tcnt1l timer1 low byte $2b($4b) ocr1ah timer1 output compare register a high byte $2a($4a) ocr1al timer1 output compare register a low byte $29($49) ocr1bh timer1 output compare register b high byte $28($48) ocr1bl timer1 output compare register b low byte $27($47) icr1h timer1 input capture register high byte $26($46) icr1l timer1 input capture register low byte $21($41) wdtcr watchdog timer control register $20($40) irdamod irda control register $1b($3b) porta data register, port a $1a($3a) ddra data direction register, port a $19($39) pina input pins, port a $18($38) portb data register, port b $17($37) ddrb data direction register, port b $16($36) pinb input pins, port b $15($35) portc data register, port c 24 at76c711 1643c?usb?10/02 the avr status register ? sreg bit 7 ? i: global interrupt enable when set, the interrupts are enabled. the individual interrupt enable control is per- formed in the individual mask registers. this bit is cleared by usb hardware after an interrupt has occurred and is set by the reti instruction to enable subsequent interrupts. bit 6 ? t: bit copy storage bit load (bld) and bit store (bst) instructions use the t-bit as source and destination for the operated bit. bit 5 ? h: half-carry flag indicates a half-carry in some arithmetic operations. bit 4 ? s: sign bit, s = n xor v is an exclusive or between the negative flag n and the two?s complement overflow flag v. bit 3 ? v: two?s complement overflow flag supports two?s complement arithmetic. bit 2 ? n: negative flag when set, indicates a negative result in arithmetic and logic operations. bit 1 ? z: zero flag when set, indicates a zero result after the different arithmetic and logic operations. bit0?c:carryflag when set, indicates a carry in the arithmetic or logic operations. the stack pointer ? sp $14($34) clk_cntr clock control register $13($33) periphen peripheral enable register $12($32) portd data register, port d $11($31) ddrd data direction register, port d $10($30) pind input pins, port d $0f($2f) spdr spi i/o data register bit 76543210 $3f ($5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 1514131211109 8 $3e ($5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 ta ble 2. at76c711 i/o space (continued) i/o address (sram address) name function 25 at76c711 1643c?usb?10/02 the mcu control register ? mcucr the mcu control register is a r/w 3-bit register with zero initial value. it consists of the following bits: bits 7, 6 ? reserved bits always read as zero. bit5?se:sleepenable when set, enables the mcu to enter sleep mode when the sleep instruction is executed. bits4-0?reservedbits these bits always read as zero mcu status register ? mcusr the mcusr is a 2-bit r/w register that provides information on which reset source caused an mcu reset. bits7..2?reservedbits always read as zero. bit1?rewd this flag indicates that an external or power-on reset has occurred. bit 0 ? porf: power-on reset flag the following table shows the value of these two bits after the three modes of reset. bit 76543210 $35 ($55) ??sesm1sm0???m cucr read/write r r r/w r/w r/w r r r initialvalue00000000 bit 76543210 $35 ($55) ??????reswdporfmcusr read/write r r rrrrr/wr/w initialvalue000000seebitdescription table 3. porf and extrf values after reset reset source porf extrf power-on reset 1 undefined external reset unchanged 1 watchdog reset unchanged unchanged 26 at76c711 1643c?usb?10/02 the user program must clear these bits as early as possible. if these bits are cleared before a reset condition occurs, the source of reset can be found by using the following truth table. the external interrupt mask register ? eimsk this is a 4-bit r/w register. its initial value is zero. it is used for masking the external interrupts. bits7..4?reservedbits always read as zero. bit3?pol1 polarity of external interrupt 1. int1 is active high when this bit is low. bit2?pol0 polarity of external interrupt 0. int0 is active high when this bit is low. bit1?int1 if it is set and the 1 bit in the status register is set, the external pin interrupt 1 is enabled. bit0?int0 if it is set and the 1 bit in the status register is set, the external pin interrupt 0 is enabled. the timer/counter interrupt mask register ? timsk external interrupts should be acknowledged using general-purpose output pins. this is an 8-bit r/w register with zero initial value, used for masking the internal timer interrupts. bit 7 ? toie1: timer/counter1 overflow interrupt enable when this bit is set and the i-bit in the status register is one, the timer/counter1 over- flow interrupt is enabled. the corresponding interrupt (at vector $001c) is executed if an overflow in timer/counter1 occurs. the timer/counter1 overflow flag is set in the timer/counter1 interrupt flag register ? tifr. ta ble 4. reset source identification porf extrf reset source 0 0 watchdog reset 0 1 external reset 10 power-onreset 11 power-onreset bit 76543210 $39 ($59) ????pol1pol0int1int0eimsk read/write rrrrr/wr/wr/wr/w initialvalue00000000 bit 76543210 $37 ($57) toie1 ocie1a ocie1b ? ticie1 ? toie0 ? timsk r/w r/w r/w r/w r r/w r r/w r initialvalue00000000 27 at76c711 1643c?usb?10/02 bit 6 ? ocie1a: timer/counter1 output compare a match interrupt enable when this bit is set and the i-bit in the status register is one, the timer/counter1 com- pare a match interrupt is enabled. the corresponding interrupt (at vector $0018) is executed if a compare a match in timer/counter1 occurs. the compare a flag in timer/counter1 is set in the timer/counter interrupt flag register ? tifr. bit 5 ? ocie1b: timer/counter1 output compare b match interrupt enable when this bit is set and the i-bit in the status register is one, the timer/counter1 com- pare b match interrupt is enabled. the corresponding interrupt (at vector $001a) is executed if a compare b match in timer/counter1 occurs. the compare b flag in timer/counter1 is set in the timer/counter interrupt flag register ? tifr. bit 4 ? reserved bit bit 3 ? ticie1: timer/counter1 input capture interrupt enable when this bit is set and the i-bit in the status register is one, the input capture event interrupt is enabled. the corresponding interrupt (at vector $0016) is executed if a cap- ture event occurs on pin pd2. the input capture flag in timer/counter1 is set in the timer/counter interrupt flag register ? tifr. bit 2 ? reserved bit bit 1 ? toie0: timer/counter0 overflow interrupt enable when this bit is set and the i-bit in the status register is one, the timer/counter0 over- flow interrupt is enabled. the corresponding interrupt (at vector $0020) is executed if an overflow in timer/counter0 occurs. the timer/counter0 overflow flag is set in the timer/counter1 interrupt flag register ? tifr. the timer/counter interrupt flag register ? tifr bit6?ocfa:outputcompareflaga the ocfa is set when a compare match between timer/counter1 and the ocr1a register occurs. this flag is cleared when written with a logic ?1?. bit 5 ? ocfb: output compare flag 1b the ocf1b is set when a compare match between timer/counter1 and the ocr1b register occurs. this flag is cleared when written with a logic ?1?. bit 4 ? reserved bit bit3?icf1:inputcaptureflag this flag, when set, indicates an input capture event, where the contents of the timer/counter1 are transferred to the icr1 register. this flag is cleared when written with a logic ?1?. bit 2 ? reserved bit bit 1 ? tov0: timer/counter1 overflow flag the tov0 is set when an overflow occurs in timer/counter0. this flag is cleared when writtenwithalogic?1?. bit 76543210 $36 ($56) tov1 ocfa ocfb ? icf1 ? tov0 ? tifr r r/w r/w r/w r r/w r r/w r initialvalue00000000 28 at76c711 1643c?usb?10/02 bit 0 ? reserved bit the timer/counter0 control register ? tccr0 bits 2-0 of tccr0 register control the prescaling of the timer0 clock according to table 5. note: 1. clk = 24 mhz the timer/counter0 ? 0 this timer/counter consists of 8 bits which can be written by the avr with any initial value to start count from. when this counter is enabled (by writing the cs0[2:0] bits of the tccr0 with the appropriate value), it starts counting up to 0xff and when overflowed it is loaded with the value of the preld register. pre-load register ? preld an 8-bit r/w register with zero initial value. the contents of this register are loaded to timer/counter0 (tcnt0) after an overflow of timer/counter0 occurs. bit 76543210 $33 ($53) ? ? ? ? ? cs02 cs01 cs00 tccr0 read/write r r r/w r/w r/w r/w r/w r/w initialvalue00000000 ta ble 5. timer0 prescale select cs02 cs01 cs00 description 0 0 0 timer 0 is stopped 001clk 010clk/8(3mhz) (1) 011clk/64 1 0 0 clk/256 1 0 1 clk/1024 1 1 0 external pin pb0, rising edge 1 1 1 external pin pb0, falling edge bit 1514131211109 8 $32 ($52) msb lsb tcnt0 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $31 ($51) msb lsb preld read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 29 at76c711 1643c?usb?10/02 the timer/counter1 control register a ? tccr1a this is an 8-bit r/w register with zero initial value. it controls the action taken by the specific output pin on compare match a or b that supports timer1. the functionality of thebitsisasfollows: bits 7, 6 ? com1a1, com1a0: compare output mode a these bits cause a specific action for the output compare pin pd6, as shown in table 6, for timer0. bits 5, 4 ? com1b1, com1b0 the same holds for compare output mode b and output compare pin pd7, as in the previous case for the compare output mode a. bits3..0?reservedbits note: 1. x = a or b the timer/counter register b ? tccr1b this is an 8-bit r/w register with zero initial value. bit 7 ? icnc1: input capture1 noise canceler (4 cks) when this bit is zero, the input canceler function is disabled. the input capture is trig- gered at the first rising/falling edge sampled on the input capture pin pb2, as specified by the ices1 bit. when this bit is set, four successive samples are measured and all samples must be high/low according to the input capture trigger specification in the ices1 bit. the actual sampling frequency is the cpu clock frequency. bit 6 ? ices1: input capture1 edge select when this bit is cleared, the timer/counter1 contents are transferred to the input cap- ture register ? icr1 on the falling edge of the input capture pin, pb2. when it is ?1?, the contents are transferred on the rising edge. bits 5, 4 ? reserved bits always read as zero. bit 7 6 5 4 3210 $2f ($4f) com11com1a0com1b1com1b0????tccr1a read/write r/w r/w r/w r/w rrrr initialvalue0 0 0 0 0000 ta ble 6. compare mode select (1) com1x1 com1x0 description 0 0 timer disconnected from output pin 0 1 toggle output pin 1 0 clear output pin 1 1 set output pin bit 76543210 $2e ($4e) icnc1 ices1 ? ? ctc1 cs12 cs11 cs10 tccr1a read/write r/w r/w r r r/w r/w r/w r/w initialvalue00000000 30 at76c711 1643c?usb?10/02 bit 3 ? ctc1: clear timer/counter1 on compare match when it is ?1?, the timer/counter1 is reset to $0000 after a compare a match. if it is cleared, the timer/counter1 continues counting after a compare a match. bits 2..0 ? cs12, cs11 and cs10: clock select1, bits 2, 1 and 0 these bits select prescaling source for the timer/counter1 according to table 7. note: 1. x = a or b the timer/counter1 ? tcnt1h and tcnt1l this timer/counter consists of 16 bits and is made by two 8-bit r/w registers with initial value of zero, namely tcnt1h and tcnt1l. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary register (temp). this temporary register is also used when accessing ocr1a, ocr1b and icr1. if the main program and inter- rupt routines perform accesses to registers using temp, interrupts must be disabled during access from the main program. tcnt1 timer/counter1 write when the cpu writes to the high byte (tcnt1h), the written data are placed in the temp register. next, when the cpu writes the low byte (tcnt1l), this byte of data is combined with the temp register and all 16 bits are written simultaneously to the timer/counter1 (tcnt1) register. consequently, the high byte must be accessed first for a full 16-bit write operation. when using timer/counter1 as an 8-bit counter, it is suf- ficient to write the low byte only. tcnt1 timer/counter1 read when the cpu reads the low byte (tcnt1l), the data are placed in the temp register. next, when the cpu reads the high byte (tcnt1h), the cpu receives the data in the temp register. consequently, the low byte must be accessed first for a full 16-bit read operation. when using timer/counter1 as an 8-bit counter, it is sufficient to read the low byte only. ta ble 7. timer1 prescale select cs12 cs11 cs10 description 0 0 0 timer1 is stopped 001clk 010clk/8 (1) 011clk/64 100clk/256 1 0 1 clk/1024 1 1 0 external pin pb1, rising edge 1 1 1 external pin pb1, falling edge bit 1514131211109 8 $2d ($4d) msb tcnt1h $2c ($4c) lsb tcnt1l 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 31 at76c711 1643c?usb?10/02 the timer/counter1 output compare register b ? ocr1bh and ocr1bl this timer/counter output compare register b consists of 16 bits and is made by two 8-bit r/w registers with initial value of zero, namely ocr1bh and ocr1bl. full 16-bit write and read operations are made according to the way specified for the timer/counter1 (tcnt1) above. the timer/counter1 input capture register ? icr1h and icr1l this timer/counter output compare register consists of 16 bits and is made by two 8-bit r/w registers with initial value of zero, namely icr1h and icr1l. full 16-bit write and read operations are made according to the way specified for the timer/counter1 (tcnt1) above. the watchdog timer control register ? wdtcr this is an 8-bit r/w register with zero initial value. bits7..5?reservedbits always read as zero. bit 4 ? wdtoe: watchdog turn off enable this bit must be set when the wde bit is cleared. otherwise, the watchdog will not be disabled. once set, usb hardware will clear this bit to zero after four clock cycles. bit 1514131211109 8 $29 ($49) msb ocr1bh $28 ($48) lsb ocr1bl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 00000000 bit 1514131211109 8 $27 ($47) msb icr1h $26 ($46) lsb icr1l 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 00000000 bit 76543210 $21 ($41) ???wdtoewdewdp2wdp1wdp0wdtcr read/write rrrr/wr/wr/wr/wr/w initialvalue00000000 32 at76c711 1643c?usb?10/02 bit 3 ? wde: watchdog enable when this bit is set, the watchdog timer is enabled; when it is zero, the watchdog timer is disabled. wde can only be cleared when the wdtoe is set. to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logic ?1? to wdtoe and wde. a logic ?1? must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logic ?0? to wde. this disables the watchdog. bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1 and 0 these bits determine the watchdog timer prescaling when the watchdog timer is enabled according to the following table. the irdamod register bits7..3?reservedbits always read as zero. bit2?pol inverts the polarity of p_irx data input to irda encoder. bit1?mode when this bit is set, serial data to and from irda codec are modulated according to a 4/16 pulse scheme. otherwise, a logic ?0? is denoted by a positive pulse, which remains high for 3 pulses of the 16x baud clock while a logic ?1? is denoted by a low-level signal for 16 pulses of the 16x baud clock. bit1?en when reset, irda codec is bypassed. ta ble 8. watchdog timer prescale register select wdp2 wdp1 wdp0 timeout period (cycles) 0 0 0 16k 0 0 1 32k 0 1 0 64k 0 1 1 128k 1 0 0 256k 1 0 1 512k 1 1 0 1024k 1 1 1 2084k bit 765432 1 0 $20 ($40) pol mode en irdamod read/write r/w r/w r/w initialvalue000000 0 0 33 at76c711 1643c?usb?10/02 i/o ports port a port a is an 8-bit bi-directional i/o port with internal pull-up resistors. the port a data register ? porta the value of any portax bit is the voltage level to the corresponding pad of porta, when the ddrax bit is high; x = 0..7 the port a data direction register ? ddra the port a data direction register controls the direction of the port a pins. when bit ddrax is set, then pax pin is output; when ddrax is cleared, pax is input; x=0..7. the port a input pins address ? pina the port a input pins address (pina) is not a physical register. instead, this address enables access to the physical voltage value on each port pin. it is a read-only address. on power up, porta is an input port and a read of pina register returns an all-1 value due to the pull-up resistors of the porta. port b port b is an 8-bit bi-directional i/o port with internal pull-ups. the port b data register ? portb the value of any portbx bit is the voltage level to the corresponding pad of portb, when the ddrbx bit is high; x = 0..7 the port b data direction register ? ddrb bit 76543210 $1b ($3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $1a ($3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $19 ($39) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue11111111 bit 76543210 $18 ($38) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $17 ($37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 34 at76c711 1643c?usb?10/02 the port b data direction register controls the direction of the port b pins. when bit ddrbx is set, then pbx pin is output; when ddrbx is cleared, pbx is input; x=0..7. the port b input pins address ? pinb the port b input pins address (pinb) is not a physical register. this address enables access to the physical voltage value on each port pin. it is a read-only address. on power up, porta is an input port and a read of pina register returns an all-1 value due to the pull-up resistors of the porta. port b, besides its use as a general-purpose i/o port, is used to support alternate func- tions. specifically, the spi interface, the input capture pin for timer/counter1 and the external clocks for the timer/counters are implemented through port b, according to the following table. port c port c is a 4-bit output port. the port c data register ? portc the value of any portcx bit controls directly the voltage level of pcx; x = 0..4 clock control register ? clk_cntr this is a 5-bit r/w register that is used for controlling the clocks of the peripheral com- ponents and the speed of the mcu. bit 76543210 $16 ($36) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value high-z high-z high-z high-z high-z high-z high-z high-z ta ble 9. port b pins alternate functions port pin alternate functions pb0 external clock pin for timer/counter0 pb1 external clock pin for timer/counter1 pb2 input capture pin for timer/counter1 pb4 ss (spi slave select input) pb5 mosi (spi bus master output/slave input) pb6 miso (spi bus master input/slave output) pb7 sck (spi bus serial clock) bit 76543 2 1 0 $15 ($35) ????portc3portc2portc1portc0portc read/write r rrrr/wr/wr/wr/w initialvalue00000 0 0 0 bit 7654 3210 $14 ($34) uosc uck irck clk_cntr read/write rrrr/wr/wr/wr/wr/w initialvalue0000 0000 35 at76c711 1643c?usb?10/02 bits7..5?reserved always read as zero. bit4?uosc enables uart oscillator when set. bit3?uck select clock source for uart0 module. when cleared, the 16x (baud rate) clock input of the uart0 is the gobbling clock generated from the 24 mhz clock after divided by 13/8 as shown in figure 6. all standard uart rates up to 921k baud can be supported. when this bit is set, the uart0 16x (baud rate) clock frequency is that of the uosc pro- vided that uosc bit is also set. bit2?irck select clock source for uart1 - irda module. when cleared, the 16x (baud rate) clock input of the uart1 is 19.2 mhz derived from the division of 96 mhz by 5, as shown in figure 6. when this bit is set, the uart1 16x (baud rate) clock frequency is that of the uosc pro- vided that uosc bit is also set. bits 1, 0 ? reserved these bits should be set to zero. peripheral enable control register ? periphen a 6-bit r/w register that enables the peripheral components of the system, such as spi, uart and usb. bits7,6?reservedbits always read as zero. bits 5..3 ? reserved bits bit2?irda when set, enables the function of irda. bit1?uart when set, enables the function of uart. bit0?usb when set, enables the function of usb (clock enable). bit 76543210 $13 ($33) irda uart usb periphen read/write r r r/w r/w r/w r/w r/w r/w initialvalue00000000 36 at76c711 1643c?usb?10/02 port d port d is an 8-bit bi-directional i/o port. note that the portd pins 7 and 6 have internal pull down resistors while the rest have internal pull-ups. the port d data register ? portd the value of any portdx bit is the voltage level to the corresponding pad of portd, when the ddrdx bit is high; x = 0..7. the port d data direction register ? ddrd the port d data direction register controls the direction of the port d pins. when bit ddrdx is set, then pdx pin is output; when ddrdx is cleared, pdx is input; x = 0..7.? the port d input pins address ? pind the port d input pins address (pind) is not a physical register. instead, this address enables access to the physical voltage value on each port pin. it is a read-only address. on power up, portd is an input port and a read of pind register returns an all-1 value for pind 5 - 0 due to the pull-up resistors of the those pins and zero for pind6, pind7 due to their pull down resistors. the spi control register ? spcr an 8-bit r/w register with zero initial value. bit 76543210 $12 ($32) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $11 ($31) ddd7 ddd6 ddd5 dddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 table 10. port d pins alternate functions port pin alternate functions pd0 uart receive input pd1 uart transmit output pd6 external interrupt input0 pd7 external interrupt input1 bit 76543210 $10 ($39) pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00111111 bit 76543210 $0d ($2d) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 37 at76c711 1643c?usb?10/02 bit 7 ? spie: spi interrupt enable this bit causes setting of the spif bit in the spsr register to execute the spi interrupt provided that global interrupts are enabled. bit 6 ? spe: spi enable when it is set, the spi is enabled and ss, mosi, miso and sck are connected to pins pb4, pb5, pb6 and pb7. bit 5 ? dord: data order when it is ?1?, the lsb of the data word is transmitted first. when it is cleared, the msb of the data word is transmitted first. bit 4 ? mstr: master/slave select this bit selects master spi when set and slave spi mode when cleared. if ss is config- ured as input and is driven low while mstr is set, mstr will be cleared and spif in spsr will become set. the user will then have to set mstr to re-enable spi master mode. bit3?cpol:clockpolarity when this bit is set, sck is high when idle. when cpol is cleared, sck is low when idle. bit 2 ? cpha: clock phase when set, the data is valid in the falling edge of sck if cpol = 0, or in the rising edge of sck when cpol = 1. when cleared, data are valid in the rising edge of sck if cpol = 0 and in the falling edge of sck if cpol = 1. bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between the slave and the oscillator clock frequency ( ) is shown in the following table.. the spi status register ? spsr this is an 8-bit read register with zero initial value. bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif bit is set and an interrupt is generated if spie in spcr is set and global interrupts are enabled. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then by accessing the spi data register. table 11. relationship between sck and the oscillator frequency spr1 spr0 scg frequency 00 /4 01 /16 10 /64 11 /128 bit 76543210 $0e ($2e) spifwcol??????spsr read/write r r r r rrrr initialvalue00000000 f cl f cl f cl f cl f cl 38 at76c711 1643c?usb?10/02 bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. during data transfer, the result of reading the spdr may be incorrect, and writing to it willhavenoeffect.thewcolbit(andthespifbit)areclearedbyfirstreadingthespi status register with wcol set, and then by accessing the spi data register. bits5..0?reserved always read as zero. the spi data register an 8-bit r/w register with zero initial value. it is used for data transfer between the reg- ister file and the spi shift register. writing to the register initiates data transmission. reading the register causes the shift register receive buffer to be read. bit 76543210 $0f ($2f) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 39 at76c711 1643c?usb?10/02 data memory peripherals ? register description uart register set there are two sets of the following registers one for each uart. for uart0, the base address for those registers is 2020/hex while for uart1 the base address is 2050/hex. in table 12, the register file and its fields are briefly presented. a more detailed description is provided in the following sections. note: 1. this register is not available for uart1 and should not be written. table 1 2. uart register file and register fields offset addr. a[3:0] register [default] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit0 0000us_rhrxxxxxxxx 0000us_thrxxxxxxxx 0001 us_ier transmitter empty interrupt receive timeout interrupt line error interrupt receive break interrupt tr a n s m i t holding register receive holding register 0010 us_fcr (1) rcvr trigger (msb) rcvr tri gg er (lsb) 00 dma mode select 0 rcvr fifo reset fifo enable 0011 us_pmr character length (msb) character length (lsb) number of stop bits (msb) number of stop bits (lsb) parity mode (ptm2) parity mode (ptm1) parity type (pt) 0 0100 us_mr channel mode (chm1) channel mode (chm0) 000000 0101 us_csr transmitter empty receive timeout parity error framing error overrun error receive break tr a n s m i t holding register ready receive holding register ready 0110 us_cr rx enable reset status bit tx enable restart timeout tx reset rx reset stop break start break 0111 us_bl msb lsb 1000 us_bm msb lsb 1001 us_rto msb lsb 1010 us_ttg msb lsb 40 at76c711 1643c?usb?10/02 receive holding register ? us_rhr transmit holding register ? us_thr interrupt enable register ? us_ier bit 7 ? transmitter empty interrupt when set, the interrupt is enabled. when both the transmit holding register (us_thr) and the transmit shift register are empty and the i-bit in the status register (sreg) of the mcu is set, an interrupt will occur. bit 6 ? receive timeout interrupt when set, the timeout interrupt is enabled. when the timeout period for the receiver has passed and the i-bit in the status register (sreg) of the mcu is set, an interrupt will occur. bit 5 ? reserved bit 4 ? reserved bit3?lineerrorinterrupt this bit, when set, enables the line error interrupt. if the i-bit in the status register (sreg) of the mcu is set, an interrupt will occur at a line error. bit 2 ? receive break interrupt when set, enables receive break interrupt. if a receive break condition is detected and both this and the i-bit of sreg of the mcu is set, an interrupt will occur. bit 1 ? transmit holding register interrupt when set, indicates that the transmit ready interrupt is enabled. when the contents of the transmit holding register are transferred to the transmit shift register and both this and the i-bit of sreg of the mcu are set, an interrupt occurs. bit 0 ? receive holding register interrupt when set, indicates that the receive holding register interrupt is enabled. if the data loaded in the receive holding register (us_rhr) are not read or the trigger level has been reached, an interrupt occurs if this bit and the i-bit of the sreg of the mcu are set. bit 76543210 $0 msb lsb us_rhr read/write w w w w w w w w initialvalue00000000 bit 76543210 $0 msb lsb us_thr read/write r r r r r r r r initialvalue00000000 bit 76543210 $1 txei rxtoi res res rlei rbri thri rhri us_ier read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 41 at76c711 1643c?usb?10/02 fifo control register ? us_fcr bits 7, 6 ? rcvr trigger bits these bits indicate the minimum number of bytes required in the receive fifo to gener- ate a receive ready interrupt. the trigger level is shown in the following table. bit 5 ? reserved bit 4 ? reserved bit 3 ? dma mode select whenset,thedmaisinburstmodeaccordingtothevalueinus_fcr.whenitis cleared, the characters are read one byte each time. bit 2 ? reserved bit 1 ? fifo reset when set, resets the receive fifo. bit 0 ? fifo enable when set, enables the 16-byte receive fifo. protocol mode register ? us_pmr bits 7, 6 ? character length these bits determine the character length, according to the following table. bit 76543210 $2 rcvr1 rcvr0 res res rdma res frs fen us_fcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 7 bit 6 trigger level 001 014 108 1114 bit 76543210 $3 chl1 chl0 sbn1 sbn0 pm1 pm0 res lsb us_pmr read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 7 bit 6 character length 005 016 107 42 at76c711 1643c?usb?10/02 bits 5, 4 ? number of stop bits these bits determine the number of stop bits, according to the following table. bits3-1?paritymode these bits determine the parity mode, according to the following table. bit 0 ? reserved mode register ? us_mr bits 7, 6 ? channel mode these bits determine the channel mode, according to the following table. bit 5 bit 4 number of stop bits 001 011.5 102 11reserved bit3 bit2 bit1 paritymode 000evenparity 001oddparity 010 space 011 mark 1xx noparity bit 76543210 $4 chm1 chm0 res res res res res res us_mr read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 7 bit 6 channel mode 0 0 normal mode 0 1 automatic echo mode 1 0 local loopback mode 1 1 remote loopback mode 43 at76c711 1643c?usb?10/02 bit 5 ? reserved control status register- us_cr bit7?transmitterempty when set, indicates that both the transmit holding register (us_thr) and transmit shift register are empty. bit 6 ? receive timeout when set, indicates that a receive timeout condition has occurred. bit5?parityerror when set, indicates that a parity error has occurred. bit4?framingerror when set, indicates that a framing error has occurred (start or stop bits have been received with errors). bit 3 ? overrun error when set, indicates that an overrun error has occurred. this means that the receive holding register is being written with a new value, while the previous one has not been read. bit 2 ? receive break when set, indicates that a break condition has occurred during reception. bit 1 ? transmit holding register ready when set, indicates that the contents of the transmit holding register have been trans- ferred to the transmit shift register. bit 0 ? receive holding register ready when set, indicates that the receive holding register is full. control register ? us_cr bit7?rxenable when set, enables the receiver block of uart. bit 6 ? reset line error status bit when set, resets the pe, fe, oe bits of us_csr. bit5?txenable when set, enables the transmitter block of uart. bit 4 ? restart timeout when set, resets the timeout counter for a new timeout period. bit 76543210 $5 txe rxto pe fe oe rbr thr rhr us_csr read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $6 rxen rles txen rsto txrs rxrs spb stb us_cr read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 44 at76c711 1643c?usb?10/02 bit3?txreset when set, resets the transmit logic. bit 2 ? rx reset when set, resets the receive logic. bit1?stopbreak break command to the transmit logic. when set, stops break condition. bit0?startbreak break command to the transmit logic. when set, starts break condition. baud rate register, low byte ? us_bl baud rate register, high byte ? us_bm receiver timeout register ? us_rto this register contains the maximum period for which the uart can wait before a char- acter arrives during the timeout function. this function is disabled when this register is zero. the value of register us_rto represents bit periods. transmitter time-guard register ? us_ttg the value of this register indicates the delay (in bit periods) that an active transmitter has to interpose between two consecutive character transmissions. bit 76543210 $7 msb lsb us_bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $8 msb lsb us_bm read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $9 msb lsb us_rto read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 bit 76543210 $a msb lsb us_ttg read/write r/w r/w r/w r/w r/w r/w r/w r/w initialvalue00000000 45 at76c711 1643c?usb?10/02 dma controller register set the base address for the dma register file is 2000/hex. the following sections describe the bits of the registers of the dma controller. txtadl ? transmit dma target address lsbs register address: 0x2001 default state: 0x00 txpll ? lsbs of packet length during direct memory readings register address: 0x2003 default state: 0x00 table 13. baud rate generation example (clock = 14,7456 mhz) output baud rate user divisor (16 clk) ubm value (hex) ubl value (hex) (decimal) (hex) 100 9216 2400 24 00 200 4608 1200 12 00 400 2304 900 09 00 600 1536 600 06 00 1200 768 300 03 00 2400 384 180 01 80 4800 192 c0 00 c0 9600 96 60 00 60 19200 48 30 00 30 38400 24 18 00 18 57.6k 16 10 00 10 76.81 12 0c 00 0c 153.6k 6 06 00 06 307.2k 3 03 00 03 460.8k 2 02 00 02 921.6k 1 01 00 01 bit mnemonic description 7 txdmaen transmit dma enable 6-4 reserved 3 - 0 txtad[11:8] most significant bits of the 12-bit transmit dma target address bit mnemonic description 7 - 0 txpl[7:0] least significant bits of the 11-bit transmit packet length field 46 at76c711 1643c?usb?10/02 txplm ? msbs of packet length during direct memory readings register address: 0x2004 default state: 0x00 txtpll ? lsbs of the number of bytes transmitted during the last transmit dma register address: 0x2005 default state: 0x00 txtplm ? msbs of the number of bytes transmitted during the last transmit dma and transmit status information register address: 0x2006 default state: 0x00 rxtadl ? received dma target address lsbs register address: 0x2007 default state: 0x00 bit mnemonic description 7 - 3 reserved 2 - 0 txpl[10:8] most significant bits of the 11-bit transmit packet length field bit mnemonic description 7 - 0 txtpl[7:0] least significant bits of the number of bytes transmitted during the last transmit dma operation bit mnemonic description 7 - 5 transmit status information (to be defined) 4 tcom dma has normally terminated after transmitting the requested number of bytes. cleared when this register is read. 3 tncom host has ceased a transmit dma before the requested buffer size is transmitted. cleared when this register is read. 2 - 0 txtpl[10:8] most significant bits of the number of bytes transmitted during the last transmit dma operation bit mnemonic description 7 - 0 rxtad[7:0] least significant bits of the 12-bit receive dma target address 47 at76c711 1643c?usb?10/02 rxtadmen ? receive dma target address msbs, dma enable register address: 0x2008 default state: 0x00 rspll ? lsbs of packet length during direct memory writings register address: 0x2009 default state: 0x00 rxplm ? msbs of packet length during direct memory writings register address: 0x200a default state: 0x00 rxtpll ? lsbs of the number of bytes received during the last receive dma register address: 0x200b default state: 0x00 bit mnemonic description 7 rxdamaen receive dma enable 6 - 4 reserved 3 - 0 rxtad[11:8] most significant bits of the 12-bit receive dma target address bit mnemonic description 7 - 0 rxpl[7:0] least significant bits of the 11-bit receive packet length field bit mnemonic description 7-3 reserved 2 - 0 rxpl[10:8] most significant bits of the 11-bit receive packet length field bit mnemonic description 7 - 0 rxtpl[7:0] least significant bits of the number of the received bytes during the last receive dma operation 48 at76c711 1643c?usb?10/02 rxtplm ? msbs of the number of bytes received during the last receive dma and receive status information register address: 0x200c default state: 0x00 intcst ? interrupt control and status register register address: 0x200d default state: 0x00 bit mnemonic description 7 rer at least one error (parity, framing, overrun) occurred during packet reception. cleared when a new receive dma is programmed. 6reserved 5reserved 4 rcom dma has normally terminated after receiving the requested number of bytes. cleared when this register is read. 3 rncom the processor has ceased dma before receiving the expected number of bytes. cleared when this register is read. 2 - 0 rxtpl[10:8] most significant bits of the number of the received bytes during the last receive dma operation bit mnemonic description 7-4 reserved 3 dtxirq this bit indicates that a transmit dma interrupt request is pending. this bit is cleared and the corresponding interrupt is acknowledged when the rxtplm register is read. 2 drxirq this bit indicates that a receive dma interrupt request is pending. this bit is cleared and the corresponding interrupt is acknowledged when the rxtplm register is read. 1 txinte enables transmit dma interrupts 0 rxinte enables receive dma interrupts 49 at76c711 1643c?usb?10/02 usb register set the usb appears to the avr just like another peripheral. the usb register file is mapped to the sram space. table 14 summarizes the usb cell-specific registers. table 14. usb register set register address default function frm_num_h 0x0fd xxxxx000 frame number high register frm_num_l 0x0fc xxxxx000 frame number low register glb_state 0x0fb xxxxx000 global state register sprsr 0x0fa xxxxx000 suspend/resume register sprsie 0x0f9 xxxxx000 suspend/resume interrupt enable register uisr 0x0f7 00000000 usb interrupt status register uiar 0x0f5 xxxxx000 usb interrupt acknowledge register uier 0x0f3 00000000 usb interrupt enable register for all eps faddr 0x0f2 00000000 function address register endppgpg 0x0f1 00000000 function endpoint ping-pong register ecr0 0x0ef 0xxx0000 endpoint0 control register ecr1 0x0ee 0xxx0000 endpoint1 control register ecr2 0x0ec 0xxx0000 endpoint2 control register ecr3 0x0ec 0xxx0000 endpoint3 control register ecr4 0x0eb 0xxx0000 endpoint4 control register ecr5 0x0ea 0xxx0000 endpoint5 control register ecr6 0x0e9 0xxx0000 endpoint6 control register csr0 0x0df x1110000 endpoint0 control and status register csr1 0x0de x1110000 endpoint1 control and status register csr2 0x0dd x1110000 endpoint2 control and status register csr3 0x0dc x1110000 endpoint3 control and status register csr4 0x0db x1110000 endpoint4 control and status register csr5 0x0da x1110000 endpoint5 control and status register csr6 0x0d9 x1110000 endpoint6 control and status register fdr0 0x0cf 00000000 fifo 0 data register fdr1 0x0ce 00000000 fifo 1 data register fdr2 0x0cd 00000000 fifo 2 data register fdr3 0x0cc 00000000 fifo 3 data register fdr4 0x0cb 00000000 fifo 4 data register fdr5 0x0ca 00000000 fifo 5 data register fdr6 0x0c9 00000000 fifo 6 data register fbyte_cnt0_l 0x0bf 00000000 byte count fifo 0 register [7:0] fbyte_cnt1_l 0x0be 00000000 byte count fifo 1 register [7:0] 50 at76c711 1643c?usb?10/02 fbyte_cnt2_l 0x0bd 00000000 byte count fifo 2 register [7:0] fbyte_cnt3_l 0x0bc 00000000 byte count fifo 3 register [7:0] fbyte_cnt4_l 0x0bb 00000000 byte count fifo 4 register [7:0] fbyte_cnt5_l 0x0ba 00000000 byte count fifo 5 register [7:0] fbyte_cnt6_l 0x0b9 00000000 byte count fifo 6 register [7:0] fbyte_cnt0_h 0x0af 00000000 byte count fifo 0 register [10:8] fbyte_cnt1_h 0x0ae 00000000 byte count fifo 1 register [10:8] fbyte_cnt2_h 0x0ad 00000000 byte count fifo 2 register [10:8] fbyte_cnt3_h 0x0ac 00000000 byte count fifo 3 register [10:8] fbyte_cnt4_h 0x0ab 00000000 byte count fifo 4 register [10:8] fbyte_cnt5_h 0x0aa 00000000 byte count fifo 5 register [10:8] fbyte_cnt6_h 0x0a9 00000000 byte count fifo 6 register [10:8] usb_slp_en 0x100 00000000 sleep mode control usb_irq_en 0x101 00000000 master interrupt enable usb_irq_stat 0x102 00000000 master interrupt status usb_bus_stat 0x103 00000000 usb bus reset condition pa_en 0x104 00000000 pair addressing enable usb_dma_adl 0x105 00000000 dma address lo usb_dma_adh 0x106 00000000 dma address hi usb_dma_plr 0x107 00000000 dma packet length requested usb_dma_ead 0x108 00000000 dma target endpoint address usb_dma_tpl 0x109 00000000 dma transferred packet length usb_dma_en 0x10a 00000000 dma enable table 14. usb register set (continued) register address default function 51 at76c711 1643c?usb?10/02 usb_dma_en: enable register for the tx or rx dma between the dprma and the usb register address: 0x10a default state: 0x00 usb_dma_tpl: usb dma transferred packet length. register address: 0x109 default state: 0x00 usb_dma_ead: usb dma endpoint. register address: 0x108 default state: 0x00 usb_dma_plr: usb dma packet length register register address: 0x107 default state: 0x00 bit field avr description 7 - 2 reserved reserved and set to 0 1 usb_rdma_en w/r enables receive dma (for out eps). this bit is automatically cleared after the end of the dma. 0 usb_tdma_en w/r enables transmit dma (for in eps). this bit is automatically cleared after the end of the dma. bit field avr description 7 - 0 tpl[7:0] r returns the number of bytes transferred during the last dma bit field avr description 7 - 0 fdra[7:0] w/r the avr writes the offset byte of fdrx address, depending on the endpoint that is going to send or has received data: the following endpoints with the corresponding offset bytes are supported by the dma channels: fdr1- 0xce fdr2- 0xcd fdr3- 0xcc fdr4- 0xcb fdr5- 0xca fdr6- 0xc9 bit field avr description 7 - 0 plr[7:0] w/r the avr writes the number of bytes for the dma that follows. 52 at76c711 1643c?usb?10/02 usb_dma_adh: usb dma dpram address high order bits register address: 0x106 default state: 0x00 usb_dma_adl: usb dma dpram address low order byte register address: 0x105 default state: 0x00 note: 1. the 10 bit value formed by the previous two registers point at any location into the dpram from 0 to 2048. in order to access the same position from the avr, the base address of the dpram (0x3000) should be added to the above location pa_en: usb pair addressing enable register address: 0x104 default state: 0x00 usb_bus_stat: usb bus state register address: 0x103 default state: 0x00 bit field avr description 7 - 3 reserved 2 - 0 uda[10:8] w/r these three bits along with the eight bits of the usb_dma_adl forms the target address at the dpram that the dma channel will use bit field avr description 7 - 0 uda[7:0] w/r the least significant byte of the target address at the dpram that the dma channel will use (1) bit field avr description 7 - 4 reserved 3 - 1 upa[3:1] w/r the endpoints ep1-ep6 use the usb physical addresses 1-7 respectively. by setting any of the these bits a pair of eps, consisting of one in and one out ep, is formed as follows: upa[1]: ep4 has the same usb physical address with ep1 upa[2]: ep5 has the same usb physical address with ep2 upa[3]: ep6 has the same usb physical address with ep3 bit field avr description 7-4, 2-0 reserved 3 usb_bus_res r this bit is set when the usb bus is in reset state 53 at76c711 1643c?usb?10/02 usb_irq_stat: usb irq status bits register address: 0x102 default state: 0x00 usb_irq_en: usb irq enable bits register address: 0x101 default state: 0x00 usb_slp_en: usb sleep mode enable register address: 0x100 default state: 0x00 frm_num_h: frame number high register register address: 0x0fd default state: 0x00 bit field avr description 7, 5-0 reserved 6 usb_ep_irq r/w this bit is set when an interrupt from the eps 6-0 is produced. the register is cleared by writing 0x0 bit field avr description 7 usb_res_ien w/r when this bit is set, it enables the interrupt due to a usb bus reset condition 6 usb_gint_en w/r usb global interrupt enable: when this bit is set, enables the interrupts for the all usb eps provided that the corresponding bits of the uier register have been set. 5-0 reserved bit field avr description 7-6, 4- 0 reserved 5 usb_slp_mod w/r this bit is set to put the device into sleep mode when a suspend condition is detected bit field avr description 7 - 3 reserved reserved and set to 0 2 - 0 fch[10:8] r these are the upper 3 bits of the 11-bit frame number of sof packet. 54 at76c711 1643c?usb?10/02 frm_num_l: frame number low register register address: 0x0fc default state: 0x00 global state register register address: 0x0fb default state: 0000000000b bit field avr description 7 - 0 fcl[7:0] r these are the lower 8 bits of the 11-bit frame number of sof packet. bit field avr description 4 - 7 reserved reserved 3 rsminpr r set by usb hardware when a resume is sent in the usb bus during remote wake-up feature (13 ms). 2 rmwupe w/r remote wake-up enable. this bit is set if the host enables the function?s remote wake-up feature. 1 confg w/r configured. this bit is set by the firmware after a valid set_configuration request is received. it is cleared by a reset or by a set_configuration with a value of 0. 0fadd enable w/r function address enable. this bit is set by firmware after the status phase of a set_address request transaction. the host will use the new address, starting at the next transaction. 55 at76c711 1643c?usb?10/02 sprsr: suspend/resume register register address: 0x0fa default state: xxxxx000b sprsie: suspend/resume interrupt enable register register address: 0x0f9 default state: xxxxx000b bit field avr description 7 reserved 6 reserved 5 reserved 4 reserved 3 sof int r start of frame (sof) interrupt. a write on this bit clears the sof interrupt 2 ext rsm r received external resume. the usb hardware sets this bit to denote an external resume interrupt. if rmwupe = 1, a resume signal is sent in usb bus. 1 rcvd rsm r received resume. the usb hardware sets this bit when a usb resume signaling is detected at its port. 0 susp r suspend. the usb hardware sets this bit when it detects no sof for 3 ms. the usb macro enters in suspend mode, the processor has to go in sleep mode. bit field avr description 7reserved 6reserved 5reserved 4reserved 3 sof ie w/r enable sof interrupt 2 extrsm ie w/r enable external resume signaling interrupt: 1 = enable, 0 = disable 1 rcvdrsm ie w/r enable bus resume signaling interrupt: 1 = enable, 0 = disable 0 susp ie w/r enable suspend signaling interrupt: 1 = enable, 0 = disable 56 at76c711 1643c?usb?10/02 uisr ? usb interrupt status register register address: 0x0f7 default state: 0x00 the function interrupt bits will be set by the usb hardware whenever the following bits in the corresponding endpoint?s control and status registers are modified by the usb hardware: 1. rx out packet is set (control and out endpoints) 2. tx packet ready is cleared (control and in endpoints) 3. rx setup is set (control endpoints only) 4. tx complete is set (control endpoints only) uiar ? usb interrupt acknowledge register the bits in this register are used to indirectly clear the bits of the uisr. a bit in the uisr is cleared if a ?1? is written in the corresponding bit of uiar. register address: 0x0f5 default state: 0x00 bit field avr description 7 reserved 6 ep6 int r/ endpoint 6interrupt 5 ep5 int r endpoint 5 interruptt 4 ep4 int r endpoint 4 interrupt 3 ep3 int r endpoint 3 interrupt 2 ep2 int r endpoint 2 interrupt 1 ep1 int r/ endpoint 1 interrupt 0 ep0 int r/\ endpoint 0 interrupt bit field avr description 7 reserved 6 ep6 inta w endpoint 6 interrupt acknowledge 5 ep5 inta w endpoint 5 interrupt acknowledge 4 ep4 inta w endpoint 4 interrupt acknowledge 3 ep3 inta w endpoint 3 interrupt acknowledge 2 ep2 inta w endpoint 2 interrupt acknowledge 1 ep1 inta w endpoint 1 interrupt acknowledge 0 ep0 inta w endpoint 0 interrupt acknowledge 57 at76c711 1643c?usb?10/02 uier ? usb interrupt enable register register address: 0x0f3 default state: 0x00 the bits in this register have the following meaning: 1 = enable interrupt 0 = disable interrupt function address register the fiu contains an address register that contains the function address assigned by the host. this function address register must be programmed by the processor once it has received a set_address command from the host and has completed the status phase of the transaction. after power up or reset, this register will contain the value of 0x00. the function enable bit (fen) allows the firmware to enable or disable the function end- points. the firmware will set this bit after receipt of a reset through the usb hardware. once this bit is set, the usb hardware passes packets to and from the host. register address: 0x0f2 default state: 0x00 bit field avr description 7 sof ie r/w enable sof interrupt 6 ep6 ie r/w enable endpoint 6 interrupt 5 ep5 ie r/w enable endpoint 5 interrupt 4 ep4 ie r/w enable endpoint 4 interrupt 3 ep3 ie r/w enable endpoint 3 interrupt 2 ep2 ie r/w enable endpoint 2 interrupt 1 ep1 ie r/w enable endpoint 1 interrupt 0 ep0 ie r/w enable endpoint 0 interrupt bit field avr description 7 fen w/r function enable 6 - 0 fadd[6:0] w/r function address 58 at76c711 1643c?usb?10/02 endppgpg: endpoint ping-pong enable register register address: 0x0f2 default state: 0x00 endpoint control register register address: 0x0ef, endp0_cntr endpoint0 0x0ee, endp1_cntr endpoint1 0x0ed, endp2_cntr endpoint2 0x0ec, endp3_cntr endpoint3 0x0eb, endp4_cntr endpoint4 0x0ea, endp5_cntr endpoint5 0x0e9, endp6_cntr endpoint6 default state: 0x000000b bit field avr description 7 reserved 6 pg pg 6 en w enable endpoint 6 ping-pong 5 pg pg 5 en w enable endpoint 5 ping-pong 4 pg pg 4 en w enable endpoint 4 ping-pong 3 pg pg 3 en w enable endpoint 3 ping-pong 2 pg pg 2 en w enable endpoint 2 ping-pong 1 pg pg 1 en w enable endpoint 1 ping-pong 0 pg pg 0 en w enable endpoint 0 ping-pong bit field avr description 7 epeds w/r endpoint enable/disable (0 = disable endpoint, 1 = enable endpoint) 6 reserved reserved 4 - 5 reserved reserved and set to 0 3 dtgle r data toggle. identifies data0 or data1 packets. 2 epdir w/r endpoint direction. only applicable for non-control endpoints (0=out,1=in). 1 - 0 eptype w/r endpoint type. these bits represent the type of the endpoint as follows: bit1 bit0 type 0 0 control 0 1 isochronous 10 bulk 1 1 interrupt 59 at76c711 1643c?usb?10/02 endpoint control and status register register address: 0x0df, fcsr0 endpoint0 0x0de, fcsr1 endpoint1 0x0dd, fcsr2 endpoint2 0x0dc, fcsr3 endpoint3 0x0db, fcsr4 endpoint4 0x0da, fcsr5 endpoint5 0x0d9, fcsr6 endpoint6 default state: 00000000b bit field avr description 7control direction w/r set by the processor to indicate to the usb hardware the direction of a control transfer. 0 = control write (no data stage) 1 = control read this bit is used by control endpoints only. 6 data end w/r indicate that the processor has placed the last data packet in fifo0, or that the processor has processed the last data packet it expects from the host. 5 force stall w/r set by the processor to indicate a stalled endpoint. the usb hardware will send a stall handshake as a response to the next in or out token. 4 tx packet ready w/r indicates that the processor has loaded the fifo with a packet of data. this bit is cleared by usb hardware after the usb host acknowledges the packet. for iso endpoints, this bit is cleared unconditionally after the data is sent. 3 stall snd r/c the usb hardware sets this bit after a stall is sent to the host. indicates end of data stage for the control endpoint only. 2 rx setup r/c the usb hardware sets this bit when it receives a valid setup packet from the host. this bit is used by control endpoints only. 1rxout packet r/c indicates that the usb hardware has decoded an out token and that the data is in the fifo. 0tx complete w/r the usb hardware sets this bit to indicate to a control endpoint that it has received an ack handshake from the host. 60 at76c711 1643c?usb?10/02 control direction this bit is used by control endpoints only and is used by firware to indicate the direction of a control transfer. it is written by the firware after it receives a rx setup interrupt. the usb hardware uses this bit to determine the status phase of a control transfer. dataend this bit is used only by control endpoints together with bit 1 (tx packet ready) to signal the usb hardware to go to the status phase after the packet currently residing in the fifo is transmitted. after the usb hardware completes the status phase, it will interrupt the processor without clearing this bit. caution: since the data end bit signals ?end of transaction?, any other endpoint controller bit set after the data end is not considered by the ping-pong controller. that is why tx_packet ready should be set before data_end. force stall the processor sets this bit if it wants to force a stall if an unsupported request is received or if the host continues to ask for data after the data is exhausted. this bit should be set at the end of any data phase or setup phase. stallsnd the usb hardware sets this bit after a stall has been sent. the firmware uses this bit when responding to a usb getstatus request. tx packet ready this bit is used for the following operations: 1. control read transactions by a control endpoint 2. in transactions with data1 pid to complete the status phase for a control end- point, when this bit is ?0?, but bit data end (bit 4) is ?1? 3. by a bulk in or iso in or int in endpoint the processor should write into the fifo only if this bit is cleared. after it has completed writing the data, it should set this bit. the data can be of zero length. for a control end- point, the processor should write to the fifo only while bit 6 (tx packet requested) is set. the usb hardware clears this bit after it receives an ack. if the interrupt is enabled, clearing this bit by the usb hardware causes an interrupt to the processor. rxsetup this bit is used by control endpoints only to signal to the processor that the usb hard- ware has received a valid setup packet and that the data portion of the packet is stored in the fifo. the usb hardware will clear all other bits in this register and will set rx setup. if the corresponding interrupt is enabled, the processor will be interrupted when rx setup is set. after the completion of reading the data from the fifo, the firm- ware should clear this bit. 61 at76c711 1643c?usb?10/02 rxoutpacket the usb hardware sets this bit after it has stored the data of an out transaction in the fifo. while this bit is set, the usb hardware will nak all out tokens. for control end- points only, bit 7 of this register, enable control write, has to be set for the usb hardware to accept the out data. the usb hardware will not overwrite the data in the fifo except for an early usb setup request. bit rx out packet is used for the follow- ing operations: 1. control write transactions by a control endpoint. 2. out transaction with data1 pid to complete the status phase of a control endpoint. 3. by a bulk out or iso out or int out endpoint. setting this bit causes an interrupt to the processor if the interrupt is enabled. the firm- ware clears this bit after the fifo are read. txcomplete this bit is used by usb hardware in a control endpoint to signal to the processor that it has successfully completed certain transactions. tx complete is set at the completion of a: 1. control read data stage 2. status stage without data stage 3. status stage after a control write transaction fifo data registers these are dual function buffer registers. received data are read by the processor from the endpoint's fifo through these data registers. in the transmit mode, the processor writes to the fifo through this register. register address: 0x0cf, fdr0 function endpoint0 0x0ce, fdr1 function endpoint1 0x0cd, fdr2 function endpoint2 0x0cc, fdr3 function endpoint3 0x0cb, fdr4 function endpoint4 0x0ca, fdr5 function endpoint5 0x0c9, fdr6 function endpoint6 default state: 00000000b bit field avr description 7-0 fifo data[7:0] w/r data to be written to fifo or data to be read from the fifo 62 at76c711 1643c?usb?10/02 byte count registers each endpoint has a register that stores the number of bytes received by the usb hardware. register address: 0x0bf, fbyte_cnt0_l endpoint0 0x0be, fbyte_cnt1_l endpoint1 0x0bd, fbyte_cnt2_l endpoint2 0x0bc, fbyte_cnt3_l endpoint3 0x0bb, fbyte_cnt4_l endpoint4 0x0ba, fbyte_cnt5_l endpoint5 0x0b9, fbyte_cnt6_l endpoint6 0x0af, fbyte_cnt0_h endpoint0 0x0ae, fbyte_cnt1_h endpoint1 0x0ad, fbyte_cnt2_h endpoint2 0x0ac, fbyte_cnt3_h endpoint3 0x0ab, fbyte_cnt4_h endpoin4 0x0aa, fbyte_cnt5_h endpoint5 0x0a9, fbyte_cnt6_h endpoint6 default state: 00000000b fbyte_cnt_l bit field avr description 7 - 0 bytct[7:0] r length of data packet in fifo fbyte_cnt_h bit field avr description 7 - 3 reserved reserved reserved 2 - 0 bytct[10:8] r length of data packet in fifo 2 - 0 endsz[10:8] r endpoint size [10:8] 63 at76c711 1643c?usb?10/02 electrical characteristics dc characteristics the values shown in this table are valid for ta = 0 cto85 c, v cc = 3.3v unless otherwise noted. note: 1. osc2 must not be used to drive other circuitry. absolute maximum ratings* operating temperature ......................................................tbd *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................................tbd voltage on any pin with respect to ground ........................................ 3.0v to 3.6v maximum operating voltage ............................................ 3.7v dc output current...................................................... 16.0 ma power supply symbol parameter condition min max unit v cc power supply 3.3 v i cc supply current 50.0 ma i ccs suspended device current 200.0 a usb signals: dp, dm symbol parameter condition min max unit i lo high-z data line leakage 0v < v in < 3.3v -10.0 +10.0 a v di differential input sensitivity dpx and dmx 0.2 v v cm differential common mode range 0.8 2.5 v v se single-ended receiver threshold 0.8 2.0 v v crs output signal crossover except first transition from idle state 1.3 2.0 v v ol1 static output low rl of 15 k ? to 3.6v 0.3 v v oh1 static output high rl of 15 k ? to gnd oscillator signals: osc1, osc2 symbol parameter condition min max unit v lh osc1 switching level 0.47 1.20 v v hl osc1 switching level 0.67 1.44 v c x1 input capacitance, osc1 9.0 pf c x2 output capacitance, osc2 (1) 9.0 pf c 12 osc1/2 capacitance 1.0 pf t su start-up time 6 mhz, fundamental 2.0 ms 64 at76c711 1643c?usb?10/02 ac characteristics note: 1. with external 27w series resistor. dp, dm driver characteristics symbol parameter condition min max unit t r rise time cl = 50 pf 4.0 20.0 ns t f fall time cl = 50 pf 4.0 20.0 ns t rfm t r /t f matching 90.0 110.0 % v crs output signal crossover except first transition from idle state 1.3 2.0 v z drv (1) driver output resistance steady-state drive 29.0 44.0 w dp,dmdatasourcetimings symbol parameter condition min max unit t drate full-speed data rate average bit rate 11.97 12.03 mbps t frame frame interval 0.9995 1.0005 ms t dj1 source differential driver jitter to next transition for paired transitions -3.5 3.5 ns t dj2 -4.0 4.0 ns t fdeop source jitter for differential transition to se0 transition -2.0 5.0 ns t feopt source se0 interval of eop 160.0 175.0 ns t feopr receiver se0 interval of eop 82.0 ns t jr1 receiver data jitter tolerance to next transition for paired transitions -18.5 18.5 ns t jr2 -9.0 9.0 ns t fst width of se0 interval during differential transition 14.0 ns printed on recycled paper. at m e l ? ,dataflash ? and avr ? are the registered trademarks of atmel. other terms and product names may be the trademarks of others. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 usa tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 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colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 1643c?usb?10/02 xm |
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