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?2001 national semiconductor corporation www.national.com cr16mct9/cr16mct5/cr16hct9/cr16hct5 16-bit reprogrammable/rom microcontroller interrupt control september 2001 cr16mct9/cr16mct5/cr16hct9/cr16hct5 16-bit reprogrammable/rom microcontroller 1.0 general description the cr16mct9/cr16mct5/cr16hct9/cr16hct5 compactrisc? microcontroller are general-purpose 16- bit microcontrollers based on a reduced instruction set computer (risc) architecture. the device operates as a complete microcomputer with all system timing, interrupt logic, flash program memory or rom memory, ram, ee- prom data memory, and i/o ports included on-chip. it is ideally suited to a wide range of embedded controller appli- cations because of its high performance, on-chip integrat- ed features and low power consumption resulting in decreased system cost. the cr16mct9/cr16mct5/cr16hct9/cr16hct5 of- fer the high performance of a risc architecture while re- taining the advantages of a traditional complex instruction set computer (cisc): compact code, on-chip memory and i/o, and reduced cost. the cpu uses a three-stage in- struction pipeline that allows execution of up to one instruc- tion per clock cycle, or up to 24 million instructions per second (mips) at a clock rate of 24 mhz. the cr16mct9/cr16mct5/cr16hct9/cr16hct5 de- vices contain a fullcan class, can serial interface for low/ high speed applications with 15 orthogonal message buff- ers, each supporting standard as well as extended mes- sage identifiers. 96k-byte flash program memory cr16can core bus peripheral bus clock generator slow clk processing unit i/o wire/spi 12-ch fast clk 4k-byte peripheral bus controller bus interface power-on-reset 2176-byte ram eeprom data miwu 2 analog comparators timing and watchdog power manage- ment 2x mft 2x usart cr16b risc core 8-bit a/d access bus 4x vtu memory unit memory fullcan 2.0b 1.5k-byte isp note: not all peripherals shown above will be contained in any device. block diagram
www.national.com 2 table of contents 1.0 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.0 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 cr16b cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.6 multi-input wake-up. . . . . . . . . . . . . . . . . . . . . . . . . 6 3.7 dual clock and reset . . . . . . . . . . . . . . . . . . . . . . . 6 3.8 power management. . . . . . . . . . . . . . . . . . . . . . . . . 6 3.9 multi-function timer . . . . . . . . . . . . . . . . . . . . . . . . 6 3.10 versatile timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.11 real-time timer and watchdog . . . . . . . . . . . . . . 6 3.12 usart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.13 microwire/spi. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.14 cr16can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.15 access.bus interface . . . . . . . . . . . . . . . . . . . . . . 7 3.16 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.17 analog comparators . . . . . . . . . . . . . . . . . . . . . . . . 7 3.18 development support . . . . . . . . . . . . . . . . . . . . . . . 7 4.0 device pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 env0 and env1 pins . . . . . . . . . . . . . . . . . . . . . . 12 5.2 module configuration (mcfg) register . . . . . . . . 12 5.3 module status (mstat) register . . . . . . . . . . . . . 12 6.0 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 open-drain operation . . . . . . . . . . . . . . . . . . . . . . 14 7.0 cpu and core registers . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 general-purpose registers . . . . . . . . . . . . . . . . . . 15 7.2 dedicated address registers . . . . . . . . . . . . . . . . 15 7.3 processor status register . . . . . . . . . . . . . . . . . . . 15 7.4 configuration register . . . . . . . . . . . . . . . . . . . . . . 16 7.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.0 bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 biu control registers . . . . . . . . . . . . . . . . . . . . . . 18 8.3 wait and hold states used . . . . . . . . . . . . . . . . . . 20 9.0 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1 flash eeprom program memory. . . . . . . . . . . . . 22 9.2 ram memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 flash eeprom data memory . . . . . . . . . . . . . . . . 25 9.4 isp memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.0 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.1 interrupt operation. . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2 non-maskable interrupt . . . . . . . . . . . . . . . . . . . . . 32 10.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . 33 10.4 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.5 interrupt programming procedures . . . . . . . . . . . . 34 11.0 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.2 power save mode . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.3 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.4 halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.5 clock inputs and reset configuration . . . . . . . . . . 36 11.6 switching between power modes . . . . . . . . . . . . . 36 12.0 dual clock and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 external crystal network . . . . . . . . . . . . . . . . . . . . 39 12.2 main system clock . . . . . . . . . . . . . . . . . . . . . . . . 40 12.3 slow system clock . . . . . . . . . . . . . . . . . . . . . . . . 40 12.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.5 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.6 dual clock and reset registers . . . . . . . . . . . . . . 41 12.7 slow clock prescaler register (prssc). . . . . . . . 41 12.8 slow clock prescaler 1 register (prssc1) . . . . .41 13.0 multi-input wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 13.1 wake-up edge detection register (wkedg) . . . .42 13.2 wake-up enable register (wkena) . . . . . . . . . . .42 13.3 wake-up interrupt control register 1 (wkctl1) .43 13.4 wake-up interrupt control register 1 (wkctl2) .43 13.5 wake-up pending register (wkpnd) . . . . . . . . . .43 13.6 wake-up pending clear register (wkpcl) . . . . .43 13.7 programming procedures . . . . . . . . . . . . . . . . . . .44 14.0 real-time timer and watchdog . . . . . . . . . . . . . . . . .45 14.1 twm structure . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 14.2 timer t0 operation . . . . . . . . . . . . . . . . . . . . . . . .45 14.3 watchdog operation . . . . . . . . . . . . . . . . . . . . .46 14.4 twm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .46 14.5 watchdog programming procedure . . . . . . . . .48 15.0 multi-function timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 15.1 timer structure. . . . . . . . . . . . . . . . . . . . . . . . . . . .49 15.2 timer operating modes . . . . . . . . . . . . . . . . . . . . .51 15.3 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .54 15.4 timer i/o functions . . . . . . . . . . . . . . . . . . . . . . . .54 15.5 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . .56 16.0 versatile-timer-unit (vtu) . . . . . . . . . . . . . . . . . . . . . . .58 16.1 vtu functional description . . . . . . . . . . . . . . . . . .58 16.2 vtu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 17.0 microwire/spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 17.1 microwire operation . . . . . . . . . . . . . . . . . . . . .65 17.2 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 17.3 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 17.4 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . .68 17.5 microwire interface registers . . . . . . . . . . . . . .68 18.0 usart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 18.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . .71 18.2 usart operation . . . . . . . . . . . . . . . . . . . . . . . . .71 18.3 usart registers . . . . . . . . . . . . . . . . . . . . . . . . . .75 18.4 baud rate calculations . . . . . . . . . . . . . . . . . . . . .77 19.0 access.bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . .78 19.1 acb protocol overview . . . . . . . . . . . . . . . . . . . . .78 19.2 acb functional description . . . . . . . . . . . . . . . . . .79 19.3 acb registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 19.4 usage hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 20.0 cr16can module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 20.1 functional description . . . . . . . . . . . . . . . . . . . . . .85 20.2 basic can concepts . . . . . . . . . . . . . . . . . . . . . . .86 20.3 message transfer . . . . . . . . . . . . . . . . . . . . . . . . .95 20.4 acceptance filtering . . . . . . . . . . . . . . . . . . . . . . . .95 20.5 receive structure . . . . . . . . . . . . . . . . . . . . . . . . . .96 20.6 transmit structure . . . . . . . . . . . . . . . . . . . . . . . . .99 20.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 20.8 time stamp counter . . . . . . . . . . . . . . . . . . . . . .103 20.9 memory organization . . . . . . . . . . . . . . . . . . . . . .103 20.10 system start-up and multi-input wake-up . . . . .113 21.0 analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . . .116 21.1 analog comparator control/status register (cmpctrl) . . . . . . . . . . . . . . . . . . . . . .116 21.2 analog comparator usage. . . . . . . . . . . . . . . . . .116 22.0 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 22.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . .118 22.2 a/d converter registers . . . . . . . . . . . . . . . . . . .119 22.3 a/d converter programming . . . . . . . . . . . . . . . .121 23.0 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 24.0 register layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 24.1 register layout . . . . . . . . . . . . . . . . . . . . . . . . . . .128 25.0 electrical and thermal characteristics . .135 26.0 appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 26.1 8/16-bit microwire/spi (mwspi16) . . . . . . . . . . . .150 26.2 timing and watchdog module . . . . . . . . . . . . . . .150 27.0 device pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 28.0 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 153
3 www.national.com 1.0 general description (continued) the device has up to 96k bytes of reprogrammable flash ee- prom program memory or rom memory, 1.5k bytes of flash eeprom in-system-programming memory, 4k bytes of static ram, 2k bytes of non-volatile eeprom data mem- ory and 128 bytes with high endurance, two usarts, two 16- bit multi-function timers, one spi/microwire-plus? seri- al interface, a 12-channel a/d converter, two analog compar- ators, watchdog? protection mechanism, and up to 56 general-purpose i/o pins. the device operates with a high-frequency crystal as the main clock source and either the prescaled main clock source or with a low frequency (32.768 khz) oscillator in power save mode. the device supports several power save modes which are combined with multi-source interrupt and wake-up capabilities. this device also has a versatile timer unit (vtu) with four timer sub-systems, a can interface, and access.bus syn- chronous serial bus interface. powerful cross-development tools are available from national semiconductor and third party suppliers to support the devel- opment and debugging of application software for the device. these tools let you program the application software in c and are designed to take full advantage of the compactrisc ar- chitecture. in the following text, device is always referred to the family of 16-bit can-enabled compactrisc microtroller. 2.0 features ? cpu features fully static core, capable of operatin g at any rate from 0 to 24 mhz (4 mhz minimum in active mode) 41.67 ns instruction cycle time with a 24 mhz external clock frequency multi-source vectored interrupts (internal, external, and on-chip peripheral) dual clock and reset ? on-chip power-on reset ? on-chip memory 96k bytes flash eeprom pro g ram memory or rom memory 4k bytes of static ram data memory for flash pro g ram memory, 1.5k bytes flash eeprom memory is used to store boot loader code 2k bytes of non-volatile eeprom data memory with low endurance (25k cycles) and 128 bytes with hi g h endurance (100k cycles) ? on-chip peripherals two universal synchronous/asynchronous receiver/ transmitter (usart) devices two dual 16-bit multi-function timers (mft1 and mft2) 8/16-bit spi/microwire-plus serial interface 12-channel, 8-bit analo g -to-di g ital (a/d) converter with external volta g e reference, pro g rammable sam- ple-and-hold delay, and pro g rammable conversion fre- quency access.bus synchronous serial bus fullcan interface with 15 messa g e buffers complaint to can specification 2.0b active versatile timer unit with four subsystems (vtu) two analo g comparators inte g rated watchdog lo g ic ? i/o features up to 56 g eneral-purpose i/o pins (shared with on-chip peripheral i/o pins) pro g rammable i/o pin characteristics: tri-state out- put, push-pull output, weak pull-up input, hi g h-imped- ance input schmitt tri gg ers on g eneral purpose inputs ? power supply 4.5v to 5.5v sin g le-supply operation ? temperature ran g e C40 c to +125 c C40 c to +85 c 0 c to +70 c ? development support real-time emulation and full pro g ram debu g capabili- ties available compactrisc tools provide c pro g rammin g and de- bu gg in g support
www.national.com 4 cr16 compactrisc microcontroller with can interface family selection guide programmable devices reprogrammable rom a rom devices note: all devices contains access.bus ( acb ) , clock and re- set, microwire/api, multi-input wake-up ( miwu ) , power mana g ement ( pmm ) , and the real-time timer and watch- do g ( twm ) modules. access.bus is compatible with i2c bus offered b y philips semiconductor. cr16 compactrisc microcontroller with can interface family devices national semiconductor currentl y offers a variet y of the cr16 compactrisc microcontrollers with can interface. the cr16mcs offer complete functionalit y in an 80-pin pqfp packa g e. nsid speed (mhz) flash (kbyte) eeprom data memory (bytes) sram (kbytes) usart timer i/os temp. range peripherals package type cr16mct9vjex 16 96 2176 4 2 2mft vtu 56 e, i, c adc, can, comparators 80pqfp cr16hct9vjex 24 96 2176 4 2 2mft vtu 56 e, i, c adc, can, comparators 80pqfp nsid speed (mhz) flash (kbyte) eeprom data memory (bytes) sram (kbytes) usart timer i/os temp. range peripherals package type cr16mct9vjex y 16 96 2176 4 2 2mft vtu 56 e, i, c adc, can, comparators 80pqfp cr16hct9vjex y 24 96 2176 4 2 2mft vtu 56 e, i, c adc, can, comparators 80pqfp nsid speed (mhz) rom (kbyte) eeprom data memory (bytes) sram (kbytes) usart timer i/os temp. range peripherals package type cr16mct5vjex y 16 96 2176 4 2 2mft vtu 56 e, i, c adc, can, comparators 80pqfp cr16hct5vjex y 24 96 2176 4 2 2mft vtu 56 e, i, c adc, can, comparators 80pqfp note: a . national offers repro g rammable rom that allow devices to be pro g rammed in factor y and repro g rammed b y the custom- er. ? suffix x in the nsid is defined below: temperature ran g es: i = industrial e = extended c= commerial ? suffix y in the nsid defines the rom code. -40 c to +125 c is represented when x is 7 -40 c to +85 c is represented when x is 8 0 c to +70 c is represented when x is 9
5 www.national.com 3.0 device overview the cr16mct9/cr16mct5/cr16hct9/cr16hct5 com- pactrisc microcontrollers are complete microcomputers with all system timing, interrupt logic, program memory, data memory, and i/o ports included on-chip, making it well-suited to a wide range of embedded controller applications. the block diagram on page 1 of the data sheet shows the major on-chip components of the cr16mct9/cr16mct5/ crhct9/cr16hct5. 3.1 cr16b cpu core the cr16mct9/cr16mct5/cr16hct9/cr16hct5 use the cr16b cpu core module. this is the same core used in other compactrisc family member designs, like dect or gsm chipsets. the high performance of the cpu core results from the im- plementation of a pipelined architecture with a two-bytes-per- cycle pipelined system bus. as a result, the cpu can support a peak execution rate of one instruction per clock cycle. compared with conventional risc processors, the cr16mct9/cr16mct5/cr16hct9/cr16hct5 differ in the following ways: the cpu core can use on-chip rather than external memory. this eliminates the need for large and com- plex bus interface units. most instructions are 16 bits, so all basic instructions are just two bytes long. additional bytes are sometimes required for immediate values, so instructions can be two or four bytes long. non-aligned word access is allowed. each instruction can operate on 8-bit or 16-bit data. the device is designed to operate with a clock rate in the 10 to 24 mhz range rather than 100 mhz or more. most embedded systems face emi and noise con- straints that limit clock speed to these lower ranges. a lower clock speed means a simpler, less costly silicon implementation. the instruction pipeline uses three stages. a smaller pipeline eliminates the need for costly branch predic- tion mechanisms and bypass registers, while maintain- ing adequate performance for typical embedded controller applications. for more information, please refer to the cr16b program- mers reference manual, literature #: 633150. 3.2 memory the compactrisc architecture supports a uniform linear ad- dress space of 2 megabytes. the device implementation of this architecture uses only the lowest 128k bytes of address space. four types of on-chip memory occupy specific inter- vals within this address space: ? 96k bytes of flash eeprom program memory (100k cy- cles) ? 4k bytes of static ram ? 2k bytes of eeprom data memory with low endurance (25k cycles) ? 128 bytes eeprom data memory with high endurance (100k cycles) ? 1.5k bytes flash eeprom memory for isp code the 4k bytes of static ram are used for temporary storage of data and for the program stack and interrupt stack. read and write operations can be byte-wide or word-wide, depend- ing on the instruction executed by the cpu. each memory access requires one clock cycle; no wait cycles or hold cycles are required. there are two types of flash eeprom data memory storage. the 2k bytes of eeprom data memory with low endurance (25k cycles) and 128 bytes of flash eeprom data memory with high endurance (100k cycles) are used for non-volatile storage of data, such as configuration settings entered by the end-user. the 96k bytes of flash eeprom program memory are used to store the application program. it has security features to prevent unintentional programming and to prevent unautho- rized access to the program code. this memory can be pro- grammed with a device external programming unit or with the device installed in the application system (in-system pro- gramming). there is a factory programmed boot memory used to store in-system-programming (isp) code. (this code allows pro- gramming of the program memory via one of the usart in- terfaces in the final application.) for flash eeprom program and data memory, the device in- ternally generates the necessary voltages for programming. no additional power supply is required. 3.3 input/output ports the device has 56 software-configurable i/o pins, organized into seven 8-pin ports called port b, port c, port f, port g, port h, port i, and port l. each pin can be configured to op- erate as a general-purpose input or general-purpose output. in addition, many i/o pins can be configured to operate as a designated input or output for an on-chip peripheral module such as the usart, timer, a/d converter, or microwire/ spi interface. the i/o pin characteristics are fully programmable. each pin can be configured to operate as a tri-state output, push- pull output, weak pull-up input, or high-impedance input. 3.4 bus interface unit the bus interface unit (biu) controls the interface between the on-chip modules to the internal core bus. it determines the configured parameters for bus access (such as the num- ber of wait states for memory access) and issues the appro- priate bus signals for each requested access. the biu uses a set of control registers to determine how many wait states and hold states are to be used when ac- cessing flash eeprom program memory, isp memory and the i/o area (port b and port c). upon start-up the configu- ration registers are set for slowest possible memory access. to achieve fastest possible program execution, appropriate values should be programmed. these settings vary with the clock frequency and the type of on-chip device being access- ed.
www.national.com 6 3.5 interrupts the interrupt control unit (icu31l) receives interrupt re- quests from internal and external sources and generates in- terrupts to the cpu. an interrupt is an event that temporarily stops the normal flow of program execution and causes a separate interrupt service routine to be executed. after the in- terrupt is serviced, cpu execution continues with the next in- struction in the program following the point of interruption. interrupts from the timers, usarts, microwire/spi inter- face, multi-input wake-up, and a/d converter are all maskable interrupts; they can be enabled or disabled by the software. there are 32 of these maskable interrupts, organized into 32 predetermined levels of priority. the highest-priority interrupt is the non-maskable interrupt (nmi ), which is generated by a signal received on the nmi in- put pin. 3.6 multi-input wake-up the multi-input wake-up (miwu16) module can be used for either of two purposes: to provide inputs for waking up (exit- ing) from the halt, idle, or power save mode; or to provide general-purpose edge-triggered maskable interrupts from external sources. this 16-channel module generates four programmable interrupts to the cpu based on the signals re- ceived on its 16 input channels. channels can be individually enabled or disabled, and programmed to respond to positive or negative edges. 3.7 dual clock and reset the dual clock and reset (clk2res) module generates a high-speed main system clock from an external crystal net- work. it also provides the main system reset signal and a power-on reset function. this module also generates a slow system clock (32.768 khz) from another external crystal network. the slow clock is used for operating the device in power-save mode. without a 32.768khz external crystal network, the low speed system clock can be derived from the high speed clock by a prescal- er. also, two independent clocks divided down from the high speed clock are available on output pins. 3.8 power management the power management module (pmm) improves the effi- ciency of the device by changing the operating mode and therefore the power consumption according to the required level of activity. the device can operate in any of four power modes: active: the device operates at full speed using the high-frequency clock. all device functions are fully op- erational. power save: the device operates at reduced speed using the slow clock. the cpu and some modules can continue to operate at this low speed. idle: the device is inactive except for the power man- agement module and timing and watchdog module, which continue to operate using the slow clock. halt: the device is inactive but still retains its internal state (ram and register contents). 3.9 multi-function timer the multi-function timer (mft16) module contains two in- dependent timer/counter units called mft1 and mft2, each containing a pair of 16-bit timer/counter registers. each timer/ counter unit can be configured to operate in any of the follow- ing modes: processor-independent pulse width modulation (pwm) mode, which generates pulses of a specified width and duty cycle, and which also provides a gener- al-purpose timer/counter. dual input capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/ counter. dual independent timer mode, which generates sys- tem timing signals or counts occurrences of external events. single input capture and single timer mode, which provides one external event counter and one system timer. 3.10 versatile timer unit the versatile timer unit (vtu) module contains four inde- pendent timer subsystems, each operating in either dual 8-bit pwm configuration, as a single 16-bit pwm timer, or a 16-bit counter with two input capture channels. each of the four tim- er subsystems offer an 8-bit clock prescaler to accommodate a wide range of frequencies. 3.11 real-time timer and watchdog the timing and watchdog module (twm) generates the clocks and interrupts used for timing periodic functions in the system. it also provides watchdog protection against soft- ware errors. the module operates on the slow system clock. the real-time timer can generate a periodic interrupt to the cpu at a software-programmed interval. this can be used for real-time functions such as a time-of-day clock. the real-time timer can trigger a wake-up condition from power-save mode via the multi-input wake-up module. the watchdog is designed to detect program execution er- rors such as an infinite loop or a runaway program. once watchdog operation is initiated, the application program must periodically write a specific value to a watchdog register, within specific time intervals. if the software fails to do so, a watchdog error is triggered, which resets the device. 3.12 usart the usart supports a wide range of programmable baud rates and data formats, and handles parity generation and several error detection schemes. the baud rate is generated on-chip, under software control. there are two independent usarts in the device and they offer a wake-up condition from the power-save mode via the multi-input wake-up module. 3.13 microwire/spi the microwire/spi (mwspi) interface module supports synchronous serial communications with other devices that conform to microwire or serial peripheral interface (spi) specifications. it supports 8-bit and 16-bit data transfers.
7 www.national.com the microwire interface allows several devices to com- municate over a single system consisting of four wires: serial in, serial out, shift clock, and slave enable. at any given time, the microwire interface operates as the master or a slave. the support supports the full set of slave select for multi- slave implementation. in master mode, the shift clock is generated on chip under software control. in slave mode, a wake-up out of power-save mode is triggered via the multi-input wake-up module. 3.14 cr16can the cr16can device contains a fullcan class, can serial bus interface for applications that require a high speed (up to 1mbits per second) or a low speed interface with can bus master capability. the data transfer between can and the cpu is established by 15 memory mapped message buffers, which can be individually configured as receive or transmit buffers. an incoming message is filtered by two masks, one for the first 14 message buffers and another one for the 15th message buffer to provide a basic can path. a priority de- coder allows any buffer to have the highest or lowest transmit priority. remote transmission requests can be processed au- tomatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon re- ception. in addition, a time stamp counter (16-bits wide) is provided to support real time applications. the cr16can device is a fast core bus peripheral, which al- lows single cycle byte or word read/write access. a set of di- agnostic features (such as loopback, listen only, and error identification) support the development with the cr16can module and provide a sophisticated error management tool. the cr16can receiver can trigger a wake-up condition out of the power-save modes via the multi-input wake-up mod- ule. 3.15 access.bus interface the access.bus interface module (acb) is a two-wire serial interface with the access.bus physical layer. it is also com- patible with intels system management bus (smbus) and philips i 2 c bus. the acb module can be configured as a bus master or slave, and can maintain bi-directional communica- tions with both multiple master and slave devices. the access.bus receiver can trigger a wake-up condition out of the power-save modes via the multi-input wake-up module. 3.16 a/d converter the a/d converter (adc) module is a 12-channel multi- plexed-input analog-to-digital converter. the a/d converter receives an analog voltage signal on an input pin and con- verts the analog signal into an 8-bit digital value using suc- cessive approximation. the cpu can then read the result from a memory-mapped register. the module supports four automated operating modes, providing single-channel or 4- channel operation in single or continuous mode. the device has a separate pin, vref, for the a/d reference voltage. 3.17 analog comparators the dual analog comparator (acmp2) module contains two independent analog comparators with all necessary control logic. each comparator unit compares the analog input volt- ages applied to two input pins and determines which voltage is higher. the cpu uses a memory-mapped register to con- trol the comparator and to obtain the comparison results. the comparison result can also be applied to comparator output pins. 3.18 development support a powerful cross-development tool set is available from na- tional semiconductor and third parties to support the devel- opment and debugging of application software for the cr16mct9/cr16mct5/cr16hct9/cr16hct5. the tool set lets you program the application software in c and is de- signed to take full advantage of the compactrisc architec- ture. there are in-system emulation (ise) devices available for the device from isystem?, as well as lower-cost evaluation boards. see your national semiconductor sales representa- tive for current information on availability and features of em- ulation equipment and evaluation boards.
www.national.com 8 4.0 device pinouts table 1 package pin assignments pin name alternate function(s) pin number type ph4 mwcs 1i/o ph5 md1d0 2 i/o ph6 md0d1 3 i/o ph7 msk 4 i/o pb0 d0 5 i/o pb1 d1 6 i/o pb2 d2 7 i/o pb3 d3 8 i/o pb4 d4 9 i/o pb5 d5 10 i/o pb6 d6 11 i/o pb7 d7 12 i/o env0 /clkout1 13 i/o sda 14 i/o scl 15 i/o gnd 16 pwr vcc 17 pwr gnd 18 pwr cantx 19 o canrx 20 i pc0 d8 21 i/o pc1 d9 22 i/o pc2 d10 23 i/o pc3 d11 24 i/o pc4 d12 25 i/o pc5 d13 26 i/o pc6 d14 27 i/o pc7 d15 28 i/o pg7 ckx1 29 i/o pg6 tdx1 30 i/o pg5 rdx1 31 i/o pg4 tio6 32 i/o pg3 tio5 33 i/o pg2 ckx2 34 i/o pg1 tdx2 35 i/o pg0 rdx2 36 i/o clkout2 37 o env1 /clk 1 37 i/o pf7 tio4 38 i/o pf6 tio3 39 i/o pf5 t2b 40 i/o pf4 t2a 41 i/o pf3 tio2 42 i/o pf2 tio1 43 i/o pf1 tib 44 i/o
9 www.national.com pf0 tia 45 i/o nmi 46 i x1cko 47 o x1cki 48 i gnd 49 pwr vcc 50 pwr gnd 51 pwr x2cko 52 o x2cki 53 i reset 2 54 i pi0 ach0 3 55 i/o pi1 ach1 3 56 i/o pi2 acn2 3 57 i/o pi3 ach3 3 58 i/o pi4 ach4 3 59 i/o pi5 ach5 3 60 i/o pi6 ach6 3 61 i/o pi7 ach7 3 62 i/o vref 63 pwr agnd 64 pwr avcc 65 pw r ph0 ach8 3 , wui4 66 i/o ph1 ach9 3 , wui5 67 i/o ph2 ach10 3 , wui6 68 i/o ph3 ach11 3 , wui7 69 i/o gnd 70 pwr vcc 71 pwr gnd 72 pwr pl0 comp1n 3 , wui0 73 i/o pl1 comp1p 3 , wui1 74 i/o pl2 comp1o, wui2 75 i/o pl3 comp2o, wui3 76 i/o pl4 comp2p 3 77 i/o pl5 comp2n 3 78 i/o pl6 tio7 79 i/o pl7 tio8 80 i/o note 1: the env0 and env1 pins each have a weak pull-up to keep the input from floating. note 2: the reset input has a weak pulldown. note 3: these functions are always enabled, due to the direct low-impedance path to these pins. table 1 package pin assignments pin name alternate function(s) pin number type
www.national.com 10 4.1 pin description some pins have alternate functions which may be enabled. these pins can be individually configured as general pur- pose pins, even when the module they belong to is enabled. the following is a brief description of all device pins. table 2 input pins signal type active pin (* for a shared pin) function x1cki osc high main oscillator clock input. x2cki osc high 32khz oscillator clock input. reset cmos low chip general reset pin. schmitt trigger input, asynchronous. ise cmos low interrupt input for development system. t1b cmos prog. * timer 1 input b. shares pin with i/o port pin pf1. t2b cmos prog. * timer 2 input b. shares pin with i/o port pin pf5. rdx1 cmos high * usart 1 receive data input. shares pin with i/o port pin pg5. rdx2 cmos high * usart 2 receive data input. shares pin with i/o port pin pg0. ach0 analog * a2d converter channel 0. shares pin with i/o port pin pi0 ach1 analog * a2d converter channel 1. shares pin with i/o port pin pi1 ach2 analog * a2d converter channel 2. shares pin with i/o port pin pi2 ach3 analog * a2d converter channel 3. shares pin with i/o port pin pi3 ach4 analog * a2d converter channel 4. shares pin with i/o port pin pi4 ach5 analog * a2d converter channel 5. shares pin with i/o port pin pi5 ach6 analog * a2d converter channel 6. shares pin with i/o port pin pi6 ach7 analog * a2d converter channel 7. shares pin with i/o port pin pi7 ach8 analog * a2d converter channel 8. shares pin with i/o port pin ph0 ach9 analog * a2d converter channel 9. shares pin with i/o port pin ph1 ach10 analog * a2d converter channel 10. shares pin with i/o port pin ph2 ach11 analog * a2d converter channel 11. shares pin with i/o port pin ph3 mwcs cmos low * spi/microwire slave select. shares pin with i/o port pin ph4. nmi cmos low external non-maskable interrupt. env0 cmos low * strap to select operating environment. env1 cmos low * strap pin to select operating environment. env2 cmos low strap pin to select operating environment. canrx cmos high can receive data input. table 3 output pins signal type active pin (* for a shared pin) function x1cko osc high main oscillator clock output. x2cko osc high 32khz oscillator clock output. clk cmos high * external reference clock for development environment (shared with env1 ). clkout1 cmos high * clock output generated through prescaler (shared with env0 ). clkout2 cmos high * clock output generated through prescaler (shared with env1 ). tdx1 cmos high * usart 1 transmit data output (shared with pg6). tdx2 cmos high * usart 2 transmit data output (shared with pg1). cantx cmos high can output.
11 www.national.com table 4 input/output pins signal type active pin (* for a shared pin) function pf[0:7] cmos high * generic i/o port. shared with t1a, t1b, tio1, tio2, t2a, t2b, tio3, tio4. pg[0:7] cmos high * generic i/o port. shared with rdx2, tdx2, ckx2, tio5, tio6, rdx1, tdx1, ckx1. pb[0:7] cmos high * generic i/o port. pc[0:7] cmos high * generic i/o port. pl[0:7] cmos high * generic i/o port. shared with 6 comparator pins, miwu16 on pl0:3. ph[0:7] cmos high * generic i/o port. shared with adc input channels 8-11, mwcs , mdido, mdodi, msk; miwu16 on ph4:7. pi[0:7] cmos high * generic i/o port. shared with adc input channels 0-7. t1a cmos prog * timer 1 input a. shared with i/o port pin pf0. t2a cmos prog * timer 2 input a. shared with i/o port pin pf4. tio[0:7] cmos prog * versatile timer unit i/os. shared with pf2:3, pf6:7, pg3:4, pl6:7. mdido cmos high * master in/slave out port: spi/microwire. shared with i/o pin ph5, mdodi cmos high * master out/slave in port: spi/microwire. shared with i/o pin ph6. msk cmos prog * spi/microwire clock. shared with i/o pin ph7. ckx1 cmos high * usart 1 clock. shared with i/o pin pg7. ckx2 cmos high * usart 2 clock. shared with i/o pin pg2 scl cmos high access.bus clock i/o. sda cmos high access.bus data i/o. table 5 power supply signal function vcc main digital power supply (4 total). vref voltage reference supply for analog to digital converter. avcc analog power supply for analog/digital converter. agnd analog reference ground supply. gnd main digital reference ground (8 total).
www.national.com 12 5.0 system configuration the device has two input pins, env0 and env1 , which are used to specify the operating environment of the device upon reset. there are also two system configuration registers, called the module configuration (mcfg) register and the module status (mstat) register. 5.1 env0 and env1 pins upon reset, the operating mode of the device is determined by the state of the env0 and env1 input pins, as indicated in table 6. in the case where the env1 and env0 pins are both high, the reset algorithm looks at the flctrl2.empty bit to de- termine whether the program memory is empty, and sets the operating mode accordingly. the env0 and env1 pins have on-chip pull-up devices that are enabled during reset while the pins are being sampled. therefore, if they are left unconnected, the inputs are consid- ered high and the normal operating mode (ire-mode) is se- lected and the cpu starts to execute code at address 0. to enter any other operating mode, the external hardware must drive the appropriate input low. in the case where the isp-mode is selected, the chip starts executing the isp code residing in the on-chip isp-memory area. the test modes are reserved for factory testing and for ex- ternal programming of the flash eeprom program memory. they should not be invoked otherwise. 5.2 module configuration (mcfg) register the mcfg register is a byte-wide, read/write register that sets the clock output features of the device. upon reset, the non-reserved bits of this register are cleared to zero. the start-up software must write a specific value to this register in order to configure the clk output pin function. when the software writes to this register, it must write a zero to each reserved bit for the device to operate properly. the register should be written in active mode only, not in power save, halt, or idle mode. however, the register contents are preserved during all power modes. the mcfg register format is shown below. clkoe cpu clock output enable. when this bit is cleared (0), the clk pin (env1) remains in the high-impedance state. when this bit is set (1) in normal operating mode, the clk pin operates as a cpu clock output. clk1oe generated clock output 1 enable. when cleared (0), the clkout1 pin (env0) stays in high impedance state. when set (1), the pin outputs the clock from the prescaler controlled by prssc1.scdiv1. clk2oe generated clock output 2 enable. when this bit is set (1) and clkoe is cleared, the clkout2 pin (env1) outputs the clock from the prescaler controlled by prssc1.scdiv2. otherwise, the clkout2 pin is in high imped- ance state. 5.3 module status (mstat) register the mstat register is a byte-wide, read-only register that in- dicates the general status of the device. the mcfg register format is shown below. oenv(1:0) operating environment. these two bits contain the values applied to the env1 and env0 pins upon reset. these bit values are controlled by the external hardware upon reset and are held constant in the register until the next reset. pgmbusy flash eeprom programming busy. this bit is automatically set to 1 when either the program memory or the data memory is busy being pro- grammed or erased. it is cleared to 0 when nei- ther of the two flash eeprom memories is busy being programmed or erased. when this bit is set, the software should not attempt any write access to either of these two memories. table 6 operating environment selection env1 env0 operating environment 0 0 test mode flash memory 0 1 test mode 1 0 in-system-programming mode (isp) 11 internal rom enabled mode (ire), if program memory is not empty; or isp- mode, if program memory is empty 7 6 5 4 3 2 1 0 reserved clk2oe reserved clk1oe clkoe reserved 74 3 2 1 0 reserved pgmbusy reserved oenv1 oenv0
13 www.national.com 6.0 input/output ports each device has up to 56 software-configurable i/o pins, or- ganized into seven ports of up to eight pins per port. the ports are named port b, port c, port f, port g, port h, port i, and port l. each pin can be configured to operate as a general-purpose input or general-purpose output. in addition, many i/o pins can be configured to operate as a designated input or output for an on-chip peripheral module such as the usart or the multi-input wakeup. this is called the pin's alternate func- tion. the alternate functions of all i/o pins are shown in the pinout diagrams in table 1. the i/o pin characteristics are fully programmable. each pin can be configured to operate as a tri-state output, push- pull output, weak pull-up input, or high-impedance input. dif- ferent pins within the same port can be individually config- ured to operate in different modes. figure 1 is a diagram showing the functional features of an i/ o port pin. the register bits, multiplexers, and buffers allow the port pin to be configured into the various operating modes.the output buffer is a tri-state buffer with weak pull-up capability. the weak pull-up, if used, prevents the port pin from going to an undefined state when it operates as an input. the input buffer is disabled when it is not needed to prevent leakage current caused by an input signals level between v cc -0.2 and v ss +0.2 [volts]. when enabled, it buffers the in- put signal and sends the pin's logic level to the appropriate on-chip module where it is latched. a schmitt-trigger mini- mizes the effects of electrical noise. the electrical characteristics and drive capabilities of the in- put and output buffers are described in section 25.0. for some pins, a direct low-impedance path is provided be- tween the pin and an internal analog function. these are the input pins to the a/d converter and the analog comparators. 6.1 port registers each port has an associated set of memory-mapped regis- ters used for controlling the port and for holding the port data. in general, there are five such registers: pxalt: port alternate function register pxdir: port direction register pxdin: port data input register pxdout: port data output register pxwkpu: port weak pull-up register in the descriptions of the ports and port registers, the lower- case letter x represents the port designation, either b, c, f, g, h, i, or l. for example, pxdir register means any one of the port direction registers: pbdir, pcdir, pfdir, and so on. all of the port registers are byte-wide read/write registers, ex- cept for the port data input registers, which are read-only reg- isters. each register bit controls the function of the corresponding port pin. for example, pfdir.2 (bit 2 of the pfdir register) controls the operation of port pin pf2. figure 1. i/o pin functional diagram pin direction data out register { direction register { weak pull-up register { alternate data input mux1 mux2 weak pull-up data out alt device data output alt alt alt device direction data in read strobe alt data input mux3 alt 1 alternate function enable *
www.national.com 14 6.1.1 port alternate function register each port that supports an alternate function (any port other than port b or port c) has an alternate function register (px- alt). this register determines whether the port pins are used for general-purpose i/o or for the predetermined alternate function. each port pin can be controlled independently. a bit cleared to 0 in the alternate function register causes the corresponding pin to be used for general-purpose i/o. in this configuration, the output buffer is controlled by the direction register and the data output register. the input buffer is rout- ed to the data input register. the input buffer is blocked ex- cept when the buffer is actually being read. a bit set to 1 in the alternate function register causes the cor- responding pin to be used for its predetermined peripheral i/ o function. the output buffer data and tri-state configura- tion are controlled by signals coming from the on-chip periph- eral device. the input buffer is enabled continuously in this case. to minimize power consumption, the input signal should be held within 0.2 volts of the vcc or gnd voltage. a reset operation clears the port alternate function registers to 0, which programs the pins to operate as general-purpose i/o ports. this register must be enabled before the corre- sponding alternate function is enabled. 6.1.2 port direction register the port direction register (pxdir) determines whether each port pin is used for input or for output. a bit cleared to 0 caus- es the pin to operate as an input, which puts the output buffer in the high-impedance state. a bit set to 1 causes the pin to operate as an output, which enables the output buffer. a reset operation clears the port direction registers to 0, which programs the pins to operate as inputs. 6.1.3 port data input register the data input register (pxdin) is a read-only register that re- turns the current state of each port pin. the cpu can read this register at any time even when the pin is configured as an output. 6.1.4 port data output register the data output register (pxdout) holds the data to be driv- en onto each port pin configured to operate as a general-pur- pose output. in this configuration, writing to the register changes the output value. reading the register returns the last value written to the register. a reset operation leaves the register contents unchanged. upon power-up, the registers contain unknown values. 6.1.5 port weak pull-up register the weak pull-up register (pxwkpu) determines whether each port pin uses a weak pull-up on the output buffer. a bit set to 1 causes the weak pull-up to be used, while a bit cleared to 0 causes the causes the weak pull-up not to be used. the pull-up device, if enabled by the register bit, operates in the general-purpose i/o mode whenever the port output buff- er is in the tri-state mode. in the alternate function mode, the pull-ups are always disabled. a reset operation clears the port weak pull-up registers to 0, which disables all pull-ups. 6.2 open-drain operation a port pin can be configured to operate as an inverting open- drain output buffer. to do this, the cpu should clear the bit in the data output register (pxdout) and then use the port di- rection register (pxdir) to set the value of the port pin. with the direction register bit set to 1 (direction=out), the value zero is forced on the pin. with the direction register bit cleared to 0 (direction=in), the pin is placed in the tri-state mode. if desired, the internal weak pull-up can be enabled to pull the signal high when the output buffer is in the tri- state mode.
15 www.national.com 7.0 cpu and core registers the device uses the same cr16b cpu core as other com- pactrisc family members. the core's reduced instruction set computer (risc) architecture allows a processing rate of up to one instruction per clock cycle. the cpu core uses a set of internal registers: general-purpose registers (r0-r13, ra, and sp) dedicated address registers (pc, isp, and intbase) processor status register (psr) configuration register (cfg) all of these registers are 16 bits wide except for the three ad- dress registers, which are 21 bits wide. some register bits are designated as reserved. the cpu must write a zero to each of these bit locations when it writes to the register. read operations from reserved bit locations return undefined values. 7.1 general-purpose registers there are 16 general-purpose registers, designated r0 through r13, ra, and sp. registers r0 through r13 can be used for any purpose such as holding variables, addresses, or index values. the ra register is usually used to store the return address upon entry into a subroutine. the sp register is usually used as the pointer to the program run-time stack. if a general-purpose register is used for a byte-wide opera- tion, only the low-order byte is referenced or modified. the high-order byte is not used or affected by a byte-wide opera- tion. 7.2 dedicated address registers there are three dedicated address registers: the program counter (pc), the interrupt stack pointer (isp), and the inter- rupt base register (intbase). each of these registers is 21 bits wide. 7.2.1 program counter the pc register contains the address of the least significant word currently being fetched. it is automatically incremented or changed by the appropriate amount each time an instruc- tion is executed. the least significant bit of the pc is always zero, thus instruc- tions must always be aligned to an even address in the range of 0000 to 1fffe hex. upon reset, the pc register is initialized to zero and program execution starts at that address (if in ire-mode). when a re- set signal is received, bits 1 through 16 of the pc register (prior to initialization) are stored in register r0. this allows the software to determine the point in the program at which the reset occurred. 7.2.2 interrupt stack pointer the isp register points to the lowest address of the last item stored on the interrupt stack. this stack is used by the hard- ware when an interrupt or trap service procedure is invoked. 7.2.3 interrupt base register the intbase register holds the address of the dispatch ta- ble for interrupts and traps. the least significant bit of the reg- ister is always zero. thus, the dispatch table starts at an even address in the range of 0000 to fffe. 7.3 processor status register the processor status register (psr) holds status informa- tion and selects the operating modes for the cpu core. the format of the register is shown below. c bit the carry (c) bit indicates whether a carry or borrow occurred after addition or subtraction. it is set to 1 if a carry or borrow occurred, or cleared to 0 otherwise. t bit the trace (t) bit, when set, causes a trace (trc) trap to be executed after every instruc- tion. this bit is automatically cleared to 0 when a trap or interrupt occurs. l bit the low (l) bit is set by comparison opera- tions. in a comparison of unsigned integers, the bit is set to 1 if the second operand (rdest) is less than the first operand (rsrc). otherwise, it is cleared to 0. f bit the flag (f) bit is a general condition flag that is set by various instructions. it may be used to signal exception conditions or to distinguish the results of an instruction. for example, integer arithmetic instructions use this bit to indicate an overflow condition after an addition or subtrac- tion operation. z bit the zero (z) bit is set by comparison opera- tions. in a comparison of integers, the bit is set to 1 if the two operands are equal. otherwise, it is cleared to 0. n bit the negative (n) bit is set by comparison oper- ations. in a comparison of signed integers, the bit is set to 1 if the second operand (rdest) is less than the first operand (rsrc). otherwise, it is cleared to 0. e bit the local maskable interrupt enable (e) bit is used to enable or disable maskable interrupts. if this bit and the global maskable interrupt en- able (i) bit are both set to 1, all maskable inter- rupts are accepted. otherwise, only the non- maskable interrupt is accepted. the e bit is set to 1 by the enable interrupts (ei) instruction and cleared to 0 by the disable interrupts (di) instruction. p bit the trace trap pending (p) bit is used together with the trace (t) bit to prevent a trace (trc) trap from occurring more than once for any in- struction. the p bit may be cleared to 0 (no trc trap pending) or set to 1 (trc trap pend- ing). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved i p e 0 n z f 0 0 l t c
www.national.com 16 i bit the global maskable interrupt enable (i) bit is used to enable or disable maskable interrupts. if this bit and the local maskable interrupt en- able (e) bit are both set to 1, all maskable inter- rupts are accepted. otherwise, only the non- maskable interrupt is accepted. this bit is auto- matically cleared to 0 when an interrupt occurs and automatically set to 1 upon completion of an interrupt service routine. upon reset, all non-reserved bits of the register are cleared to 0 except for the e bit (bit 9), which is set to 1. when a de- vice reset occurs, the psr contents prior to the reset are stored into register r1, allowing the initialization software to determine the state of the device prior to the reset operation. 7.4 configuration register the configuration (cfg) register is a 16-bit core register that determines the size of the intbase register. for the device, the cfg register should always be left in its default state (cleared to zero), resulting in a 16-bit intbase register. 7.5 addressing modes each instruction operates on one or more operands. an op- erand can be a register or a memory location. most instructions use one, two, or three device registers as operands. the instruction opcode specifies the registers to be operated on. some instructions may use an immediate value (a value provided in the instruction itself) instead of a register. memory locations are accessed only by the load and store commands. the memory location to use for a particular in- struction can be specified as an absolute, relative, or far-rel- ative address. the instruction set supports the following addressing modes: for additional information on the instruction set and instruc- tion encoding, see the compactrisc cr16b programmer's reference manual. 7.6 stacks a stack is a one-dimensional data buffer in which values are entered and removed one at a time. the last valued entered is the first one removed. a register called the stack pointer contains the current address of the last item entered on the stack. in the device, when an item is entered or pushed onto the stack, the stack expands downward in memory (the stack pointer is decremented). when an item is removed or popped from the stack, the stack shrinks upward in memory (the stack pointer is incremented). the device uses two type of stacks: the program stack and the interrupt stack. the program stack is used by the software to save and re- store register values upon entry into and exit from a subrou- tine. the software can also use the program stack to store local and temporary variables. the stack pointer for this stack is the sp register. the interrupt stack is used to save and restore the program state when an exception occurs (an interrupt or software trap). the on-chip hardware automatically pushes the pro- gram state information onto the stack before the exception service procedure is executed. upon exit from the exception service procedure, the hardware pops this information from the stack and restores the program state. the stack pointer for this stack is the isp register. 7.7 instruction set table 7 is a summary list of all instructions in the device in- struction set. for each instruction, the table shows the mne- monic and a brief description of the operation performed. in the mnemonic column, the lower-case letter i is used to indicate the type of integer that the instruction operates on, either b for byte or w for word. for example, the notation addi for the add instruction means that there are two forms of this instruction, addb and addw, which operate on bytes and words, respectively. similarly, the lower-case string cond is used to indicate the type of condition tested by the instruction. for example, the notation jcond represents a class of conditional jump instruc- tions: jeq for jump on equal, jne for jump on not equal, and so on. register mode the operand is a general-purpose regis- ter: r0 through r13, ra, or sp. for exam- ple: addb r1, r2 immediate mode a constant operand value is specified with- in the instruction. in a branch instruction, the immediate operand is a displacement from the program counter (pc). in the as- sembly language syntax, a dollar sign indi- cates an immediate value. for example: mulw $4, r4 relative mode the operand is located in memory. its ad- dress is obtained by adding the contents of a general purpose register to the constant value encoded into the displacement field of the instruction. for example: loadw 12(r5), r6 far-relative mode the operand is located in memory. its ad- dress is obtained by concatenating a pair of adjacent general-purpose registers to form a 21-bit value, and adding this value to the constant value encoded into the dis- placement field of the instruction. absolute mode the operand is located in memory. its ad- dress is specified within the instruction. for example: loadb 4000, r6
17 www.national.com for detailed information on all instructions, see the compactrisc cr16b programmer's reference manual. table 7 device instruction set summary mnemonic description addi add integer addui add unsigned integer addci add integer with carry andi bitwise logical and ashui arithmetic shift unsigned bcond conditional branch bcond0i compare register to 0 and branch bcond1i compare register to 1and branch bal branch and link br unconditional branch cbiti clear bit in integer cmpi compare integer di disable maskable interrupts ei enable maskable interrupts eiwait enable interrupts and wait for interrupt excp exception jcond conditional jump jal jump and link jump jump loadi load integer loadm load multiple registers lpr load processor register lshi logical shift integer movi move integer movxb move with sign-extension movzb move with zero-extension muli multiply integer mulsi multiply signed muluw multiply unsigned nop no operation ori bitwise logical or pop pop registers from stack popret pop and jump ra push push registers on stack retx return from exception scond save condition as boolean muli multiply integer sbiti set bit in integer stori store integer storm store registers to memory subi subtract integer subci subtract integer with carry tbit test bit wait wait for interrupt xori bitwise logical exclusive or table 7 device instruction set summary mnemonic description
www.national.com 18 8.0 bus interface unit the bus interface unit (biu) controls the interface between the internal core bus and those on-chip modules which are mapped into biu zones. these on-chip modules are the flash eeprom program memory, the isp-memory and the i/o- zone. it determines the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for the requested access. note: the device is manufactured in a 224-pin version which is used in emulation equipment. in the 224-pin device, the biu controls access to both on-chip and off-chip memory and peripherals. operation of the 224-pin device and the use of chip-external memory is beyond the scope of this data sheet. 8.1 bus cycles there are four types of data transfer bus cycles: normal read fast read early write late write the type of data cycle used in a particular transaction de- pends on the type of cpu operation (a write or a read), the type of memory or i/o being accessed, and the access type programmed into the biu control registers (early/late write or normal/fast read). for read operations, a basic normal read takes two clock cy- cles, whereas a fast read bus cycle takes one clock cycle. upon reset of the device, normal read bus cycles are enabled by default. for write operations, a basic late write bus cycle takes two clock cycles, whereas a basic early write bus cycle takes three clock cycles. upon reset of the device, early write bus cycles are enabled by default. however, late write bus cycles are needed for ordinary write operations, so this configura- tion should be changed by the application software (see section 8.2.1). in certain cases, one or more additional clock cycles are add- ed to a bus access cycle. there are two types of additional clock cycles for ordinary memory accesses, called internal wait cycles (tiw) and hold (t hold ) cycles. a wait cycle is inserted in a bus cycle just after the memory address has been placed on the address bus. this gives the accessed memory more time to respond to the transaction request. a hold cycle is inserted at the end of a bus cycle. this holds the data on the data bus for an extended number of clock cycles. 8.2 biu control registers the biu has a set of control registers that determine how many wait cycles and hold cycles are to be used for access- ing memory. upon start-up of the device, these registers should be programmed with appropriate values so that the minimum allowable number of cycles is used. this number varies with the clock frequency used. there are four applicable biu registers: the biu configura- tion (bcfg) register, the i/o configuration (iocfg) register, the static zone 0 configuration (szcfg0) register and the static zone 1configuration (szcfg1) register. these regis- ters control the bus cycle configuration used for accessing the various on-chip memory types. note: a system configuration register called the module configuration (mcfg) register controls the number of wait cycles used for accessing the eeprom data memory. this register is described in section 5.1. 8.2.1 biu configuration (bcfg) register the biu configuration (bcfg) register is a byte-wide, read/ write register that selects either early write or late write bus cycles. the register address is f900 hex. upon reset, the register is initialized to 07 hex. the register format is shown below. ewr early write. this bit is cleared to 0 for late write operation (two clock cycles to write) or set to 1 for early write operation. note 1: these bits (bit 1 or bit 2) control the configuration of the 224-pin device used in emulation equipment. the cpu should set this bit to 1 when it writes to the register. upon reset, the bcfg register is initialized to 07 hex, which selects early write operation. however, late write operation is required for normal device operation, so the software should change the register value to 06 hex. 8.2.2 i/o zone configuration (iocfg) register the i/o zone configuration (iocfg) register is a word-wide, read/write register that sets the timing and bus characteris- tics of i/o zone memory accesses. in the device implemen- tation, the registers associated to port b and port c reside in the i/o memory array. (these ports are used as a 16-bit data port, if the device operates in development mode.) 7 6 5 4 3 2 1 0 reserved note 1 note 1 ewr
19 www.national.com the iocfg register address is f902 hex. upon reset, the register is initialized to 069f hex. the register format is shown below. wait memory wait cycles this field specifies the number of tiw (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no addi- tional tiw wait cycles to 111 binary for seven additional tiw wait cycles. hold memory hold cycles this field specifies the number of t hold clock cycles used for each memory access, ranging from 00 binary for no t hold cycles to 11 binary for three t hold clock cycles. bw bus width. this bit defines the bus width of the zone. if cleared to 0, a bus width of 8-bit is used. if set to 1, a bus width of 16-bit is used. for the device, a bus width of 16-bit needs to be set. ipst post idle. an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. if cleared to 0, no idle cycle is inserted. if set to 1, one idle cycle is inserted. the ipst bit can be cleared to 0, as no idle cy- cles are required for on-chip accesses. note: reserved bits must be cleared to 0 when the cpu writes to the register. 8.2.3 static zone 0 configuration (szcfg0) register the static zone 0 configuration (szcfg0) register is a word-wide, read/write register that sets the timing and bus characteristics of zone 0 memory accesses. in the device im- plementation of the compactrisc architecture, zone 0 is oc- cupied by the flash eeprom program memory. the sccfg0 register address is f904 hex. upon reset, the register is initialized to 069f hex. the register format is shown below. wait memory wait cycles this field specifies the number of tiw (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no addi- tional tiw wait cycles to 111 binary for seven additional tiw wait cycles. these bits are ig- nored if the szcfg0.fre bit is set to 1. hold memory hold cycles this field specifies the number of t hold clock cycles used for each memory access, ranging from 00 binary for no t hold cycles to 11 binary for three t hold clock cycles. these bits are ig- nored if the szcfg0.fre bit is set to 1. bw bus width. this bit defines the bus width of the zone. if cleared to 0, a bus width of 8-bit is used. if set to 1, a bus width of 16-bit is used. for the devicedevice a bus width of 16-bit needs to be set. fre fast read enable this bit enables (1) or disables (0) fast read bus cycles. a fast read operation takes one clock cycle. a normal read operation takes at least two clock cycles. ipst post idle. an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. if cleared to 0, no idle cycle is inserted. if set to 1, one idle cycle is inserted. the ipst bit can be cleared to 0, as no idle cy- cles are required for on-chip accesses. ipre preliminary idle. an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a dif- ferent zone. if cleared to 0, no idle cycle is inserted. if set to 1, one idle cycle is inserted. the ipre bit can be cleared to 0, as no idle cy- cles are required for on-chip accesses. note: reserved bits must be cleared to 0 when the cpu writes to the register. 8.2.4 static zone 1 configuration (szcfg1) register the static zone 1 configuration (szcfg1) register is a word-wide, read/write register that sets the timing and bus characteristics of zone 1 memory accesses. in the device im- plementation of the compactrisc architecture, zone 1 is oc- cupied by the boot rom memory (isp-memory). the sccfg1 register address is f906 hex. upon reset, the register is initialized to 069f hex. the register format is shown below. wait memory wait cycles this field specifies the number of tiw (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no addi- tional tiw wait cycles to 111 binary for seven additional tiw wait cycles. these bits are ig- nored if the szcfg0.fre bit is set to 1. 15 14 13 12 11 10 9 8 reserved ipst reserved 7 6 5 4 3 2 1 0 bw reserved hold wait 15 14 13 12 11 10 9 8 reserved fre ipre ipst reserved 7 6 5 4 3 2 1 0 bw reserved hold wait 15 14 13 12 11 10 9 8 reserved fre ipre ipst reserved 7 6 5 4 3 2 1 0 bw reserved hold wait
www.national.com 20 hold memory hold cycles this field specifies the number of t hold clock cycles used for each memory access, ranging from 00 binary for no t hold cycles to 11 binary for three t hold clock cycles. these bits are ig- nored if the szcfg0.fre bit is set to 1. bw bus width. this bit defines the bus width of the zone. if cleared to 0, a bus width of 8-bit is used. if set to 1, a bus width of 16-bit is used. for the device a bus width of 16-bit needs to be set. fre fast read enable this bit enables (1) or disables (0) fast read bus cycles. a fast read operation takes one clock cycle. a normal read operation takes at least two clock cycles. ipst post idle. an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. if cleared to 0, no idle cycle is inserted. if set to 1, one idle cycle is inserted. the ipst bit can be cleared to 0, as no idle cy- cles are required for on-chip accesses. ipre preliminary idle. an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a dif- ferent zone. if cleared to 0, no idle cycle is inserted. if set to 1, one idle cycle is inserted. the ipre bit can be cleared to 0, as no idle cy- cles are required for on-chip accesses. note: reserved bits must be cleared to 0 when the cpu writes to the register. 8.3 wait and hold states used the number of wait cycles and hold cycles inserted into a bus cycle depends on whether it is a read or write operation, the type of memory or i/o being accessed, and the control regis- ter settings. 8.3.1 flash eeprom program memory when the cpu accesses the flash eeprom program mem- ory (address ranges 0000-bfff and 10000-1bfff), the number of added wait and hold cycles depends on the type of access and the biu register settings. in fast read mode (szcfg0.fre=1), a read operation is a single cycle access. this limits the maximum cpu operating frequency to either 10 mhz or 24 mhz (see section 9.1.1). for a read operation in normal read mode (szcfg0.fre=0), the number of inserted wait cycles is one plus the value writ- ten to the szcfg0.wait field. the number in this field can range from zero to seven, so the total number of wait cycles can range from one to eight. the number of inserted hold cy- cles is equal to the value written to the sccfg0.hold field, which can range from zero to three. for a write operation in fast read mode (szcfg0.fre=1), the number of inserted wait cycles is one. no hold cycles are used. for a write operation normal read mode (szcfg0.fre=0), the number of wait cycles is equal to the value written to the szcfg0. wait field plus one (in the late write mode) or two (in the early write mode). the number of inserted hold cycles is equal to the value written to the sccfg0.hold field, which can range from zero to three. writing to the flash eeprom program memory is a flash programming operation that requires some additional steps, as explained in section 9.3. 8.3.2 ram memory read and write accesses to on-chip ram is performed within a single cycle, regardless of the biu settings. 8.3.3 eeprom data memory there is either no wait state or one wait state used when the cpu accesses the eeprom data memory (address f000- f27f hex). the number of required wait states (zero or one) depends on the cpu clock frequency and operating mode, and is controlled by programming of the dmcsr.zerows bit in the mcfg register, as explained in section 9.3. no hold cycles are used. 8.3.4 accesses to peripheral when the cpu accesses on-chip peripherals in the range of f800-faff hex and fc00-ffff hex, one wait cycle and one preliminary idle cycle is used. no hold cycles are used. the iocfg register determines the access timing for the ad- dress range fb00-fb16 hex (ports b and port c). 8.3.5 access timing summary table table 8 is a summary showing the number of access cycles used for various address ranges. 8.3.6 recommended register settings table 9 shows the recommended register settings for various clock rates. different clock rates require different register set- tings because the flash eeprom program memories have specific setup and hold requirements that can be met only by using enough wait cycles and hold cycles.
21 www.national.com table 8 access timing table address range (hex) memory or i/o type access cycles read write 0000-bfff flash eeprom program memory szcfg0.fre=1: 1 cycle szcfg0.fre=1: 1 cycle + bcfg.ewr (+ programming time) szcfg0.fre=0: 2 cycles + szcfg0.wait + szcfg0.hold szcfg0.fre=0: 2 cycles + bcfg.ewr + szcfg0.wait + szcfg0.hold (+ programming time) c000-cfff static ram memory 1 cycle 1 cycle f000-f27f eeprom data memory mcfg.zerows=1: 1 cycle mcfg.zerows=1: 1 cycle (+ programming time) mcfg.zerows=0: 2 cycles mcfg.zerows=0: 2 cycles (+ programming time) f900-ffff f800-f9ff fc00-ffff on-chip peripherals 2 cycles 2 cycles fb00-fbff ports b and c 3 cycle + iocfg.wait + iocfg.hold 3 cycle + bcfg.ew + iocfg.wait + iocfg.hold 10000-1bfff flash eeprom program memory szcfg0.fre=1: 1 cycle szcfg0.fre=1: 1 cycle + bcfg.ewr (+ programming time) szcfg0.fre=0: 2 cycles + szcfg0.wait + szcfg0.hold szcfg0.fre=0: 2 cycles + bcfg.ewr + szcfg0.wait + szcfg0.hold (+ programming time) table 9 recommended register settings clock rate szcfg0 szcfg1 iocfg < 16 mhz, 0 wait state for both cr16mct and cr16hct 0880 hex 0880 hex 0080 hex 16 to 24mhz, 0 wait state for cr16hct 0880 hex 0880 hex 0080 hex 16 to 24mhz, 1wait state for cr16mct 0080 hex 0080 hex 0080 hex
www.national.com 22 9.0 memory the compactrisc architecture supports a uniform linear ad- dress space of 2 megabytes, addressed by 21 bits. the de- vice implementation of this architecture uses only the lowest 128k bytes of address space. each memory location con- tains a byte consisting of eight bits. various types of on-chip memory occupy specific intervals within the address space: 96k bytes of flash eeprom pro- gram memory, 4k bytes of static ram, 2k bytes of low endur- ance eeprom data memory, 128 bytes of high endurance eeprom data memory, and 1.5k bytes of isp memory. all of these memories are 16 bits wide, and their contents can be accessed either as bytes (eight bits wide) or words (16 bits wide except for the program memory which only supports word access). the cpu core uses the load and store instructions to ac- cess memory. these instructions can operate on bytes or words. for a byte access, the cpu operates on a single byte occupying a specified memory address. for a word access, the cpu operates on two consecutive bytes. in that case, the specified address refers to the least significant byte of the data value; the most significant byte is located at the next higher address. thus, the ordering of bytes in memory is from least to most significant byte, known as little-endian or- dering. for more efficient data access operations, 16-bit vari- ables should be stored starting at word boundaries (at even address). 9.1 flash eeprom program memory the flash eeprom program memory is used to store the ap- plication program. the 96k bytes of this memory reside in the address range of 0000-bfff hex and 10000-1bfff in zone 0 of the cr16b address space. a normal cpu write opera- tion to this memory has no effect. the flash eeprom program memory module has the follow- ing features: 96k bytes arranged in 2 blocks each organized as 24k by 16 bits page size of 64 words 30 m s programming pulse per word page mode erase with a 1 ms pulse, mass erase with 4ms pulse all erased flash eeprom program memory bits read 1 fast single cycle read access flexible software controlled in-system-programming (isp) capability pipelined programming cycles through double-buff- ered data register, with write access disabled when the register is full programming high voltage and timing generated on- chip memory disabled when address is out of range requires valid key for program and erase to proceed provide busy status during programming and erase read accesses disabled during programming and erase security features to limit read/write access 9.1.1 reading program memory read accesses can operate without wait cy- cles with a cpu clock rate of up to 24mhz in the normal mode. at higher clock rates, memory read accesses can op- erate with one wait state. the programmed number of wait cycles used (either zero or one) is controlled by the biu configuration (bcfg) register and the static zone 0 configuration (szcfg0) register. these registers are described in section 8.0. 9.1.2 conventional programming modes the flash eeprom program memory can be programmed either with the device plugged into a flash eeprom pro- grammer unit (external programming) or with the device al- ready installed in the application system (in-system- programming). if the device is programmed using a flash eeprom program- mer, the device is set into an external programming mode. in this mode the device operates as if it were a pure flash mem- ory device. the flash memory is programmed without involv- ing any cpu activity. if the device is to be programmed within the user application, it can either be done by an user written boot loader or by uti- lizing a pre-programmed in-system-programming code (isp- code) residing in the boot rom array of the device. the device executes the pre-programmed in-system-pro- gramming code if it operates in the in-system-programming mode (isp-mode). to enter the isp-mode the device must be reset (or powered-up) with the env0-pin set to low level and the env1-pin set to high level (or left open). also if the flash program memory is not programmed yet (flctrl2.empty bit is still set) the device automatically enters the isp-mode after reset, even though both pins env0 and env1are at high level (or left open). if the device enters the isp-mode it starts execution at address e000 hex. in isp-mode the program code can be downloaded into the device using one of the on-chip usarts and written into the flash program memory. for more detailed information on the in-system-programming features of the pre-programmed isp-code please refer to the isp-monitor manual. 9.1.3 user-coded programming routines instead of using a flash eeprom programmer unit or the conventional in-system programming mode, you can write your own processor code to program and erase the flash eeprom program memory. user-written code is more flexi- ble than using the other programming methods. like the con- ventional in-system programming mode, the device is programmed while it is installed in the system. it is not nec- essary to reset the device or use the env0 /env1 pins to configure the device. user-written flash programming code must reside outside of the flash program memory. this is because the entire pro- gram memory becomes unavailable while programming or erasing any part of this memory.
23 www.national.com 9.1.4 flash eeprom programming and verify the flash eeprom program memory programming and erase can be performed using different methods. it can be done through user code that is stored in system ram, or through in-system-programming mode, but should not be programmed through the flash eeprom program memory it- self as no instruction or data can be fetched from it while it is being programmed. all program and erase operations must be preceded immediately by writing the proper key to the pro- gram memory key register pgmkey. the flash eeprom program memory is divided into 768 pages, each page containing 64 words (each 16 bits wide). each page is further divided into two adjacent rows. a page erase will erase one page. programming is done by writing to all the words within a row, one word following another se- quentially within one single high voltage pulse. this is sup- ported through a double-buffered write-data buffer scheme. byte programming is not supported. programming should be done on erased rows. a mass erase requires the following code sequence (assum- ing that this sequence will not be interrupted to do another flash erase or programming): 1. check for mstat.pgmbusy not set. 2. set up flash timing reload registers for mass erase oper- ation. 3. set flcsr.merase = 1. 4. if interrupt was enabled, disable interrupt. 5. write proper key value to pgmkey. 6. write to any valid location within the flash eeprom pro- gram memory. 7. if interrupt was disabled in step 4, re-enable interrupt. 8. wait for mstat.pgmbusy to clear. 9. set flcsr.merase = 0. 10. restore flash timing reload registers for normal opera- tion. a page erase requires the following code sequence (assum- ing that this sequence will not be interrupted to do another flash erase or programming): 1. check for mstat.pgmbusy not set. 2. set flcsr.erase = 1. 3. if interrupt was enabled, disable interrupt. 4. write proper key value to pgmkey. 5. write to any valid location within the page to be erased. 6. if interrupt was disabled in step 3, re-enable interrupt. 7. set flcsr.erase = 0. when programming, the data to be written into the flash ee- prom program memory is first written into a double-buffered write-data buffer. when a piece of data is written to the page while the flash eeprom program memory is idle, the write cycle will start. due to the double-buffered nature of the write- data buffer, a second word can be written to the flash ee- prom program memory. this will then set flcsr.pml- full flag indicating the buffer is now full. when the first write is done, the memory address would be incremented, and the second word would be written to that address while keeping the high voltage pulse active; the flcsr.pmlfull flag is cleared. another word can then be written to the buffer, and this programming will repeat until there are no more words to be programmed. this allows pipelined writes to different words on the same row within the same high voltage pulse. if the programming sequence exceeds a row, the flash pro- gramming interface will automatically initiate a programming pulse for the next row. the flcsr.pmlfull bit is also cleared when programming of the last word of the current row is completed, e.g. programming of the entire row is complet- ed and mstat.pgmbusy is cleared. this means, the sepa- ration of the program memory into rows is transparent to the user, as the transition is handled by the flash program mem- ory interface. figure 3 shows a flowchart for a programming sequence. 9.1.5 erase and programming timing the internal hardware of the device handles the timing of erase and programming operations. to drive the timing con- trol circuits, the device divides the system clock by a pro- start mstat.pgmbusy =1? disable interrupt if necessary write pgmkey re-enable interrupt if necessary write memory last word? done ye s no ye s ye s flcsr.pmlfull =0? no no figure 2. programming sequence for the program memory
www.national.com 24 grammable prescaler factor. you should select a prescaler value to produce a program/erase clock of 200 khz (or as close as possible to 200 khz without exceeding 200 khz). for the timing control circuit to operate correctly, you must pro- gram the prescaler value in advance and leave it unchanged while a program or erase operation is in progress. a similar (but separate) prescaler factor is applied to the eeprom data memory. see section 9.1.7 and section 9.3.4 for de- tails. 9.1.6 flash eeprom program memory control and status register (flcsr) the flash eeprom program memory control and status (flcsr) register is a byte-wide, read/write register that con- tains several status and control bits related to the program memory. all reserved bits must be written with 0 for the mem- ory to operate properly when writing to this register. upon re- set, this register is cleared to zero when the flash memory on the chip is in the idle state. the register format is shown below. pmer flash eeprom program memory page erase. when set (1) with merase bit cleared, a valid write to the flash eeprom program memory erases the entire flash eeprom program memory page pointed to by the write address rather than performing a write to the addressed memory location. pmbusy program memory busy. this bit is automatical- ly set to 1 when the flash eeprom program memory is busy being programmed, and cleared to 0 at all other times. (the mstat.pg- mbusy is also set to 1 whenever the pmbusy bit is set to 1.) pmlfull program memory write-latch buffer full. when set (1), the double-buffered data register for program memory write operations is full. when cleared (0), the double-buffered data register is not full. merase mass erase flash eeprom program memory array. when set (1) in isp or test mode, a valid write to the flash eeprom program memory performs an erase to the whole flash eeprom program memory rather than perform a write to the addressed memory location. however, it is necessary to enter new values into the flerase and flend registers to adjust the mass erase timing before starting the mass erase. 9.1.7 program memory timing prescaler register (flpslr) the flpslr register is a byte-wide, read/write register that selects the prescaler divider ratio for the flash eeprom pro- gram memory programming clock. before you program or erase the program memory for the first time, you should pro- gram the flpslr register with the proper prescaler value, an 8-bit value called ftdiv. the device divides the system clock by (ftdiv+1) to produce the program memory programming clock. you should choose a value of ftdiv to produce a clock of the highest possible frequency that is equal to or just less than 200 khz. for example, if the system clock frequency is 12.5 mhz, use the value 3e hex (62 decimal) for ftdiv, because 12.5 mhz / (62+1) = 198.4 khz. do not modify this register while a flash eeprom program or erase operation is in progress. upon reset, this register is programmed by default with the value 63 hex (99 decimal), which is an appropriate setting for a 20 mhz system clock. 9.1.8 program memory start time reload (flstart) the flstart register is a byte-wide read/write register that controls the program and erase start delay time. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you program or erase the program memory for the first time, pro- gram the flstart register with the proper prescaler value, ftstart. the flash timing counter generates a delay of (ftstart + 1) prescaler output clocks. the default value provides a delay time of 10 m s when the prescaler output clock is 200khz. do not modify this register while a program or erase operation is in progress. upon reset, this register resets to 01 16 when the flash mem- ory on the chip is in an idle state. 9.1.9 program memory transition time reload register (fltran) the fltran register is a byte-wide read/write register that controls some program/erase transition times. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you program or erase the program memory for the first time, you should program the fltram register with the proper prescal- er value, fttran. the flash timing counter generates a de- lay of (fttran + 1) prescaler output clocks. the default value provides a delay time of 5 m s when the prescaler output clock is 200khz. do not modify this register while a program or erase operation is in progress. upon reset, this register resets to 00 16 when the flash mem- ory on the chip is in an idle state. 9.1.10 program memory programming time reload register (flprog) the flprog register is a byte-wide read/write register that controls the programming pulse width. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you program or erase the program memory for the first time, pro- gram the flprog register with the proper prescaler value, ftprog. the flash timing counter generates a program- ming pulse width of (ftprog + 1) prescaler output clocks. the default value provides a delay time of 30 m s when the prescaler output clock is 200khz. do not modify this register while program/erase operation is in progress. upon reset, this register resets to 05 16 when the flash mem- ory on the chip is in idle state. 7 6 4 3 2 1 0 merase reserved pmlfull pmbusy pmer reserved
25 www.national.com 9.1.11 program memory erase time reload register (flerase) the flerase register is a byte-wide read/write register that controls the erase pulse width. this value is loaded into the upper 8 bits of the flash timing counter, and at the same time, 11 2 is loaded into the lower 2 bits. before you program or erase the program memory for the first time, program the flerase register with the proper prescaler value, fter. the flash timing counter generates a erase pulse width of 4 (fter + 1) prescaler output clocks. the default value pro- vides a delay time of 1ms when the prescaler output clock is 200khz. do not modify this register while a program or erase operation is in progress. upon reset, this register resets to 31 16 when the flash mem- ory on the chip is in idle state. for mass erase, this value should be changed to c7 16 to gen- erate a pulse width that is four times as long as the page erase. 9.1.12 program memory end time reload register (flend) the flend register is a byte-wide read/write register that controls the delay time after a program/erase operation. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you program or erase the program memory for the first time, program the flend register with the proper prescaler value, ftend. the flash timing counter generates a delay of (ftend + 1) prescaler output clocks. the default value provides a delay time of 5 m s when the prescaler output clock is 200khz. do not modify this register while program/ erase operation is in progress. upon reset, this register resets to 00 16 when the flash mem- ory on the chip is in idle state. for mass erase, this value should be changed to 13 16 to pro- vide for a delay time twenty times that of the standard delay. 9.1.13 program memory prescaler count register (flpcnt) the flpcnt register is a byte-wide read-only register that returns the value of the program memory prescaler counter. fpcnt contains the flash timing prescaler present count val- ue. 9.1.14 program memory timer count register 1 (flcnt1) the flcnt1 register is a byte-wide read-only register that returns the lower 8 bits of the program memory timing counter value. flcntl is the lower 8 bits of the flash timer present count value. 9.1.15 program memory timer count register 2 (flcnt2) the flcnt2 register is a byte-wide read-only register that returns the upper 2 bits of the program memory timing counter value and also the state of the key flash memory in- terface timing signals. the interface timing signals are only used in special test modes. their function is beyond the scope of this document. 9.1.16 program memory write key register (pgmkey) the pgmkey register is a byte-wide, write-only register that must be written with a key value (a3 16 ) immediately prior to each write to the flash eeprom program memory. other- wise, the write operation to the program memory will fail. this feature is intended to prevent unintentional programming of the program memory. reading this register always returns ff hex. upon reset, the write enable status that is generated as a re- sult of writing to this key register is cleared. 9.2 ram memory the static ram memory is used for temporary storage of data and for the program and interrupt sta cks. the 4k bytes of this memory reside in the address range of c000-cfff hex. each memory access requires one clock cycle, for a byte or word access. no wait cycles or hold cycles are re- quired. for non-aligned word access, each memory access requires multiple clock cycles. 9.3 flash eeprom data memory the flash eeprom data memory is used for non-volatile storage of data. the 2k bytes of low endurance memory re- side in the address range of e800-efff hex and the 128 bytes of high endurance memory reside in the address range of f000-f07f hex. the cpu reads or writes this memory by using ordinary byte-wide or word-wide memory access com- mands. this memory shares the same array as the isp flash program memory. this memory also support flash memory test mode and there is no read protection or permanent write protection for this memory. 9.3.1 reading the flash eeprom data memory read accesses can oper- ate without wait cycles with a cpu clock rate of up to 20mhz in the normal mode. at higher clock rates, read accesses can operate with one wait state. the programmed number of wait cycles used (either zero or one) is controlled by a bit in the data memory control status register (dmcsr.zerows). this register is described in section 9.3.3. 9.3.2 programming before you begin programming the flash eeprom data memory, you should set the value in the eeprom data memory prescaler register. this register sets the prescaler used to generate the data memory programming clock from the system clock, as described in section 9.3.4. a code fetch from isp flash eeprom program memory is not possible while flash eeprom data memory is being pro- grammed because they share the same memory array. after the cpu performs a write to the flash eeprom data memory, the on-chip hardware completes the eeprom pro- gramming in the background. when programming begins, the on-chip hardware sets the dmcsr.dmbusy bit to 1, and also sets the mstat.pgmbusy bit to 1. when programming is completed, it resets these status bits back to 0. once the software writes to the flash eeprom data memory, it should
www.national.com 26 not attempt to access the eeprom data memory again until programming is completed and the status bit is reset to 0. the device hardware internally generates the voltages and timing signals necessary for programming. no additional power supply is required, nor any software required except to check the status bit for completion of programming. the min- imum time required to erase and reprogram a byte or word is 1.1 ms. the programmed values can be verified by using nor- mal memory read operations. the prescaler output drives a 10-bit counter to generate timing pulses and there are five re- load registers to produce various pulse widths. if a reset occurs during a programming or erase operation, the operation is terminated. the reset is extended until the flash memory returns to the idle state. therefore, the timing logic and program or erase state machine is not cleared on reset; they are cleared on power-up with the clear signal ac- tive until the bus signals are in a known state. the flash eeprom data memory does not have permanent read-protection or write-protection features like those avail- able for the eeprom program memory. however, the data memory write key register provides a way to lock the data written to the data memory. 9.3.3 data memory control and status register (dmcsr) the dmcsr register is a byte-wide, read/write register used with the flash eeprom data memory or isp flash eeprom program memory. when writing to this register, all reserved bits must be written with 0 for the memory to operate proper- ly. there are two status/control bits, as shown in the register format below. zerows zero wait-state access. when cleared (0), the flash eeprom data memory will be read in two cycles. when set (1), the flash eeprom data memory will be r ead in one cycle. dmbusy data memory busy. this bit is automatically set to 1 when the flash eeprom data memory or the isp flash eeprom program memory is busy being programmed, and cleared to 0 at all other times. (the mstat.pgmbusy is also set to 1 whenever the dmbusy bit is set to 1.) erase erase isp flash program memory page. when set (1) a valid write to the isp flash eeprom program memory will erase the entire isp flash eeprom program memory page pointed to by the write address rather than performing a write to the addressed memory location. this bit should be cleared to 0 and remain cleared after the write operation. upon reset, the dmcsr register is cleared to zero when the flash memory on the chip is in the idle state. 9.3.4 data memory prescaler register (dmpslr) the dmpslr register is a byte-wide, read/write register that selects the prescaler divider ratio for the eeprom data memory programming clock. before you write to the data memory for the first time, you should program the dmpslr register with the proper prescaler value, an 8-bit value called ftdiv. the device divides the system clock by (ftdiv+1) to produce the data memory programming clock. you should choose a value of ftdiv to produce a clock of the highest possible frequency that is equal to or just less than 200 khz. upon reset, this register is programmed by default with the value 63 hex (99 decimal), which is an appropriate setting for a 20 mhz system clock. 9.3.5 data memory start time reload register (dmstart) the dmstart register is a byte-wide read/write register that controls the program/erase start delay time. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you write to the data memory for the first time, you should pro- gram the dmstart register with the proper prescaler value, an 8-bit value called ftstart. the flash timing counter gen- erates a delay of (ftstart + 1) prescaler output clocks. the default value provides a delay time of 10 m s when the prescal- er output clock is 200khz. do not modify this register while program/erase operation is in progress. upon reset, this register resets to 01 16 when the flash mem- ory on the chip is in idle state. 9.3.6 data memory transition time reload register (dmtran) the dmtran register is a byte-wide read/write register that controls some program/erase transition times. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you write to the data memory for the first time, you should pro- gram the dmtran register with the proper prescaler value, an 8-bit value called fttran. the flash timing counter gen- erates a delay of (fttran + 1) prescaler output clocks. the default value provides a delay time of 5 m s when the prescaler output clock is 200khz. do not modify this register while pro- gram/erase operation is in progress. upon reset, this register resets to 00 16 when the flash mem- ory on the chip is in idle state. 9.3.7 data memory programming time reload register (dmprog) the dmprog register is a byte-wide read/write register that controls the programming pulse width. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you write to the data memory for the first time, you should pro- gram the dmprog register with the proper prescaler value, an 8-bit value called ftprog. the flash timing counter gen- erates a programming pulse width of (ftprog + 1) prescal- er output clocks. the default value provides a delay time of 30 m s when the prescaler output clock is 200khz. do not mod- ify this register while program/erase operation is in progress. upon reset, this register resets to 05 16 when the flash mem- ory on the chip is in idle state. 9.3.8 data memory erase time reload register (dmerase) the dmerase register is a byte-wide read/write register that controls the erase pulse width. this value is loaded into the upper 8 bits of the flash timing counter, and at the same 7 6 5 4 3 2 1 0 reserved erase dmbusy zerows reserved
27 www.national.com time, 11 2 is loaded into the lower 2 bits. before you write to the data memory for the first time, you should program the dmerase register with the proper prescaler value, an 8-bit value called fter. the flash timing counter generates a erase pulse width of 4 (fter + 1) prescaler output clocks. the default value provides a delay time of 1ms when the prescaler output clock is 200khz. do not modify this register while program/erase operation is in progress. upon reset, this register resets to 31 16 when the flash mem- ory on the chip is in idle state. for mass erase, this value should be changed to c7 16 when the flash eeprom data memory goes to idle mode. 9.3.9 data memory end time reload register (dmend) the dmend register is a byte-wide read/write register that controls the delay time after a program/erase operation. this value is loaded into the lower 8 bits of the flash timing counter, and at the same time, 00 2 is loaded into the upper 2 bits. before you write to the data memory for the first time, you should program the dmend register with the proper prescaler value, an 8-bit value called ftend. the flash tim- ing counter generates a delay of (ftend + 1) prescaler out- put clocks. the default value provides a delay time of 5 m s when the prescaler output clock is 200khz. do not modify this register while program/erase operation is in progress. upon reset, this register resets to 00 16 when the flash mem- ory on the chip is in idle state. for mass erase, this value should be changed to 13 16 . 9.3.10 data memory prescaler count register (dmpcnt) the dmpcnt register is a byte-wide read-only register that returns the value of the data memory prescaler counter. fpcnt is the flash timing prescaler present count value. 9.3.11 data memory timer count register (dmcnt) the dmcnt register is a word-wide read-only register that returns the data memory timing counter value. the reserved bits return 000000 2 . ftcnt[0:9] is the flash timer present count value. 9.3.12 data memory write key register (dmkey) the dmkey register is a byte-wide, read/write register that provides a way to lock the data contained in the eeprom data memory. upon reset, the register is automatically set to c9 hex, which is the key value. writing to the eeprom data memory is allowed as long as the dmkey register contains this value. when the register contains any value other than c9 hex, writing the eeprom data memory is disallowed. to lock the current data stored in the data memory, write an- other value (such as 00 hex) to the dmkey register. to un- lock the data memory, write the value c9 hex to the dmkey register. note: operation of this register is different in from the pgmkey register used with the program memory. it is not necessary to write the key value to dmkey every time you write to the data memory. 9.4 isp memory the in-system program memory is part of the flash memory array that contains the flash eeprom data memory. it is not possible to access the isp memory while programming the flash eeprom data memory or access the flash eeprom data memory while programming the isp memory. the 1.5k bytes of isp memory resides in the address range of e000- e5ff and is used for storing the boot rom. the rom con- tains the code that performs in-system programming, and is programmed at the factory. in isp mode, code execution starts at address e000. the isp program memory and flash eeprom data memory share the same memory array, which makes it impossible to access one type of memory while the other is being pro- grammed. the isp memory has the following features: 1.5k bytes flash eeprom program memory page size of 4 words, divided into two rows of 2 words each odd and even bytes within a page can be erased sep- arately 30 m s programming pulse width per word page mode erase with 1ms pulse, mass erase with 4ms pulse all erased memory bits read 1 fast read access time requires valid key for program and erase to proceed provide memory protection and security features for flash eeprom program memory security features may limit accesses to isp memory disable memory when address is out of range to pre- vent accessing data memory mass erase only allowed in test modes provide busy status during programming and erase read/write accesses disabled during programming/ erase programming high voltage and timing generated on- chip 9.4.1 reading the isp flash eeprom program memory read accesses can operate without wait cycles with a cpu clock rate of up to 20mhz in the normal mode. at higher clock rates, read ac- cesses can operate with one wait state. the programmed number of wait cycles used (either zero or one) is controlled by biu configuration (bcfg) register and the static zone 1 configuration (szcfg1) register. these registers are described in section 8.0. 9.4.2 user-coded programming routines all program and erase operations must be preceded by writ- ing the proper key to the program memory key register isp- key. the programming code can be in-system ram, but cannot be from isp flash eeprom program memory or flash eeprom data memory as accesses within these ranges are not permitted while isp flash eeprom program memory is being programmed. the isp flash memory is divided into 192 pages, each page containing 4 words (each 16 bits wide). each page is further divided into two rows. erase is carried out one page at a time,
www.national.com 28 whereas programming is carried out one row (or one partial row) at a time. once an erase or programming operation is started, the pg- mbusy bit in the mstat register is automatically set, and then cleared when the operation is complete. all high-voltage pulses and timing needed for programming and erasing are provided internally. the program memory cannot be access- ed while the pgmbusy bit is set. erase procedure erasing a page requires the following code sequence: 1. verify that the mstat.pgmbusy bit is cleared. 2. set the dmcsr.erase bit to 1. 3. locally disable interrupts. 4. write proper key value to the ispkey register. 5. write to any valid page to be erased. 6. re-enable interrupts disabled in step 3. 7. set the dmcsr.erase bit to 0. 9.4.3 programming procedure programming is done by writing one byte or word at a time and should be done on already erased memory. programming the isp flash eeprom program memory re- quires the following code sequence: 1. verify that the mstat.pgmbusy bit is cleared. 2. locally disable interrupts. 3. write proper key value to the ispkey register. 4. write a byte or word to the addressed location. 5. re-enable interrupts disabled in step 2. programmed values can be verified through normal read op- erations. if a reset occurs in the middle of an erase or programming op- eration, the operation is terminated. the reset is extended until the flash eeprom memory returns to the idle state. 9.4.4 erase and programming timing the program and erase timing are controlled by the flash ee- prom data memory logic. 9.4.5 memory control and protection features the last 8 bytes of the isp memory are reserved for special functions and some of these bytes provide memory protec- tion and security for the flash eeprom program memory. read and various types of write protection are provided. during the reset stretch period, bytes located at e5fe and e5ff are read out to the flctrl2 and flsec registers re- spectively. upon reset and before an instruction fetch, bytes located at e5fc and e5fd are read out to the flctrl2 and flctrl1 registers respectively. parts of flctrl2 register are loaded at different times. e5fe byte upon reset of the chip, the byte located at e5fe is read into the flctrl2 register. it can be written in the isp or test en- vironments. it can also be written in the ire environment through a byte write instruction when the write instruction is anywhere within the user boot rom area (defined above) ex- cept for the last two words. when the user boot rom area has been disabled, this word cannot be programmed in the ire environment. note that when this word is erased for re- programming, the other words in the same page must first be saved, and then re-programmed. codearea[9:8] the 2 least significant bits in address e5fe contains the two most significant bits of the 10- bit codearea field. the description of codearea is shown in the e5fc section. empty the empty status indicates if the flash ee- prom program memory array is empty or not. it is located in the 3 most significant bits in ad- dress e5fe. when two or more bits in the empty field are set, the flash eeprom pro- gram memory is empty. upon reset of the de- vice and the environment select pins are all high, the device operates in isp environment rather than ire environment. after the program memory has been filled with user code, this field should be cleared to 000 2 . 000, 001, 010, 100: program memory contains user code 011, 101, 11x: program memory is empty, do not start up in ire e5ff byte upon reset, the byte located in the e5ff address is read into the flsec register. this byte cannot be written to in the ire environment. the format of the e5ff byte is shown below: the fromrd and fromwr fields in address location e5ff respectively provide read and write security to the flash eeprom program memory array while executing instruc- tions in all environments except ire. the user should always write 0000 2 to enable security feature. 0000, 0001, 0010, 0100, 1000: security feature enabled 0011, 0101, 011x, 1001, 101x, 11xx: security feature disabled fromrd upon reset of the chip, read security is enabled and 0000 is returned in all environments except ire. the internal program code can only be ex- ecuted in the ire environment when read se- curity is activated. fromwr upon reset of the chip, write security is enabled and program and erase operations to the flash eeprom program memory in either program- ming modes are prevented. once read/write security is enabled, the odd numbered bytes from address e5f9 to e5ff cannot be erased. once a secu- rity feature has been enabled, it cannot be undone. to pre- vent the security status from being erased, the isp and data memory array cannot be mass erased. note: in flash memory test mode, this condition also pre- vents the odd numbered bytes of the high endurance flash eeprom data memory (f001 to f07f) from being erased; however, the even numbered bytes of the high endurance flash eeprom data memory (f000 to f07e) and the isp flash eeprom program memory (e000 to e5fe) can be erased. read/write is overridden through padx. 7 5 4 2 1 0 empty reserved codearea[9:8] 7 4 3 0 fromwr fromrd
29 www.national.com e5fc byte upon reset of the chip, e5fc is read into the flctrl2 reg- ister. the byte at e5fc is written in the isp or test environ- ments, or in the ire environment through a byte-write instruction when the write instruction is anywhere within the user boot rom area except for the last two words. when the user boot rom area has been disabled by having a value of 7f 16 in bootarea, this word cannot be programmed in the ire environment. note that when this word is erased for re- programming, the other words in the same page must first be saved, and then re-programmed also. the e5fc register for- mat is shown below: this byte contains the lowest 8 bits of the codearea field. when appended to the left with the lowest 2 bits in the ad- dress e5fe, it forms the complete codearea field, which provides write protection to all or part of the program memo- ry, see figure 3. when write security is not enabled and codearea does not contain the value 3ff 16 , the program memory range from (codearea 128) to 1ffff is consid- ered as protected user code area and cannot be written. the minimum protected memory range is therefore 256 bytes when codearea contains the value 3fe. note that the c000-ffff memory range is not considered as program memory and is not protected by codearea. figure 3. memory protection through codearea when codearea contains the value 3ff 16 , write protec- tion is disabled. when the user code area overlaps into the user boot rom area, the overlap area is governed by a more restrictive write protection feature, which is the user boot rom area. when write security has been enabled, the entire program memory area is already write protected in all envi- ronments. note that when a new value is written into codearea, write protection controlled by codearea is updated after the next device reset. e5fd byte upon the reset of the chip, the byte located at the e5fd ad- dress is read into the flctrl1 register. this byte can only be written in the isp or test environments but not in the ire environment. if this byte is erased for re-programming, the user must first save the other bytes in the same page, and then re-program those bytes. the format of the e5fd byte is shown below: bootarea provides write protection to part of the program memory, see figure 4. when the write security feature is not enabled and bootarea does not contain the value 7f 16 , then the program memory range from 0 to (bootar- ea*128)+127 is considered as user boot rom area and can- not be written to. the maximum protected memory range is therefore 16k-127 bytes when bootarea contains the val- ue 7e 16 . figure 4. memory protection through bootarea when bootarea contains the value 7f 16 , write protection is disabled. when write security has been enabled, the entire program memory area is already write protected in all envi- ronments. note that when a new value is written into bootarea, write protection controlled by bootarea is updated after the next device reset. 9.4.6 test mode the isp flash eeprom program memory test mode allows direct access to the flash memory from the device pins, and bypasses the cr16b core. this test mode also accesses the flash memory cells that are not used in data memory (three out of four bytes in each page). 9.4.7 flash program memory control register 1 (flctrl1) the flctrl1 register is a read-only byte-wide register. the value of this register is loaded from memory address e5fd 16 when the chip comes out of reset. the bootarea field de- fines a user boot rom area to be write protected. the flash eeprom program memory control register 1 format is shown below: when bootarea has any value other than 7f 16 , then the memory at 0 to (bootarea 128)+15 is considered as user boot rom area and is write protected. when it has a value of 7f 16 , then there is no user boot rom area to be write pro- tected. 7 0 codearea[7:0] 0000h 10000h 1ffffh address map cr16mhr6 codearea 128 protected user code area c000h non-code area, not protected protected user code area 7 6 0 reserved bootarea 7 6 0 reserved bootarea 0000h 3f80h 1ffffh address map cr16mhr6 (bootarea 128)+127 protected user boot area boot area maximum limit
www.national.com 30 9.4.8 flash program memory control register 2 (flctrl2) the flctrl2 register is a read-only word-wide register. the value of this register is loaded from memory addresses e5fc 16 and e5fe 16 when the chip comes out of reset. when the device starts execution, the empty bit indicates whether the flash eeprom program memory is empty of not, and se- lects the chip to be in ire or isp environment if the external environment pins are all high. the codearea field defines a user code area to be write protected. the flash eeprom program memory control register 2 format is shown below: empty when the bits are either 011 2 , 101 2 , 110 2 , or 111 2 , and if the devices environment select pins are all high, the device will come out of re- set in isp environment instead of ire environ- ment. codearea when it has any value other than 3ff 16 , then the memory (codearea 128) to 1ffff 16 is considered as user code area and is write pro- tected. when it has a value of 3ff 16 , then there is no code protection area to be write protect- ed. 9.4.9 flash program memory security register (flsec) the flsec register is a read-only byte-wide register. when the chip comes out of reset, the value of this register is load- ed from memory address e5ff 16 . the fromrd and fromwr field control the read and write security of the flash eeprom program memory respectively. the flash ee- prom program memory security register format is shown below: 0000, 0001, 0010, 0100, 1000: security feature enabled 0011, 0101, 011x, 1001, 101x, 11xx: security feature disabled fromrd when read security feature is enabled, the flash eeprom program memory can only be read in ire environment, but will return 0000 16 in other environments; also, erase to odd num- bered bytes from address e5f9 16 to e5ff 16 and mass erase to isp and flash eeprom data memory array are ignored unless padx is activated (see security override below). fromwr unless padx is activated (see override below), when write security feature is enabled, all fur- ther writes and erases to flash eeprom pro- gram memory, erase to odd numbered bytes from address e5f9 16 to e5ff 16 , and mass erase to isp and flash eeprom data memory array are ignored. 9.4.10 isp memory write key register (ispkey) the in-system-programming memory write key (ispkey) register is a byte-wide, write-only register. it contains the en- able key to enable writes to isp flash eeprom program memory. a value of 6a 16 must be written to this register im- mediately preceding every write to the isp flash eeprom program memory for the flash write operation to proceed, otherwise any other write operation will clear the key (the only exception is that the subsequent write is another write to this key register with the proper key, in which case the key is still set). a read always returns ff 16 . engineering note: on reset, the write enable status that is generated as a result of a write to this key register is cleared. the isp memory write key register format is shown below: ispkyval is the isp flash program memory write enable key value. 15 13 12 10 9 0 empty reserved codearea 7 4 3 0 fromwr fromrd 7 0 ispkyval
31 www.national.com 10.0 interrupts the interrupt control unit (icu31l) receives interrupt re- quests from internal and external sources and generates in- terrupts to the cpu. interrupts from the timers, usarts, microwire/spi interface, multi-input wake-up, and a/d converter are all maskable interrupts. the highest-priority in- terrupt is the non-maskable interrupt (nmi), which is trig- gered by a falling edge received on the nmi input pin. 10.1 interrupt operation an exception is an event that temporarily stops the normal flow of program execution and causes execution of a sepa- rate service routine. upon completion of the service routine, execution of the interrupted program continues from the point at which it was stopped. there are two kinds of exceptions, called traps and inter- rupts . a trap is the result of some action or condition in the program itself, such as execution of an exception (excp) in- struction. an interrupt is a cpu-external event, such as a sig- nal received on a multi-input wake-up input or a request from an on-chip peripheral module for service. the operation of traps is beyond the scope of this data sheet. for information on traps, and for additional detailed informa- tion on interrupts not provided in this data sheet, please refer to the compactrisc cr16b programmer's reference man- ual. 10.1.1 interrupt operation summary when an interrupt occurs, the on-chip hardware performs the following steps: 1. decrements the interrupt stack point (isp) by four. 2. saves the contents of the program counter (pc) and processor status register (psr) on the interrupt stack. 3. clears the i, p, and t bits in the processor status regis- ter (psr). these are the global maskable interrupt en- able bit, trace trap pending bit, and trace bit, respectively. 4. reads the interrupt vector from the interrupt vector reg- ister (ivct). 5. combines the interrupt vector with the value in the inter- rupt base (intbase) register to obtain an address in the interrupt dispatch table, and loads the dispatch ta- ble entry into the program counter (pc). from this point onward, the cpu executes the interrupt ser- vice routine. the service routine ends with a return from ex- ception (retx) instruction. this returns the cpu to the interrupted program. the cpu restores the contents of the pc and psr registers from the stack and increments the in- terrupt stack pointer by four. 10.1.2 service routine addresses when an interrupt or trap occurs, the cpu executes a service routine. there are different service routines for different inter- rupts and traps. each service routine may reside anywhere in program memory. the starting addresses of the service routines are contained in a table called the dispatch table. entries in the table are organized in the order shown in ta b l e 1 0 . each entry in the dispatch table consists of two bytes that provide bits 1 through 16 of the starting address of the corre- table 10 dispatch table entries 0: reserved 1: nmi 2: reserved 3: reserved 4: reserved 5: svc (supervisor call trap) 6: dvc (divided by zero trap) 7: flg (flag trap) 8: bpt (breakpoint trap) 9: trc (trace trap) 10: und (undefined instruction trap) 11: reserved 12: reserved 13: reserved 14: reserved 15: reserved 16: int0 (reserved) 17: int1 (flash eeprom program memory) 18: int2 (reserved) 19: int3 (reserved) 20: int4 (reserved) 21: int5 (adc) 22: int6 (miwu interrupt 3) 23: int7 (miwu interrupt 2) 24: int8 (miwu interrupt 1) 25: int9 (miwu interrupt 0) 26: int10 (usart 2 tx) 27: int11 (usart 1tx) 28: int12 (reserved) 29: int13 (microwire/spi rx/tx) 30: int14 (access.bus) 31: int15 (usart 2 rx) 32: int16 (usart 1 rx) 33: int17 (reserved) 34: int18 (can) 35: int19 (reserved) 36: int20 (reserved) 37: int21 (reserved)
www.national.com 32 sponding service routine. the full 21-bit address of a service routine is reconstructed by adding a leading 0 and a trailing 0 to the 16-bit table entry. the intbase register is a pointer to the dispatch table. upon reset, the initialization software must write the starting address of the dispatch table to the intbase register, a 21- bit register with the five most significant bits and the least sig- nificant bit always equal to 0. it is typically kept in the flash eeprom program memory. the dispatch table is 48 words long. each interrupt or trap source has an associated vector num- ber ranging from 0 to 31, as indicated in table 10. when an interrupt occurs, the hardware multiplies the vector by 2, adds the result to the contents of the intbase register, and uses the resulting address to obtain the service routine start- ing address from the corresponding entry in the dispatch ta- ble. this address is placed in the program counter so that the cpu begins executing the interrupt service routine. figure 5 summarizes the method used by the device to gen- erate the starting address of a service routine. 10.1.3 stack usage when an interrupt occurs, the cpu automatically preserves the contents of the program counter (pc) and processor status register (psr) by pushing them on the interrupt stack and decrementing the interrupt stack pointer by four. the service routine ends with a return from exception (retx) in- struction, which returns control to the interrupted program by restoring the pc and psr values and incrementing the inter- rupt stack pointer (isp) by four. prior to using any interrupts, the interrupt stack pointer (isp) must be initialized so that it points to a space in ram where the interrupt stack will be kept. the stack grows downward in memory (toward address zero) when an interrupt occurs and items are pushed onto the stack. the stack shrinks upward in memory when an interrupt service routine ends and items are popped from the stack. many routines need to use the general-purpose registers r0 through r13. to preserve the existing register contents, a routine can save register contents on the program stack upon start of the routine and restore the register contents prior to completion of the routine. the software can also use the pro- gram stack to transfer data parameters from one routine to another when the parameters are too large to easily fit into the registers. a high-level language typically allocates the lo- cal (non-static) variables on the stack. the pointer to the program stack is the sp register, which must be initialized prior to any register save/restore opera- tions or data transfer operations. using the program stack, an interrupt routine needs to initially save the contests of all reg- isters that it uses, and restore those register contents before returning to the interrupted program. 10.2 non-maskable interrupt a non-maskable interrupt is triggered by a falling edge on the nmi input pin, which generates a software trap. the nmi pin is an asynchronous input with schmitt trigger characteristics and an internal synchronization circuit. therefore, no exter- nal synchronizing is needed. upon reset, the non-maskable interrupt is disabled and should remain disabled until the software initializes the inter- rupt table, interrupt base, and interrupt stack pointer. it can be enabled by setting either of two control bits in the external nmi control/status (exnmi) register. the two bits are called the en (enable) bit and the enlck (enable and lock) bit. the en bit enables the nmi trap until an nmi trap event or a reset occurs. an nmi trap automatically resets the en bit. us- ing this bit to enable the nmi trap is intended for applications where the nmi pin is toggled frequently but nested nmi traps are not needed. the trap service routine should re-enable the nmi trap by setting the en bit before returning to the main program. 38: int22 (reserved) 39: int23 (vtud interrupt request 4) 40: int24 (vtud interrupt request 3) 41: int25 (vtud interrupt request 3) 42: int26 (vtud interrupt request 1) 43: int27 (t2b timer 2 interrupt b) 44: int28 (t2a timer 2 interrupt a) 45: int29 (t1b timer 1interrupt b) 46: int30 (t1a timer 1interrupt a) 47: int31 (rti timer 0) table 10 dispatch table entries figure 5. intbase ~ ~ ~ ~ non-maskable interrupt reserved supervisor call trap divide by zero trap flag trap breakpoint trap trace trap undefined instruction maskable interrupts nmi reserved reserved svc dvz flg bpt trc und reserved reserved ise intn 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 127 in-system emulator 31 0 reserved reserved dbg debug trap interrupt tr a p
33 www.national.com the enlck bit enables the nmi trap and locks it in the en- abled state. in other words, it leaves the nmi trap enabled even after the trap occurs. it can be cleared only by a reset operation. after the bit is set, an nmi trap is triggered by each falling edge on the nmi pin, allowing nested nmi traps. to use the en bit, the enlck must remain cleared to 0. oth- erwise, the en bit is ignored. 10.3 maskable interrupts maskable interrupts can be enabled or disabled under soft- ware control. there are 31 level-triggered maskable interrupt sources (including some reserved for future expansion), or- ganized into levels of priority. if more than one interrupt event occurs at any given time, the interrupt source with the highest priority is serviced first. the others must wait until the high- est-priority interrupt is serviced and is no longer pending. figure 11 lists the maskable interrupt sources of the device in order of priority, from the highest-priority interrupt (irq31) to the lowest (irq0). to enable a maskable interrupt, the enable bit must be set in the applicable peripheral module and also in the appropriate interrupt and enable mask register, ienam0 or ienam1. in addition, both the global maskable interrupt enable bit (i) and the local maskable interrupt enable bit (e) must be set to 1 in the psr register. if either one of these bits is 0, then all maskable interrupts are disabled. the cr16b core sup- ports irq0, but icu31l reserves irq0 so that it is not con- nected to any interrupt source. both the e bit and i bit can be controlled with the load pro- cessor register (lpr) instruction. in addition, the e bit is easily changed by executing the enable interrupts (ei) or dis- able interrupts (di) instruction. using the ei and di instruc- tions avoids the possibility of an interrupt occurring within a read-modify-write operation on the psr register. 10.4 interrupt registers the interrupt control unit uses the following interrupt control and status registers: non-maskable interrupt status register (nmistat) non-maskable interrupt status monitor reg. (nmimn- tr) external nmi control/status register (exnmi) interrupt enable and mask register 0 (ienam0) interrupt enable and mask register 1 (ienam1) interrupt vector register (ivct) interrupt status register 0 (istat0) interrupt status register 1 (istat1) interrupt debug register (idbg) the following cpu core registers are also used in processing interrupts: interrupt stack pointer (isp) interrupt base register (intbase) 10.4.1 non-maskable interrupt status register (nmistat) the nmistat register is a byte-wide, read-only register that holds the current pending status of the non-maskable inter- rupt (nmi). this register is cleared upon reset. it is also cleared each time it is read. the register format is shown be- low. ext external non-maskable interrupt request. when set to 1 by the hardware, it indicates an external non-maskable interrupt request has occurred. see the description of the exnmi register below for more information. 10.4.2 external nmi control/status register (exnmi) the exnmi register is a byte-wide, read/write register that shows the current state of the nmi pin and also allows the nmi trap to be enabled by setting either the en bit or the en- lck bit. both of these bits are cleared upon reset. when the software writes to this register, it must write 0 to all reserved bit positions for the device to function properly. en, enlck, and tst are cleared upon reset. the register format is shown below. table 11 maskable interrupt priority list interrupt request source irq31 rti (timer 0), highest priority irq30 t1a (timer 1 input a) irq29 t1b (timer 1 input b) irq28 t2a (timer 2 input a) irq27 t2b (timer 2 input b) irq26 vtua (vtu interrupt request 1) irq25 vtub (vtu interrupt request 2) irq24 vtuc (vtu interrupt request 3) irq23 vtud (vtu interrupt request 4) irq22-irq19 reserved irq18 can irq17 reserved irq16 usart1 rx irq15 usart2 rx irq14 access.bus irq13 microwire/spi rx/tx irq12 reserved irq11 usart1 tx irq10 usart2 tx irq9 miwu16 interrupt 0 irq8 miwu16 interrupt 1 irq7 miwu16 interrupt 2 irq6 miwu16 interrupt 3 irq5 adc irq4-irq2 reserved irq1 flash program memory irq0 reserved, lowest priority 7 6 5 4 3 2 1 0 reserved ext
www.national.com 34 en enable nmi trap. when set to 1, nmi traps are enabled and falling edge on the nmi pin gener- ates a nmi trap. each occurrence of an nmi trap automatically clears the en bit. the trap service routine should set the en bit to 1 before returning control to the interrupted program. when en is cleared to 0, nmi traps are dis- abled unless they are enabled with the enlck bit. when the enlck bit is set to 1, the en bit is ignored. pin nmi pin. this bit shows the current state of the nmi input pin (without logical inversion). a 1 in- dicates a high level and a 0 indicates a low level on the pin. this is a read-only bit. in a write op- eration, the value written to this bit position is ignored. enlck enable and lock nmi trap. when set to 1, nmi traps are enabled and locked in the enabled state. each falling edge on the nmi pin gener- ates a nmi trap, even if a previous nmi trap has occurred and is still being processed. when enlck is cleared to 0, nmi traps are disabled unless they are enabled with the en bit. 10.4.3 interrupt vector register (ivct) the ivct register is a byte-wide, read-only register that con- tains the encoded value of the enabled and pending maskable interrupt with the highest priority. the on-chip hard- ware automatically updates this field whenever there is a change in the highest-priority enabled and pending maskable interrupt. the cpu reads this register during an interrupt ac- knowledge core bus cycle to determine where to begin exe- cuting the interrupt service routine. the register contents are guaranteed to be valid at that time. the register is not guar- anteed to contain valid data during a hardware update oper- ation. the register format is shown below. intvect interrupt vector. this 6-bit field contains the en- coded value of the enabled and pending maskable interrupt with the highest priority. for example, if interrupts irq1 and irq6 are both enabled and pending, the higher-priority inter- rupt is irq6. as a result the 6 bit interrupt vec- tor is 010110. 10.4.4 interrupt enable and mask register 0 (ienam0) the ienam0 register is a word-wide, read/write register that enables or disables the individual interrupts irq0 through irq15. the register format is shown below. a bit set to 1 enables the corresponding interrupt. a bit cleared to 0 disables the corresponding interrupt. upon reset, this register is initialized to ffff hex. 10.4.5 interrupt enable and mask register 1 (ienam1) the ienam0 register is a word-wide, read/write register that enables or disables the individual interrupts irq16 through irq31. the register format is shown below. a bit set to 1 enables the corresponding interrupt. a bit cleared to 0 disables the corresponding interrupt. upon reset, this register is initialized to ffff hex. 10.4.6 interrupt status register 0 (istat0) the istat0 register is a word-wide, read-only register that in- dicates which maskable interrupt inputs to the icu31l (irq0 through irq15) are currently active. the register format is shown below. ist(15:0) interrupt status bits. each bit indicates the cur- rent status of an interrupt input to the icu31l, corresponding to interrupts irq0 through irq15. a bit set to 1 indicates an active inter- rupt input, even when the interrupt is masked out by the ienam0 register. a bit cleared to 0 indicates an inactive interrupt input. 10.4.7 interrupt status register 1 (istat1) the istat1 register is a word-wide, read-only register that in- dicates which maskable interrupt inputs to the icu31l (irq16 through irq31) are currently active. the register for- mat is shown below. ist(31:16) interrupt status bits. each bit indicates the cur- rent status of an interrupt input to the icu31l, corresponding to interrupts irq16 through irq31. a bit set to 1 indicates an active inter- rupt input, even when the interrupt is masked out by the ienam0 register. a bit cleared to 0 indicates an inactive interrupt input. 10.4.8 interrupt debug register the idbg register is a word-wide read-only register, which contains various status information of the icu31l. the low- est 6 bits contain the intvect value during the last read from address fe00. the next 6 bits contain the intvect val- ue when a maskable interrupt request is sent to the cr16b core. upon reset, this register is set to 0000 hex. 10.5 interrupt programming procedures the following subsections provide information on initializing the device for interrupts, clearing interrupts, and nesting in- terrupts. 10.5.1 initialization upon reset, all interrupts are disabled. to program the device for interrupt operation and to enable interrupts, use the fol- lowing procedure in the application software: 7 6 5 4 3 2 1 0 reserved enlck pin en 7 6 5 4 3 2 1 0 0 0 intvect 15 0 iena(15:0) 15 0 iena(31:16) 15 0 ist(15:0) 15 0 ist(31:16)
35 www.national.com 1. set the interrupt stack pointer (isp) 2. load the intbase register so that it points to the base of the interrupt dispatch table. 3. perform any required preparation steps for the interrupt service routines. 4. initialize the peripheral devices that can generate inter- rupts and set their respective interrupt enable bits. 5. set the relevant bits in the interrupt mask registers (ienam0 and ienam1) note: the miwu16 interrupts have no local interrupt en- able bits, which means you can only disable the miwu16 interrupts if you clear the specific bits in the ie- nam register. 6. use the load processor register (lpr) instruction to set i bit in the psr register. 7. when the device is ready to execute interrupts, set the e bit in the psr register by executing the enable interrupts (ei) instruction. once maskable interrupts are enabled by setting the e and i bits, you can disable and re-enable all maskable interrupts lo- cally by using the enable interrupts (ei) and disable inter- rupts (di) instructions, which set and clear the e bit. 10.5.2 clearing interrupts clearing an interrupt request before it is serviced may cause a spurious interrupt because the cpu may detect an inter- rupt not reflected in the interrupt vector (ivct) register. to ensure reliable operation, clear interrupt requests only while interrupts are disabled. changing the polarity of an interrupt input (for example, in the multi-input wake-up module) can cause a spurious interrupt, and therefore should be done only while interrupts are dis- abled. for the same reason, clearing an enable bit in a peripheral module should be carried out only while the interrupt is dis- abled. 10.5.3 nesting interrupts interrupts may be nested, or in other words, an interrupt ser- vice routine can itself be interrupted by a different interrupt source. there is no hardware limitation on the number of in- terrupt nesting levels. however, the interrupt stack must not be allowed to overflow its allocated memory space. unless specifically enabled by the software, nested interrupts will not occur. w hen the cpu acknowledges an interrupt, the i bit in the psr register is automatically cleared to 0 for the duration of the service routine, disabling any further maskable interrupts. to allow nested interrupts, an interrupt service routine should first set or clear the respective interrupt enable bits to specify which peripherals will be allowed to interrupt the current ser- vice routine. the present interrupt routine should be disabled (or interrupt pending bit cleared). the service routine should then set the psr.i bit to 1, thus enabling maskable interrupts. this bit can be controlled with the store processor register (spr) and load processor register (lpr) instructions. note: clearing the pending bit of the current interrupt should not be immediately followed by enabling further interrupts by setting the i bit in the psr register. wait states must be inserted into the software after clearing the interrupt pending bit and be- fore another interrupt. placing a nop instruction will perform this instruction. this is because the instruction which resets the pending bit may not yet be finished when the interrupts are already enabled again by setting the i bit in the psr reg- ister. to avoid this situation the user has to make sure that pri- or to enabling the interrupt an additional instruction is inserted. this could look like the example below: sbiti $0, t1icrl # clear pending bit nop # nop instruction movw $0x0a00, r0 # enable further interrupts lpr r0, psr a cbiti or sbiti instruction may be used to clear the inter- rupt pending bit. in such cases, a spurious interrupt may oc- cur.
www.national.com 36 11.0 power management the power management module (pmm) improves the effi- ciency of the device by changing the operating mode (and therefore the power consumption) according to the required level of device activity. the device can operate in any of four power modes: active power save idle halt table 12 summarizes the main properties of the four operat- ing modes: the state of the high-frequency oscillator (on or off), the type of clock used by most modules, and the clock used by the timing and watchdog module (twm). the low-frequency oscillator continues to operate in all four modes and power must be provided continuously to the de- vice power supply pins. in the halt mode, however, the inter- nal slclk does not toggle, and as a result, the twm timer and watchdog module do not operate. for the power save and idle modes, the high-frequency oscillator can be turned on or off under software control, as long as the low-frequency oscillator is used. 11.1 active mode in the active mode, all device modules are fully operational. this is the operating mode upon reset. most device modules use the clock generated by the high-frequency clock oscilla- tor. the clock rate is determined by the external crystal net- work. power consumption in the active mode can be reduced by selectively disabling unused modules and/or by executing the wait instruction. when wait is executed, the core stops ex- ecuting new instructions and waits for an interrupt. 11.2 power save mode in the power save mode, all device modules operate off the low-frequency clock. if the low-frequency clock is generated from an external crystal network, the high-frequency clock oscillator can be turned off to further reduce power consump- tion. all on-chip modules continue to operate in the power save mode, with the slclk acting as their system clock. if this mode is entered by using the wait command, the cpu is in- active and waits for an interrupt to wake up. otherwise, cpu continues to function normally at the lower frequency of the slow clock. the low frequency of the clock in power save mode limits the operation of modules such as the usarts, microwire in- terface, a/d converter, and timers because they are driven by the slow clock rather than the normal high-speed clock. in order to work properly in power save mode, modules that perform real-time operations (such as a usart baud rate generator) must be reprogrammed to use the slower clock. to reduce power consumption as much as possible, the pro- gram should execute a wait instruction during periods of cpu inactivity. 11.3 idle mode in the idle mode, the clock is stopped for most of the device. only the power management module and timing and watch- dog module continue to operate. both of these modules use the slow clock in this mode. 11.4 halt mode in the halt mode, all device clocks are disabled and the high- frequency oscillator is shut off. in this mode, the device con- sumes the least possible power while maintaining the device memory and register contents. the low-frequency oscillator continues to operate in this mode, but with very low power consumption due to its power-optimized design. 11.5 clock inputs and reset configuration the system uses a high frequency clock active mode. the source of this clock in the device is a high frequency crystal oscillator. the oscillating high frequency clock (ohfc) in- put indicates to the power management module (pmm) when this clock is stable and therefore usable. the clock can be used when ohfc is set to 1. the pmm does not use the high frequency clock when ohfc is set to 0. ohfc can be the output of a clock monitor or a strapped input signal to this module. the low frequency clock is used in power save mode as the system clock source. in idle mode, it is used as the clock source for the pmm and the twm, both of which remain clocked. the clock source may be a low frequency clock os- cillator or the prescaler from the high frequency clock. the oscillating low frequency clock (olfc) input indicates to the pmm when the clock is stable and therefore usable. when olfc is set to 1, it indicates that the clock can be used. when olfc is set to 0, the pmm does not use the low frequency clock. olfc is generated by the slow clock good output of the dual clock and reset module (clk2res). while in reset (i.e., the reset signal is active), the pmm out- puts the clock as long as the clock selected for use upon re- set is stable (ohfc or olfc are 1). if the clock selected is not stable, the pmm clock output remains low. 11.6 switching between power modes switching from a higher to a lower power consumption mode is accomplished by writing an appropriate value to the power management control/status register (pmcsr). switching from a lower power consumption mode to the active mode is usually triggered by a hardware interrupt. figure 6 shows the four power consumption modes and the events that trigger a transition from one mode to another. some of the power-up transitions are based on the occur- rence of a wake-up event. an event of this type can be either table 12 power mode operating summary mode high-frequency oscillator clock used twm clock active on main clock slow clock power save on or off slow clock slow clock idle on or off none slow clock halt off none none
37 www.national.com a maskable interrupt or a non-maskable interrupt (nmi). all of the maskable hardware wake-up events are gathered and processed by the multi-input wake-up module, which is ac- tive in all modes. once a wake-up event is detected, it is latched until an interrupt acknowledge cycle occurs or a reset is applied. a wake-up event causes a transition to the active mode and restores normal clock operation, but does not start execution of the program. it is the interrupt service routine associated with the wake-up source (miwu16 or nmi) that causes actu- al program execution to resume. 11.6.1 power management control/status register (pmcsr) the power management control/status register (pmcsr) is a byte-wide, read/write register that controls the operating power mode (active, power save, idle, or halt) and enables or disables the high-frequency oscillator in the power save and idle modes. the two most significant bits, olfc and ohfc, are read-only status bits controlled by the hardware. upon reset, the non-reserved bits of this register are cleared. the format of the register is shown below. psm power save mode. when this bit is 0, the de- vice operates in the active mode. writing a 1 to this bit position puts the device into the power save mode, either immediately or upon execu- tion of the next wait instruction, depending on the wbpsm bit. the psm bit can be set and cleared by the soft- ware. it is also cleared by the hardware when a hardware wake-up event is detected. dhf disable high-frequency oscillator. this bit en- ables (0) or disables (1) the high-frequency os- cillator in the power save or idle mode. (the high-frequency oscillator is always enabled in active mode and always disabled in halt mode, regardless of this bit settings.) the dhf bit is cleared automatically when a hardware wake- up event is detected. idle idle mode. when this bit is set and the device is in power save mode, the device enters the idle mode upon execution of a wait instruc- tion. in order to enter the idle mode directly from the active mode, the wbpsm bit must be set before the wait instruction is executed. the idle bit can be set and cleared by the soft- ware. when a hardware wake-up event is de- tected, this bit is cleared automatically and the device returns to the active mode. halt halt mode. when this bit is set and the device is in idle mode, the device enters the halt mode upon execution of a wait instruction. in order to enter the halt mode directly from the active mode, the wbpsm bit must be set before the wait instruction is executed. the halt bit can be set and cleared by the soft- ware. when a hardware wake-up event is de- tected, this bit is cleared automatically and the device returns to the active mode. wbpsm wait before entering power save mode. when the cpu writes a 1 to the psm bit, the wbpsm determines when the transition from active to power save mode is done. if the wbpsm bit is 0, the switch to power save mode is initiated immediately; the psm bit in the register is set to 1 upon completion of the switch to power save mode. if the wbpsm bit is 1, the device continues to operate in active mode until the next wait instruction, and then enters the power save mode. in this case, the psm bit is set to 1 immediately, even if a wait instruction has not yet been executed. in the active mode, the wbpsm bit must be set in order to enter the idle or halt mode. ohfc oscillating high-frequency clock. this read- only bit indicates the status of the high-frequen- cy clock. if this bit is 1, the high-frequency clock is available and stable. if this bit is 0, the high- frequency clock is either disabled, not available to the power management module, or operat- ing but not yet stable. the device can switch to the active mode only when this bit is 1. olfc oscillating low-frequency clock. this read- only bit indicates the status of the low-frequen- cy (slow) clock. if this bit is 1, it indicates that the slow clock is running and stable. the slow clock can be either the prescaled fast clock (the default) or the external oscillator (if selected). the dual clock module will not allow a transi- tion to the slow crystal mode unless the slow crystal is operating, so this bit should be 1 un- der normal circumstances. the device can switch from the active mode to the power save or idle mode only if the olfc bit is 1. there is no such restriction on switch- ing to the halt mode. 11.6.2 active to power save mode a transition from the active mode to the power save mode is accomplished by writing a 1 to the pmcsr.psm bit. the transition to power save mode is either initiated immediately or upon execution of the next wait instruction, depending on the pmcsr.wbpsm bit. figure 6. power modes and transitions 7 6 5 4 3 2 1 0 olfc ohfc wbpsm reserved halt idle dhf psm active power save idle halt idle =1 and wait psm =1 hw event or psm =0 halt =1 hw event and wait reset hw event
www.national.com 38 for an immediate transition to power save mode (pmc- sr.wbpsm=0), the cpu continues to operate using the low- frequency clock. the pmcsr.psm bit is set to 1 when the transition to the power save mode is completed. for a transition upon the next wait instruction (pmc- sr.wbpsm=1), the cpu continues to operate in the active mode until it executes a wait instruction. upon execution of the wait instruction, the device enters the power save mode and the cpu waits for the next interrupt event. in this case, the pmcsr.psm bit is set to 1 when it is written, even before the wait instruction is executed. 11.6.3 entering the idle mode entry into the idle mode is accomplished by writing a 1 to the pmcsr.idle bit and then executing a wait instruction. the idle mode can be entered only from the active or power save mode. for entry from the active mode, the pmc- sr.wbpsm bit must be set before the wait instruction is ex- ecuted. 11.6.4 disabling the high-frequency clock in systems where the low-frequency crystal is available and is used to generate the slow clock (slclk), power con- sumption can be reduced further in the power save or idle mode by disabling the high-frequency clock. this is accom- plished by writing a 1 to the pmcsr.dhf bit before executing the wait instruction that puts the device in the power save or idle mode. the high-frequency clock is turned off only after the device enters the power save or idle mode. the cpu operates on the low-frequency clock in power save mode. it can turn off the high-frequency clock at any time by writing a 1 to the pmcsr.dhf bit. the high-frequency oscillator is always enabled in active mode and always disabled in halt mode, regardless of the pmcsr.dhf bit setting. immediately following power-up and entry into the active mode, the software must wait for the low-frequency clock to become stable before it can put the device in the power save mode. it should monitor the pmcsr.olfc bit for this pur- pose. once this bit is set to 1, the slow clock is stable and the power save mode can be entered. 11.6.5 entering the halt mode entry into the halt mode is accomplished by writing a 1 to the pmcsr.halt bit and then executing a wait instruction. the halt mode can be entered only from the active or power save mode. for entry from the active mode, the pmc- sr.wbpsm bit must be set before the wait instruction is ex- ecuted. 11.6.6 software-controlled transition to active mode a transition from the power save mode to the active mode can be accomplished by either a software command or a hardware wake-up event. the software method is to write a 0 to the pmcsr.psm bit. the value of the register bit changes only after the transition to the active mode is completed. if the high-frequency oscillator is disabled for power save op- eration, the oscillator must be enabled and allowed to stabi- lize before the transition to active mode. to enable the high- frequency oscillator, the software writes a 0 to the pmc- sr.dhf bit. before writing a 0 to the pmcsr.psm bit, the software should first monitor the pmcsr.ohfc bit to deter- mine whether the oscillator has stabilized. 11.6.7 wake-up transition to active mode a hardware wake-up event switches the device directly from power save, idle, or halt mode to the active mode. hardware wake-up events are: ? a non-maskable interrupt (nmi) ? a valid wake-up event on a multi-input wake-up channel when a wake-up event occurs, the on-chip hardware per- forms the following steps: 1. clears the pmcsr.dhf bit, thus enabling the high-fre- quency clock (if it was disabled). 2. waits for the pmcsr.ohfc bit to be set, which indi- cates that the high-frequency clock is operating and is stable. 3. switches the device into the active mode. 11.6.8 power mode switching protection the power management module has several mechanisms to protect the device from malfunctions caused by missing or unstable clock signals. the pmcsr.ohfc and pmcsr.olfc bits indicate the cur- rent status of the high-frequency and low-frequency clock os- cillators, respectively. the software can check the appropriate bit before it changes to an operating mode that requires the clock. a status bit set to 1 indicates an operating, stable clock. a status bit cleared to 0 indicates a clock that is disabled, not available, or not yet stable. during a power mode transition, if there is a request to switch to a mode that uses clock with its status bit cleared to 0, the switch is delayed until that bit is set to 1 by the hardware. when the system is built without an external crystal network for the low-frequency clock, the high-frequency clock is divid- ed by a prescaler factor to produce the low-frequency clock. in this situation, the high-frequency clock is disabled only in the halt mode, and cannot be disabled for the power save or idle mode, regardless of the software command issued . without an external crystal network for the low-frequency clock, the device comes out of the halt or idle mode and en- ters the active mode with the high-speed oscillator used as the clock. the device can still enter the power save from the active mode by using the high-frequency-clock divider to generate the slow clock (pmcsr.dhf=0). note: for correct operation in the absence of a low-frequen- cy crystal, the x2cki pin must be tied low (not left floating) so that the hardware can detect the absence of the crystal.
39 www.national.com 12.0 dual clock and reset the dual clock and reset module (clk2res) generates a high-speed main system clock from an external crystal net- work and a slow clock (32.768 khz or other rate) for operating the device in power save mode. it also provides the main system reset signal, a power-on reset function, a main clock prescaler to generate two additional low speed clo cks, and an 32khz oscillator start-up delay. figure 7 is block diagram of the dual clock and reset mod- ule. 12.1 external crystal network an external crystal network is required at pins x1cki and x1cko for the main clock. a similar external crystal network may be used at pins x2cki and x2cko for the slow clock in packages that have these pins. if an external crystal network is not used for the slow clock, the clock is generated by divid- ing the fast main clock. the crystal oscillator you choose may require external com- ponents different from the ones specified above. in that case, consult with nationals engineer for the component specifica- tions the crystals and other oscillator components should be placed close to the x1cki/x1cko and x2cki/x2cko device input pins to keep the printed trace lengths to an absolute minimum. figure 8 shows the required crystal network at x1cki/ x1cko and optional crystal network at x2cki/x2cko. table 13 shows the component specifications for the main crystal network and table 14 shows the component specifi- cations for the 32.768 khz crystal network. figure 7. dual clock and reset module block diagram 8-bit 14-bit timer 6-bit timer start-up-delay start-up-delay preset preset power-on-reset system reset stop main osc in reset x1cki x1cko x2cki x2cko main osc. 32khz osc. stop main osc. stop 32khz osc. main clk good main clk low speed clk good low speed clk stop low speed clk time-out time-out mux prescaler div. by-2 4-bit prescaler 2 low speed clk 4-bit prescaler outputs
www.national.com 40 choose capacitor component values in the tables obtain the specified load capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and pack- age (which can vary from 0 to 8 pf). as a guideline, the load capacitance is: c l = (c 1 * c 2 )/(c 1 +c 2 ) + c parasitic c 2 > c 1 c 1 can be trimmed to obtain the desired load capacitance. the start-up time of the 32.768 khz oscillator can vary from one to six seconds. the long start-up time is due to the high q value and high serial resistance of the crystal necessary to minimize power consumption in power save mode. 12.2 main system clock the main system clock is generated by the main oscillator. it can be stopped by the power management module to reduce power consumption during periods of reduced activity. when the main clock is restarted, a 14-bit timer generates a good main clk signal after a start-up delay of 32,768 clock cycles. this signal is an indicator that the main clock oscillator is sta- ble. the stop main osc signal from the power management module stops and starts the main oscillator. when this signal is asserted, it presets the 14-bit timer to 3fff hex and stops the main oscillator. when the signal goes inactive, the main oscillator starts and the 14-bit timer counts down from its pre- set value. when the timer reaches zero, it stops counting and asserts the good main clk signal. 12.3 slow system clock the slow (32.768 khz) clock is necessary for operating the device in power save modes and to provide a clock source for modules such as the timing and watchdog module. the slow clock operates in a manner similar to the main clock. the stop slow osc signal from the power manage- ment module stops and starts the slow oscillator. when this signal is asserted, it presets a 6-bit timer to 3f hex and dis- ables the slow oscillator. when the signal goes inactive, the slow oscillator starts and the 6-bit timer counts down from its preset value. when the timer reaches zero, it stops counting figure 8. external crystal network table 13 component values of the high frequency crystal circuit component parameters values values values values values tolerance oscillator resonance frequency ty p e max. serial resistance max. shunt capacitance load capacitance 4 mhz at- c u t 75 w 4 pf 12 pf 12 mhz at- c u t 35 w 4 pf 15 pf 16 mhz at- c u t 35 w 4 pf 15 pf 20 mhz at- c u t 35 w 4 pf 20 pf 24 mhz at- c u t 35 w 4 pf 20 pf n/a crystal resistor r1 1 m w 1 m w 1 m w 1 m w 1 m w 5% resistor r2 0 w 0 w 0 w 0 w 0 w 5% capacitor c1, c2 22 pf 20 pf 20 pf 20 pf 20 pf 20% x1cki / x2cki x1cko / x2cko r1 r2 xtal c2 c1 table 14 component values of the low frequency crystal circuit component parameters values tolerance oscillator resonance frequency ty p e maximum serial resistance maximum shunt capacitance load capacitance 32.768khz parallel n-cut or xy-bar 40 k w 2 pf 9-13 pf n/a crystal resistor r1 10-20 m w 5% resistor r2 4.7 k w 5% capacitor c1, c2 20 pf 20%
41 www.national.com and asserts the good low speed clk signal, thus indicating that the slow clock is stable. for systems that do not require a reduced power consump- tion mode, the external crystal network may be omitted for the slow clock. in that case, the slow clock can be created by dividing the main clock by a prescaler factor. the prescaler circuit consists of a fixed divide-by-2 counter and a program- mable 8-bit prescaler register. this allows a choice of clock divisors ranging from 2 to 512. the resulting slow clock fre- quency must not exceed 100 khz. a software-programmable multiplexer selects either the pres- caled main clock or the 32.768 khz oscillator as the slow clock. upon reset, the prescaled main clock is selected, en- suring that the slow clock is always present initially. selection of the 32.768 khz oscillator as the slow clock disables the clock prescaler, which allows the clk1 oscillator to be turned off during power-save operation, thus reducing power con- sumption and radiated emissions. this can be done only if the module detects a togging low-speed oscillator. if the low- speed oscillator is not operating, the prescaler remains avail- able as the slow clock source. 12.4 power-on reset the power-on reset circuit generates a system reset signal upon power-up and holds the signal active for a period of time to allow the crystal oscillator to stabilize. the circuit detects a power turn-on condition, which presets the 14-bit timer to 3fff hex. once oscillation starts and the clock becomes ac- tive, the timer starts counting down. when the count reaches zero, the 14-bit timer stops counting and the internal reset signal is deactivated (unless the reset pin is held low). the circuit sets a power-on reset flag bit upon detection of a power-on condition. the cpu can read this flag to determine whether a reset was caused by a power-up or by the reset input. note: power-on reset circuit cannot be used to detect a drop in the supply voltage. 12.5 external reset an active-low reset input pin called reset allows the device to be reset at any time. when the signal goes low, it gener- ates an internal system reset signal that remains active until the reset signal goes high again. 12.6 dual clock and reset registers the dual clock and reset module (clk2res) contains two registers: the clock and reset control register (crctrl) and the slow clock prescaler register (prssc). 12.6.1 clock and reset control register (crctrl) clock and reset control register (crctrl) is a byte-wide read/write register that contains the power-on reset flag and selects the type of slow clock. the register format is shown below. sclk slow clock select. when this bit is set to 1, the 32.728 khz oscillator is used for the slow clock. when this bit is cleared to 0, the prescaled main clock is used for the slow clock. upon re- set, this bit is cleared to 0. por power-on reset. this bit is set to 1 by the hardware when a power-on condition is detect- ed, allowing the cpu to determine whether a power-up has occurred. the cpu can clear this bit to 0 but cannot set it to 1. any attempt by the cpu to set this bit is ignored. 12.7 slow clock prescaler register (prssc) the slow clock prescaler (prssc) register is a byte-wide read/write register that holds the clock divisor used to gener- ate the slow clock from the main clock. the format of the reg- ister is shown below. scdiv slow clock divisor. if the clock divider is en- abled (crctrl.sclk=0), the main clock is di- vided by (scdiv+1)*2 to produce the slow system clock. upon reset, prssc register is set to ff hex. 12.8 slow clock prescaler 1 register (prssc1) the slow clock prescaler 1 (prssc1) register is a byte- wide read/write register that holds the clock divisor used to generate the two additional slow clocks from the high-speed clock. upon reset, the register is set to 00. the format of the register is shown below. scdiv1 slow clock divisor 1. the main clock is divided by (scdiv1+1) to obtain the first slow system clock. scdiv1 slow clock divisor 2. the main clock is divided by (scdiv2+1) to obtain the second slow sys- tem clock. 7 6 5 4 3 2 1 0 reserved por sclk 7 6 5 4 3 2 1 0 scdiv 7 4 3 0 scdiv2 scdiv1
www.national.com 42 13.0 multi-input wake-up the multi-input wake-up (miwu16) module monitors its 16 input channels for a software-selectable trigger condition. upon detection of a trigger condition, the module generates an interrupt request and if enabled, a wake-up request. a wake-up request can be used by the power management unit to exit the halt, idle, or power save mode and return to the active mode. an interrupt request generates an interrupt to the cpu (interrupt irq2), allowing interrupt processing in re- sponse to external events. the wake-up event only activates the clocks and cpu, but does not by itself initiate execution of any code. it is the inter- rupt request associated with the miwu16 that gets the cpu to start executing code, by jumping to the proper interrupt routine. therefore, setting up the miwu16 interrupt handler is essential for any wake-up operation. there are four interrupt requests that can be routed to the icu as shown in figure 9. each of the 16 miwu channels can be programmed to activate one of these four interrupt re- quests. the input pins for the multi-input wake-up channels are named wui0 through wui15. each input can be configured to trigger on rising or falling edges, as determined by the setting in the wkedg register. each trigger event is latched into the wkpnd register. if a trigger event is enabled by its respective bit in the wkena register, an active wake-up/interrupt signal is generated. the software can determine which channel has generated the ac- tive signal by reading the wkpnd register. the multi-input wake-up module is active at all times, includ- ing the halt mode. all device clocks are stopped in this mode. therefore, detecting an external trigger condition and the subsequent setting of the pending flag are not synchronous to the system clock. 13.1 wake-up edge detection register (wkedg) the wake-up edge detection (wkedg) register is a word- wide read/write register that controls the edge sensitivity of the multi-input wake-up pins. register bits 0 through 15 con- trol input pins wui0 through wui15, respectively. a bit cleared to 0 configures the corresponding input to trigger on a rising edge (a low-to-high transition). a bit set to 1 config- ures the corresponding input to trigger on a falling edge (a high-to-low transition). this register is cleared upon reset, which configures all 16 in- puts to be triggered on rising edges. the register format is shown below. 13.2 wake-up enable register (wkena) the wake-up enable (wkena) register is a word-wide read/ write register that enables or disables each of the multi-input wake-up channels. register bits 0 through 15 control chan- nels wui0 through wui15, respectively. a bit cleared to 0 dis- ables the wake-up function and a bit set to 1 enables the function. this register is cleared upon reset, which disables all eight wake-up/interrupt channels. wui0 pl0 wui1 pl1 wui2 pl2 wui3 pl3 wui4 ph0 wui5 ph1 wui6 ph2 wui7 ph3 wui8 twm-t0out wui9 access.bus wui10 canards wui11 mwcs wui12 rdx1 wui13 rdx2 wui14 comparator 1 wui15 comparator 2 15 0 wked15-wked0
43 www.national.com the register format is shown below. 13.3 wake-up interrupt control register 1 (wkctl1) the wake-up interrupt control register 1 (wkictl1) regis- ter is a word-wide read/write register that selects the interrupt request signal for the associated channels wui0 to wui7. upon reset, wkictl1 is set to 0, which selects miwu inter- rupt request 0 for all eight channels. the register format is shown below. wkintr0:7 wake-up interrupt request select. each field selects which of the following four interrupt re- quests outputs to the icu31l are to be activat- ed for the corresponding channel. 00 enables miwu interrupt request 0 01 enables miwu interrupt request 1 10 enables miwu interrupt request 2 11 enables miwu interrupt request 3 13.4 wake-up interrupt control register 1 (wkctl2) the wake-up interrupt control register 2 (wkictl2) regis- ter is a word-wide read/write register that selects the interrupt request signal for the associated channels wui8 to wui15. upon reset, wkictl2 is set to 0, which selects miwu inter- rupt request 0 for all eight channels. the register format is shown below. wkintr8:5 wake-up interrupt request select. each field selects which of the following four interrupt re- quests outputs to the icu31l are to be activat- ed for the corresponding channel. 00 enables miwu interrupt request 0 01 enables miwu interrupt request 1 10 enables miwu interrupt request 2 11 enables miwu interrupt request 3 13.5 wake-up pending register (wkpnd) the wake-up pending (wkpnd) register is a word-wide read/write register in which the multi-input wake-up module latches any detected trigger conditions. register bits 0 through 15 serve as latches for channels wui0 through wui15, respectively. a bit cleared to 0 indicates that no trig- ger condition has occurred. a bit set to 1 indicates that a trig- ger condition has occurred and is pending on the corresponding channel. this register is cleared upon reset. the cpu can only write a 1 to any bit position in this register. if the cpu attempts to write a 0, it has no effect on that bit. to clear a bit in this register, the cpu must use the wkpcl register (described below). this implementation prevents a potential hardware-software conflict during a read-modify- write operation on the wkpnd register. the register format is shown below. 13.6 wake-up pending clear register (wkpcl) the wake-up pending clear (wkpcl) register is a word- wide write-only register that lets the cpu clear bits in the wkpnd register. writing a 1 to a bit position in the wkpcl register clears the corresponding bit in the wkpnd register. writing a 0 leaves the corresponding bit in the wkpnd reg- ister unchanged. reading this register location returns unknown data. there- fore, do not use a read-modify-write sequence to set the indi- vidual bits. in other words, do not attempt to read the register figure 9. multi-input wake-up module block diagram peripheral bus 15 0 wkena wui0 wui15 0 15 . . . . . . . . . . wkedg wkpnd to p o w e r m g t wake-up signal exint3:0 to icu wkictl1-2 4 15 0 wken15-wken0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wkintr 7 wkintr 6 wkintr 5 wkintr 4 wkintr 3 wkintr 2 wkintr 1 wkintr 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wkintr 15 wkintr 14 wkintr 13 wkintr 12 wkintr 11 wkintr 10 wkintr 9 wkintr 8 15 0 wkpd15-wkpd0
www.national.com 44 and do a logical or with the register value. instead, just write the mask directly to the register address. the register format is shown below. 13.7 programming procedures to set up and use the multi-input wake-up function, use the following procedure. performing the steps in the order shown will prevent false tri ggering of a wake-up condition. this same procedure should be used following a reset because the wake-up inputs are left floating, resulting in unknown data on the input pins. 1. clear the wkena register to disable the wake-up chan- nels. 2. if the input originates from an i/o port (the usual case), set the corresponding bit in the port direction register to configure the i/o pin to operate as an input. 3. write the wkedg register to select the desired type of edge sensitivity (clear to 0 for rising edge, set to 1 for fall- ing edge). 4. set all bits in the wkpcl register to clear any pending bits in the wkpnd register. 5. set up the wkictl1 and wkictl2 registers to define the interrupt request signal used for each channel. 6. set the bits in the wkena register corresponding to the wake-up channels to be activated. to change the edge sensitivity of a wake-up channel, use the following procedure. performing the steps in the order shown will prevent false triggering of a wake-up/interrupt c ondition. 1. clear the wkena bit associated with the input to be re- programmed. 2. write the new value to the corresponding bit position in the wkedg register to reprogram the edge sensitivity of the input. 3. set the corresponding bit in the wkpcl register to clear the pending bit in the wkpnd register. 4. set the same wkena bit to re-enable the wake-up func- tion. 15 0 wkcl15-wkcl0
45 www.national.com 14.0 real-time timer and watchdog the timing and watchdog module (twm) generates the clocks and interrupts used for timing periodic functions in the system, and also provides watchdog protection against soft- ware errors. the module operates off the slow clock either generated by the external 32khz oscillator or from the pres- caled high speed system clock. the maximum operating clock frequency is 100khz. the watchdog is designed to detect program execution errors. once watchdog operation is initiated, the software must periodically write a specific value to a watchdog reg- ister. if the software fails to do so, a watchdog error is trig- gered, which resets the device. the twm is flexible in allowing selection of a variety of clock ratios and clock sources for the watchdog circuit. once the software configures the twm, it can lock the configura- tion for a higher level of protection against erroneous soft- ware action. once locked, the twm can be released only by a device reset. 14.1 twm structure figure 10 is a block diagram showing the internal structure of the timing and watchdog module. there are two main sections: the real-time timer (t0) section at the top and the watchdog section on the bottom. all counting activities of the module are based on the slow clock (slclk). a prescaler counter divides this clock to make a slower clock. the prescaler factor is defined by a 3-bit field in the timer and watchdog prescaler register, which se- lects either 1, 2, 4, 8, 16, or 32 and the divide-by factor. thus, the prescaled clock period can be set to 1, 2, 4, 8, 16, or 32 times the slow clock period. the prescaled clock signal is called t0in. 14.2 timer t0 operation timer t0 is a programmable 16-bit down counter that can be used as the time base for real-time operations such as a pe- riodic audible tick. it can also be used to drive the watch- dog circuit. the timer starts counting from the value loaded into the twmt0 register and counts down on each rising edge of t0in. when the timer reaches zero, it is automatically reload- ed from the twmt0 register and continues counting down from that value. thus, the frequency of the timer is: f slclk / [(twmt0+1) * prescaler] when an external crystal oscillator is used as the slclk source or when the fast clock is divided accordingly, f slclk is 32.768 khz. the value stored in twmt0 can range from 0001 hex to ffff hex. figure 10. timing and watchdog module block diagram (twcp) 16-bit timer (timer0) 5-bit pre-scale r counter watchdog timer peripheral bus clkin1 t0out watchdog error twmt0 register wdcnt wdsdm watchdog service logic restart underflow t0csr contrl. reg. restart underflow t0lint wderr (to icu) (to multi-input- wake-up) slow clock from dual clock and reset module real time timer (t0) watchdog t0in
www.national.com 46 when the counter reaches zero, an internal timer signal called t0out is set to 1 for one t0in clock cycle. this signal sets the tc bit in the twmt0 control and status register (t0csr). it also generates an interrupt called rti (irq14) if the interrupt is enabled by the t0csr.t0inte bit. if the software loads twmt0 with a new value, the timer uses that value the next time that it reloads the 16-bit timer register (in other words, after reaching zero). the software can restart the timer at any time (on the very next edge of the t0in clock) by setting the restart (rst) bit in the t0csr register. the t0csr.rst bit is cleared automatically upon restart of the 16-bit timer. note: if the user wishes to switch to power save or idle mode after setting t0csr.rst, the user must wait for reset opera- tion to complete before doing the switch. 14.3 watchdog operation the watchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. upon reset, the watchdog is disabled; it does not count and no watch- dog signal is generated. a write to either the watchdog count (wdcnt) register or the watchdog service data match (wdsdm) register starts the counter. the watch- dog counter counts down from the value programmed in to the wdcnt register. once started, only a reset can stop the watchdog from operating. the watchdog can be programmed to use either t0out or t0in as its clock source (the output and input of timer t0, respectively). the twcfg.wdct0i bit controls this clock selection. the software must periodically service the watchdog. there are two ways to service the watchdog, the choice depending on the programmed value of the wdsdme bit in the timer and watchdog configuration (twcfg) register. if twcfg.wdsdme bit is cleared to 0, the watchdog is serviced by writing a value to the wdcnt register. the value written to the register is reloaded into the watchdog counter. the counter then continues counting down from that value. if twcfg.wdsdme bit is set to 1, the watchdog is ser- viced by writing the value 5c hex to the watchdog service data match (wdsdm) register. this reloads the watch- dog counter with the value previously programmed into the wdcnt register. the counter then continues counting down from that value. a watchdog error signal is generated by any of the follow- ing events: the watchdog serviced too late. the watchdog serviced too often. the wdsdm register is written with a value other than 5c hex when wdsdm type servicing is enabled (twcfg.wdsdme=1). a watchdog error condition resets the device. 14.3.1 register locking the timer and watchdog configuration (twcfg) register is used to set the watchdog configuration. it controls the watchdog clock source (t0in or t0out), the type of watchdog servicing (using wdcnt or wdsdm), and the locking state of the twcfg, twcpr, timer0, t0csr, and wdcnt registers. a register that is locked cannot be read or written. a write operation is ignored and a read operation re- turns unpredictable results. if the twcfg register is itself locked, it remains locked until the device is reset. any other locked registers also remain locked until the device is reset. this feature prevents a run- away program from tampering with the programmed watch- dog function. 14.3.2 power save mode operation the timer and watchdog module is active in both the power save and idle modes. the clocks and counters contin- ue to operate normally in these modes. the wdsdm register is accessible in the power save and idle modes, but the other twm registers are accessible only in the active mode. therefore, watchdog servicing must be carried out using the wdsdm register in the power save or idle mode. in the halt mode, the entire device is frozen, including the timer and watchdog module. upon return to the active mode, operation of the module resumes at the point at which it was stopped. note: after a restart or watchdog service through wd- cnt, do not enter power save mode for a period equivalent to 5 slow clock cycles. 14.4 twm registers the twm registers controls the operation of the timing and watchdog module. there are six such registers: timer and watchdog configuration register (twcfg) timer and watchdog clock prescaler register (twcp) twm timer 0 register (twmt0) twmt0 control and status register (t0csr) watchdog count register (wdcnt) watchdog service data match register (wdsdm) the wdsdm register is accessible in both active and power save mode. the other twm registers are accessible only in active mode. 14.4.1 timer and watchdog configuration register (twcfg) the twcfg register is a byte-wide, read/write register that selects the watchdog clock input and service method, and also allows the watchdog registers to be selectively locked. once a bit is set, that bit cannot be cleared until the device resets. upon reset, the non-reserved bits of the regis- ter are all cleared to 0. the register format is shown below. ltwcfg lock twcfg register. when cleared to 0, ac- cess to the twcfg register is allowed. when set to 1, the twcfg register is locked. a locked register cannot be read or written; a read operation returns unpredictable values and a write operation is ignored. locking the twcfg register remains in effect until the de- vice is reset. 7 6 5 4 3 2 1 0 reserved wdsdme wdct0i lwdcnt lt w m t 0 lt w c p lt wc f g
47 www.national.com ltwcp lock twcp register. when cleared to 0, ac- cess to the twcp register is allowed. when set to 1, the twcp register is locked. ltwmt0 lock twmt0 register. when cleared to 0, ac- cess to the twmt0 and t0csr registers are allowed. when set to 1, the twmt0 and t0csr registers are locked. lwdcnt lock ldwcnt register. when cleared to 0, access to the ldwcnt register is allowed. when set to 1, the ldwcnt register is locked. wdct0i watchdog clock from t0in. when cleared to 0, the t0out signal (the output of timer t0) is used as the watchdog clock. when set to 1, the t0in signal (the prescaled slow clock) is used as the watchdog clock. wdsdme watchdog service data match enable. when cleared to 0, watchdog servicing is accomplished by writing a count value to the wdcnt register; write operations to the watchdog service data match (wdsdm) register are ignored. when set to 1, watch- dog servicing is accomplished by writing the value 5c hex to the wdsdm register. 14.4.2 timer and watchdog clock prescaler register (twcp) the twcp register is a byte-wide, read/write register that de- fines the prescaler value used for dividing the low frequency clock to generate the t0in clock. upon reset, the non-re- served bits of the register are cleared to 0. the register for- mat is shown below. mdiv main clock divide. this 3-bit field defines the prescaler factor used for dividing the low speed device clock to create the t0in clock. the al- lowed 3-bit values and the corresponding clock divisors and clock rates are listed below. 14.4.3 twm timer 0 register (twmt0) the twmt0 register is a word-wide, read/write register that defines the t0out interrupt rate. upon reset, twmt0 regis- ter is initialized to ffff hex. the register format is shown be- low. preset timer t0 preset. timer t0 is reloaded with this value on each underflow. thus, the frequency of the timer t0 interrupt is the frequency of t0in divided by (preset+1). the allowed val- ues of preset are 0001 hex through ffff hex. 14.4.4 twmt0 control and status register (t0csr) the t0csr register is a byte-wide, read/write register that controls timer t0 and shows its current status. upon reset, the non-reserved bits of the register are cleared to 0. the register format is shown below. rst restart. when this bit is set to 1, it forces the timer to reload the value in the twmt0 register on the next rising edge of the selected input clock. the rst bit is reset automatically by the hardware on the same rising edge of the se- lected input clock. writing a 0 to this bit position has no effect. upon reset, the non-reserved bits of the register are cleared to 0. tc terminal count. this bit is set to 1 by the hard- ware when the timer t0 count reaches zero and is cleared to 0 when the software reads the t0csr register. it is a read-only bit. any data written to this bit position is ignored. t0inte timer t0 interrupt enable. when this bit is set to 1, it enables an interrupt to the cpu each time the timer t0 count reaches zero. when this bit is cleared to 0, timer t0 interrupts are disabled. 14.4.5 watchdog count register (wdcnt) the wdcnt register is a byte-wide, write-only register that holds the value that is loaded into the watchdog counter each time the watchdog is serviced. the watchdog is started by the first write to this register. each successive write to this register restarts the watchdog count with the written value. upon reset, this register is initialized to 0f hex. 14.4.6 watchdog service data match register (wdsdm) the wsdsm register is a byte-wide, write-only register used for servicing the watchdog. when this type of servicing is enabled (twcfg.wdsdme=1), the watchdog is ser- viced by writing the value 5c hex to the wsdsm register. each such servicing reloads the watchdog counter with the value previously written to the wdcnt register. writing any data other than 5c hex triggers a watchdog error. writing to the register more than once in one watchdog clock cycle also triggers a watchdog error signal. if this type of servicing is disabled (twcfg.wdsdme=0), any write to the wsdsm register is ignored. 7 6 5 4 3 2 1 0 reserved mdiv mdiv clock divisor toin frequency (f sclk =32.768 khz) 000 1 32.768 khz 001 2 16.384 khz 010 4 8.192 khz 011 8 4.096 khz 100 16 2.056 khz 101 32 1.024 khz other reserved n/a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 preset 7 6 5 4 3 2 1 0 reserved t0inte tc rst
www.national.com 48 14.5 watchdog programming procedure the highest level of protection against software errors is achieved by programming and then locking the watchdog registers and using the wdsdm register for servicing. this is the procedure: 1. write the desired values into the twm clock prescaler register (twcp) and the twm timer 0 register (twmt0) to control the t0in and t0out clock rates. the frequency of t0in can be programmed to any of six frequencies ranging from 1/32*f slclk to f slclk . the fre- quency of t0out is equal to the frequency of t0in di- vided by (1+preset), where preset is the value written to the twmt0 register. 2. configure the watchdog clock to use either t0in or t0out by setting or clearing the twcfg.wdct0i bit. 3. write the initial value into the wdcnt register. this starts operation of the watchdog and specifies the maximum allowed number of watchdog clock cycles between service operations. 4. lock the watchdog registers and enable the watch- dog service data match enable function by setting bits 0, 1, 2, 3, and 5 in the twcfg register. 5. service the watchdog by periodically writing the val- ue 5c hex to the wdsdm register at an appropriate rate. servicing must occur at least once per period pro- grammed into the wdcnt register, but no more than once in a single watchdog input clock cycle.
49 www.national.com 15.0 multi-function timer the multi-function timer (mft16) module contains two in- dependent timer/counter units called mft1 and mft2, each containing a pair of 16-bit timer/counters. each timer/counter unit offers a choice of clock sources for operation and can be configured to operate in any of the following modes: ? processor-independent pulse width modulation (pwm) mode, which generates pulses of a specified width and duty cycle, and which also provides a general-purpose timer/counter ? dual input capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/counter ? dual independent timer mode, which generates system timing signals or counts occurrences of external events ? single input capture and single timer mode, which pro- vides one external event counter and one system timer the two timer units, mft1 and mft2, are identical in opera- tion and separately programmable. each timer unit uses two i/o pins, called t1a and t1b (for timer mft1) or t2a and t2b (for timer mft2). the timer i/o pins are alternate func- tions of the port f i/o pins. in the description of the timers, the lower-case letter n rep- resents the timer number, either 1 or 2. for example, tna means i/o pin t1a or t2a. 15.1 timer structure figure 11 is a block diagram showing the internal structure of each timer. there are two main functional blocks: a timer/ counter and action block and a clock source block. the tim- er/counter and action block contains two separate timer/ counter units, called timer/counter i and timer/counter ii (a total of four timer/counter unit in both mft1 and mft2). 15.1.1 timer/counter block the timer/counter block contains the following functional blocks: two 16-bit counters, timer/counter i (tncnt1) and timer/counter ii (tncnt2) two 16-bit reload/capture registers, tncra and tncrb control logic necessary to configure the timer to oper- ate in any of the four operating modes interrupt control and i/o control logic in a power-saving mode that uses the low-frequency (32.768 khz) clock as the system clock, the synchronization circuit re- quires that the slow clock operate at no more than one-fourth the speed of the 32.768 khz system clock. 15.1.2 clock source block the clock source block generates the signals used to clock the two timer/counter registers. the internal structure of the clock source block is shown in figure 12. counter clock source select there are two clock source selectors that allow the software to independently select the clock source for each of the two 16-bit counters from any one of the following sources: no clock (which stops the counter) prescaled system clock external event count based on tnb pulse accumulate mode based on tnb slow clock (derived from the low-frequency oscillator or divided from the high-speed oscillator) prescaler the 5-bit clock prescaler allows the software to run the timer with a prescaled clock signal. the prescaler consists of a 5- bit read/write prescaler register (tnprsc) and a 5-bit down counter. the system clock is divided by the value contained in the prescaler register plus 1. thus, the timer clock period can be set to any value from 1 to 32 divisions of the system clock period. the prescaler register and down counter are both cleared upon reset. figure 11. multi-function timer block diagram reload/capture a timer/counter 1 reload/capture timer/counter 2 b timer/counter clock source action system clock tnb toggle/capture/interrupt mode select + control pwm/capture/counter tna external event interrupt a interrupt b clock prescaler/selector
www.national.com 50 external event clock the tnb i/o pin can be configured to operate as an external event input clock for either of the two 16-bit counters. this in- put can be programmed to detect either rising or falling edg- es. the minimum pulse width of the external signal is one system clock cycle. this means that the maximum frequency at which the counter can run in this mode is one-half of the system clock frequency. this clock source is not available in the capture modes (modes 2 and 4) because the tnb pin is used as one of the two capture inputs. pulse accumulate mode the counter can also be configured to count prescaler output clock pulses when the tnb is high and not count when tnb is low, as illustrated in figure 13. the resulting count is an in- dicator of the cumulative time that tnb is high. this is called the pulse accumulate mode. in this mode, an and gate generates a clock signal for the counter whenever a prescaler clock pulse is generated and tnb input is high. (the polarity of the tnb signal is programmable, so the counter can count when tnb is low rather than high.) the pulse accumulate mode is not available in the capture modes (modes 2 and 4) because the tnb pin is used as one of the two capture inputs. slow clock the slow clock is generated by the dual clock and reset (clk2res) module. the clock source is either the divided fast clock or the external 32.768 khz clock crystal (if available and selected). the slow clock can be used as the clock source for the two 16-bit counters. because the slow clock can be asynchronous to the system clock, a circuit is provid- ed to synchronize the clock signal to the high-frequency sys- tem clock before it is used for clocking the counters. the synchronization circuit requires that the slow clock operate at no more than one-fourth the speed of the system clock. limitations in low-power modes the power save mode uses the low-frequency clock as the system clock. in this mode, the slow clock cannot be used as a clock source for the timers because both clk and slclk are driven then at the same frequency, and the 2:1 system- clock to input clock ratio needed for the synchronization can- not be maintained. however, the external event clock and pulse accumulate mode will still work, as long as the external event pulses are at least the size of the whole slow-clock pe- riod. using the prescaled system clock will also work, but at a much slower rate than the original system clock. some power save modes stops the system clock (the high- frequency and/or low-frequency clock) completely. if the sys- tem clock is stopped, the timer stops counting until the sys- tem clock resumes operation. i n the idle or halt mode, the system clock stops completely, which stops the operation of the timers. in that case, the tim- ers stop counting until the system clock resumes operation. figure 12. clock source block diagram prescaler register tnprsc prescaler counter 5-bit system clock reset tnb pulse accumulate external event no clock prescaled clock counter i clock select counter ii clock select counter i clock counter ii clock synchr. figure 13. pulse accumulate mode operation tnb prescaler output counter clock
51 www.national.com 15.2 timer operating modes each timer/counter unit can be configured to operate in any of the following modes: processor-independent pulse width modulation (pwm) mode dual input capture mode dual independent timer mode single input capture and single timer mode upon reset, the timers are disabled. to configure and start the timers, the software must write a set of values to the reg- isters that control the timers. the registers are described in section 15.5. 15.2.1 mode 1: processor-independent pwm mode 1 is the processor-independent pulse width modula- tion (pwm) mode, which generates pulses of a specified width and duty cycle, and which also provides a separate general-purpose timer/counter. figure 14 is a block diagram of the multi-function timer con- figured to operate in mode 1. timer/counter i (tncnt1) functions as the time base for the pwm timer. it counts down at the clock rate selected for the counter. when an underflow occurs, the timer register is reloaded alternately from the tncra and tncrb register, and counting proceeds down- ward from the loaded value. on the first underflow, the timer is loaded from tncra, then from tncrb on the next underflow, then from tncra again on the next underflow, and so on. every time the counter is stopped and restarted, it always obtains its first reload value from tncra. this is true whether the timer is restarted upon reset, after entering mode 1 from another mode, or after stopping and restarting the clock with the timer/counter i clock selector. the timer can be configured to toggle the tna output bit upon each underflow. this generates a clock signal on tna with the width and duty cycle determined by the values stored in the tncra and tncrb registers. this is a processor-inde- pendent pwm clock because once the timer is set up, no more action is required from the cpu to generate a continu- ous pwm signal. the timer can be configured to generate separate interrupts upon reload from tncra and tncrb. the interrupts can be enabled or disabled under software control. the cpu can de- termine the cause of each interrupt by looking at the tnap- nd and tnbpnd flags, which are set by the hardware upon each occurrence of a timer reload. in mode 1, timer/counter ii (tncnt2) can be used either as a simple system timer, an external event counter, or a pulse accumulate counter. the clock counts down using the clock selected with the timer/counter ii clock selector. it generates an interrupt upon each underflow if the interrupt is enabled with the tndien bit. 15.2.2 mode 2: dual input capture mode 2 is the dual input capture mode, which measures the elapsed time between occurrences of external events, and which also provides a separate general-purpose timer/ counter. figure 15 is a block diagram of the multi-function timer con- figured to operate in mode 2. the time base of the capture timer depends on timer/counter i, which counts down using the clock selected with the timer/counter i clock selector. figure 14. mode 1: processor-independent pwm block diagram reload a = time 1 timer/counter i reload b = time 2 timer i clock underflow tna tnaien tnapnd tncnt1 tncra tncrb tnbien tnbpnd timer interrupt a timer interrupt b tnaen timer/counter ii tncnt2 timer ii clock tndien tndpnd timer interrupt d tnb clock selector underflow
www.national.com 52 the tna and tnb pins function as capture inputs. a transition received on the tna pin transfers the timer contents to the tncra register. similarly, a transition received on the tnb pin transfers the timer contents to the tncrb register. each input pin can be configured to sense either rising or falling edges. the tna and tnb inputs can be configured to preset the counter to ffff hex upon reception of a valid capture event. in this case, the current value of the counter is transferred to the corresponding capture register and then the counter is preset to ffff hex. using this approach allows the software to determine the on-time and off-time and period of an exter- nal signal with a minimum of cpu overhead. the values captured in the tncra register at different times reflect the elapsed time between transitions on the tna pin. the same is true for the tncrb register and the tnb pin. the input signal on tna or tnb must have a pulse width equal to or greater than one system clock cycle. there are three separate interrupts associated with the cap- ture timer, each with its own enable bit and pending flag. the three interrupt events are reception of a transition on tna, re- ception of a transition on tnb, and underflow of the tncnt1 counter. the enable bits for these events are tnaien, tnbi- en, and tncien, respectively. in mode 2, timer/counter ii (tncnt2) can be used as a sim- ple system timer. the clock counts down using the clock se- lected with the timer/counter ii clock selector. it generates an interrupt upon each underflow if the interrupt is enabled with the tndien bit. neither timer/counter i (tncnt1) nor timer/counter ii (tncnt2) can be configured to operate as an external event counter or to operate in the pulse accumulate mode because the tnb input is used as a capture input. attempting to select one of these configurations will cause one or both counters to stop. 15.2.3 mode 3: dual independent timer/counter mode 3 is the dual independent timer mode, which gener- ates system timing signals or counts occurrences of external events. figure 16 is a block diagram of the multi-function timer con- figured to operate in mode 3. the timer is configured to oper- ate as a dual independent system timer or dual external event counter. in addition, timer/counter i can generate a 50% duty cycle pwm signal on the tna pin. the tnb pin can be used as an external event input or pulse accumulate input and can be used as the clock source for either timer/counter i or timer/counter ii. both counters can also be clocked by the prescaled system clock. figure 15. mode 2: dual input capture block diagram capture a timer/counter i capture b tncnt1 tncra tncrb timer/counter ii tncnt2 timer i clock timer ii clock tnb tna tnaien tnapnd timer interrupt i tnbien tnbpnd timer interrupt i tncien tncpnd timer interrupt i underflow tndien tndpnd timer interrupt ii underflow tnaen preset preset tnben
53 www.national.com timer/counter i (tncnt1) counts down at the rate of the se- lected clock. upon underflow, it is reloaded from the tncra register and counting proceeds down from the reloaded val- ue. in addition, the tna pin is toggled on each underflow if this function is enabled by the tnaen bit. the initial state of the tna pin is software-programmable. when the tna pin is toggled from low to high, it sets the tncpnd interrupt pend- ing flag and also generates an interrupt if the interrupt is en- abled by the tnaien bit. because tna toggles on every underflow, a 50% duty cycle pwm signal can be generated on tna without any further ac- tion from the cpu once the pulse train is initiated. timer/counter ii (tncnt2) counts down at the rate of the se- lected clock. upon underflow, it is reloaded from the tncrb register and counting proceeds down from the reloaded val- ue. in addition, each underflow sets the tndpnd interrupt pending flag and generates an interrupt if the interrupt is en- abled by the tndien bit. 15.2.4 mode 4: input capture plus timer mode 4 is the single input capture and single timer mode, which provides one external event counter and one system timer. figure 17 is a block diagram of the multi-function timer con- figured to operate in mode 4. this mode offers a combination of mode 3 and mode 2 functions. timer/counter i is used as a system timer as in mode 3 and timer/counter ii is used as a capture timer as in mode 2, but with a single input rather than two inputs. timer/counter i (tncnt1) operates the same as in mode 3. it counts down at the rate of the selected clock. upon under- flow, it is reloaded from the tncra register and counting pro- ceeds down from the reloaded value. the tna pin is toggled on each underflow if this function is enabled by the tnaen bit. when the tna pin is toggled from low to high, it sets the tncpnd interrupt pending flag and also generates an inter- rupt if the interrupt is enabled by the tnaien bit. a 50% duty cycle pwm signal can be generated on tna without any fur- ther action from the cpu once the pulse train is initiated. timer/counter ii (tncnt1) counts down at the rate of the se- lected clock. the tnb pin functions as the capture input. a transition received on tnb transfers the timer contents to the tncrb register. the input pin can be configured to sense ei- ther rising or falling edges. the tnb input can be configured to preset the counter to ffff hex upon reception of a valid capture event. in this case, the current value of the counter is transferred to the capture register and then the counter is preset to ffff hex. the values captured in the tncrb register at different times reflect the elapsed time between transitions on the tna pin. the input signal on tnb must have a pulse width equal to or greater than one system clock cycle. there are two separate interrupts associated with the cap- ture timer, each with its own enable bit and pending flag. the two interrupt events are reception of a transition on tnb and underflow of the tncnt2 counter. the enable bits for these events are tnbien and tndien, respectively. neither timer/counter i (tncnt1) nor timer/counter ii (tncnt2) can be configured to operate as an external event counter or to operate in the pulse accumulate mode because the tnb input is used as a capture input. attempting to select one of these configurations will cause one or both counters to stop. in this mode, timer/counter ii must be enabled at all times. figure 16. mode 3: dual independent timer/counter block diagram reload a timer/counter i reload b timer i clock tna tnaien tnapnd tncnt1 tncra tncrb tndien tndpnd timer interrupt i timer interrupt ii tnaen timer/counter ii tncnt2 timer ii clock tnb clock selector underflow underflow
www.national.com 54 15.3 timer interrupts each multi-function timer unit has four interrupt sources, designated a, b, c, and d. interrupt sources a, b, and c are mapped into a single system interrupt called timer interrupt i, while interrupt source d is mapped into a system interrupt called timer interrupt ii. each of the four interrupt sources has its own enable bit and pending flag. the enable flags are named tnaien, tnbien, tncien, and tndien. the pend- ing flags are named tnapnd, tnbpnd, tncpnd, and tnd- pnd. for multi-function timer unit mft1, timer interrupts i and ii are system interrupts t1a and t1b (irq13 and irq12), re- spectively. for multi-function timer unit mft2, timer inter- rupts i and ii are system interrupts t2a and t2b (irq11 and irq10), respectively. table 15 shows the events that trigger interrupts a, b, c, and d in each of the four operating modes. note that some inter- rupt sources are not used in some operating modes, as indi- cated by the notation n/a (not applicable) in the table. 15.4 timer i/o functions each multi-function timer unit uses two i/o pins, called t1a and t1b (for timer mft1) or t2a and t2b (for timer mft2). the function of each pin depends on the timer operating mode and the tnaen and tnben enable bits. table 16 shows the functions of the pins in each operating mode, and for each combination of enable bit settings. when pin tna is configured to operate as a pwm output (tnaen = 1), the state of the pin is toggled on each underflow of the tncnt1 counter. in this case, the initial value on the pin is determined by the tnaout bit. for example, to start with tna high, the software should set the tnaout bit to 1 prior to enabling the timer clock. this option is available only when the timer is configured to operate in mode 1, 3, or 4 (in other words, when tncra is not used in capture mode) . l figure 17. mode 4: input capture plus timer block diagram reload a timer/counter i capture b timer i clock tna tnaien tnapnd tncnt1 tncra tncrb timer interrupt i tnaten timer/counter ii tncnt2 timer ii clock underflow tndien tndpnd timer interrupt ii tnbien tnbpnd timer interrupt i tnb tnben preset
55 www.national.com table 15 timer interrupts overview sys. int. interrupt pending flag mode 1 mode 2 mode 3 mode 4 pwm + counter dual input capture + counter dual counter single capture + counter timer int. i (tna int.) tnapnd tncnt1 reload from tncra input capture on tna transition tncnt1 reload from tncra tncnt1 reload from tncra tnbpnd tncnt1 reload from tncrb input capture on tnb transition n/a input capture on tnb transition tncpnd n/a tncnt1 underflow n/a n/a timer int. ii (tnb int.) tndpnd tncnt2 underflow tncnt2 underflow tncnt2 reload from tncrb tncnt2 underflow table 16 timer i/o functions i/o tnaen tnben mode 1 mode 2 mode 3 mode 4 pwm + counter dual input capture + counter dual counter single capture + counter tna tnaen=0 tnben=x no output capture tncnt1 into tncra no output toggle no output toggle tnaen=1 tnben=x toggle output on underflow of tncnt1 capture tncnt1 into tncra and preset tncnt1 toggle output on underflow of tncnt1 toggle output on underflow of tncnt1 tnb tnaen=x tnben=0 ext. event or pulse accumulate input capture tncnt1 into tncrb ext. event or pulse accumulate input capture tncnt2 into tncrb tnaen=x tnben=1 ext. event or pulse accumulate input capture tncnt1 into tncrb and preset tncnt1 ext. event or pulse accumulate input capture tncnt2 into tncrb and preset tncnt2
56 www.national.com 15.5 timer registers the following cpu-accessible registers are used to control the multi-function timers: clock prescaler register (tnprsc) clock unit control register (tnckc) timer/counter i register (tncnt1) timer/counter ii register (tncnt2) reload/capture a register (tncra) reload/capture b register (tncrb) timer mode control register (tnctrl) timer interrupt control register (tnictl) timer interrupt clear register (tniclr) 15.5.1 clock prescaler register (tnprsc) the clock prescaler (tnprsc) register is a byte-wide, read/ write register that holds the current value of the 5-bit clock prescaler (clkps). this register is cleared upon reset. the register format is shown below. clkps clock prescaler. when the timer is configured to use the prescaled clock, the system clock is divided by clkps+1 to produce the timer clock. thus, the system clock divide-by factor can range from 1 to 32. 15.5.2 clock unit control register (tnckc) the clock unit control (tnckc) register is a byte-wide, read/ write register that selects the clock source for each timer/ counter. selecting the clock source also starts the counter. this register is cleared upon reset, which disables the timer/ counters. the register format is shown below. c1csel counter i clock select. this 3-bit field defines the clock mode for timer/counter i as follows: 000 = no clock (timer/counter i stopped) 001 = prescaled system clock 010 = external event on tnb (modes 1 and 3 only) 011 = pulse accumulate mode based on tnb (modes 1 and 3 only) 100 = slow clock * other values = undefined c2csel counter ii clock select. this 3-bit field defines the clock mode for timer/counter ii as follows: 000 = no clock (timer/counter ii stopped modes 1, 2, and 3 only) 001 = prescaled system clock 010 = external event on tnb (modes 1 and 3 only) 011 = pulse accumulate mode based on tnb (modes 1 and 3 only) 100 = slow clock * other values = undefined * operation of the slow clock is determined by the crc- trl.sclk control bit, as described in section 12.6.1. 15.5.3 timer/counter i register (tncnt1) the timer/counter i (tncnt1) register is a word-wide, read/ write register that holds the current count value for timer/ counter i. the register contents are not affected by a reset and are unknown upon power-up. 15.5.4 timer/counter ii register (tncnt2) the timer/counter ii (tncnt2) register is a word-wide, read/ write register that holds the current count value for timer/ counter ii. the register contents are not affected by a reset and are unknown upon power-up. 15.5.5 reload/capture a register (tncra) the reload/capture a (tncra) register is a word-wide, read/write register that holds the reload or capture value for timer/counter i. the register contents are not affected by a reset and are unknown upon power-up. 15.5.6 reload/capture b register (tncrb) the reload/capture b (tncrb) register is a word-wide, read/write register that holds the reload or capture value for timer/counter ii. the register contents are not affected by a reset and are unknown upon power-up. 15.5.7 timer mode control register (tnctrl) the timer mode control (tnctrl) register is a byte-wide, read/write register that sets the operating mode of the timer/ counter and the tna and tnb pins. this register is cleared upon reset. the register format is shown below. mdsel mode select. this 2-bit field sets the operating mode of the timer/counter as follows: 00 = mode 1: pwm plus system timer 01 = mode 2: dual input capture plus system timer 10 = mode 3: dual timer/counter 11 = mode 4: single input capture and single timer tnaedg tna edge polarity. when cleared (0), input pin tna is sensitive to falling edges (high to low transitions). when set (1), input pin tna is sen- sitive to rising edges (low to high transitions). tnbedg tnb edge polarity. when cleared (0), input pin tnb is sensitive to falling edges (high to low transitions). when set (1), input pin tnb is sen- sitive to rising edges (low to high transitions). in pulse accumulate mode, when this bit is set (1), the counter is enabled only when tnb is high; when this bit is cleared (0), the counter is en- abled only when tnb is low. tnaen tna enable. when set (1), the tna pin is en- abled to operate as a preset input or as a pwm output, depending on the timer operating mode. in mode 2 (dual input capture), a tran- sition on the tna pin presets the tncnt1 counter to ffff hex. in the other modes, tna functions as a pwm output. when this bit is 7 6 5 4 3 2 1 0 reserved clkps 7 6 5 4 3 2 1 0 reserved c2csel c1csel 7 6 5 4 3 2 1 0 reserved tnaout tnben tnaen tnbedg tnaedg mdsel
57 www.national.com cleared (0), operation of the pin for the timer/ counter is disabled. tnben tnb enable. when set (1), the tnb pin in en- abled to operate in mode 2 (dual input cap- ture) or mode 4 (single input capture and single timer). a transition on the tnb pin pre- sets the corresponding timer/counter to ffff hex (tncnt1 in mode 2 or tncnt2 in mode 4). when this bit is cleared (0), operation of the pin for the timer/counter is disabled. this bit setting has no effect in mode 1 or mode 3. tnaout tna output data. this is a status bit that indi- cates the current state of the tna pin when the pin is used as a pwm output. when set (1), the tna pin is high; when cleared (0), the tna pin is low. the hardware sets and clears this bit, but the software can also read or write this bit at any time and thus control the state of the out- put pin. in case of conflict, a software write has precedence over a hardware update. this bit setting has no effect when tna is used as an input. 15.5.8 timer interrupt control register (tnictl) the timer interrupt control (tnictl) register is a byte-wide, read/write register that contains the interrupt enable bits and interrupt pending bits for the four timer interrupt sources, des- ignated a, b, c, and d. the condition that causes each type of interrupt depends on the operating mode, as shown in ta b l e 1 5 . this register is cleared upon reset. the register format is shown below. tnapnd timer interrupt source a pending. when this bit is set (1), it indicates that timer interrupt con- dition a has occurred. when this bit is cleared (0), it indicates that the interrupt condition has not occurred. for an explanation of interrupt conditions a, b, c, and d, see table 15 this bit can be set by the hardware or by the software. to clear this bit, the software must use the timer interrupt clear register (tni- clr). any attempt by the software to directly write a 0 to this bit is ignored. tnbpnd timer interrupt source b pending. see the de- scription of tnapnd. tncpnd timer interrupt source c pending. see the de- scription of tnapnd. tndpnd timer interrupt source d pending. see the de- scription of tnapnd. tnaien timer interrupt a enable. when set (1), this bit enables an interrupt on each occurrence of in- terrupt condition a. when cleared (0), an oc- currence of interrupt condition a does not generate an interrupt to the cpu, but still sets the associated pending flag (tnapnd). for an explanation of interrupt conditions a, b, c, and d, see table 15. tnbien timer interrupt b enable. see the description of tnaien. tncien timer interrupt c enable. see the description of tnaien. tndien timer interrupt d enable. see the description of tnaien. 15.5.9 timer interrupt clear register (tniclr) the timer interrupt clear (tniclr) register is a byte-wide, write-only register that allows the software to clear the tnap- nd, tnbpnd, tncpnd, and tndpnd bits in the timer inter- rupt control (tnictrl) register. the register format is shown below. tnaclr timer pending a clear. when written with a 1, the timer interrupt source a pending bit (tnapnd) is cleared in the timer interrupt control register (tnictl). writing a 0 to the tnaclr bit has no effect. tnbclr timer pending b clear. see the description of tnaclr. tncclr timer pending c clear. see the description of tnaclr. tndclr timer pending d clear. see the description of tnaclr. 7 6 5 4 3 2 1 0 tndien tncien tnbien tnaien tndpnd tncpnd tnbpnd tnapnd 7 6 5 4 3 2 1 0 reserved tndclr tncclr tnbclr tnaclr
www.national.com 58 16.0 versatile-timer-unit (vtu) the versatile timer unit (vtu) contains four fully indepen- dent 16-bit timer subsystems. each timer subsystem can op- erate either as dual 8-bit pwm timers, as a single 16-bit pwm timer, or as a 16-bit counter with 2 input capture channels. these timer subsystems offers an 8-bit clock prescaler to ac- commodate a wide range of system frequencies. the versatile timer unit offers the following features: ? the versatile timer unit (vtu) can be configured to pro- vide: eight fully independent 8-bit pwm channels four fully independent 16-bit pwm channels eight 16-bit input capture channels ? the vtu consists of four timer subsystems, each of which contains: a 16-bit counter two 16-bit capture / compare registers an 8-bit fully programmable clock prescaler ? each of the four timer subsystems can operate in the fol- lowing modes: low power mode, i.e. all clocks are stopped dual 8-bit pwm mode 16-bit pwm mode dual 16-bit input capture mode ? the versatile-timer-unit controls a total of eight i/o pins, each of which can function as either: pwm output with programmable output polarity capture input with programmable event detection and timer reset ? a flexible interrupt scheme with four separate system level interrupt requests a total of 16 interrupt sources each with a separate in- terrupt pending flag and interrupt enable bit 16.1 vtu functional description the versatile-timer-unit (vtu) is comprised of four timer subsystems. each timer subsystem contains an 8-bit clock prescaler, a 16-bit up-counter and two 16-bit registers. each timer subsystem controls two i/o pins which either function as pwm outputs or capture inputs depending on the mode of operation. there are four system level interrupt requests, one for each timer subsystem. each system level interrupt re- quest is controlled by four interrupt pending flags with asso- ciated enable/disable bits. all four timer subsystems are fully independent and each may operate as a dual 8-bit pwm tim- er, a 16-bit pwm timer or as a dual 16-bit capture timer. fig- ure 18 illustrates the main elements of the versatile-timer- unit (vtu). prescaler counter c2prsc == count2 percap2 dtycap2 i/o control i/o control tio3 tio4 compare - capture compare - capture 0 7 0 15 prescaler counter c3prsc == count3 percap3 dtycap3 i/o control i/o control tio5 tio6 compare - capture compare - capture 0 7 0 15 prescaler counter c4prsc == count4 percap4 dtycap4 i/o control i/o control tio7 tio8 compare - capture compare - capture 0 7 0 15 prescaler counter c1prsc == count1 percap1 dtycap1 i/o control i/o control tio1 tio2 compare - capture compare - capture 0 7 0 15 timer subsystem 1 timer subsystem 2 timer subsystem 3 timer subsystem 4 mode io1ctl io2ctl intpnd intctl 0 15 0 15 0 15 0 15 0 15 figure 18. vtu block diagram
59 www.national.com 16.1.1 dual 8-bit pwm mode each timer subsystem may be configured to generate two ful- ly independent pwm waveforms on the respective tiox pins. in this mode, the counter countx is split and operates as two independent 8-bit counters. each counter increments at the rate determined by the clock prescaler. each of the two 8-bit counters may be started and stopped separately via the associated txrun bits. once either of the two 8-bit timers is running the clock prescaler starts counting. once the clock prescaler counter value matches the value of the associated cxprsc register field, countx is incre- mented. the period of the pwm output waveform is determined by the value of the percapx register. the tiox output starts at the default value as pro-grammed via the ioxctl.pxpol bit. once the counter value reaches the value of the period reg- ister percapx, the counter is reset to 00 16 upon the next counter increment. upon the following increment from 00 16 to 01 16 , the tiox output will change to the opposite of the de- fault value. the duty cycle of the pwm output waveform is controlled by the dtycapx register value. once the counter value reach- es the value of the duty cycle register dtycapx, the pwm output tiox changes back to its default value upon the next counter increment. figure 19 illustrates this concept. the period time is determined by the following formula: pwmperiod = (percapx + 1) * (cxprsc + 1) * t clk the duty cycle in percent is calculated as follows: dutycycle[%] = (dtycapx / (percapx+1)) *100 if the duty cycle register (dtycapx) holds a value which is greater then the value held in the period register (percapx) the tiox output will remain at the opposite of its default value which corresponds to a duty cycle of 100%. if the duty cycle register (dtycapx) register holds a value of 00 16 , the tiox output will remain at the default value which corresponds to a duty cycle of 0%. in that case the value contained in the percapx register is irrelevant. this scheme allows the duty cycle to be programmed in a range from 0% to 100%. in order to allow fully synchronized updates of the period and duty cycle compare values, the percapx and dtycapx registers are double buffered when operating in pwm mode. therefore if the user writes to either the period or duty cycle register while either of the two pwm channels is enabled, the new value will not take effect until the counter value matches the previous period value or the timer is stopped. reading the percapx or dtycapx register will always re- turn the most recent value written to it. the counter registers can be written if both 8-bit counters are stopped. this allows the user to preset the counters before starting and therefore generate pwm output waveforms with a phase shift relative to one another. if the counter is written with a value other then 00 16 it will start incrementing from that value while tiox remains at its default value until the first 00 16 to 01 16 transition of the counter value occurs. if the counter is preset to values which are smaller or equal then the value held in the period register (percapx) the counter will count up until a match between the counter value and the percapx register value occurs. the counter will then be re- set to 00 16 and continue counting up. alternatively the counter may be written with a value which is greater then the 00 countx percapx dtycapx tiox (pxpol=0) tiox (pxpol=1) txrun=1 01 00 01 02 03 04 05 06 07 08 09 0a 02 03 04 05 06 07 08 09 0a figure 19. vtu pwm generation
www.national.com 60 value held in the period register. in that case the counter will count up to ff 16 and then roll over to 00 16 . in any case the tiox pin always changes its state at the 00 16 to 01 16 transi- tion of the counter. the user software may only write to the countx register if both txrun bits of a timer subsystem are cleared. any writes to the counter register while either timer is running will be ig- nored. the two i/o pins associated with a timer subsystem function as independent pwm outputs in the dual 8-bit pwm mode. if a pwm timer is stopped via its associated mode.txrun bit the following actions result: the associated tiox pin will return to its default value as defined by the ioxctl.pxpol bit. the counter will stop and will retain its last value. any pending updates of the percapx and dtycapx register will be completed. the prescaler counter will be stopped and reset if both mode.txrun bits are cleared. figure 20 illustrates the configuration of a timer subsystem while operating in dual 8-bit pwm mode. the numbering in figure 20 refers to timer subsystem 1 but equally applies to the other three timer subsystems. 16.1.2 16-bit pwm mode each of the four timer subsystems may be independently configured to provide a single 16-bit pwm channel. in this case the lower and upper bytes of the counter are concate- nated to form a single 16-bit counter. operation in 16-bit pwm mode is conceptually identical to the dual 8-bit pwm operation as outlined under dual 8-bit pwm mode on page 59. the 16-bit timer may be started or stopped with the lower mode.txrun bit, i.e. t1run for tim- er subsystem 1. the two tiox outputs associated with a timer subsystem can be used to produce either two identical pwm waveforms or two pwm waveforms of opposite polarities. this can be ac- complished by setting the two pxpol bits of the respective timer subsystem to either identical or opposite values. figure 21 illustrates the configuration of a timer subsystem while operating in 16-bit pwm mode. the numbering in figure 21 refers to timer subsystem 1 but equally applies to the other three timer subsystems. figure 21. vtu 16-bit pwm mode 16.1.3 dual 16-bit capture mode in addition to the two pwm modes, each timer subsystem may be configured to operate in an input capture mode which provides two 16-bit capture channels. the input capture mode can be used to precisely measure the period and duty cycle of external signals. in capture mode the counter countx operates as a 16-bit up-counter while the two tiox pins associated with a timer subsystem operate as capture inputs. a capture event on the tiox pins causes the contents of the counter register (countx) to be copied to the percapx or dtycapx regis- ters respectively. starting the counter is identical to the 16-bit pwm mode, i.e. setting the lower of the two mode.txrun bits will start the counter and the clock prescaler. in addition, the capture event inputs are enabled once the mode.txrun bit is set. the tiox capture inputs can be independently configured to detect a capture event on either a positive transition, a nega- tive transition or both a positive and a negative transition. in addition, any capture event may be used to reset the counter countx and the clock prescaler counter. this avoids the need for the user software to keep track of timer overflow con- ditions and greatly simplifies the direct frequency and duty cycle measurement of an external signal. figure 22 illustrates the configuration of a timer subsystem while operating in capture mode. the numbering in figure 22 prescaler counter c1prsc == count1[15:8] percap1[15:8] dtycap1[15:8] tio2 compare compare 0 7 8 15 count1[7:0] percap1[7:0] dtycap1[7:0] compare compare 0 7 [7:0] [15:8] s r q p2pol tio1 s r q p1pol t1run t2run res res tmod1=01 figure 20. vtu dual 8-bit pwm mode prescaler counter c1prsc == count1[15:0] percap1[15:0] dtycap1[15:0] tio2 compare compare 0 7 0 15 [15:0] s r q p2pol tio1 s r q p1pol t1run restart tmod1=10
61 www.national.com refers to timer subsystem 1 but equally applies to the other three timer subsystems. figure 22. vtu dual 16-bit capture mode 16.1.4 low power mode in case a timer subsystem is not used, the user can place it in a low-power-mode. all clocks to a timer subsystem are stopped and the counter and prescaler contents are frozen once low-power-mode is entered. the user may continue to write to the mode, intctl, ioxctl and clkxps registers. write operations to the intpnd register are allowed; but if a timer subsystem is in low power mode, its associated inter- rupt pending bits cannot be cleared. the user cannot write to the countx, percapx and dtycapx registers of a timer subsystem while it is in low-power-mode. all registers can be read at any time. 16.1.5 interrupts the versatile-timer-unit (vtu) has a total of 16 interrupt sources, four for each of the four timer subsystems. all inter- rupt sources have a pending flag and an enable bit associat- ed with them. all interrupt pending flags are denoted ixapd through ixdpd where x relates to the specific timer sub- system. there is one system level interrupt request for each of the four timer subsystems. figure 23 illustrates the interrupt structure of the versatile timer module. figure 23. vtu interrupt request structure each of the timer pending flags - ixapd through ixdpd - is set by a specific hardware event depending on the mode of operation, i.e., pwm or capture mode. table 17 outlines the specific hardware events relative to the operation mode which cause an interrupt pending flag to be set. 16.1.6 ise mode operation the vtu supports breakpoint operation of the in-system- emulator (ise). if freeze is asserted, all timer counter clocks will be inhibited and the current value of the timer reg- isters will be frozen; in capture mode, all further capture events are disabled. once freeze becomes inactive, counting will resume from the previous value and the capture input events are re-enabled. 16.2 vtu registers the versatile-timer-unit contains a total of 19 user accessi- ble registers. all registers are word-wide and are initialized to a known value upon reset. all software accesses to the vtu registers must be word accesses. prescaler counter c1prsc == count1[15:0] percap1[15:0] dtycap1[15:0] capture capture 0 7 0 15 [15:0] tio1 c1edg t1run restart 2 0 tio2 c2edg 2 0 cap cap rst rst tmod1=11 i1apd i1bpd i1cpd i1dpd i1aen i1ben i1cen i1den system interrupt request 1 i4apd i4bpd i4cpd i4dpd i4aen i4ben i4cen i4den system interrupt request 4 table 17 vtu interrupt sources pending flag dual 8-bit pwm mode 16-bit pwm mode capture mode ixapd low byte duty cycle match duty cycle match capture to dtycapx ixbpd low byte period match period match capture to percapx ixcpd high byte duty cycle match n/a counter overflow ixdpd high byte period match n/a n/a
www.national.com 62 16.2.1 mode control register (mode) the mode control (mode) registries a word-wide read/write register which controls the mode selection of all four timer subsystems. the register is cleared (0000 16 ) upon reset. txrun timer start/stop. if set (1), the associated counter and clock prescaler is started depend- ing on the mode of operation. once set, the clock to the clock prescaler and the counter are enabled and the counter will increment each time the clock prescaler counter value matches the value defined in the associated clock pres- caler field (cxprsc). tmodx timer system operating mode. this 2-bit wide field enables or disables the timer subsystem and defines its operating mode. 00: low-power-mode enabled. all clocks to the counter subsystem are stopped. the counter is stopped regardless of the val- ue of the txrun bits. read operations to the timer subsystem will return the last value; the user shall not perform any write operations to the timer sub- system while it is disabled since those will be ignored. 01: dual 8-bit pwm mode enabled. each 8- bit counter may individually be started or stopped via its associated txrun bit. the tiox pins will function as pwm out- puts. 10: 16-bit pwm mode enabled. the two 8- bit counters are concatenated to form a single 16-bit counter. the counter may be started or stopped with the lower of the two txrun bits, i.e. t1run, t3run, t5run and t7run. the tiox pins will function as pwm outputs. 11: capture mode enabled. both 8-bit counters are concatenated and operate as a single 16-bit counter. the counter may be started or stopped with the lower of the two txrun bits, i.e., t1run, t3run, t5run and t7run. the tiox pins will function as capture inputs. 16.2.2 i/o control register 1 (io1ctl) the i/o control register 1 (io1ctl) is a word-wide read/ write register. the register controls the functionality of the i/o pins tio1 through tio4 depending on the selected mode of operation. the register is cleared (0000 16 ) upon reset. cxedg capture edge control. defines the polarity of a capture event and the reset of the counter. the value of this three bit field has no effect while operating in pwm mode. pxpol pwm polarity. while operating in pwm mode the bit defines the output polarity of the corre- sponding pwm output (tiox). 0 = the pwm output is set (1) upon the 00 16 to 01 16 transition of the counter and will be reset (0) once the counter value matches the duty cycle value. 1 = the pwm output is reset (0) upon the 00 16 to 01 16 transition of the counter and will be set (1) once the counter val- ue matches the duty cycle value. once a counter is stopped, the output will assume the value of pxpol, i.e., its initial value. the pxpol bit has no effect while operating in capture mode. 16.2.3 i/o control register 2 (io2ctl) the i/o control register 2 (io2ctl) is a word-wide read/ write register. the register controls the functionality of the i/o pins tio5 through tio8 depending on the selected mode of operation. the register is cleared (0000) upon reset. the functionality of the bit fields of the io2ctl register is identical to the ones described in the io1ctl register sec- tion. 16.2.4 interrupt control register (intctl) the interrupt control (intctl) register is a word-wide read/ write register. it contains the interrupt enable bits for all 16 in- terrupt sources of the versatile-timer-unit. each interrupt enable bit corresponds to an interrupt pending flag located in the interrupt pending register (intpnd). all intctl register bits are solely under software control. the register is cleared (0000 16 ) upon reset.. ixaen timer x interrupt a enable. enable/disable an interrupt request based on the corresponding ixapd flag being set. the associated ixapd 15 14 13 12 11 10 9 8 tmod4 t8run t7run tmod3 t6run t5run 7 6 5 4 3 2 1 0 tmod2 t4run t3run tmod1 t2run t1run 15 14 12 11 10 8 7 6 4 3 2 0 p4pol c4edg p3pol c3edg p2pol c2edg p1pol c1edg cxedg capture counter reset 000 rising edge no 001 falling edge no 010 rising edge ye s 011 falling edge ye s 100 both edges no 101 both edges rising edge 110 both edges falling edge 111 both edges both edges 15 14 12 11 10 8 7 6 4 3 2 0 p8pol c8edg p7pol c7edg p6pol c6edg p5pol c5edg 15 14 13 12 11 10 9 8 i4den i4cen i4ben i4aen i3den i3cen i3ben i3aen 7 6 5 4 3 2 1 0 i2den i2cen i2ben i2aen i1den i1cen i1ben i1aen
63 www.national.com flag will be updated regardless of the value of the ixaen bit. 0 enable system interrupt request for the ixapd pending flag 1 disable system interrupt request for the ixapd pending flag ixben timer x interrupt b enable. enable/disable an interrupt request based on the corresponding ixbpd flag being set. the associated ixbpd flag will be updated regardless of the value of the ixben bit. 0 enable system interrupt request for the ixbpd pending flag 1 disable system interrupt request for the ixbpd pending flag ixcen timer x interrupt c enable. enable/disable an interrupt request based on the corresponding ixcpd flag being set. the associated ixcpd flag will be updated regardless of the value of the ixcen bit. 0 enable system interrupt request for the ixcpd pending flag 1 disable system interrupt request for the ixcpd pending flag ixden timer x interrupt d enable. enable/disable an interrupt request based on the corresponding ixdpd flag being set. the associated ixdpd flag will be updated regardless of the value of the ixden bit. 0 enable system interrupt request for the ixdpd pending flag 1 disable system interrupt request for the ixdpd pending flag 16.2.5 interrupt pending register (intpnd) the interrupt pending (intpnd) register is a word-wide read/write register which contains all 16 interrupt pending flags. there are four interrupt pending flags called ixapd through ixdpd per timer subsystem. each interrupt pending flag is set by a hardware event and can be cleared if the user software writes a 1 to the bit position. the value will remain unchanged if a 0 is written to the bit position. all interrupt pending flags are cleared (0) upon reset. ixapd timer x interrupt a pending. if set (1), indicates that an interrupt condition for the related timer subsystem has occurred. table 17 on page 61 lists the hardware condition which causes this bit to be set. ixbpd timer x interrupt b pending. if set (1), indicates that an interrupt condition for the related timer subsystem has occurred. table 17 on page 61 lists the hardware condition which causes this bit to be set. ixcpd timer x interrupt c pending. if set (1), indicates that an interrupt condition for the related timer subsystem has occurred. table 17 on page 61 lists the hardware condition which causes this bit to be set. ixdpd timer x interrupt d pending. if set (1), indicates that an interrupt condition for the related timer subsystem has occurred. table 17 on page 61 lists the hardware condition which causes this bit to be set. 16.2.6 clock prescaler register 1 (clk1ps) clk1ps is a word-wide read/write register. the register is split into two 8-bit wide field called c1prsc and c2prsc. each field holds the 8-bit clock prescaler compare value for timer subsystems 1 and 2 respectively. the register is cleared upon reset. c1prsc clock prescaler 1 compare value. holds the 8- bit prescaler value for timer subsystem 1. the counter of timer subsystem is incremented each time when the clock prescaler compare value matches the value of the clock prescaler counter. the divide-by-ratio is equal to c1prsc+1 i.e. a value of 00 16 results in a di- vide by 1 whereas the maximum divide-by ratio is 256 for a c1prsc value of ff 16 . c2prsc clock prescaler 2 compare value. holds the 8- bit prescaler value for timer subsystem 2. the functionality of this field is identical to the one described for c1prsc in the previous para- graph. 16.2.7 clock prescaler register 2 (clk2ps) the clock prescaler register 2 (clk2ps) is a word-wide read/write register. the register is split into two 8-bit wide fields called c3prsc and c4prsc. each field holds the 8- bit clock prescaler compare value for timer subsystems 3 and 4 respectively. the register is cleared upon reset. c3prsc clock prescaler 3 compare value. holds the 8- bit prescaler value for timer subsystem 3. the functionality of this field is identical to the one described for c1prsc on page 63. c4prsc clock prescaler 4 compare value. holds the 8- bit prescaler value for timer subsystem 4. the functionality of this field is identical to the one described for c1prsc on page 63. 16.2.8 counter registers (countx) the counter (countx) registers are word wide read/write registers. there are a total of four registers called count1 through count4, one for each of the four timer subsystems. the user software may read the registers at any time. read- ing the register will return the current value of the counter. 15 14 13 12 11 10 9 8 i4dpd i4cpd i4bpd i4apd i3dpd i3cpd i3bpd i3apd 7 6 5 4 3 2 1 0 i2dpd i2cpd i2bpd i2apd i1dpd i1cpd i1bpd i1apd 15 8 7 0 c2prsc c1prsc 15 8 7 0 c4prsc c3prsc
www.national.com 64 the register may only be written if the counter is stopped i.e. if both txrun bits associated with a timer subsystem are cleared. the registers are cleared upon reset (0000). 16.2.9 period/capture registers (percapx) the period/capture (percapx) registers are word-wide read/write registers. there are a total of four registers called percap1 through percap4, one for each timer sub- system. the register hold the period compare value in pwm mode of the counter value at the time the last associated cap- ture event occurred. in pwm mode the register is double buff- ered. if a new period compare value is written while the counter is running, the write will not take effect until counter value matches the previous period compare value or until the counter is stopped. reading may take place at any time and will return the most recent value which was written. the per- capx registers are reset to 0000 upon reset. 16.2.10 duty cycle / capture registers (dtycapx) the duty cycle/capture (dtycapx) registers are word-wide read/write registers. there are a total of four registers called dtycap1 through dtycap4, one for each timer sub- system. the registers hold the period compare value in pwm mode or the counter value at the time the last associated cap- ture event occurred. in pwm mode the register is double buff- ered. if a new duty cycle compare value is written while the counter is running, the write will not take effect until the counter value matches the previous period compare value or until the counter is stopped. in other words, the update takes effect on period boundaries only. reading may take place at any time and will return the most recent value which was writ- ten. the dtycapx registers are reset to 0000 16 upon reset . 15 0 cntx 15 0 pcapx 15 0 dcapx
65 www.national.com 17.0 microwire/spi microwire/plus is a synchronous serial communications protocol, originally implemented in national semiconductor's cops? and hpc? families of microcontrollers to minimize the number of connections, and therefore the cost, of com- municating with peripherals. the device has an enhanced microwire/spi interface module (mwspi) that can communicate with all peripherals that conform to microwire or serial peripheral interface (spi) specifications. this enhanced microwire interface is capable of operating as either a master or slave and in 8- or 16-bit mode. figure 24 shows a typical enhanced microw- ire interface application. the enhanced microwire interface module includes the following features: programmable operation as a master or slave programmable shift-clock frequency (master only) programmable 8- or 16-bit mode of operation 8- or 16-bit serial i/o data shift register two modes of clocking data serial clock can be low or high when idle 16-bit read buffer busy flag, read buffer full flag, and overrun flag for polling and as interrupt sources supports multiple masters maximum bit rate of 10m bits/second (master mode) 5m bits/second (slave mode) at 20mhz system clock supports very low-end slaves with the slave ready output echo back enable/disable (slave only) 17.1 microwire operation the microwire interface allows several devices to be con- nected on one three-wire system. at any given time, one of these devices operates as the master while all other devices operate as slaves. the master device supplies the synchronous clock (msk) for the serial interface and initiates the data transfer. the slave devices respond by sending (or receiving) the requested da- ta. each slave device uses the masters clock for serially shift- ing data out (or in), while the master shifts the data in (or out). the three-wire system includes: the serial data in signal (mdido for master mode, mdodi for slave mode), the serial data out signal (mdodi for master mode, mdido for slave mode) and the serial clock (msk). in slave mode, an optional fourth signal (mcs ) may be used to enable the slave transmit. at any given time, only one slave can respond to the master. each slave device has its own chip select signal (mcs ) for this purpose. the microwire interface allows the device to operate ei- ther as a master or slave transferring 8- or 16-bits of data. this is configured via the mmns bit. figure 25 shows a block diagram of the enhanced microw- ire serial interface in the device. 17.1.1 shifting the microwire interface is a full duplex transmitter/receiv- er. a 16-bit shifter, which can be split into a low and high byte, is used for both transmitting and receiving. in 8-bit mode, only the lower 8-bits are used to transfer data. the transmitted data is shifted out through mdodi pin (master mode) or mdi- do pin (slave mode), starting with the most significant bit. at the same time, the received data is shifted in through mdido pin (master mode) or mdodi pin (slave mode), also starting with the most significant bit first. the shift in and shift out are controlled by the msk clock. in each clock cycle of msk, one bit of data is transmitted/re- ceived. the 16-bit shifter is accessible via the mwdat regis- ter. reading the mwdat register returns the value in the read buffer. writing to the mwdat register updates the 16-bit shifter. 17.1.2 reading the enhanced microwire interface implements a double buffer on read. as illustrated in figure 25, the double read buffer consists of the 16-bit shifter and a buffer, called the read buffer. figure 24. microwire interface do 5 chip select lines cs cs cs cs mdido do mdido mdodi mdodi di di di di master slave msk msk sk sk sk sk 8-bit a/d 1k bit eeprom lcd display driver vf display driver i/o lines i/o lines mcs mcs do
www.national.com 66 the 16-bit shifter loads the read buffer with new data when the data transfer sequence is completed and previous data in the read buffer has been read. in master mode, an overrun error occurs when the read buffer is full, the 16-bit shifter is full and a new data transfer sequence starts. when 8-bit mode is selected, the lower byte of the shift reg- ister is loaded into the lower byte of the read buffer and the read buffers higher byte remains unchanged. the receive buffer full (mrbf) bit indicates if the mwdat register holds valid data. the movr bit indicates that an overrun condition has occurred. 17.1.3 writing the microwire busy (mbsy) bit indicates whether the mwdat register can be written. all write operations to the mwdat register update the shifter while the data contained in the read buffer is not affected. undefined results will occur if the mwdat register is written to while the mbsy bit is set to 1. 17.1.4 clocking modes two clocking modes are supported: the normal mode and the alternate mode. in the normal mode, the output data, which is transmitted on the mdodi pin (master mode) or the mdido pin (slave mode), is clocked out on the falling edge of the shift clock msk. the input data, which is received via the mdido pin (master mode) or the mdodi pin (slave mode), is sampled on the rising edge of msk. in the alternate mode, the output data is shifted out on the ris- ing edge of msk on the mdodi pin (master mode) or mdido pin (slave mode). the input data, which is received via mdi- do pin (master mode) or mdodi pin (slave mode), is sam- pled on the falling edge of msk. the clocking modes are selected with the mskm bit. the midl bit allows selection of the value of msk when it is idle (when there is no data being transferred). various msk clock frequencies can be programmed via the mcdv bits. figures 27, 28, 29, and 30 show the data transfer timing for the nor- mal and the alternate modes with the midl bit equal to 0 and equal to 1. note that when data is shifted out on mdodi (master mode) or mdido (slave mode) on the leading edge of the msk clock, bit 14 (16-bit mode) is shifted out on the second lead- ing edge of the msk clock. when data are shifted out on mdodi (master mode) or mdido (slave mode) on the tra iling edge of msk, bit 14 (16-bit mode) is shifted out on the first trailing edge of msk. 17.2 master mode in master mode, the msk pin is an output for the shift clock, msk. when data is written to the (mwndat register), eight or sixteen msk clocks, depending on the mode selected, are figure 25. microwire block diagram master master slave slave 16-bit shift register master clock prescaler + select 8 16-bit read buffer mwdat system clock write data read data control + status interrupt request data in data out msk mcs mdodi mdido msk 8
67 www.national.com generated to shift the eight or sixteen bits of data and then msk goes idle again. the msk idle state can be either high or low, depending on the midl bit. 17.3 slave mode in slave mode, the msk pin is an input for the shift clock msk. mdido is placed in tri-state mode when mcs is in- active. data transfer is enabled when mcs is active. the slave starts driving mdido when mcs is activated. the most significant bit (lower byte in 8-bit mode or upper byte in 16-bit mode) is output onto the mdido pin first. after eight or sixteen clocks (depending on the selected mode), the data transfer is completed. figure 26. normal mode, midl bit = 0 figure 27. normal mode, midl bit = 1 figure 28. alternate mode, midl bit = 0 data in msb msb-1 msb-2 5 bit 1 bit 0 end of transfer msb msb-1 msb-2 bit 1 bit 0 sample point shift out data out msk (lsb) (lsb) data out data in msb msb-1 msb-2 bit 1 bit 0 (lsb) end of transfer sample point shift out msb msb-1 msb-2 bit 1 bit 0 (lsb) msk end of transfer data out data in msb msb-1 msb-2 bit 1 bit 0 (lsb) msb msb-1 msb-2 bit 1 bit 0 (lsb) mskn sample point shift out
www.national.com 68 if a new shift process starts before mwdat was written, i.e., while mwdat does not contain any valid data, and the echo enable (mech) bit is set to 1, the data received from mdodi is transmitted on mdido in addition to being shifted to mw- dat. if the mech bit is cleared to 0, the data transmitted on mdido is the data held in the mwdat register, regardless of its validity. the master may negate the mcs signal to syn- chronize the bit count between the master and the slave. in the case that the slave is the only slave in the system, mcs can be tied to v ss . 17.4 interrupt generation an interrupt is generated in any of the following cases: when the read buffer is full (mrbf=1) and the enable interrupt for read bit is set (meir=1). whenever the shifter is not busy, i.e. the mbsy bit is cleared (mbsy=0) and the enable interrupt for write bit is set (meiw=1). when an overrun condition occurs (movr is set to 1) and the enable interrupt on overrun bit is set (meio=1). this usage is restricted to master mode. figure 30 illustrates the various interrupt capabilities of this module. 17.5 microwire interface registers the software interacts with the microwire interface by ac- cessing the microwire registers. there are five such reg- isters: microwire data register (mwdat) microwire control register (mwctl) microwire status register (mwstat) 17.5.1 microwire data register (mwdat) the mwdat register is a word-wide, read/write register used to transmit and receive data through the mdodi and mdido pins. figure 31 shows the hardware structure of the register. . figure 29. alternate mode, midl bit = 1 end of transfer sample point shift out data out data in msb msb-1 msb-2 bit 1 bit 0 (lsb) msb msb-1 msb-2 bit 1 bit 0 (lsb) mskn figure 30. mwspi interrupts interrupt mwspi movr = 1 mrbf = 1 mbsy = 0 meiw meir meio
69 www.national.com upon reset, all non-reserved bits are cleared to 0. the regis- ter format is shown below. men microwire enable. this bit enables (1) or disables (0) the microwire interface module. clearing this bit disables the module, clears the status bits in the microwire status register (the mbsy, mrbf, and movr flags in mw- stat), and places the microwire interface pins in the states described in table 18. mmns microwire master/slave select. when cleared to 0, the device operates as a slave. when set to 1, the device operates as the mas- ter. mmod microwire mode select (8- or 16-bit). when set to 0, the device operates in 8-bit mode. when set to 1, the device operates in 16-bit mode. this bit should only be changed when the module is disabled or the microwire in- terface is idle (mwstat.mbsy=0). mech microwire echo back. this bit enables (1) or disables (0) the echo back function in slave mode. this bit should be written only when the microwire interface is idle (mwstat.mb- sy=0). the mech bit is ignored in master mode. the mwdat register is valid from the time the register has been written until the end of the transfer. in the echo back mode, mdodi is transmitted (echoed back) on mdido if mwdat does not contain any valid data. with the echo back function disabled, the data held in the mwdat register is transmitted on mdido, whether or not the data is valid. meio microwire enable interrupt on overrun. this bit enables or disables the overrun error interrupt. when set to 1, an interrupt is gener- ated when the receive overrun error flag (mwstat.movr) is set. otherwise, no inter- rupt is generated when an overrun error oc- curs. this bit should only be enabled in master mode. meir microwire enable interrupt for read. when set to 1, an interrupt is generated when the read buffer full flag (mwstat.mrbf) is set. otherwise, no interrupt is generated when the read buffer is full. meiw microwire enable interrupt for write. when set to 1, an interrupt is generated when the busy bit (mwstat.mbsy) is cleared, which in- dicates that a data transfer sequence has been completed and the read buffer is ready to re- ceive the new data. otherwise, no interrupt is generated when the busy bit is cleared. mskm microwire clocking mode. when cleared to 0, the device uses the normal clocking mode. when set to 1, the device uses the alternate clocking mode. in the normal mode, the output data is clocked out on the falling edge of msk figure 31. mwdat register structure shift register read buffer low-byte high-byte write (store) 1 0 mwmod dout din read (store & mwmod) low-byte high-byte mwdat 15 9 8 7 6 5 4 3 2 1 0 mcdv [6:0] midl mskm meiw meir meio mech mmod mmns men table 18 pin values with microwire disabled msk master: mnidl bit slave: input mcs input mdido master: input slave: tri-state mdodi master: known value slave: input
www.national.com 70 and the input data is sampled on the rising edge of msk. in the alternate mode, the output data is clocked out on the rising edge of msk and the input data is sampled on the falling edge of msk. midl microwire idle. this bit sets the value of the msk output when the microwire interface is idle: 0 for low or 1 for high. this bit should be changed only when the microwire interface module is disabled (men=0) or when no bus transaction is in progress (mwstat.mbsy=0). mcdv microwire clock divider value. this 7-bit field specifies the divide-by factor used for gen- erating the msk shift clock from the system clock. the divide-by factor is 2*(mcdv[6:0]+1). this allows selection of a divide-by ratio from 2 to 256. this field is ignored in slave mode (mwctl1.mmns=0). 17.5.2 microwire status register (mwstat) the microwire status register is a word-wide, read-only register that shows the current status of the microwire in- terface module. upon reset, all non-reserved bits are cleared to 0. the register format is shown below. mbsy microwire busy. this bit, when set to 1, in- dicates that the microwire shifter is busy. in master mode, mbsy is set to 1 when the mwdat register is written. in slave mode, this bit is set to 1 on the first leading edge of msk when mcs is asserted or when the mwdat register is written, whatever occurs first. in both master and slave modes, this bit is cleared to 0 when the microwire data trans- fer sequence is completed and the read buffer is ready to receive the new data; in other words, when the previous data held in the read buffer has already been read. if the previous data in the read buffer has not been read and a new data has been received into the shift register, the mbsy will not be cleared, as the transfer could not be complet- ed. this is because the contents of the shift register could not be copied into the read buff- er. mrbf microwire read buffer full. this bit, when set to 1, indicates that the microwire read buffer is full and ready to be read by the soft- ware. it is set to 1 when the shifter loads the read buffer, which occurs upon completion of a transfer sequence if the read buffer is empty. the mrbf bit is updated when the mwdat register is read. at that time, the mrbf bit is cleared to 0 if the shifter does not contain any new data (in other words, the shifter is not re- ceiving data or has not yet received a full byte of data). the mrbf bit remains set to 1 if the shifter already holds new data at the time that mwdat is read. in that case, mwdat is imme- diately reloaded with the new data and is ready to be read by the software. movr microwire receive overrun error. this bit, when set to 1 in master mode, indicates that a receive overrun error has occurred. this error occurs when the read buffer is full, the 8-bit shifter is full, and a new data transfer sequence starts. this bit is undefined in slave mode. the movr bit, once set, remains set until cleared by the software. the software clears this bit by writing a 1 to its bit position. writing a 0 to this bit position has no effect. no other bits in the mwstat register are affected by a write operation to the register. 15 3 2 1 0 reserved movr mrbf mbsy
71 www.national.com 18.0 usart the usart module is a full-duplex universal synchronous/ asynchronous receiver/transmitter that supports a wide range of software-programmable baud rates and data for- mats. it handles automatic parity generation and several er- ror detection schemes. there are one or two independent usart modules in each device, depending on the package type. each usart module offers the following features: full-duplex double-buffered receiver/transmitter synchronous or asynchronous operation programmable baud rate from sys_clk/ [2*(1+2^11)*16] up to sysclk/2 for usart config- ured to run in synchronous mode programmable baud rate from sys_clk/ [16*(1+2^11)*16] up to sysclk/16 for usart config- ured to run in asynchronous mode programmable framing formats: seven, eight, or nine data bits; one or two stop bits; and odd, even, mark, space, or no parity hardware parity generation for data transmission and parity check for data reception interrupts on transmit ready and receive ready con- ditions, separately enabled software-controlled break transmission and detection internal diagnostic capability automatic detection of parity, framing, and overrun er- rors 18.1 functional overview figure 32 is a block diagram of the usart module showing the basic functional units in the usart: transmitter receiver baud rate generator control and error detection note: in the description of the usart, the lower-case letter n represents the usart number. for example, tdxn means tdx1 or tdx2. the transmitter block consists of an 8-bit transmit shift regis- ter and an 8-bit transmit buffer. data bytes are loaded in par- allel from the buffer into the shift register and then shifted out serially on the tdxn pin. the receiver block consists of an 8-bit receive shift register and an 8-bit receive buffer. data is received serially on the rdxn pin and shifted into the shift register. once eight bits have been received, the contents of the shift register are transferred in parallel to the receive buffer. the transmitter and receiver blocks both contain extensions for 9-bit data transfers, as required by the 9-bit and loopback operating modes. the baud rate generator generates the clock for the syn- chronous and asynchronous operating modes. it consists of two registers and a two-stage counter. the registers are used to specify a prescaler value and a baud rate divisor. the first stage of the counter divides the usart clock based on the value of the programmed prescaler to create a slower clock. the second stage of the counter divides the output of the first stage based on the programmed baud rate divisor to create the baud rate clock. the control and error detection block contains the usart control registers, control logic, error detection circuit, parity generator/checker, and interrupt generation logic. the con- trol registers and control logic determine the data format, mode of operation, clock source, and type of parity used. the error detection circuit generates parity bits and checks for parity, framing, and overrun errors. 18.2 usart operation the usart has two basic modes of operation: synchronous and asynchronous. in addition, there are two special- purpose synchronous and asynchronous modes, called at- tention and diagnostic. this section describes the operating modes of the usart. 18.2.1 asynchronous mode the asynchronous mode of the usart enables the device to communicate with other devices using just two communica- tion signals: transmit and receive. in the asynchronous mode, the transmit shift register (tsft) and the transmit buffer (untbuf) double-buffer the data for transmission. to transmit a character, a data byte is loaded in the untbuf register. the data is then transferred to the tsft register. while the tsft is shifting out the current character (lsb first) on the tdxn pin, the untbuf register is loaded by software with the next byte to be transmitted. when tsft finishes transmission of the last stop bit of the current frame, the contents of untbuf are transferred to the tsft register and the transmit buffer empty flag (untbe) is set. the untbe flag is automatically reset by the usart when the software loads a new character into the untbuf register. during transmission, the unxmip bit is set high by the usart. this bit is reset only after the usart has sent the last stop bit of the current character and the untbuf reg- ister is empty. the untbuf register is a read/write register. the tsft register is not user accessible. in asynchronous mode, the input frequency to the usart is 16 times the baud rate. in other words, there are 16 clock cy- cles per bit time. in asynchronous mode the baud rate gen- erator is always the usart clock source. the receive shift register (rsft) and the receive buffer (un- rbuf) double buffer the data being received. the usart re- ceiver continuously monitors the signal on the rdxn pin for a low level to detect the beginning of a start bit. upon sensing this low level, the usart waits for seven input clock cycles and samples again three times. if all three samples still indi- cate a valid low, then the receiver considers this to be a valid start bit, and the remaining bits in the character frame are each sampled three times, around the mid-bit position. for any bit following the start bit, the logic value is found by ma- jority voting, i.e. the two samples with the same value define the value of the data bit. figure 33 illustrates the process of start bit detection and bit sampling. serial data input on the rdxn pin is shifted into the rsft register. upon receiving the complete character, the contents of the rsft register are copied into the unrbuf register and the receive buffer full flag (unrbf) is set. the unrbf
www.national.com 72 flag is automatically reset when software reads the character from the unrbuf register. the rsft register is not user ac- cessible. 18.2.2 synchronous mode the synchronous mode of the usart enables the device to communicate with other devices using three communication signals: transmit, receive, and clock. in this mode, data bits are transferred synchronously with the usart clock signal. data bits are transmitted on the rising edges and received on the falling edges of the clock signal, as shown in figure 34. data bytes are transmitted and received least significant bit (lsb) first. in the synchronous mode, the transmit shift register (tsft) and the transmit buffer (untbuf) double-buffer the data for transmission. to transmit a character, a data byte is loaded in the untbuf register. the data is then transferred to the tsft register. the tsft register shifts out one bit of the cur- rent character, lsb first, on each rising edge of the clock. figure 32. usart block diagram internal bus sys_clk baud clock baud clock tdxn rdxn transmitter receiver baud rate generator control and error detection parity generator/checker ckxn figure 33. usart asynchronous communication 12345678910111213141516 1 16 sample sample startbit data (lsb) 12345678910111213141516 1 16 sample databit
73 www.national.com while the tsft is shifting out the current character on the tdxn pin, the untbuf register may be loaded by the soft- ware with the next byte to be transmitted. when the tsft fin- ishes transmission of the last stop bit within the current frame, the contents of untbuf are transferred to the tsft register and the transmit buffer empty flag (untbe) is set. the untbe flag is automatically reset by the usart when the software loads a new character into the untbuf register. during transmission, the unxmip bit is set high by the usart. this bit is reset only after the usart has sent the last frame bit of the current character and the untbuf regis- ter is empty. the receive shift register (rsft) and the receive buffer (unrbuf) double-buffer the data being received. serial data received on the rdxn pin is shifted into the rsft register at the first falling edge of the clock. each subsequent falling edge of the clock causes an additional bit to be shifted into the rsft register. the usart assumes a complete charac- ter has been received after the correct number of rising edg- es on ckxn (based on the selected frame format) have been detected. upon receiving a complete character, the contents of the rsft register are copied into the unrbuf register and the receive buffer full flag (unrbf) is set. the unrbf flag is automatically reset when the software reads the char- acter from the unrbuf register. the transmitter and receiver may be clocked from either an external source provided to the ckxn pin or by the internal baud rate generator. in the latter case, the clock signal is placed on the ckxn pin as an output. 18.2.3 attention mode the attention mode is available for networking this device with other processors. this mode requires the 9-bit data for- mat with no parity. the number of start bits and number of stop bits are programmable. in this mode, two types of 9-bit characters are sent on the network: address characters con- sisting of 8 address bits and a 1 in the ninth bit position and data characters consisting of 8 data bits and a 0 in the ninth bit position. while in attention mode, the usart receiver monitors the communication flow but ignores all characters until an ad- dress character is received. upon the receipt of an address character, the contents of the receive shift register are copied to the receive buffer. the unrbf flag is set and an interrupt (if enabled) is generated. the unatn bit is automatically re- set to zero, and the usart begins receiving all subsequent characters. the software must examine the contents of the unrbuf register and respond by accepting the subsequent characters (by leaving the unatn bit reset) or waiting for the next address character (by setting the unatn bit again). the operation of the usart transmitter is not affected by the selection of this mode. the value of the ninth bit to be trans- mitted is programmed by setting or clearing a bit called unxb9 in the usart frame select register. the value of the ninth bit received is read from unrb9 in the usart status register. 18.2.4 diagnostic mode the diagnostic mode is available for testing of the usart. in this mode, the tdxn and rdxn pins are internally connected together, and data that is shifted out of the transmit shift reg- ister is immediately transferred to the receive shift register. this mode supports only the 9-bit data format with no parity. the number of start and stop bits is programmable. 18.2.5 frame format selection the format shown in figure 35 consists of a start bit, seven data bits (excluding parity), and one or two stop bits. if parity bit generation is enabled by setting the unpen bit, a parity bit is generated and transmitted following the seven data bits. the format shown in figure 36 consists of one start bit, eight data bits (excluding parity), and one or two stop bits. if parity bit generation is enabled by setting the unpen bit, a parity bit is generated and transmitted following the eight data bits. the format shown in figure 37 consists of one start bit, nine data bits, and one or two stop bits. this format also supports the usart attention feature. when operating in this format, all eight bits of untbuf and unrbuf are used for data. the figure 34. usart synchronous communication ckx tdx rdx sample input figure 35. seven data bit frame options figure 36. eight data bit frame options 1 start bit 7 bit data s 1a start bit 7 bit data 2s 1c start bit 7 bit data 2s pa 1b start bit 7 bit data s pa 2 start bit 8 bit data s 2a start bit 8 bit data 2s 2b start bit 8 bit data s pa 2c start bit 8 bit data 2s pa
www.national.com 74 ninth data bit is transmitted and received using two bits in the control registers, called unxb9 and unrb9. parity is not gen- erated or verified in this mode. 18.2.6 baud rate generator the baud rate generator creates the basic baud clock from the system clock. the system clock is passed through a two- stage divider chain consisting of a 5-bit baud rate prescaler (unpsc) and an 11-bit baud rate divisor (undiv). the relationship between the 5-bit prescaler select (unpsc) setting and the prescaler factors is shown in table 19. a prescaler factor of zero corresponds to no clock. the no clock condition is the usart power down mode, in which the usart clock is turned off to reduce power consumption. the application program should select the no clock condi- tion before entering a new baud rate. otherwise, it could cause incorrect data to be received or transmitted. the unpsr register must contain a value other than zero when an external clock is used at ckxn. in asynchronous mode, the baud rate is calculated by: where br is the baud rate, sys_clk is the system clock, n is the value of the baud rate divisor + 1, and p is the prescaler divide factor selected by the value in the unpsr register. the divide by 16 is performed because in the asynchronous mode, the input frequency to the usart is 16 times the baud rate. in synchronous mode, the input clock to the usart equals the baud rate. 18.2.7 interrupts the usart is capable of generating interrupts on: ? receive buffer full ? receive error ? transmit buffer empty figure 38 shows a diagram of the interrupt sources and as- sociated enable bits. figure 37. nine data bit frame options table 19 prescaler factors prescaler select prescaler factor prescaler select prescaler factor 00000 1 10000 8.5 00001 1 10001 9 00010 1.5 10010 9.5 00011 2 10011 10 00100 2.5 10100 10.5 00101 3 10101 11 00110 3.5 10110 11.5 00111 4 10111 12 01000 4.5 11000 12.5 01001 5 11001 13 01010 5.5 11010 13.5 01011 6 11011 14 3 start bit 9 bit data s 3a start bit 9 bit data 2s 01100 6.5 11100 14.5 01101 7 11101 15 01110 7.5 11110 15.5 01111 8 11111 16 table 19 prescaler factors prescaler select prescaler factor prescaler select prescaler factor br sys _ clk 16 np () ------------------------------ - = figure 38. usart interrupts uneei uneri unerr unrbf unfe undoe unpe rx interrupt uneti untbe tx interrupt
75 www.national.com the interrupts can be individually enabled or disabled using the enable transmit interrupt (uneti), enable receive inter- rupt (uneri) and enable receive error interrupt (uneer) bits in the unictrl register. a transmit interrupt is generated when both the untbe and uneti bits are set. to remove this interrupt, software must ei- ther disable the interrupt by clearing the uneti bit or write to the untbuf register (thus clearing the untbe bit). a receive interrupt is generated on two conditions: 1. both the unrbf and uneri bits are set. to remove this interrupt, software must either disable the interrupt by clearing the uneri bit or read from the unrbuf register (thus clearing the unrbf bit). 2. both the unerr and the uneei bits are set. to remove this interrupt the software must either disable it by clear- ing the uneei bit or read the unstat register (thus clearing the unerr bit). 18.2.8 break generation and detection a line break is generated when the brk bit is set in the un- mdsl register. the tdxn line remains low until the program resets the brk bit. a line break is detected if rdxn remains low for 10 bit times or longer after a missing stop bit is detected. 18.2.9 parity generation and detection parity is only generated or checked with the 7-bit and 8-bit data formats. it is not generated or checked in the diagnostic loopback mode, the attention mode, or in the normal mode with the 9-bit data format. parity generation and checking are enabled and disabled via the pen bit in the unfrs register. the unpsel bits in the unfrs register are used to select odd, even, mark, or space parity. 18.3 usart registers the software interacts with the usart by accessing the us- art registers. there are eight such registers: usart receive data buffer (unrbuf) usart transmit data buffer (untbuf) usart baud rate prescaler register (unpsr) usart baud rate divisor register (unbaud) usart frame select register (unfrs) usart mode select register (unmdsl) usart status register (unstat) usart interrupt control register (unictrl) 18.3.1 usart receive data buffer (unrbuf) the usart receive data buffer is a byte-wide, read/write register used to receive each data byte. 18.3.2 usart transmit data buffer (untbuf) the usart transmit data buffer is a byte-wide, read/write register used to transmit each data byte. 18.3.3 usart baud rate prescaler (unpsr) the usart baud rate prescaler register is a byte-wide, read/write register that contains the 5-bit clock prescaler and the upper three bits of the baud rate divisor. this register is cleared upon reset. the register format is shown below. unpsc prescaler. this 5-bit field specifies the prescal- er value used for dividing the system clock in the first stage of the two-stage divider chain. for the prescaler factors corresponding to each 5-bit value, see table 19. undiv[10:8] baud rate divisor (bits 10-8). this field con- tains the three highest-order bits (bits 10, 9, and 8) of the usart baud rate divisor used in the second stage of the two-stage divider chain. the remaining bits of the baud rate divi- sor are contained in the unbaud register. 18.3.4 usart baud rate divisor (unbaud) the usart baud rate divisor register is a byte-wide, read/ write register that contains the lower eight bits of the baud rate divisor. this register contents are unknown upon power- up and are left unchanged by a reset operation. the register format is shown below. undiv[7:0] baud rate divisor (bits 7-0). this field contains the eight lowest-order bits of the usart baud rate divisor used in the second stage of the two-stage divider chain. the three highest-or- der bits are contained in the unpsr register. the divisor value used is the 11-bit undiv val- ue plus 1. 18.3.5 usart frame select register (unfrs) the usart frame select register is a byte-wide, read/write register that controls the frame format, including the number of data bits, number of stop bits, and parity type. this register is cleared upon reset. the register format is shown below. unchar character frame format. this 2-bit field se- lects the number of data bits per frame, not in- cluding the parity bit, as follows: 00 = eight data bits per frame 01 = seven data bits per frame 10 = nine data bits per frame 11 = loopback mode; nine data bits per frame unstp number of stop bits. this bit sets the number of stop bits transmitted in each frame. if this bit is 0, one stop bit is transmitted. if this bit is 1, two stop bits are transmitted. unxb9 transmit 9th data bit. this bit is the value of the ninth data bit, either 0 or 1, transmitted when the usart is configured to transmit nine data bits per frame. it has no effect when the usart is configured to transmit seven or eight data bits per frame. 7 6 5 4 3 2 1 0 unpsc undiv10 undiv9 undiv8 7 6 5 4 3 2 1 0 undiv7 undiv6 undiv5 undiv4 undiv3 undiv2 undiv1 undiv0 7 6 5 4 3 2 1 0 reserved unpen unpsel unxb9 unstp unchar
www.national.com 76 unpsel parity select. this 2-bit field selects parity type as follows: 00 = odd parity 01 = even parity 10 = mark (0) 11 = space (1) when the usart is configured to transmit nine data bits per frame, the parity bit is omitted and the unpsel field is ignored. unpen parity enable. this bit enables (1) or disables (0) parity bit generation and parity checking. when the usart is configured to transmit nine data bits per frame, there is no parity bit and the unpen bit is ignored. 18.3.6 usart mode select register (unmdsl) the usart mode select register is a byte-wide, read/write register that selects the clock source, synchronization mode, attention mode, and line break generation. this register is cleared upon reset. when the software writes to this register, the reserved bits must be cleared to 0 for proper operation. the register format is shown below. unmod mode of operation. set to 0 for asynchronous operation or 1 for synchronous operation. unatn attention mode. when set to 1, this bit selects the attention mode of operation for the usart. when cleared to 0, the attention mode is dis- abled. the hardware clears this bit after an ad- dress frame is received. an address frame is a 9-bit character with a 1 in the ninth bit position. unbrk force transmission break. setting this bit to 1 causes the tdxn pin to go low. tdxn remains low until the unbrk bit is cleared to 0 by the software. uncks synchronous clock source. this bit controls the clock source when the usart operates in the synchronous mode (unmod=1). if the uncks bit is set to 1, the usart operates from an external clock provided on the ckxn pin. if the uncks bit is cleared to 0, the usart operates from the baud rate clock produced by the usart on the ckxn pin. this bit is ignored when the usart operates in the asynchro- nous mode. 18.3.7 usart status register (unstat) the usart status register is a byte-wide, read-only regis- ter that contains the receive and transmit status bits. this register is cleared upon reset. any attempt by the software to write to this register is ignored. the register format is shown below. unpe parity error. this bit is set to 1 when a parity er- ror is detected within a received character. this bit is automatically cleared to 0 by the hardware when the unstat register is read. unfe framing error. this bit is set to 1 when the us- art fails to receive a valid stop bit at the end of a frame. this bit is automatically cleared to 0 by the hardware when the unstat register is read. undoe data overrun error. this bit is set to 1 when a new character is received and transferred to the unbuf register before the software has read the previous character from unbuf. this bit is automatically cleared to 0 by the hardware when the unstat register is read. unerr error status flag. this bit is set when a parity, framing, or overrun error occurs (any time that the unpe, unfe, or undoe bit is set). it is au- tomatically cleared to 0 by the hardware when the unpe, unfe, and undoe bits are all 0. unbkd break detect. this bit is set to 1 when a line break condition occurs. this condition is de- tected if rdxn remains low for at least ten bit times after a missing stop bit has been detect- ed at the end of a frame. the hardware automatically clears the unbkd bit upon read of the unstat register, but only if the break condition on rxdn no longer exists. if reading the unstat register does not clear the unbkd bit because the break is still active- ly driven on the line, the hardware clears the bit as soon as the break condition no longer exists (when rxdn returns to a high level). unrb9 received 9th data bit. with the usart config- ured to operate in the 9-bit data format, this is equal to the ninth data bit of the last frame re- ceived. unxmip transmit in progress. the hardware sets this bit to 1 when the usart is transmitting data and clears it to 0 at the end of the last frame bit. 18.3.8 usart interrupt control register (unictrl) the usart interrupt control register is a byte-wide register that contains the receive and transmit interrupt status flags (read-only bits) and the interrupt enable bits (read/write bits). the register is set to 01 hex upon reset. the register format is shown below. untbe transmit buffer empty. this read-only bit is set to 1 by the hardware when the usart trans- fers data from the untbuf register to the transmit shift register for transmission. it is au- tomatically cleared to 0 by the hardware on the next write to the untbuf register. unrbf receive buffer full. this read-only bit is set by the hardware when the usart has received a complete data frame and has transferred the data from the receive shift register to the unr- buf register. it is automatically cleared to 0 by the hardware when the unrbuf register is read. 7 6 5 4 3 2 1 0 reserved uncks unbrk unatn unmod 7 6 5 4 3 2 1 0 reserved unxmip unrb9 unbkd unerr undoe unfe unpe 7 6 5 4 3 2 1 0 uneei uneri uneti reserved unrbf untbe
77 www.national.com uneti enable transmitter interrupt. this read/write bit, when set to 1, enables generation of an in- terrupt when the hardware sets the untbe bit. uneri enable receiver interrupt. this read/write bit, when set to 1, enables generation of an inter- rupt when the hardware sets the unrbf bit. uneei enable receive error interrupt. this read/write bit, when set to 1, enables generation of an in- terrupt when the hardware sets the unerr bit in the unstat register. 18.4 baud rate calculations the usart baud rate is determined by the system clock fre- quency and the values programmed into the unpsr and un- baud registers. unless the system clock frequency is an exact multiple of the desired baud rate, there will be a small amount of error in the resulting baud rate clock. the method of baud rate calculation depends on whether the usart is configured to operate in the asynchronous or syn- chronous mode. 18.4.1 baud rate in asynchronous mode the equation for calculating the baud rate in asynchronous mode is: where br is the baud rate, sys_clk is the system clock, n is the value of the baud rate divisor + 1, and p is the prescaler divide factor selected by the value in the unpsr register. assuming a system clock of 5 mhz and a desired baud rate of 9600, the nxp term according to the equation above is: the nxp term is then divided by each prescaler factor from table 19 to obtain a value closest to an integer. the factor for this example is 6.5. the baud rate register is programmed with a baud rate divi- sor of 4 (n = baud rate divisor +1). this produces a baud clock of: note that the percent error is much lower than would be pos- sible without the non-integer prescaler factor. refer to the ta- ble below for more examples. 18.4.2 baud rate in synchronous mode the equation for calculating the baud rate in synchronous mode is: where br is the baud rate, sys_clk is the system clock, n is the value of the baud rate divisor + 1, and p is the prescaler divide factor selected by the value in the unpsr register. use the same procedure to determine the values of n and p as in the asynchronous mode. in this case, however, only in- teger prescaler values are allowed. br sys _ clk 16 np () ------------------------------ - = np 5 6 10 () 16 9600 () ---------------------------- - 32.552 == n 32.552 6.5 --------------- - 5.008 (n = 5) == br 5 6 10 () 1656.5 () --------------------------------- 9615.385 == % error 9615.385 9600 C () 9600 -------------------------------------------- -0.16 == system clock desired baud rate np actual baud rate percent error 4 mhz 9600 2 13 9615.385 0.16 5 mhz 9600 5 6.5 9615.385 0.16 10 mhz 19200 5 6.5 19230.769 0.16 20 mhz 19200 5 13 19230.769 0.16 br sys _ clk 2 np () --------------------------- - =
www.national.com 78 19.0 access.bus interface the access.bus interface module (acb) is a two wire serial interface compatible with the access.bus physical layer. it permits easy interfacing to a wide range of low-cost memo- ries and i/o devices, including: eeproms, srams, timers, a/d converters, d/a converters, clock chips and peripheral drivers. it is also compatible with intels smbus and philips i 2 c bus. the module can be configured as a bus master or slave, and can maintain bi-directional communications with both multiple master and slave devices. this section presents an overview of the bus protocol, and its implementation by the module. access.bus, smbus and i 2 c compliant access.bus master and slave supports polling and interrupt controlled operation generate a wake-up signal on detection of a start con- dition, while in power-down mode optional internal pull-up on sda and scl pins 19.1 acb protocol overview the access.bus protocol uses a two-wire interface for bi-di- rectional communications between the ics connected to the bus. the two interface lines are the serial data line (sda), and the serial clock line (scl). these lines should be con- nected to a positive supply, via a pull-up resistor, and remain high even when the bus is idle. the access.bus protocol supports multiple master and slave transmitters and receivers. each ic has a unique ad- dress and can operate as a transmitter or a receiver (though some peripherals are only receivers). during data transactions, the master device initiates the transaction, generates the clock signal and terminates the transaction. for example, when the acb initiates a data transaction with an attached access.bus compliant periph- eral, the acb becomes the master. when the peripheral re- sponds and transmits data to the acb, their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed. 19.1.1 data transactions one data bit is transferred during each clock pulse. data is sampled during the high state of the serial clock (scl). con- sequently, throughout the clocks high period, the data should remain stable (see figure 39). any changes on the sda line during the high state of the scl and in the middle of a trans- action aborts the current transaction. new data should be sent during the low scl state. this protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. figure 39. bit transfer each data transaction is composed of a start condition, a number of byte transfers (set by the software), and a stop condition to terminate the transaction. each byte is trans- ferred with the most significant bit first, and after each byte (8 bits), an acknowledge signal must follow. at each clock cycle, the slave can stall the master while it handles the previous data, or prepares new data. this can be done for each bit transferred or on a byte boundary by the slave holding scl low to extend the clock-low period. typical- ly, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored, or if the next byte to be transmitted is not yet ready. some microcontrollers with limited hardware support for acess.bus extend the access after each bit, thus allowing the software time to handle this bit. start and stop the access.bus master generates start and stop condi- tions (control codes). after a start condition is generated the bus is considered busy and it retains this status until a certain time after a stop condition is generated. a high-to-low tran- sition of the data line (sda) while the clock (scl) is high in- dicates a start condition. a low-to-high transition of the sda line while the scl is high indicates a stop condition (figure 40). figure 40. start and stop conditions in addition to the first start condition, a repeated start con- dition can be generated in the middle of a transaction. this allows another device to be accessed, or a change in the di- rection of the data transfer. acknowledge cycle the acknowledge cycle consists of two signals: the acknowl- edge clock pulse the master sends with each byte trans- sda scl data line stable: data valid change of data allowed sda scl s p start condition stop condition
79 www.national.com ferred, and the acknowledge signal sent by the receiving device (figure 41). figure 41. access.bus data transaction the master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. the transmitter releas- es the sda line (permits it to go high) to allow the receiver to send the acknowledge signal. the receiver must pull down the sda line during the acknowledge clock pulse, thus sig- nalling the correct reception of the last data byte, and its readiness to receive the next byte. figure 42 illustrates the acknowledge cycle. figure 42. access.bus acknowledge cycle the master generates an acknowledge clock pulse after each byte transfer. the receiver sends an acknowledge sig- nal after every byte received. there are two exceptions to the acknowledge after every byte rule. 1. when the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (nega- tive acknowledge) the last byte clocked out of the slave. this negative acknowledge still includes the acknowl- edge clock pulse (generated by the master), but the sda line is not pulled down. 2. when the receiver is full, otherwise occupied, or a prob- lem has occurred, it sends a negative acknowledge to in- dicate that it can not accept additional data bytes. addressing transfer formats each device on the bus has a unique address. before any data is transmitted, the master transmits the address of the slave being addressed. the slave device should send an ac- knowledge signal on the sda line, once it recognizes its ad- dress. the address is the first seven bits after a start condition. the direction of the data transfer (r/w ) depends on the bit sent after the address the eighth bit. a low-to-high transition during a scl high period indicates the stop condition, and ends the transaction (figure 43). figure 43. a complete access.bus data transaction when the address is sent, each device in the system com- pares this address with its own. if there is a match, the device considers itself addressed and sends an acknowledge sig- nal. depending upon the state of the r/w bit (1:read, 0:write), the device acts as a transmitter or a receiver. the i 2 c bus protocol allows sending a general call address to all slaves connected to the bus. the first byte sent speci- fies the general call address (00 16 ) and the second byte specifies the meaning of the general call (for example, write slave address by software only). those slaves that require the data acknowledge the call and become slave receivers; the other slaves ignore the call. arbitration on the bus multiple master devices on the bus, require arbitration be- tween their conflicting bus-access demands. control of the bus is initially determined according to address bits and clock cycle. if the masters are trying to address the same ic, data comparisons determine the outcome of this arbitration. in master mode, the device immediately aborts a transaction if the value sampled on the sda lines differs from the value driven by the device. (exceptions to this rule are sda while receiving data; in these cases the lines may be driven low by the slave without causing an abort). the scl signal is monitored for clock synchronization pur- pose and allow the slave to stall the bus. the actual clock pe- riod will be the one set by the master with the longest clock period or by the slave stall period. the clock high period is determined by the master with the shortest clock high period. when an abort occurs during the address transmission, the master that identify the conflict, give-up the bus and should switch to slave mode and continue to sample sda to see if it is being addressed by the winning master on the ac- cess.bus. 19.2 acb functional description the acb module provides the physical layer for an ac- cess.bus compliant serial interface. the module is config- urable as either a master or slave device. as a slave device, the acb module may issue a request to become the bus master. s p start condition stop condition sda scl msb ack ack 12 3 - 6 7 8 91 2 3 - 8 9 acknowledgment signal from receiver byte complete i nterrupt within receiver clock line held low by receiver while interrupt is serviced s start condition scl 12 3 - 6 7 8 9 transmitter stays off the bus during the ackno wledgment clock ackno wledgment signal from receiver data output by transmitter data output by receiver s p start condition stop condition sda scl 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 address r/w ack data ack data ack
www.national.com 80 19.2.1 master mode an access.bus transaction starts with a master device re- questing bus mastership. it sends a start condition, followed by the address of the device it wants to access. if this trans- action is successfully completed, the software can assume that the device has become the bus master. for a device to become the bus master, the software should perform the following steps: 1. set acbctl1.start, and configure acbctl1.inten to the desired operation mode (polling or interrupt). this causes the acb to issue a start condition on the ac- cess.bus, as soon as the access.bus is free (acbcst.bb=0). it then stalls the bus by holding scl low. 2. if a bus conflict is detected, (i.e., some other device pulls down the scl signal before this device does), acb- st.ber is set. 3. if there is no bus conflict, acbst.master and acb- st.sdast are set. 4. if acbctl1.inten is set, and either acbst.ber or acbst.sdast is set, an interrupt is sent to the icu. sending the address byte once this device is the active master of the access.bus (acbst.master is set), it can send the address on the bus. the address sent should not be this devices own address as defined in acbaddr.addr if acbaddr.saen is set, nor should it be the global call address if acbst.gcmtch is set. to send the address byte use the following sequence: 1. configure the acbctl1.inten bit according to the de- sired operation mode. for a receive transaction where the software wants only one byte of data, it should set the acbctl1.ack bit. if only an address needs to be sent, set (1) the acbctl1.stastre bit. 2. write the address byte (7-bit target device address), and the direction bit, to the acbsda register. this causes the module to generate a transaction. at the end of this transaction, the acknowledge bit received is copied to acbst.negack. during the transaction the sda and scl lines are continuously checked for conflict with oth- er devices. if a conflict is detected, the transaction is aborted, acbst.ber is set, and acbst.master is cleared. 3. if acbctl1.stastre is set, and the transaction was successfully completed (i.e., both acbst.ber and acbst.negack are cleared), acbst.stastr is set. in this case, the acb stalls any further access.bus op- erations (i.e., holds scl low). if acbctl1.inte is set, it also sends an interrupt to the core. 4. if the requested direction is transmit, and the start trans- action was completed successfully (i.e., neither acb- st.negack nor acbst.ber is set, and no other master has accessed the device), acbst.sdast is set to indicate that the module awaits attention. 5. if the requested direction is receive, the start transaction was completed successfully and acbctl1.stastre is cleared, the module starts receiving the first byte auto- matically. 6. check that both acbst.ber and acbst.negack are cleared. if the acbctl1.inten bit is set, an interrupt is generated when either acbst.ber or acbst.negack is set. master transmit after becoming the bus master, the device can start transmit- ting data on the access.bus. to transmit a byte, the software should: 1. check that the ber and negack bits in acbst are cleared and acbst.sdast is set. also, if acbctl1.stastre is set, check that acbst.stastr is cleared. 2. write the data byte to be transmitted to the acbsda reg- ister. when the slave responds with a negative acknowledge, the acbst.negack bit is set and the acbst.sdast bit re- mains cleared. in this case, if acbctl1.inten is set, an in- terrupt is sent to the core. master receive after becoming the bus master, the device can start receiving data on the access.bus. to receive a byte, the software should: 1. check that acbst.sdast is set and acbst.ber is cleared. also, if acbctl1.stastre is set, check that acbst.stastr is cleared. 2. set the acbctl1.ack bit to 1, if the next byte is the last byte that should be read. this causes a negative ac- knowledge to be sent. 3. read the data byte from the acbsda register. master stop a stop condition may be issued only when this device is the active bus master (acbst.mastrer=1). to end a transac- tion, set (1) acbctl1.stop before clearing the current stall flag (i.e., acbst.sdast, acbst.negack or acbst.stas- tr). this causes the module to send a stop condition imme- diately, and clear acbctl1.stop. master bus stall the acb module can stall the access.bus between trans- fers while waiting for the cores response. the access.bus is stalled by holding the scl signal low after the acknowl- edge cycle. note that this is interpreted as the beginning of the following bus operation. the user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared. the flags that can cause a stall in master mode are: negative acknowledge after sending a byte (acbst- negack=1). acbst.sdast bit is set. if acbctl1.stastre=1, after a successful start (acbst.stastr=1). repeated start a repeated start is performed when this device is already the bus master (acbst.master is set). in this case the ac- cess.bus is stalled and the acb is awaiting the core han- dling due to: negative acknowledge (acbst.negack=1),
81 www.national.com empty buffer (acbst.sdast=1) and/or a stop after start (acbst.stastr=1). for a repeated start: set the acbctl1.start bit. in master receive mode, read the last data item from acbsda. follow the address send sequence, as described in sending the address byte on page 80. if the acb was awaiting handling due to acbst.stas- tr=1, clear it only after writing the requested address and direction to acbsda. master error detections the acb detects illegal start or stop conditions (i.e., a start or stop condition within the data transfer, or the acknowl- edge cycle) and a conflict on the data lines of the ac- cess.bus. if an illegal action is detected, ber is set, and the master mode is exited (master is cleared). bus idle error recovery when a request to become the active bus master or a restart operation fails, the acbst.ber bit is set to indicate the error. in some cases, both this device and the other device may identify the failure and leave the bus idle. in this case, the start sequence may not be completed and the access.bus may remain deadlocked forever. to recover from deadlock, use the following sequence: 1. clear the acbst.ber bit and acbcst.bb bit. 2. wait for a time-out period to check that there is no other active master on the bus (i.e., acbcst.bb remains cleared). 3. disable, and re-enable the acb to put it in the non-ad- dressed slave mode. 4. at this point some of the slaves may not identify the bus error. to recover, the acb becomes the bus master by issuing a start condition and sends an address field; then issue a stop condition to synchronize all the slaves. 19.2.2 slave mode a slave device waits in idle mode for a master to initiate a bus transaction. whenever the acb is enabled, and it is not act- ing as a master (i.e., acbst.master is cleared), it acts as a slave device. once a start condition on the bus is detected, this device checks whether the address sent by the current master matches either: the acbaddr.addr value if acbaddr.saen is set. the general call address if acbctl1.gcm is set. this match is checked even when acbst.master is set. if a bus conflict (on sda or scl) is detected, acbst.ber is set, acbst.master is cleared and this device continues to search the received message for a match. if an address match, or a global match, is detected: this device asserts its data pin during the acknowl- edge cycle. the acbcst.match and acbst.nmatch bits are set. if acbst.xmit is set (i.e., slave transmit mode), acbst.sdast is set to indicate that the buffer is emp- ty. if acbctl1.inten is set, an interrupt is generated if both the inten and nminte bits in acbctl1 regis- ters are set. the software then reads the acbst.xmit bit to identi- fy the direction requested by the master device. it clears the acbst.nmatch bit so future byte transfers are identified as data bytes. slave receive and transmit slave receive and transmit are performed after a match is detected and the data transfer direction is identified. after a byte transfer the acb extend the acknowledge clock until the software reads or writes the acbsda register. the receive and transmit sequence are identical to those used in the master routine. slave bus stall when operating as a slave, this device stalls the ac- cess.bus by extending the first clock cycle of a transaction in the following cases: acbst.sdast is set. acbst.nmatch, and acbctl1.nminte are set. slave error detections the acb detects illegal start and stop conditions on the ac- cess.bus (i.e., a start or stop condition within the data transfer or the acknowledge cycle). when an illegal start or stop condition is detected, the ber bit is set and match and gmatch are cleared, setting the module to be an unad- dressed slave. power down when this device is in power save, idle, or halt mode, the acb module is not active but retains its status. if the acb is enabled (acbctl2.enable=1) on detection of a start con- dition, a wake-up signal is issued to the miwu module. use this signal to switch this device to active mode. the acb module cannot check the address byte following the start condition that has awaken this device for a match. the acb responds with a negative acknowledge, and the device should re-send both the start condition and the address af- ter this device has had time to wake up. check that the acbcst.busy bit is inactive before entering power save, idle or halt mode. this guarantees that this de- vice does not acknowledge an address sent, and stop re- sponding later. 19.2.3 sda and scl pins configuration the sda and scl are open-drain signals. for more informa- tion, see the i/o configuration section. 19.2.4 acb clock frequency configuration the acb module permits the user to set the clock frequency used for the access.bus clock. the clock is set by the acbctl2.sclfrq field. this field determines the scl clock period used by this device. this clock low period may be extended by stall periods initiated by the acb module or by another access.bus device. in case of a conflict with an- other bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved.
www.national.com 82 19.3 acb registers the access.bus interface uses the following registers: acb serial data register (acbsda) acb status register (acbst) acb status control register (acbcst) acb control 1 register (acbctl1) acb control 2 register (acbctl2) acb own address register (acbaddr) 19.3.1 acb serial data register (acbsda) the acb serial data register (acbsda) is a byte-wide, read/write shift register used to transmit and receive data. the most significant bit is transmitted (received) first and the least significant bit is transmitted (received) last. reading or writing to the acbsda register is allowed when acb- st.sdast is set; or for repeated starts after setting the start bit. an attempt to access the register in other cases produces unpredictable results. 19.3.2 acb status register (acbst) the acb status register (acbst) is a byte-wide, read-only register that maintains current acb status. upon reset, and when the module is disabled, acbst is cleared (00 16 ). xmit direction bit. the xmit bit is set when the acb module is currently in master/slave transmit mode. otherwise it is cleared. master master. when set, the master bit indicates that the module is currently in master mode. it is set when a request for bus mastership suc- ceeds. it is cleared upon arbitration loss (ber is set) or the recognition of a stop condition. nmatch new match. the nmatch bit is set when the address byte following a start condition, or re- peated starts, causes a match or a global-call match. nmatch is cleared when 1 is written to it. writing 0 to nmatch is ignored. if acbctl1.inten is set, an interrupt is sent when this bit is set. stastr stall after start. the stastr bit is set by the successful completion of an address sending (i.e., a start condition sent without a bus error, or negative acknowledge) if acbctl1.stas- tre is set. this bit is ignored in slave mode. when stastr is set, it stalls the access.bus by pulling down the scl line, and suspends any other action on the bus (e.g., receives first byte in master receive mode). in addition, if acbctl1.inten is set, it also sends an inter- rupt to the core. writing 1 to stastr clears it. it is also cleared when the module is disabled. writing 0 to stastr has no effect. negack negative acknowledge. this bit is set by hard- ware when a transmission is not acknowledged on the ninth clock. (in this case sdast is not set.) writing 1 to negack clears it. it is also cleared when the module is disabled. writing 0 to negack is ignored. ber bus error. ber is set by the hardware when a start or stop condition is detected during data transfer (i.e., start or stop condition during the transfer of bits 2 through 8 and acknowledge cycle), or when an arbitration problem is detect- ed. writing 1 to ber clears it. it is also cleared when the module is disabled. writing 0 to ber is ignored. sdast sda status. when set, this bit indicates that the sda data register is waiting for data (trans- mit - master or slave) or holds data that should be read (receive - master or slave). this bit is cleared when reading from the acbsda regis- ter during a receive, or when written to during a transmit. when acbctl1.start is set, read- ing acbsda register does not clear sdast. this enables the acb to send a repeated start in master receive mode. slvstp slave stop. if set, slvstp indicates that a stop condition was detected after a slave transfer (i.e., after a slave transfer in which match or gcmatch is set). writing 1 to slvstp clears it. it is also cleared when the module is dis- abled. writing 0 to slvstp is ignored. 19.3.3 acb control status register (acbcst) acb control status register (acbcst) is a byte-wide, read/ write register that maintains current acb status. upon reset and when the module is disabled, the non-reserved bits of acbcst are cleared (0). busy busy. when busy is set, it indicates that the acb module is: ? generating a start condition ? in master mode (acbst.master is set) ? in slave mode (acbcst.match or acbcst.gcmtch is set) ? in the period between detecting a start and completing the reception of the address byte. after this, the acb either becomes not busy or enters slave mode. the busy bit is cleared by the completion of any of the above states, and by disabling the module. busy is a read only bit. it should al- ways be written with 0. bb bus busy when set, bb indicates the bus is busy. it is set when the bus is active (i.e., a low level on either sda or scl), or by a start con- dition. it is cleared when the module is dis- abled, upon detection of a stop condition, or when writing 1 to this bit. see usage hints on page 84 for a description of the use of this bit. this bit should be set when either sda or scl are low. this should be done by sampling the sda and scl lines continuously and, setting the bit if one of them is low. the bit remains set until cleared by a stop condition or a one is written to it. 7 0 data 7 6 5 4 3 2 1 0 slvstp sdast ber negack stastr nmatch master xmit 7 6 5 4 3 2 1 0 reserved tgscl tsda gcmtch match bb busy
83 www.national.com match address match. in slave mode, match is set when acbaddr.saen is set and the first sev- en bits of the address byte (the first byte trans- ferred after a start condition) matches the 7-bit address in the acbaddr register. it is cleared by start condition, repeated start and stop condition (including illegal start or stop condi- tion). gcmtch global call match bit. in slave mode, gcmtch is set when acbctl1.gcmen is set and the address byte (the first byte transferred after a start condition) is 00 16 . it is cleared by start condition, repeated start and stop condition (including illegal start or stop condition). tsda test sda line. reads the current value of the sda line. this bit can be used while recovering from an error condition in which the sda line is constantly pulled low by a slave that went out of synch. this bit is a read-only bit. data written to it is ignored. tgscl toggle scl line. this bit enables toggling the scl line during the process of error recovery. when the sda line is low, writing 1 to this bit toggles the scl line for one cycle. writing 1 to tgscl when sda is high is ignored. the bit is cleared when the clock toggle is completed. 19.3.4 acb control 1 register (acbctl1) acb control 1 register (acbctl1) is a byte-wide, read/write register that configures and controls the acb module. upon reset and while the module is disabled (acbctl2.en- able=0), the acbctl1 is cleared (00 16 ). start start. this bit is set when a start condition needs to be generated on the access.bus. the start bit is cleared when the start con- dition is sent, or upon detection of a bus error (acbst.ber=1). this bit should be set only when in master mode, or when requesting master mode. if this device is not the active master of the bus (acbst.master=0), setting start gener- ates a start condition as soon as the access.bus is free (acbcst.bb=0). an ad- dress send sequence should then be per- formed. if this device is the active master of the bus (acbst.master=1), when start is set, a write to the acbsda register generates a start condition, then the acbsda data is transmit- ted as the slaves address and the requested transfer direction. this case is a repeated start condition. it may be used to switch the direction of the data flow between the master and the slave, or to choose another slave device without using a stop con- dition in between. stop stop. in master mode, setting this bit gener- ates a stop condition that completes or aborts the current message transfer. this bit clears it- self after the stop is issued. inten interrupt enable. when inten is cleared acb interrupt is disabled. when inten is set, inter- rupts are enabled. an interrupt is generated (the interrupt signals to the icu is high) upon one of the following events: ? an address match is detected (acb- st.nmatch=1) and nminte is set. ? a bus error occurs (acbst.berr=1). ? negative acknowledge after sending a byte (acbst.negack=1). ? an interrupt is generated upon acknowl- edge of each transaction (same as the hardware set of the acbst.sdast bit). ? in master mode if acbctl1.stastre=1, after a successful start (acbst.stas- tr=1). ? detection of a stop condition while in slave receive mode (acbst.slvstp=1). ack acknowledge bit. when acting as a receiver (slave or master), this bit holds the value this device sends during the next acknowledge cy- cle. setting this bit to 1 instructs the transmit- ting device to stop sending data, since the receiver either does not need, or cannot re- ceive, any more data. this bit is cleared after the first acknowledge cycle. this bit is ignored when in transmit mode. gcmen global call match enable. when this bit is set, it enables the match of an incoming address byte to the general call address (start condi- tion followed by address byte of 00 16 ) while the acb is in slave mode. when cleared, the acb does not respond to a global call. nminte new match interrupt enable. set nminte to enable the interrupt on a new match (i.e., when acbst.nmatch is set). the interrupt is issued only if acbctl1.inten is set. stastre stall after start enable. when set enables the stall after start mechanism. in such a case, the acb is stalled after the address byte. when stastre is cleared, acbst.stastr is al- ways cleared. 19.3.5 acb control 2 register (acbctl2) the acb control 2 register (acbctl2) is a byte-wide, read/ write register that enables/disables the module and deter- mines acb clock rate. upon reset acbctl2 is set to 00 16 . enable enable. when this bit is set, the acb module is enabled. when the enable bit is cleared, the acb module is disabled, acbctl1, acbst and acbcst are cleared, and the clocks are halted. sclfrq scl frequency. this field defines the scls pe- riod (low time and high time) when this device 7 6 5 4 3 2 1 0 stastre nminte gcmen ack reserved inten stop start 7 1 0 sclfrq enable
www.national.com 84 serves as a bus master. the clock low time and high time are defined as follows: t scll = t sclh = 2*sclfrq*t clk where t clk is this devices clock cycle when in active mode. sclfrq may be programmed to values in the range of 0001000 2 (8 10 ) through 1111111 2 (127 10 ). using any other value has unpredict- able results. 19.3.6 acb own address register (acbaddr) acb own address register (acbaddr) is a byte-wide, read/write register that holds the modules access.bus ad- dress. reset value is undefined. addr own address. holds the 7-bit access.bus ad- dress of this device. when in slave mode, the first seven bits received after a start condition are compared to this field (first bit received to bit-6, and the last to bit-0). if the address field matches the received data and saen is set, a match is declared. saen slave address enable. when set saen indi- cates that the addr field holds a valid address and enables the match of addr to an incoming address byte. when cleared, the acb does not check for an address match. 19.4 usage hints 1. when the acb is disabled the acbcst.bb bit is cleared. after enabling the acb (acbctl2.enable is set to 1) in systems with more then one master, the bus may be in the middle of a transaction with another device, which is not reflected by bb. there is a need to allow the acb to synchronize to the bus activity status before issuing a request to become the bus master, to prevent bus errors. thus, before issu- ing a request to become the bus master for the first time, the software should check that there is no activity on the bus by checking the bb bit after the bus allowed time-out period. 2. when waking up from power down, before checking acbcst.match, use acbcst.busy to make sure that the address transaction is over. 3. the bb bit is intended to solve a deadlock in which two, or more, devices detect a usage conflict on the bus and both devices cease being bus masters at the same time. in this situation, the bb bits of both devices are active (because each deduces that there is another master currently performing a transaction, while in fact no de- vice is executing a transaction), and the bus would stay locked until some device sends a acbctl1.stop con- dition. the acbcst.bb bit allows the software to monitor bus usage, so it can avoid sending a stop signal in the mid- dle of the transaction of some other device on the bus. this bit detects whether the bus remains unused over a certain period, while the bb bit is set. 4. in some cases the bus may get stuck with the scl and/ or sda lines active. a possible cause to this is an erro- neous start or stop conditions that occur in the middle of a slave receive session. when the scl line is stuck active, there is nothing that can be done, and it is the responsibility of the module that holds the bus to release it. in case of sda line is stuck active, the acb module en- able the release of the bus by using the following se- quence. note that in normal cases scl may be toggled only by the bus master. this protocol is a recovery scheme which is an exception that should be used only in the case where there is no other master on the bus. the recovery scheme is as follows: a. disable and re-enable the module to set it into the not addressed slave mode. b set the acbctl1.start bit to make an attempt to issue a start condition. c. check if the sda line is active (low) by reading acbcst.tsda bit. if it is active, issue a single scl cycle by writing 1 to acbcst.tgscl bit. if the sda line is not active, continue from step e. d. check if acbst.master is set, which indicates that the start condition was sent. if not, repeat step c and d until the sda is released. e. clear the bb bit. this enables the start bit to be executed. continue according to bus idle error re- covery on page 81. 7 6 0 saen addr
85 www.national.com 20.0 cr16can module the cr16can device contains a full-can class, can (controller area network) serial bus interface for low/high speed applications. it supports the reception and transmis- sion of extended frames with 29-bit identifier, standard frames with 11-bit identifier, applications that require a high speed (up to 1mbit/s), and a low speed can interface with can master capability. the data transfer between can and the cpu is established by 15 message buffers, which can be individually configured as receive or transmit buffers. every message buffer includes a status/control register which pro- vides information about its current status and capabilities to configure the buffer. all message buffers are able to generate an interrupt upon the reception of a valid frame or the suc- cessful transmission of a frame. in addition, an interrupt on bus errors can be generated. an incoming message is only accepted if the message iden- tifier passes one of two acceptance filtering masks. the filter- ing mask can be configured to receive a single message id per buffer or a group of ids per receive buffer. one of the buff- ers uses a separate message filtering procedure. this pro- vides the capability to establish a basic-can path. remote transmission requests can be processed automatically by automatic reconfiguration to a receiver after transmission or by automated transmit scheduling upon reception. a priority decoder allows any buffer to have one of 16 transmit priorities including the highest or lowest absolute priority, totaling 240 different transmit priorities. a decided bit time counter (16-bit wide) is provided to support real time applications. the contents of this counter is cap- tured into the message buffer ram upon reception or trans- mission. the counter can be synchronized via the can network. this synchronization feature allows a reset of the counter after the reception or transmission of a message in buffer 0. the cr16can is a fast core bus peripheral which allows sin- gle cycle byte or word read/write access. the cpu controls the cr16can by modifying the various registers in the cr16can register block. this includes the initialization of the can baud rate, the can pin logic level, and the enable/ disable of the cr16can. a set of diagnostic features, such as loopback, listen only and error identification, support the development with the cr16can module and provide a so- phisticated error management tool. the cr16can implements the following features: ? can specification 2.0b standard data and remote frames extended data and remote frames 0 - 8 bytes data length programmable bit rate up to 1 mbit/s ? 15 message buffers, each configurable as receive or transmit buffers message buffers are 16-bit wide dual-port ram one buffer may be used as basic-can path ? remote frame support automatic transmission after reception of a remote transmission request (rtr) auto receive after transmission of a rtr ? acceptance filtering two filtering capabilities: global acceptance mask & in- dividual buffer identifiers one of the buffers uses an independent acceptance fil- tering procedure ? programmable transmit priority ? interrupt capability one interrupt vector for all message buffers (receive/ transmit/error) each interrupt source can be enabled/disabled ? 16-bit counter with time stamp capability on successful re- ception or transmission of a message ? power save capabilities with programmable wake-up over the can bus (alternate source for the multi-input wake-up module) ? push-pull capability of the input/output pins ? diagnostic functions error identification loopback and listen-only features for test and initializa- tion purposes 20.1 functional description as shown in figure 44, the cr16can module is separated into three blocks: the can core, the interface management and a dual ported ram containing the message buffers. there are two dedicated device pins for the cr16can inter- face, cantx as the transmit output and canrx as the re- ceive input. the can core implements the basic can protocol features such as bit-stuffing, crc calculation/checking and error management. it controls the transceiver logic and creates er- ror signals according to the bus rules. in addition, it converts the data stream from the cpu (parallel data) to the serial can bus data. the interface management is divided into the register block and the interface management processor. the register block provides the can interface with control information from the cpu and in turn provides the cpu with status information from the can module. additionally it generates the interrupt to the cpu. the interface management processor is a state machine ex- ecuting the cpus transmission and reception commands and controlling the data transfer between several message buffers and rx/tx shift registers. fifteen message buffers are memory mapped into ram to transmit/receive data via the can bus. eight 16-bit registers belong to each buffer. one of the registers contains control and status information about the message buffer configura- tion and the current state of the buffer. the other registers are used for the message identifier, a maximum of up to eight data bytes and the time stamp information. during the re- ceive process the incoming message will be stored at first in a hidden receive buffer until the message is valid. then the buffer contents will be copied into the first message buffer which accepts the id of the received message.
www.national.com 86 20.2 basic can concepts this section provides a generic overview of the basic con- cepts of the controller area network (can). the can protocol is a message based protocol that allows a total of 2032 ( = 2 11 -16) different messages in the standard format and 512 million ( = 2 29 -16) different messages in the extended frame format. every can frame is broadcasted on the common bus. each module receives every frame and filters out the frames which are not required for the module's task. for example, if a dash- board sends a request to switch on headlights, the can mod- ule responsible for brake lights must not process this message. a can master module has the ability to set a specific bit called the remote data request bit (rtr) in a frame. such a interface management cantx transceiver logic bit stream processor error management logic tx/rx control can core status register acceptance masks message buffer 0 btl, rx shift, tx shift, crc figure 44. block diagram cr16can interface tx/rx message buffer 1 message buffer 14 tx/rx acceptance filtering interface management processor ram data control status control can prescaler btl config core bus canrx 0 1 2:1 01 2:1 ctx crx wakeup data
87 www.national.com message is also called remote frame. it causes another module, either another master or a slave which accepts this remote frame, to transmit a data frame after the remote frame has been completed. additional modules can be added to an existing network with- out a configuration change. these modules can either per- form completely new functions requiring new data, or process existing data to perform a new functionality. as the can network is message oriented, a message can be used as a variable which is automatically updated by the con- trolling processor. if any module cannot process information, it can send an overload frame. the can protocol allows several transmitting modules to start a transmission at the same time as soon as they monitor the bus to be idle. during the start of transmission, every node monitors the bus line to detect whether its message is overwritten by a message with a higher priority. as soon as a transmitting module detects another module with a higher priority accessing the bus, it stops transmitting its own frame and switches to receive mode. for illustration, see figure 45. if a data or remote frame loses arbitration on the bus due to a higher-prioritized data or remote frame, or if it is destroyed by an error frame, the transmitting module will automatically retransmit it until the transmission was successful or the user has canceled the transmit request. if a transmitted message loses arbitration, the cr16can will restart transmission at the next possible time with the mes- sage which has the highest internal transmit priority. 20.2.1 can frame formats communication via the can bus is basically established by means of four different frame types: data frame remote frame error frame overload frame data and remote frames can be used in both standard and extended frame format. if no message is being transmitted, i.e., the bus is idle, the bus is kept at the recessive level. remote and data frames are non-return to zero (nrz) coded with bit-stuffing in every bit field, which holds computable in- formation for the interface, i.e., start of frame, arbitration field, control field, data field (if present) and crc field. error and overload frames are also nrz coded but without bit-stuffing. after five consecutive bits of the same value (including insert- ed stuff bits so that the stuffed bit stream will not have more than five consecutive bits of the same value), a stuff bit of the inverted value is inserted into the bit stream by the transmit- ter and deleted by the receiver. the following shows the stuffed and destuffed bit stream for consecutive ones and ze- ros. frame fields data and remote frames consist of the following different bit fields: start of frame arbitration field control field data field crc field ack field eof field module a txpin rxpin module b bus line recessive dominant module a suspends transmission rxpin txpin figure 45. can message arbitration original or destuffed bit stream 10000011111x a a. x = {0,1} 01111100000x stuffed bit stream 100000 1 1111 0 1x 011111 0 0000 1 0x
www.national.com 88 the start of frame indicates the beginning of data and re- mote frames. it consists of a single 'dominant' bit. a node is only allowed to start transmission when the bus is idle. all nodes have to synchronize to the leading edge (first edge af- ter the bus was idle) caused by sof of the node which starts transmission first. the arbitration field consists of the identifier field and the rtr (remote transmission request) bit. for extended frames there is also a srr (substitute remote request) and a ide (id extension) bit inserted between id18 and id17 of the identifier field. the value of the rtr bit is 'dominant' in a data frame and 'recessive' in a remote frame. the control field consists of six bits. for standard frames it starts with the id extension bit (ide) and a reserved bit (rb0). for extended frames the control field starts with two reserved bits (rb1, rb0). these bits are followed by the 4- bit data length code (dlc). the cr16can receiver accepts all possible combinations of the reserved bits (rb1, rb0). the transmitter must be con- figured to send only '0' bits. the dlc indicates the number of bytes in the data field. it consists of four bits. the data field can be of length zero. the admissible number of data bytes for a data frame ranges from 0 to 8. the data field consists of the data to be transferred within a data frame. it can contain 0 to 8 bytes. a remote frame has no data field. the crc field consists of the crc sequence followed by the crc delimiter. the crc sequence is derived by the transmit- ter from the modulo 2 division of the preceding bit fields, starting with the sof up to the end of the data field, excluding stuff-bits, by the generator polynomial: the remainder of this division is the crc sequence transmit- ted over the bus. on the receiver side, the module divides all bit fields up to the crc delimiter excluding stuff-bits, and checks if the result is zero. this will then be interpreted as a valid crc. after the crc sequence a single recessive bit is transmitted as the crc delimiter. the ack field is two bits long and contains the ack slot and the ack delimiter. the ack slot is filled with a recessive bit by the transmitter. this bit is overwritten with a dominant bit by every receiver that has received a correct crc sequence. the second bit of the ack field is a recessive bit called the acknowledge delimiter. the end of frame field closes a data and a remote frame. it consists of seven recessive bits. x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 d r r r r r r r r standard data frame (number of bits = 44 + 8n) start of frame id 10 id0 rtr ide rb0 dlc3 dlc0 data field crc field crc acknowledgement ack del end of identifier data 11 4 8 16 15 8 frame 8n ( 0 n 8) length code d start of frame id28 id18 srr identifier 11 ide 18 rtr rb1 r r r r r r r rb0 dlc3 dlc0 data field crc field crc crc del ack ack del end of data 4 8 15 8 frame 8n ( 0 n 8) length code 28 ... 18 identifier 17 ... 0 id17 id0 extended data frame (number of bits = 64 + 8n) crc del 10 ... 0 arbitration field control field control field arbitration field bit stuffing bit stuffing d dd d d d r r note: d = dominant r = recessive r r 16 r r figure 46. can data frame (standard and extended)
89 www.national.com a can data frame consists of the following fields as previous- ly described: start of frame (sof) arbitration field + extended arbitration control field data field cyclic redundancy check field (crc) acknowledgment field (ack) end of frame (eof) remote frame figure 47 shows the structure of a standard and extended re- mote frame. a remote frame is comprised of the following fields sections, which is the same as a data frame (see frame fields on page 87) except for the data field, which is not present. start of frame (sof) arbitration field + extended arbitration control field cyclic redundancy check field (crc) acknowledgment field (ack) end of frame (eof) note that the dlc must have the same value as the corre- sponding data frame to prevent contention on the bus. the rtr bit is recessive. error frame as shown in figure 48, the error frame consists of the error flag and the error delimiter bit fields. the error flag field is built up from the various error flags of the different nodes. there- fore, its length may vary from a minimum of six bits up to a maximum of twelve bits depending on when a module has detected the error. whenever a bit error, stuff error, form er- ror, or acknowledgment error is detected by a node, this node starts transmission of an error flag at the next bit. if a crc error is detected, transmission of the error flag starts at the bit following the acknowledge delimiter, unless an error flag for a previous error condition has already been started. if a device is in the error active state, it can send a dominant error flag, whereas a error passive device is only allowed to transmit recessive error flags. this is done to prevent the can bus from getting stuck due to a local defect. for the var- ious can device states, please refer to error detection and management on page 91. d r d r r r r r r r d standard remote frame (number of bits = 44) start of frame id 10 id0 rtr ide rb0 dlc3 dlc0 crc field crc acknowledgement ack del end of identifier data 11 4 16 15 frame length code id3 d start of frame id28 id18 srr identifier 11 ide 18 rtr rb1 r d r r r r r r r rb0 dlc3 dlc0 crc field crc crc del ack ack del end of data 4 16 15 frame length code 28 ... 18 identifier 17 ... 0 id17 id0 extended remote frame (number of bits = 64) crc del 10 ... 0 control field arbitration field control field arbitration field note: d = dominant r = recessive d r r r r r r figure 47. can remote frame (standard and extended)
www.national.com 90 overload frame as shown in figure 49, an overload frame consists of the overload flag and the overload delimiter bit fields. the bit fields have the same length as the error frame field: six bits for the overload flag and eight bits for the delimiter. the over- load frame can only be sent after the end of frame (eof) field and in this way destroys the fixed form of the intermission field. as a result, all other nodes also detect an overload con- dition and start the transmission of an overload flag. after an overload flag has been transmitted, the overload frame is closed by the overload delimiter. note: the cr16can never initiates an overload frame due to its inability to process an incoming message. however, it is able to recognize and respond to overload frames initiated by other devices. d d d d d d d d 6 8 6 r r r r d r r r d r error flag echo error flag error delimiter data frame or remote frame inter-frame space or overload frame an error frame can start anywhere within a frame. error frame note: d = dominant r = recessive figure 48. can error frame r r d r r r r d r r d d d d d 8 6 overload flag overload delimiter overload frame inter-frame space or error frame end of frame or error delimiter or overload delimiter an overload frame can only start at the end of a frame. note: d = dominant r = recessive figure 49. can overload frame
91 www.national.com interframe space data and remote frames are separated from every preceding frame (data, remote, error and overload frames) by the inter- frame space (see figure 50). error and overload frames are not preceded by an interframe space; they can be transmit- ted as soon as the condition occurs. the interframe space consists of a minimum of three bit fields depending on the er- ror state of the node. 20.2.2 error detection and management there are multiple mechanisms in the can protocol to detect errors and inhibit erroneous modules from disabling all bus activities. each can module includes two error counters, a receive and a transmit error counter, for error management. error types the following errors can be detected: bit error a can device which is currently transmitting also mon- itors the bus. if the monitored bit value is different from the transmitted bit value, a bit error is detected. how- ever, the reception of a dominant bit instead of a re- cessive bit during the transmission of a passive error flag, during the stuffed bit stream of the arbitration field or during the acknowledge slot is not interpreted as a bit error. stuff error a stuff error is detected if the bit level after 6 consecu- tive bit times has not changed in a message field that has to be coded according to the bit stuffing method. form error a form error is detected, if a fixed frame bit (e.g., crc delimiter, ack delimiter) does not have the specified value. for a receiver, a dominant bit during the last bit of end of frame does not constitute a frame error. bit crc error a crc error is detected if the remainder of the crc calculation of a received crc polynomial is non-zero. acknowledgment error an acknowledgment error is detected whenever a transmitting node does not get an acknowledgment from any other node (i.e., when the transmitter does not receive a dominant bit during the ack frame) error states the device can be in one of four states with respect to error handling (see figure 51) synchronize once the cr16can is enabled, it goes into a synchro- nization state to synchronize with the bus by waiting for 11 consecutive recessive bits. after that the cr16can becomes error active and can participate in the bus communication. this state must also be entered after waking-up the device via the multi-input wake-up fea- ture. see system start-up and multi-input wake-up on page 113. error active an error active unit can participate in bus communica- tion and may send an active (dominant) error flag. error warning the error warning state is a sub-state of error active to indicate a heavily disturbed bus. the cr16can be- haves as in error active mode. the device is reset into the error active mode if the value of both counters is less than 96. error passive an error passive unit can participate in bus communi- cation. however, if the unit detects an error it is not al- lowed to send an active error flag. the unit sends only a passive (recessive) error flag. a device is error pas- sive when the transmit error counter or the receive er- ror counter is greater than 127. a device becoming error passive will send an active error flag. an error passive device becomes error active again when both transmit and receive error counter are less than 128. bus off a unit that is bus off has the output drivers disabled, i.e., it does not participate in any bus activity. a device is bus off when the transmit error counter is greater than 255. a bus off device will become error active again after monitoring 128*11 recessive bits (includ- ing bus idle) on the bus. when the device goes from bus off to error active, both error counters will have the value 0. r r r r r r r r 3 8 r r r r r r r r d r int suspend transmit bus idle data frame or remote frame int = intermission interframe space r r r r r r start of frame any frame suspend transmission is only for error passive nodes. note: d = dominant r = recessive figure 50. can interframe space
www.national.com 92 error counters the cr16can module contains two error counters to per- form the error management. the receive error counter (rec) and the transmit error counter (tec) are 8-bits wide, located in the 16-bit wide canec register. the counters are modified by the cr16can according to the rules listed in table 20 er- ror counter handling. the error counters can be read by the users software as de- scribed under can error counter register (canec) on page 112. error (tec and rec) < 128 bus tec > 255 128 occurrences of figure 51. cr16can bus states 11 consecutive recessive bits active passive off (tec or rec) > 127 error error warning (tec or rec) > 95 (tec and rec) < 96 sync 11 consecutive recessive bits received external reset or enable cr16can table 20 error counter handling condition a action receive error counter conditions b a receiver detects a bit error during sending an active error flag. increment by 8 a receiver detects a dominant bit as the first bit after sending an error flag increment by 8 after detecting the 14th consecutive dominant bit following an active error flag or overload flag, or after detecting the 8th consecutive dominant bit following a passive error flag. after each sequence of additional 8 consecutive dominant bits. increment by 8 any other error condition (stuff, frame, crc, ack) increment by 1 a valid reception or transmission decrement by 1 unless counter is already 0 transmit error counter conditions a transmitter detects a bit error during sending an active error flag increment by 8 after detecting the 14th consecutive dominant bit following an active error flag or overload flag or after detecting the 8th consecutive dominant bit following a passive error flag. after each sequence of additional 8 consecutive dominant bits. increment by 8 any other error condition (stuff, frame, crc, ack) increment by 8 a valid reception or transmission decrement by 1 unless counter is already 0 a. this table provides an overview of the can error conditions and the behavior of the cr16can; for a detailed description of the error management and fault confinement rules, please refer to the can specification 2.0b b. if the msb (bit 7) of the rec is set, the node is error passive and the rec will not increment any further.
93 www.national.com special error handling for the tec counter is performed in the following situations: a stuff error occurs during arbitration, when a transmit- ted recessive stuff bit is received as a dominant bit. this does not lead to an increment of the tec. an ack-error occurs in an error passive device and no dominant bits are detected while sending the passive error flag. this does not lead to an increment of the tec. if only one device is on the bus and this device trans- mits a message, it will get no acknowledgment. this will be detected as an error and the message w ill be re- peated. when the device goes error passive and de- tects an acknowledge error, the tec counter is not incremented. therefore the device will not go from er- ror passive to the bus off state due to such a condi- tion. 20.2.3 bit time logic in the bit time logic (btl), the can bus speed and the syn- chronization jump width can be configured by the user. cr16can divides a nominal bit time into three time seg- ments: synchronization segment, time segment 1 (tseg1) and time segment 2 (tseg2). figure 52 shows the various elements of a can bit time. can bit time the number of time quanta in a can bit (can bit time) lies between 4 and 25. the sample point is positioned between tseg1 and tseg2 and the transmission point is positioned at the end of tseg2. the time segment 1 includes the propagation segment and the phase segment 1 as specified in the can specification 2.0.b. the length of the time segment 1 in time quantas (tq) is defined by the tseg1[3:0] bits. the time segment 2 represents the phase segment 2 as specified in the can specification 2.0.b. the length of the time segment 2 in time quantas (tq) is defined by the tseg2[3:0] bits. the synchronization jump width (sjw) defines the max- imum number of time quanta (tq) by which a received can bit can be shortened or lengthened in order to achieve re- synchronization on recessive to dominant data transitions on the bus. in the cr16can implementation the sjw has to be configured less or equal to tseg1 or tseg2, whatever is smaller. synchronization a can device expects the transition of the data signal to be within the synchronization segment of each can bit time. this segment has the fixed length of one time quantum. however, two can nodes never operate at exactly the same clock rate and furthermore the bus signal may deviate from the ideal waveform due to the physical conditions of the net- work (bus length and load). in order to compensate for the various delays within a network, the sample point can be po- sitioned by programming the length of time segments 1 and 2 (see figure 52). in addition to that, two types of synchronization are support- ed. the btl logic compares the incoming edge of a can bit with the internal bit timing. the internal bit timing can be adapted by either hard or soft synchronization (re-synchroni- zation). hard synchronization is done at the beginning of a new frame with the falling edge on the bus while the bus is idle. this is interpreted as the sof. it restarts the internal logic. soft synchronization is used during the reception of a bit stream to lengthen or shorten the internal bit time. depend- ing on the phase error (e), the time segment 1 may be in- creased or the time segment 2 may be decreased by a specific value, the re-synchronization jump width (sjw). the phase error is given by the deviation of the edge to the sync segment, measured in can clocks. the value of the phase error is defined as: e = 0, if the edge occurs within the sync segment. e > 0, if the edge occurs within tseg1 e < 0, if the edge occurs within tseg2 of the previous bit. re-synchronization is performed according to the following rules: one time quantum internal time quanta a time segment 1 (tseg1) time segment 2 (tseg2) 1 tq 2 to 16 tq 1 to 8 tq sample a = synchronization segment (sync) figure 52. bit timing 4 to 25 tq clock transmission point point
www.national.com 94 ? if the magnitude of e is less or equal to the programmed value of sjw, re-synchronization will have the same effect as hard synchronization. ? if e > sjw, the time segment 1 will be lengthened by the value of the sjw (see figure 53). ? if e < -sjw, the time segment 2 will be shortened by the value sjw (see figure 54). 20.2.4 clock generator the can prescaler (psc) is shown is figure 55. it divides the cki input clock by the value defined in the ctim register. the resulting clock is called time quanta clock and defines the length of one time quanta (tq). please refer to can timing register (ctim) on page 109 for a detailed description of the ctim register. note: psc is the value of the clock prescaler. tseg1 and tseg2 are the length of time segment 1 and 2 in tq. the resulting bus clock can be calculated by the equation: the values of psc and tseg 1 and 2 are specified by the contents of the registers psc, tseg1 and tseg2 as fol- lows: psc = psc[5:0] + 2 tseg1 = tseg1[3:0] + 1 tseg2 = tseg2 [2 : 0] + 1 bus signal can previous a tseg1 tseg2 next bit clock bit previous a tseg1 tseg2 next bit bit sjw normal bit time bit time lengthened by sjw e figure 53. re-synchronization (e > sjw) bus signal can previous a tseg1 tseg2 clock bit nominal bit time previous a tseg1 tseg2 next bit bit bit time shortened by sjw figure 54. re-synchronization (e < -sjw) e busclock cki psc () x 1 tseg 1 tseg 2 ++ () ------------------------------------------------------------------------------------ - = figure 55. bit rate generation psc : - internal time bit rate cki (1+tseg1+tseg2) : - quanta clock (1/tq)
95 www.national.com 20.3 message transfer the cr16can has access to 15 independent message buff- ers, memory mapped in ram. each message buffer consists of 8 different 16-bit ram locations and can be individually configured as a receive message buffer or as a transmit mes- sage buffer. a dedicated acceptance filtering procedure enables the user to configure each buffer to receive only a single message id or a group of messages. one buffer uses an independent fil- tering procedure, which provides the possibility to establish a basic-can path. for reception of data frame or remote frames, the cr16can follows a receive on first match rule which means that a giv- en message is only received by one buffer the first one which matches to the received message id. the transmission of a frame can be initiated by the user soft- ware writing to the transmit status and priority register. an al- ternate way to schedule a transmission is the automatic answer to remote frames. in the latter case, the cr16can will sc hedule every buffer for transmission to respond to re- mote frames with a given identifier if the acceptance mask matches. this implies that a single remote frame is able to poll multiple matching buffers configured to respond to the triggering remote transmission request. 20.4 acceptance filtering two 32-bit masks are used to filter unwanted messages from the can bus gmask and bmask. figure 56 shows the mask and the buffers controlled by the masks. the acceptance filtering of the incoming messages for the buffers 0...13 is done by means of a global filtering mask (gmask) and by the buffer id of each buffer. the acceptance filtering of incoming messages for buffer 14 is done via a separate filtering mask (bmask) and by the buffer id of each that buffer. once a received object is waiting in the hidden buffer (see receive buffer structure on page 97) to be copied into a buff- er, cr16can scans all buffer configured as receive buffers for a matching filtering mask. the buffers 0 to 13 are checked in ascending order beginning with buffer 0. the contents of the hidden buffer are copied into the first buffer with matching filtering mask. bits holding a 1 in the global filtering mask (gmask) can be represented as a dont care of the associated bit of each buffer identifier, regardless of whether the buffer identifier bit is 1 or 0. this provides the capability to accept only a single id per buffer or to accept a group of ids. the following two examples illustrate the difference. example 1: acceptance of a single identifier if the global mask is set to 00 16 the acceptance filtering of an incoming message is only determined by the individual buffer id. this means that only one message id is accepted per buffer. example 2: reception of an identifier group bits in the global mask register set to 1 change the corre- sponding bit status within the buffer id to dont care (x). therefore all messages which match the non-dont care bits are accepted. buffer 0 buffer13 buffer14 gmask1 gmask2 bmask1 bmask2 buffer_id buffer_id buffer_id figure 56. acceptance filtering structure gmask1 gmask2 buffer_id1 buffer_id2 00000000 00000000 00000000 00000 10101010 10101010 10101010 10101 10101010 10101010 10101010 10101 accepted id figure 57. acceptance of a single identifier gmask1 gmask2 buffer_id1 buffer_id2 00000000 00000000 00000 10101010 10101010 10101010 10101010 xxxxxxxx 10101010 accepted id group 10101 10101 figure 58. acceptance of a group of identifiers 11111111
www.national.com 96 a separate filtering path is used for buffer 14. for this buffer the acceptance filtering is established by the buffer id in con- junction with the basic filtering mask. this basic mask uses the same method as the global mask. setting a bit to 1 changes the associated bit in the buffer id to a dont care bit. therefore the basic mask allows a large number of infrequent messages to be received by this buffer. note: if the bmask register is equal to the gmask register, the buffer 14 can be used the same way as the buffers 0 to 13. the buffers 0 to 13 are scanned prior to buffer 14. subse- quently, the buffer 14 will not be checked for a matching id when one of the buffers 0 to 13 has already received an ob- ject. by setting the bufflock bit in the configuration register, the receiving buffer is automatically locked after a reception of one valid frame. the buffer will be unlocked again after the cpu has read the data and has written rx_ready in the buffer status field. with this lock function, the user has the ca- pability to save several messages with the same identifier or same identifier group into more than one buffer. for example, a buffer with the second highest priority will receive a mes- sage if the buffer with the highest priority has already re- ceived a message and is now locked (provided that both buffers use the same acceptance filtering mask). as shown in figure 59, several messages with the same id are received while bufflock is enabled. the filtering mask of the buffers 0, 1, 13 and 14 is set to accept this message. the first incoming frame will be received by buffer 0. as buffer 0 is now locked the next frame will be received by buffer 1, and so on. if all matching receive buffers are full and locked, a further incoming message will not be received by any buff- er. 20.5 receive structure all received frames will initially be buffered in a hidden re- ceive buffer until the frame is valid. (the validation point for a received message is the penultimate bit of eof.) the re- ceived identifier is then compared to every buffer id together with the respective mask and the status. as soon as the val- idation point is reached, the whole contents of the hidden buffer is copied into the matching message buffer as shown in figure 60. note: the hidden receive buffer must not be accessed by the cpu. the following section gives an overview of the reception of the different types of frames. gmask 00000 11111111 00000000 00000000 01010 xxxxxxxx 10101010 10101010 01010 10101010 10101010 10101010 buffer0_id buffer1_id buffer14_id buffer13_id bmask 00000 11111111 00000000 00000000 saved when buffer is empty saved when buffer is empty saved when buffer is empty 01010 01010 01010 10101010 10101010 10101010 10101010 10101010 10101010 xxxxxxxx xxxxxxxx xxxxxxxx saved when buffer is empty received id figure 59. message storage with bufflock enabled
97 www.national.com the received data frame will be stored in the first matching receive buffer beginning with buffer 0. for example, if the message is accepted by buffer 5, then at the time the mes- sage will be copied, the rx request is cleared and cr16can will not try to match the frame to any subseq uent buffer. all contents of the hidden receive buffer are always copied into the respective receive buffer. this includes the received message id as well as the received data length code (dlc); therefore when some mask bits are set to dont care, the id field will get the received message id which could be different from the previous id. the dlc of the receiving buffer will be updated by the dlc of the received frame. note that the dlc of the received message is not compared with the dlc already present in the cnstat register of the message buffer. this implies that the dlc code of the cnstat register indicates how may data bytes actually belong to the latest re- ceived message. the remote frames are handled by the cr16can interface in two different ways. firstly, remote frames can be received like data frames by configuring the buffer to be rx_ready and setting the id bits including the rtr bit. in that case the same procedure applies as described for data frames. sec- ondly, a remote frame can trigger one or more message buff- er to transmit a data frame upon reception. this procedure is described under to answer remote frames on page 99. 20.5.1 receive timing as soon as cr16can receives a dominant bit on the can bus, the receive process is started. the received id and data will be stored in the hidden receive buffer if the global or basic acceptance filtering matches. after the reception of the data, cr16can tries to match the buffer id of buffer 0...14. the data will be copied into the buffer after the reception of the 6th eof bit as a message is valid at this time. the copy process of every frame, regardless of the length, takes at least 17 cki cycles (see also cpu access to cr16can registers/mem- ory on page 103). figure 61 illustrates the receive timing. in order to indicate that a frame is waiting in the hidden buffer, the busy bit st[0] of the selected buffer is set during the copy procedure. the busy bit will be cleared by cr16can right after the data bytes are copied into the buffer. after the copy process is finished, cr16can changes the status field to rx_full. in turn the cpu should change the status field to rx_ready when the data is processed. when a new ob- ject has been received by the same buffer, before the cpu changed the status to rx_ready, the cr16can will change the status to rx_overrun to indicate that at least one frame has been overwritten by a new one. table 21 summa- rizes the current status and the resulting update from the cr16can. buffer 0 buffer 13 buffer 14 buffer_id buffer_id buffer_id hidden buffer cr16can figure 60. receive buffer structure receive sof arbitration field data field (if present) crc ack field eof 1 bit 12/29 bit + 6 bit n * 8 bit 16 bit 2 bit 7 bit field ifs 3 bit + control bus idle copy to buffer rx_start figure 61. receive timing busy table 21 writing to buffer status code during rx_busy current status resulting status rx_ready rx_full rx_not_active rx_not_active rx_full rx_overrun
www.national.com 98 during the assertion of the busy bit, all writes to the receiv- ing buffer are disabled with the exception of the status field. if the status is changed during busy being active, the status is updated by the cr16can as shown in table 21. the buffer states are indicated and controlled by the st[3:0] bits in the cnstat register (see buffer status/control regis- ter (cnstat) on page 104. the various receive buffer states are explained in rx buffer states on page 99. 20.5.2 receive procedure the user has to execute the following procedure to initialize a message buffer for the reception of a can message. 1. configure the receive masks (gmask or bmask, re- spectively). 2. configure the buffer id. 3. configure the message buffer status as rx_ready. in order to read the out of a received message, the cpu has to execute the following steps (see figure 62): the first step is only applicable if polling is used to get the sta- tus of the receive buffer. it can be deleted for an interrupt driv- en receive routine. 1. read the status (cnstat) of the receive buffer. if the status is rx_ready, no was the message received, ex- it. if the status is rx_busy, copy process from hidden receive buffer is not completed yet, read cnstat again. if a buffer is configured to rx_ready and its interrupt is enabled, it will generate an interrupt as soon as the buff- er has received a message and entered the rx_full state (see also interrupts on page 101). in that case the procedure described below should be followed. 2. read the status to determine if a new message has overwritten the one originally received which triggered the interrupt. 3. write rx_ready into cnstat. 4. read the id/data and object control (dlc/rtr) from the message buffer. 5. read the buffer status again and check it is not rx_busyx. if it is, repeat this step until rx_busyx has gone away. 6. if the buffer status is rx_full or rx_overrun, one or more messages were copied. in that case, start over with step 2. 7. if status is still rx_ready (as set by the cpu at step 2), clear interrupt pending bit and exit. read buffer read cnstat rx_ready? rx_overrun? rx_full? or y n read buffer (id/data/cntrl) write rx_ready exit y n y n figure 62. buffer read routine (bufflock disabled) read cnstat interrupt entry point clear rx_pnd a new message has receive buffer (optional, for information) rx_busyx? been received while reading data from the rx_overrun? rx_busyx? n y
99 www.national.com when the bufflock function is enabled (see bufflock on page 96), it is not necessary to check for new messages received during the read process from the buffer, as this buff- er is locked after the reception of the first valid frame. a read from a locked receive buffer can be performed as shown in figure 63. for simplicity only the applicable interrupt routine is shown: 1. read the id/data and object control (dlc/rtr) from the message buffer. 2. write rx_ready into cnstat. 3. clear interrupt pending bit and exit. 20.5.3 rx buffer states as shown in figure 64, a receive procedure starts as soon as the user has set the buffer from the rx_not_active state into the rx_ready state. the status section of cnstat reg- ister is set from 0000 2 to 0010 2 . when a message is re- ceived, the buffer will be rx_busyx during the copy process from the hidden receive buffer into the message buff- er. afterwards this buffer is rx_full. now the cpu can read the buffer data and either reset the buffer status to rx_ready or receive a new frame before the cpu reads the buffer. in the second case, the buffer state will automati- cally change to rx_overrun to indicate that at least one message was lost. during the copy process the buffer will again be rx_busyx for a short time, but in this case the cn- stat status section will be 0101 2 , as the buffer was rx_full (0100 2 ) before. after finally reading the last re- ceived message, the cpu can reset the buffer to rx_ready. 20.6 transmit structure in order to transmit a can message, the user has to config- ure the message buffer by changing the buffer status to tx_not_active. the buffer is configured for transmission if the st[3] bit of the buffer status code (cnstat) is set to 1. in tx_not_active status, the buffer is ready to receive data from the cpu. after receiving all transmission data (id, data bytes, dlc and pri), the cpu can start the transmis- sion by writing tx_once into the buffer status register. dur- ing the transmission the status of the buffer is tx_busyx. after successful transmission cr16can will reset the buffer status to tx_not_active. when the transmission process fails, the buffer condition will remain tx_busyx for re-trans- mission until the frame was successfully transmitted or the cpu has canceled the transmission request. in order to send a remote frame (remote transmission request) to other can nodes, the user needs to set the rtr bit of the message identifier to 1 (see storage of remote messages on page 107) and change the status of the mes- sage buffer to tx_once. after this remote frame has been transmitted successfully, this message buffer will automati- cally enter the rx_ready state and is ready to receive the appropriate answer. note that the mask bits rtr/xrtr need to be set to receive a data frame (rtr = 0) in a buffer which was configured to transmit a remote frame (rtr = 1). to answer remote frames if the cpu writes tx_rtr in the buffer status register, the buffer will wait for a remote frame. when a remote frame passes the acceptance filtering mask of one or more buffers, the buffer status w ill change to tx_once_rtr, the contents of the buffer will be transmit- ted and afterwards cr16can will write tx_rtr in the status code register again. if the cpu writes tx_once_rtr in the buffer status, the contents of the buffer will be transmitted, and the successful transmission the buffer goes into the wait for remote frame condition tx_rtr. 20.6.1 transmit scheduling after writing tx_once in the buffer status, the transmission process begins and the busy-bit is set. as soon as a buffer gets the tx_busy status, the buffer is not accessible any- more by the cpu except for the st[3:1] bits of the cnstat register. starting with the beginning of the crc field of the current frame, cr16can looks for another buffer transmit re- quest and selects the buffer with the highest priority for the next transmission by changing the buffer state from tx_once to tx_busy. this transmit request can be can- celed by the cpu or can be overwritten by another transmit request of a buffer with a higher priority as long as the trans- mission of the next frame has not yet started. this means that between the beginning of the crc field of the current frame and the transmission start of the next frame, two buff- ers, the current buffer and the buffer scheduled for the next transmission, are in the busy status. in order to cancel the transmit request of the next frame, the cpu has to change the buffer state to tx_not_active. when the transmit re- quest has been overwritten by another request of a higher priority buffer, cr16can changes the buffer state from tx_busy to tx_once. thus, the transmit request remains pending. figure 64 further illustrates the transmit timing. if the transmit process fails or the arbitration is lost, the trans- mission process will be stopped and will continue after the in- terrupting reception or the error signaling has finished (see figure 65). in that case a new buffer select follows and the tx process is executed again. note: the canceled message can be delayed by a tx re- quest of a buffer with a higher priority. during tx_busy high, the user cannot change the contents of the message buffer object. in all cases writing to the busy bit will be ignored. read buffer (id/data/cntrl) write rx_ready exit figure 63. buffer read routine (bufflock enabled) interrupt entry point clear rx_pnd
www.national.com 100 20.6.2 transmit priority cr16can is able to generate a stream of scheduled mes- sages without releasing the bus between two messages so that an optimized performance can be achieved. it will arbi- trate for the bus right after sending the previous message and will only release the bus due to a lost arbitration. if more than one buffer is scheduled for transmission, the pri- ority is built by the message buffer number and the priority code in the cnstat register. the 8-bit value of the priority is combined by the 4-bit txpri value and the 4-bit buffer num- ber (0...14) as shown below. the lowest resulting number re- sults in the highest transmit priority. table 22 shows the transmit priority configuration if the prior- ity is set to txpri = 0 for all transmit buffers: table 23 shows the transmit priority configuration if txpri is different from the buffer number: note: if two buffers have the same priority (pri), the buffer with the lower buffer number will have the hi gher priority. tx_busy begin selection of next buffer if new tx_request current buffer tx_busy next buffer sof arbitration field data field (if present) crc ack field eof 1 bit 12/29 bit + 6 bit n * 8 bit 16 bit 2 bit 7 bit field ifs 3 bit figure 64. data transmission + control bus idle cpu write tx_once in buffer status table 22 transmit priority (txpri=0) txpri buffer number pri tx priority 000highest 011 : : : : : : : : 01414lowest txpri buffer # table 23 transmit priority (txpri not 0) txpri buffer number pri tx priority 14 0 224 lowest 13 1 209 12 2 194 11 3 179 10 4 164 9 5 149 8 6 134 7 7 119 6 8 104 5989 41074 31159 21244 11329 0 14 14 highest
101 www.national.com 20.6.3 transmit procedure the transmission of a can message has to be executed as follows (see also figure 65) 1. configure cnstat status field as tx_not_active. if the status is tx_busy, a previous transmit request is still pending and the user has no access to the data con- tents of the buffer. in that case the user may choose to wait until the buffer becomes available again as shown. other options are to exit from the update routine until the buffer has been transmitted with an interrupt generated, or the transmission is aborted by an error. 2. load buffer identifier & data registers. (for remote frames the rtr bit of the identifier needs to be set and loading data bytes can be omitted.) 3. configure cnstat status field to the desired value: tx_once to trigger the transmission process of a sin- gle frame. tx_once_rtr to trigger the transmission of a single data frame and then wait for a received remote frame to trigger consecutive data frames. tx_rtr waits for a remote frame to trigger the trans- mission of a data frame. writing tx_once or tx_once_rtr in the cnstat status field will set the internal transmit request for the cr16can. if a buffer is configured as tx_rtr and a remote frame is re- ceived, the data contents of the addressed buffer will be transmitted automatically without further cpu activity. 20.6.4 tx buffer states the transmission process can be started after the user has loaded the buffer registers (data, id, dlc, pri) and set the buffer status from tx_not_active to tx_once, tx_rtr or tx_once_rtr. when the cpu writes tx_once, the buffer will be tx_busy as soon as cr16can has scheduled this buffer for the next transmission. after the frame could be success- fully transmitted, the buffer status will be automatically reset to tx_not_active when a data frame was transmitted or to rx_ready when a remote frame was transmitted. if the cpu configures the message buffer to tx_once_rtr, it will transmit its data contents. during the transmission the buffer state is 1111 2 as the cpu wrote 1110 2 into the status section of the cnstat register. after the successful transmission the buffer enters the tx_rtr state and waits for a remote frame. when it receives a remote frame, it will go back into the tx_once_rtr state, transmit its data bytes and return to tx_rtr. if the cpu writes 1010 2 into the buffer status section, it will only enter the tx_rtr state. but it will not send its data bytes before it waits for a re- mote frame. figure 66 illustrates the possible transmit buffer states. 20.7 interrupts cr16can has access to one interrupt vector in the cr16 cpu. the interrupt process can be initiated from the following sources. ? can data transfer reception of a valid data frame in the buffer. (buffer state changes from rx_ready to rx_full or rx_overrun). successful transmission of a data frame. (buffer state changes from tx_once to tx_not_active or rx_ready) successful response to a remote frame. (buffer state changes from tx_once_rtr to tx_rtr). transmit scheduling. (buffer state changes from tx_rtr to tx_once_rtr). ? can error conditions is the detection of an can error. (the ceipnd bit in the cipnd register will be set as well as the corresponding bits in the error diagnostic register cediag). the receive/transmit interrupt access to every message buff- er can be individually enabled/disabled in the cien register. the pending flags of the message buffer are located in the cipnd register (read only) and can be cleared by resetting the flags in the ciclr registers. 20.7.1 highest priority interrupt code in order to reduce decoding time of the cipnd register, the buffer interrupt request with the highest priority is placed as interrupt status code into the ist[3:0] section of the cstpnd register. write_buffer tx_busyx? y n write write id/data write exit figure 65. buffer write routine tx_once or tx_once_rtr or tx_rtr tx_not_active (see text)
www.national.com 102 each of the buffer interrupts as well as the error interrupt can be individually enabled or disabled in the can interrupt en- able register (cien). as soon as an interrupt condition oc- curs, every interrupt request is indicated by a flag in the can interrupt pending register (cipnd). when the interrupt code logic for the present highest priority interrupt request is en- abled, this interrupt will be translated into the ist[3:0] bits of the can status pending register (cstpnd). an interrupt re- quest can be cleared by setting the corresponding bit in the can interrupt clear register (ciclr) to 1. figure 67 illustrates the cr16can interrupt management. figure 66. transmit buffer states tx_once tx_not_active rx_ready tx done request cancelled remote transmission tx_rtr rtr cpu writes 1010 transmit failed can tx_busy0 tx_once_rtr tx_busy2 tx done can schedules tx transmit transmit request cancelled transmit failed received cpu writes 1100 tx request tx request cpu writes 1110 cpu writes 1000 cpu writes 1000 schedules tx 1110 1111 1010 1000 1100 0010 1101 *1 *1: tx request delayed by a tx request of higher priority message request sent - now wait to receive a data frame figure 67. cr16can interrupt management cipnd ist0 ist1 ist2 ist3 icode clear interrupt flags of every irq ciclr cien cicen message buffer individually
103 www.national.com the highest priority interrupt source is translated into the bits irq and ist[3:0] as shown in table 24. 20.7.2 usage hints the interrupt code ist[3:0] can be used within the interrupt handler as a displacement in order to jump to the relevant subroutine. the can interrupt code enable (cicen) register is used in the can interrupt handler if the user wants to service all re- ceive buffer interrupts first followed by all transmit buffer inter- rupts. in this case, the user can first enable only all receive buffer interrupts to be coded, scan and service all pending in- terrupt requests in the order of their priority. then, the user changes the cicen register to disable all receive buffers, but enable all transmit buffers and service all pending transmit buffer interrupt requests according to their priorities. 20.8 time stamp counter cr16can features a free running 16-bit timer (ctmr) incre- menting every bit time recognized on the can bus. the value of this timer during the ack slot is captured into the tstp register of a message buffer after a successful transmission or reception of a message. figure 68 shows a simplified block diagram of the time stamp counter. the timer can be synchronized over the can network by re- ceiving or transmitting a message to/from buffer 0. in that case the tstp register of buffer 0 captures the current ctmr value during the ack slot of a message (as above) and afterwards the ctmr is reset to 0000 2 . synchronization can be enabled or disabled via the cgcr.tstpen bit. 20.9 memory organization cr16can occupies 144 words in the memory address space. this space is separated into 15*8 + 8(reserved) words for the message buffers and 14 + 2(reserved) words for control and status. 20.9.1 cpu access to cr16can registers/memory all memory locations occupied by the message buffers are shared by the cpu and cr16can (dual ported ram). the cr16can and the cpu normally have single cycle access to this memory. however, if an access contention occurs, the access to the memory is altered every cycle until the conten- tion is resolved. this internal access arbitration is transpar- ent to the user. both word and byte access to the buffer ram are allowed. if a buffer is busy during the reception of an object (copy pro- cess from the hidden receive buffer) or is scheduled for trans- mission, the cpu has no write access to the data contents of the buffer. write to the status/control byte and read access to the whole buffer is always enabled. all configuration and status registers can either be accessed by cr16can or the cpu only. these registers provide single cycle word and byte access without any potential wait state. all register descriptions within the next sections utilize the fol- lowing layout: table 24 highest priority interrupt code (icen=ffff) can interrupt request irq ist3 ist2 ist1 ist0 no request00000 error interrupt10000 buffer 0 10001 buffer 1 10010 buffer 2 10011 buffer 3 10100 buffer 4 10101 buffer 5 10110 buffer 6 10111 buffer 7 11000 buffer 8 11001 buffer 9 11010 buffer 10 11011 buffer 11 11100 buffer 12 11101 buffer 13 11110 buffer 14 11111 bit 15 ... bit number ... bit 0 ... bit name ... ... reset value ... ... cpu access ... r = register bit is read only w = register bit is write only r/w = register bit is read/write 16-bit counter tstp register can bits on the bus ack slot & buffer 0 active ack slot +1 reset figure 68. time stamp counter
www.national.com 104 20.9.2 message buffer organization the message buffers are the communication interfaces be- tween can and the cpu for the transmission and the recep- tion of can frames. there are 15 message buffers located at fixed addresses in the ram location. as shown in table 25, each buffer consists of two words reserved for the identifiers, 4 words reserved for up to eight can data bytes, one word is reserved for time stamp and one word for data length code, transmit priority code and the buffer status code. 20.9.3 buffer status/control register (cnstat) the buffer status, the buffer priority and the data length code are controlled by manipulating the contents of the buffer sta- tus/control register (cnstat). cpu and cr16can have access to this register. st[3:0] buffer status the cnstat register has a status section, which contains the status infor- mation of the buffer as shown in table 26. this section can be modified by cr16can. the st0 bits acts as a buffer busy indication. when the busy bit is set, any write access to the buffer is disabled with the exception of the lower byte of the cntstat register. the cr16can sets this bit if the buffer data is cur- rently copied from the hidden buffer or if a mes- sage is scheduled for transmission or is currently transmitting. the cr16can will al- ways reset this bit on a status update. pri[3:0] transmit priority code. the pri[3:0] bits con- tain the user defined transmit priority code for the message buffer. dlc[3:0] data length code. the dlc[3:0] bits deter- mine the number of data bytes within a re- ceived/transmitted frame. for transmission, these bits need to be set according to the num- ber of data bytes to be transmitted. for recep- tion, these bits indicate the number of valid received data bytes available in the message buffer. table 27 shows the possible bit combi- nations for dlc[3:0] for data lengths from 0 to 8 bytes. table 25 message buffer organization addr buffer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxe 16 id1 xi28 id10 xi27 id9 xi26 id8 xi25 id7 xi24 id6 xi23 id5 xi22 id4 xi21 id3 xi20 id2 xi19 id1 xi18 id0 srr rtr ide xi17 xi16 xi15 xxxc 16 id0 xi14 xi13 xi12 xi11 xi10 xi9 xi8 xi7 xi6 xi5 xi4 xi3 xi2 xi1 xi0 rtr xxxa 16 data0 data 1.7 data 1.6 data 1.5 data 1.4 data 1.3 data 1.2 data 1.1 data 1.0 data 2.7 data 2.6 data 2.5 data 2.4 data 2.3 data 2.2 data 2.1 data 2.0 xxx8 16 data1 data 3.7 data 3.6 data 3.5 data 3.4 data 3.3 data 3.2 data 3.1 data 3.0 data 4.7 data 4.6 data 4.5 data 4.4 data 4.3 data 4.2 data 4.1 data 4.0 xxx6 16 data2 data 5.7 data 5.6 data 5.5 data 5.4 data 5.3 data 5.2 data 5.1 data 5.0 data 6.7 data 6.6 data 6.5 data 6.4 data 6.3 data 6.2 data 6.1 data 6.0 xxx4 16 data3 data 7.7 data 7.6 data 7.5 data 7.4 data 7.3 data 7.2 data 7.1 data 7.0 data 8.7 data 8.6 data 8.5 data 8.4 data 8.3 data 8.2 data 8.1 data 8.0 xxx2 16 tstp tstp15 tstp14 tstp13 tstp12 tstp11 tstp10 tstp 9 tstp 8 tstp 7 tstp 6 tstp 5 tstp 4 tstp 3 tstp 2 tstp 1 tstp 0 xxx0 16 cntstat dlc3 dlc2 dlc1 dlc0 reserved pri3 pri2 pri1 pri0 st3 st2 st1 st0 15 12 11 8 7 4 3 0 dlc[3:0] reserved pri[3:0] st[3:0] 0 r/w table 26 buffer status section of the cnstat register st3 (dir) st2 st1 st0 (busy) buffer status 0 0 0 0 rx_not_active 0 0 0 1 reserved for rx_busy a 0 0 1 0 rx_ready 0 0 1 1 rx_busy0 b 0 1 0 0 rx_full 0 1 0 1 rx_busy1 b 0 1 1 0 rx_overrun 0 1 1 1 rx_busy2 b 1 0 0 0 tx_not_active 1 0 0 1 reserved for tx_busy c 1 1 0 0 tx_once
105 www.national.com note: the maximum number of data bytes received/trans- mitted is 8, even if the data length code is set to a value great- er than 8. thus, if the data length code is greater or equal to eight bytes, the bits dlc2 to dlc0 are ignored. 20.9.4 storage of standard messages during the processing of standard frames, the extended- identifier-bit (ide) is set to 0. the bits id1[3:0], id0[15:0] are dont care bits. a standard frame with eight data bytes is shown in table 28. ide identifier extension. ide is set to 0 to indicate that the message is a standard frame using 11 identifier bits. if ide is set to 1, the object stored in the buffer is handled as an extended frame. rtr remote transmission request. rtr is set to 1 to indicate that the message is a remote frame. for a data frame, the rtr bit is set to 0. id[10:0]the id buffer bits id10 to id0 are used for the 11 standard frame identifier bits. 1 1 0 1 tx_busy0 d 101 0 tx_rtr (automatic response to a remote frame) 1 0 1 1 reserved for tx_busy1 e 111 0 tx_once_rtr (changes to tx_rtr after transmission) 1 1 1 1 tx_busy2 d a. this condition indicates that the user wrote rx_not_active to a buffer when the data copy process is still active. b. rx_busyx indicates that coping is in progress at three possible times - data is copied for the first time rx_ready ? rx_busy0 - data is copied for the second time rx_full ? rx_busy1 - data is copied for the third or more time rx_overrun ? rx_busy2 c. this state indicates that the user wrote tx_not_active to a transmit buffer which is scheduled for transmission or is currently transmitting. d. tx_busyx indicates that a buffers is scheduled for transmission or is actively transmitting; it can be due to one of two cases: - a message is pending for transmission or is currently transmitting - an automated answer is pending for transmission or is currently transmitting e. this condition does not occur table 26 buffer status section of the cnstat register st3 (dir) st2 st1 st0 (busy) buffer status table 27 data length coding number of data bytes dlc3 dlc2 dlc1 dlc0 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 table 28 standard frame with 8 data bytes addr buffer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxe 16 id1 id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 rtr ide dont care xxxc 16 id0 dont care xxxa 16 data0 data 1.7 data 1.6 data 1.5 data 1.4 data 1.3 data 1.2 data 1.1 data 1.0 data 2.7 data 2.6 data 2.5 data 2.4 data 2.3 data 2.2 data 2.1 data 2.0 xxx8 16 data1 data 3.7 data 3.6 data 3.5 data 3.4 data 3.3 data 3.2 data 3.1 data 3.0 data 4.7 data 4.6 data 4.5 data 4.4 data 4.3 data 4.2 data 4.1 data 4.0 xxx6 16 data2 data 5.7 data 5.6 data 5.5 data 5.4 data 5.3 data 5.2 data 5.1 data 5.0 data 6.7 data 6.6 data 6.5 data 6.4 data 6.3 data 6.2 data 6.1 data 6.0
www.national.com 106 20.9.5 storage of messages with less than 8 data bytes the data bytes that are not used for data transfer are dont cares. if the object is transmitted, the data within these bytes will be i gnored. if the object is received, the data within these bytes will be overwritten with invalid data. 20.9.6 storage of extended messages if the ide bit is set to 1, the buffer handles extended frames. the storage of the extended id follows the descriptions in table 29. the srr bit is at the bit position of the rtr bit for standard frame and needs to be transmitted as 1. srr substitute remote request. srr replaces the rtr bit used in standard frames at this bit po- sition. the srr bit needs to be set to 1 by the user if the buffer is configured to transmit a message with an extended identifier. it will be received as monitored on the can bus. ide identifier extension. ide is set to 0 to indicate that the message is a standard frame using 11 identifier bits. if ide is set to 1, the object stored in the buffer is handled as an extended frame. rtr remote transmission request. rtr is set to 1 to indicate that the message is a remote frame. for a data frame, the rtr bit is set to 0. id[28:0] the id bits 28 to 0 are used to build the 29-bit identifier of an extended frame. xxx4 16 data3 data 7.7 data 7.6 data 7.5 data 7.4 data 7.3 data 7.2 data 7.1 data 7.0 data 8.7 data 8.6 data 8.5 data 8.4 data 8.3 data 8.2 data 8.1 data 8.0 xxx2 16 tstp tstp 15 tstp 14 tstp 13 tstp 12 tstp 11 tstp 10 tstp 9 tstp 8 tstp 7 tstp 6 tstp 5 tstp 4 tstp 3 tstp 2 tstp 1 tstp 0 xxx0 16 cntstat dlc3 dlc2 dlc1 dlc0 reserved pri3 pri2 pri1 pri0 st3 st2 st1 st0 table 28 standard frame with 8 data bytes addr buffer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 29 extended messages with 8 data bytes addr buffer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxe 16 id1 id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 srr ide id17 id16 id15 xxxc 16 id0 id14 id13 id12 id11 id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 rtr xxxa 16 data0 data 1.7 data 1.6 data 1.5 data 1.4 data 1.3 data 1.2 data 1.1 data 1.0 data 2.7 data 2.6 data 2.5 data 2.4 data 2.3 data 2.2 data 2.1 data 2.0 xxx8 16 data1 data 3.7 data 3.6 data 3.5 data 3.4 data 3.3 data 3.2 data 3.1 data 3.0 data 4.7 data 4.6 data 4.5 data 4.4 data 4.3 data 4.2 data 4.1 data 4.0 xxx6 16 data2 data 5.7 data 5.6 data 5.5 data 5.4 data 5.3 data 5.2 data 5.1 data 5.0 data 6.7 data 6.6 data 6.5 data 6.4 data 6.3 data 6.2 data 6.1 data 6.0 xxx4 16 data3 data 7.7 data 7.6 data 7.5 data 7.4 data 7.3 data 7.2 data 7.1 data 7.0 data 8.7 data 8.6 data 8.5 data 8.4 data 8.3 data 8.2 data 8.1 data 8.0 xxx2 16 tstp tstp 15 tstp 14 tstp 13 tstp 12 tstp 11 tstp 10 tstp 9 tstp 8 tstp 7 tstp 6 tstp 5 tstp 4 tstp 3 tstp 2 tstp 1 tstp 0 xxx0 16 cntstat dlc3 dlc2 dlc1 dlc0 reserved pri3 pri2 pri1 pri0 st3 st2 st1 st0
107 www.national.com 20.9.7 storage of remote messages during remote frame transfer, the buffer registers data[3:0] are dont cares. if a remote frame is transmitted, the con- tents of these registers are ignored. if a remote frame is re- ceived, the contents of these registers will be overwritten with invalid data. the structure of a message buffer set up for a remote frame with extended identifier is shown in table 30. srr substitute remote request. srr replaces the rtr bit used in standard frames at this bit po- sition. the srr bit needs to be set to 1 by the user. ide identifier extension. ide is set to 0 to indicate that the message is a standard frame using 11 identifier bits. if ide is set to 1, the object stored in the buffer is handled as an extended frame. rtr remote transmission request. rtr is set to 1 to indicate that the message is a remote frame. for a data frame, the rtr bit is set to 0. id[28:0] the id bits 28 to 0 are used to build the 29-bit identifier of an extended frame. the id1 buffer bits id28 to id18 are used for the 11 standard frame identifier bits. 20.9.8 can global configuration register (cgcr) the can global configuration register (cgcr) is a 16-bit wide register used to: ? enable/disable the cr16can ? configure the bufflock function for the message buffer 0...14 ? enable/disable the time stamp synchronization ? set the logic levels of the can input/output pins canrx/cantx ? choose the data storage direction (ddir) ? select the error interrupt type (eit) ? enable/disable diagnostic functions canen can enable. this bit enables/disables the cr16can. when the cr16can is disabled, all internal states and the tec and rec counter registers are cleared. in addition the cr16can clock is disabled. all cr16can control registers and the contents of the object memory are left unchanged. the user needs to make sure that no message is pending for transmission before the cr16can is disabled. 0 cr16can is disabled 1 cr16can is enabled ctx control transmit. this bit configures the logic level of the can transmit pin cantx. 0 dominate state is 0; recessive state is 1 1 dominate state is 1; recessive state is 0 crx control receive. this bit configures the logic level of the can receive pin canrx. 0 dominate state is 0; recessive state is 1 1 dominate state is 1; recessive state is 0 table 30 extended remote frame addr buffer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxe 16 id1 id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 srr ide id17 id16 id15 xxxc 16 id0 id14 id13 id12 id11 id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 rtr xxxa 16 data0 dont care xxx8 16 data1 dont care xxx6 16 data2 dont care xxx4 16 data3 dont care xxx2 16 tstp tstp15 tstp14 tstp13 tstp12 tstp11 tstp10 tstp 9 tstp 8 tstp 7 tstp 6 tstp 5 tstp 4 tstp 3 tstp 2 tstp 1 tstp 0 xxx0 16 cntstat dlc3 dlc2 dlc1 dlc0 reserved pri3 pri2 pri1 pri0 st3 st2 st1 st0 15 12 11 10 9 8 reserved eit diagen internal loopback 0 r/w 7 6 5 4 3 2 1 0 ignack lo ddir tstpen bufflock crx ctx canen 0 r/w
www.national.com 108 buffloc buffer lock. with this bit the user can configure the buffer lock function. if this feature is en- abled, a buffer will be locked upon a successful frame reception. the buffer will be unlocked again by writing rx_ready in the buffer status register, i.e., after reading data. 0 lock function is disabled for all buffers 1 lock function is enabled for all buffers tstpen time sync enable. the time sync bit enables or disables the time stamp synchronization function of the cr16can. 0 time synchronization disabled. the time stamp counter value is not reset upon re- ception or transmission of a message to/ from buffer 0. 1 time synchronization enabled. the time stamp counter value is reset upon recep- tion or transmission of a message to/from buffer 0. ddir data direction. by setting or resetting the ddir bit, the user can select the direction the data bytes are transmitted and received. the cr16can transmits and receives the can data byte data1 first and the data byte data8 last (data1, data2,...,data7, data8). if ddir is set to 0 the data contents of a re- ceived message is stored with the first byte at the highest data address and the last data at the lowest data address (see figure 69). the same applies for transmitted data. setting the ddir bit to 1 will cause the direction of the data storage to be reversed the last byte received is stored at the highest address and the first byte is stored at the lowest address. see figure 70 for illustration. lo listen only by setting the lo-bit to 1 the cr16can interface is configured to behave only as a receiver. this means: ? it cannot transmit any message. ? it cannot send a dominant ack bit. ? when errors are detected on the bus, the cr16can will behave as in the error pas- sive mode. using this listen only function, the cr16can interface can be adjusted when it gets connect- ed to an operating network with unknown bus speed. ignack ignore acknowledge. if the ignore ack function is enabled, then by setting the ignack bit to 1, cr16can does not expect to receive a dominant ack bit to indicate the validity of a 0a 16 08 16 06 16 04 16 data bytes data8 data7 data6 data5 data4 data3 data2 data1 addr offset data1 data3 data2 data4 data5 data6 data7 data8 t sequence of data bytes on the bus storage of data bytes in the buffer memory id crc figure 69. data direction bit set to 0 t addroffset data bytes data1 data2 data3 data4 data5 data6 data7 data8 sequence of data bytes on the bus storage of data bytes in the buffer memory data1 data3 data2 data4 data5 data6 data7 data8 id crc figure 70. data direction bit set to 1 0a 16 08 16 06 16 04 16
109 www.national.com transmitted message. it will not send an error frame when the transmitted frame in not ac- knowledged by any other can node. this feature can be used in conjunction with the loopback option for stand-alone tests outside of a can network. loopback loopback. by setting the loopback bit, all messages sent by cr16can can also be re- ceived by a cr16can buffer with a matching buffer id. however, cr16can does not ac- knowledge a message sent by itself. therefore cr16can will send an error frame when no other device connected to the bus has ac- knowledged the message. internal internal. if the internal function is enabled, the tx- and rx-pin of the cr16can are inter- nally connected to each other. this feature can be used in conjunction with the loopback mode. this means that cr16can can receive its own sent messages without connecting an external transceiver chip to the rx- and tx- pin; it allows the user to run real stand-alone tests without any peripheral devices. diagen diagnostic enable. the diagen bit globally enables or disables the special diagnostic fea- tures of cr16can. this includes the following functions: ? lo (listen only) ? ignack (ignore acknowledge) ? loopback (loopback) ? internal (internal loopback) ? write access to hidden receive buffer eit error interrupt type. this bit configures when the error interrupt pending bit (cipnd.eipnd) is set and an error interrupt is generated if en- abled by the error interrupt enable (cien.eien). 0 the eipnd bit is set on every error on the can bus. 1 the eipnd bit is set only if the error state (cstpnd.ns) changes as a result of in- crementing either the receive or transmit error counter. 20.9.9 can timing register (ctim) the can timing register (ctim) defines the configuration of the bit time logic (btl). psc[6:0] prescaler configuration. these bits set the can prescaler. the settings are shown in ta b l e 3 1 sjw[1:0] synchronization jump width. these bits set the synchronization jump width which can be programmed between 1 and 4 time quanta (see table 32). note: the settings of sjw has to be configured to be small- er or equal to tseg1 and tseg2 tseg1[3:0] time segment 1. these bits configure the length of the time segment 1 (tseg1). it is not recommended to configure the time segment 1 to be smaller than 2tq. (see table 33). 15 9 8 7 6 3 2 0 psc[6:0] sjw[1:0] tseg1[3:0] tseg2[2:0] 0 r/w table 31 can prescaler settings ps c6 ps c5 ps c4 ps c3 ps c2 ps c1 ps c0 can prescaler (psc) 0000000 2 0000001 3 0000010 4 0000011 5 0000100 6 :::::: : 1111101 127 1111110/1 128 table 32 sjw settings sjw1 sjw0 synchronization jump width (sjw) 00 1 tq 01 2 tq 10 3 tq 11 4 tq
www.national.com 110 tseg2[2:0] time segment 2. the tseg2[2:0] bits set the number of time quanta (tq) for phase segment 2 (see table 34). 20.9.10 global mask registers (gmsk gmskb and gmskx) the gmskb and gmskx registers allow you to globally mask, or dont care the incoming extended/standard identi- fier bits, rtr/xrtr and ide. throughout this document, the gmskb and gmskx 16-bit registers are referenced as a 32- bit register gmsk. gm[28:15] the following are the bits for the gmskb regis- ter. gm[14:0] the following are the bits for the gmskx regis- ter. for all gmskb and gmskx register bits, the following ap- plies: 0 is the incoming identifier bit must match the corre- sponding bit in the message buffer identifier register. 1 accept 1 or 0 (dont care) of the incoming id bit independent from the corresponding bit in the mes- sage buffer id registers. the corresponding id bit in the message buffer will be overwritten by the incoming identifier bits. when an extended frame is received from the can bus, all global mask bits gm28 through gm0, ide, rtr and xrtr are used to mask the incoming message. during the reception of standard frames only the global mask bits gm28 to gm18, rtr and ide are utilized. 20.9.11 basic mask registers (bmsk bmskb and bmskx) the two registers bmskb and bmskx allow to mask the buffer 14, or dont care the incoming extended/standard identifier bits, rtr/xrtr and ide. throughout this docu- ment, the two 16-bit registers bmskb and bmskx are refer- enced to as a 32-bit register bmsk. bm[28:15] the following are the bits for the bmskb regis- ter. bm[14:0] the following are the bits for the bmskx regis- ter. table 33 time segment 1 settings tseg 13 tseg 12 tseg 11 tseg 10 length of time (tseg1) 0000not recommended 0001 2 tq 0010 3 tq 0011 4 tq 0100 5 tq 0101 6 tq 0110 7 tq 0111 8 tq 1000 9 tq 1001 10 tq 1010 11 tq 1011 12 tq 1100 13 tq 1101 14 tq 1110 15 tq 1111 16 tq table 34 time segment 2 settings tseg22 tseg21 tseg20 length of tseg2 0 0 0 1 tq 0 0 1 2 tq 0 1 0 3 tq 0 1 1 4 tq 1 0 0 5 tq 1 0 1 6 tq 1 1 0 7 tq 1 1 1 8 tq 15 5 4 3 2 0 gm[28:18] rtr ide gm[17:15] 0 r/w 15 1 0 gm[14:0] xrtr 0 r/w global mask gm[28:18] rtr a a. the rtr bit has a different position in standard and extended frames for standard frames the gmsk_rtr bit is used to mask this bit for extended frames the gmsk_xrtr bit is used to mask this bit ide gm[17:0] xrtr standard frame id[10:0] rtr ide unused extended frame id[28:18] srr ide id[17:0] rtr 15 5 4 3 2 0 bm[28:18] rtr ide bm[17:15] 0 r/w 15 1 0 bm[14:0] xrtr 0 r/w
111 www.national.com for all bmskb and bmskx register bits the following ap- plies: 0 incoming identifier bit must match the correspond- ing bit in the message buffer identifier register. 1 accept 1 or 0 (dont care) of the incoming id bit independent from the corresponding bit in the mes- sage buffer id registers. the corresponding id bit in the message buffer will be overwritten by the incoming identifier bits. when an extended frame is received from the can bus all basic mask bits bm28 through bm0, ide, rtr and xrtr are used to mask the incoming message. during the reception of standard frames only the basic mask bits bm28 to bm18, rtr and ide are utilized. 20.9.12 can interrupt enable register (cien) the can interrupt enable (cien) register enables the trans- mit/receive interrupts of the message buffers 0 through 14 as well as the can error interrupt. eien error interrupt enable. this bit allows the cr16can to interrupt the cpu if any kind of can receive/transmit errors are detected. this means any error status change in the error counter registers rec/tec is able to generate an error interrupt if eien is enabled. 0 the error interrupt is disabled and no error interrupt will be generated. 1 the error interrupt is enabled and a change in rec/tec will cause an inter- rupt to be generated. ien[14:0] buffer interrupt enable. the ien[14:0] allow the user to enable/disable interrupt source for each of the message buffers i.e., ien14 configures buffer14 and ien0 configures buffer0. 0 buffer as interrupt source disabled 1 buffer as interrupt source enabled 20.9.13 can interrupt pending register (cipnd) the cipnd register indicates any can receive/transmit in- terrupt requests caused by the message buffers 0..14 and can error occurrences. eipnd error interrupt pending eipnd indicates the status change of tec/rec and will execute an error interrupt if eien is set. the user has the responsibility to reset eipnd by means of the ciclr register. 0 can status is not changed 1 can status is changed ipnd[14:0] buffer interrupt pending ipnd[14:0] bits are set by cr16can following a successful trans- mission or reception of a message to or from message buffer 0...14, ipnd14 for buffer 14 and ipnd0 for buffer 0. 0 no interrupt pending for this message buff- er 1 message buffer has generated an inter- rupt 20.9.14 can interrupt clear register (ciclr) the bits in the ciclr register separately clear all can inter- rupt pending flags caused by the message buffers 0...14 and from the error management logic. eiclr error interrupt clear. the eiclr bit can clear the eipnd bit: 0 the contents of the eipnd bit is un- changed 1 the contents of the eipnd bit is reset iclr[14:0] buffer interrupt clear. the user is able to clear the buffer interrupt pending bits by iclr[14:0]: 0 the contents of the respective ipnd bit is unchanged 1 the contents of the respective ipnd bit is reset 20.9.15 can interrupt code enable register (cicen) the can interrupt code enable register (cicen) deter- mines whether the interrupt pending flag in ipnd should be translated into the interrupt code field of the cstpnd regis- ter. all interrupt requests, can error and buffer 0...14 inter- rupts can be enabled/disabled separately for the interrupt code indication field. eicen error interrupt code enable: 0 error interrupt pending is not indicated in the interrupt code 1 error interrupt pending is indicated in the interrupt code icen[14:0] buffer interrupt code enable: 0 buffer interrupt pending is not indicated in the interrupt code 1 buffer interrupt pending is indicated in the interrupt code basic mask bm[28:18] rtr a a. the rtr bit has a different position in standard and extended frames for standard frames the bmsk_rtr bit is used to mask this bit for extended frames the bmsk_xrtr bit is used to mask this bit ide bm[17:0] xrtr standard frame id[10:0] rtr ide unused extended frame id[28:18] srr ide id[17:0] rtr 15 14 0 eien ien[14:0] 0 r/w 15 14 0 eipnd ipnd[14:0] 0 r 15 14 0 eiclr iclr[14:0] 0 w 15 14 0 eicen icen[14:0] 0 r/w
www.national.com 112 20.9.16 can status pending register (cstpnd) the can status pending register (cstpnd) contains the status of the can node and the interrupt code. ns[2:0] can node status. this bits indicate the status of the can node as it is described in table 35. irq,ist[3:0] interrupt code. this section of the status pending register represents the interrupt source of the highest priority interrupt currently pending and enabled in the cicen register. table 36 shows the several interrupt codes for cicen=ffff. 20.9.17 can error counter register (canec) the can error counter register contains the value of the can receive error counter and the can transmit error counter. rec[7:0] can receive error counter. the bits rec[7:0] holds the value of the receive error counter. tec[7:0] can transmit error counter. the bits tec[7:0] holds the value of the transmit error counter. 20.9.18 can error diagnostic register (cediag) the can error diagnostic (cediag) register provides infor- mation about the last detected error. cr16can is able to identify the field within the can frame format, in which the er- ror occurred, and it identifies the bit number of the erroneous bit within the according frame field. the cpu has read only access and all bits will be cleared upon reset. efid[3:0] error field identifier. the ediag bits 3...0 iden- tify the frame field in which the last error oc- curred. how the various frame fields are coded into the efid bits is shown in table 37. 15 8 7 5 4 3 0 reserved ns[2:0] irq ist[3:0] 0 r table 35 can node status ns2 ns1 ns0 node status 0 0 0 not active 010 error active 0 1 1 error warning level 1 0 x error passive 1 1 x bus off table 36 highest priority interrupt code (cicen = ffff) can interrupt request irq ist3 ist2 ist1 ist0 no request 0 0 0 0 0 error interrupt 1 0 0 0 0 buffer 0 10001 buffer 1 10010 buffer 2 10011 buffer 3 10100 buffer 4 10101 buffer 5 10110 buffer 6 10111 buffer 7 11000 buffer 8 11001 buffer 9 11010 buffer 10 1 1 0 1 1 buffer 11 1 1 1 0 0 buffer 12 1 1 1 0 1 buffer 13 1 1 1 1 0 buffer 14 1 1 1 1 1 15 8 7 0 rec[7:0] tec[7:0] 0 r 15 14 13 12 11 10 9 4 3 0 reserved drive mon crc stuff txe ebid[5:0] efid[3:0] 0 r table 37 error field identifier field efid3 efid2 efid1 efid0 error 0000 error del 0 0 0 1 error echo 0 0 1 0 bus idle 0 0 1 1 ack 0100 eof 0101 intermission 0 1 1 0 suspend transmission 0111 sof 1000 arbitration 1 0 0 1 ide 1010 extended arbitration 1011 r1/r0 1100 dlc 1101 data 1110 crc 1 1 1 1
113 www.national.com ebid[5:0] error bit identifier. the ediag[9:4] bits contain the number (position) of the incorrect bit within the erroneous frame field. the bit number starts with the value equal to the respective frame field length minus one at the beginning of each field and is decremented with each can bit. figure 71 shows an example on how the ebid is calculated. assume the efid resulted in 1110 2 and the ebid showed a value of 111001 2 . this means that faulty field was the data field. to calculate the bit position of the error, the dlc of the message needs to be known. for example, for a dlc of 8 data bytes, the bit counter starts with the value: 8 x 8 - 1 = 63; so when ebid[5:0] = 111001 2 = 57, then the bit number was 63 - 57 = 6. the following bits provide an information of the error type. txe transmit error. if set, this bit indicates that the cr16can was an active transmitter at the time the error occurred. if reset, the cr16can was a receiver. stuff stuff error. if set, this bit indicates that a the bit stuffing rule was violated at the time the error occurred. note that certain bit fields do no use bit stuffing and therefore this bit may be ignored in those. crc crc error. if set, this bit indicates that the crc is invalid. this bit should only be used if the efid shows the code of the ack field. mon monitor. this bit shows the bus value on the canrx pin as seen by the cr16can at the time of the error. drive drive. this bit shows the output value on the cantx pin at the time of the error. note that a receiver will not drive the bus except during ack and during an active error flag. 20.9.19 can timer register (ctmr) the current value of the time stamp counter as described in section 20.8 can be monitored via the can timer register. the can time register is a free running 16-bit counter. it contains the number of can bits recognized by cr16can since the register has been reset. the counter starts to incre- ment from the value 0000 16 after a hardware reset. if the tim- er stamp enable flag (tstpen) in the can global configuration register (cgcr) is set, the counter will also be reset upon a message transfer of the message buffer 0. as described in time stamp counter on page 103, the con- tents of ctmr are captured into the time stamp register of the message buffer after successfully sending or receiving a frame. 20.10 system start-up and multi-input wake-up after system start-up, all cr16can related registers are in their reset state. the cr16can module can be enabled after all configuration registers are set to their desired value. the following initial setting need to be made: configure the can timing register (ctim) see bit time logic on page 93. configure every buffer to its function as receive/trans- mit buffer status/control register (cnstat) on page 104. set the acceptance filtering masks. see acceptance filtering on page 95. enable the cr16can interface. see can global con- figuration register (cgcr) on page 107. before disabling the cr16can module, the user has to make sure that no transmission is still pending. note: the device can be awaken from a power saving mode by an activity on the can bus by selecting the can rx pin as an input to the multi-input wake-up module. in this case the cr16can module must not be disabled before entering the power saving mode. disabling the cr16can module also disables the can rx pin. as an alternative, the can rx pin can be connected to any other input pin of the multi-input wake-up module. this input channel must then be configured to trigger a wake-up event on a falling edge (if a dominant bit is represented by a low lev- el). in this case the cr16can module can be disabled before entering a power saving mode. after the device has been waken up, the user has to manually enable the cr16can again. all configuration and buffer registers still contain the same data as prior to the power down phase. 20.10.1 external connection the cr16can uses two external pins, cantx and canrx to connect to the physical layer of the can interface. they provide the functionality as described in table 38. the logic levels are configurable by means of two control flags ctx and crx of the global configuration register cgcr (see can global configuration register (cgcr) on page 107. 15 0 ctmr[15:0] 0 r rrrrrr incorrect bit data field figure 71. ebid example table 38 external cr16can pins signal name type description cantx output transmit data to the can bus canrx input receive data from the can bus
www.national.com 114 20.10.2 transceiver connection an external transceiver chip needs to be connected be- tween the can block and the bus. it is used to establish a bus connection in differential mode and furthermore provides the driver and protection requirements. figure 72 shows a possible iso-high-speed configuration . 20.10.3 timing requirements processing messages and updating message buffers require a certain number of clock cycles by cr16can as shown in table 39. these requirements may lead to some restrictions regarding the bit time logic settings and the overall cr16can performance which are described below in more detail. the critical path derives from receiving a remote frame which triggers the transmission of one or more data frames. there are a minimum of four bit times in-between two consecutive frames. these bit times start at the validation point of re- ceived frame (reception of 6th eof bit) and end at the earli- est possible transmission start of the next frame, which is after the third intermission bit at 100% burst bus load. these four bit times have to be set in perspective with the tim- ing requirements of the cr16can. the minimum duration of the four can bit times is deter- mined by the following bit time logic settings: psc = pscmin = 2 tseg1 = tseg1min = 2 tseg2 = tseg2min = 1 bit time = synch + time segment 1 + time segment 2 = (1 + 2 + 1) tq = 4 tq = (4 tq x psc) clock cycles = (4 tq x 2) clock cycles = 8 clock cycles for these minimum btl settings, four can bit times take 32 clock cycles. the following is an example that assumes typical case: minimum btl settings reception and copy of a remote frame update of one buffer from tx_rtr schedule of one buffer from transmit as outlined in table 39 the copy process, update and sched- uling the next transmission gives a total of 17+3+2=22 clock cycles. therefore under these conditions there is no timing restriction. the following example assumes the worst case: minimum btl settings reception and copy of a remote frame update of the 14 remaining buffers from tx_rtr schedule of one buffer for transmit all these actions in total require 17 + 14 x 3 + 2 = 61 clock cycles to be executed by cr16can. this leads to the limita- tion of the bit time logic of 61 / 4 = 15.25 clock cycles per can bit as a minimum, resulting in the minimum clock fre- quencies listed below (the frequency depends on the desired baud rate and assumes the worst case scenario can occur in the application). table 40 gives examples for the minimum clock frequency in order to ensure proper functionality at various can bus speeds. 20.10.4 bit time logic calculation examples the calculation of the can bus clocks using cki = 16mhz is shown in the following examples. the desired baud rate for both examples is 1mbit/s. example 1 psc = psc[5:0] + 2 = 0 + 2 = 2 tseg1 = tseg1[3:0] + 1 = 3 + 1 = 4 tseg2 = tseg2[2:0] + 1 = 2 + 1 = 3 sjw = tseg2 = 3 table 39 cr16can internal timing task # cycles a a. wait cycles need to be added for cpu access to the object memory as described in cpu access to cr16can registers/memory on page 103. occurrence/ frame b b. depends on the number of matching identifiers. copy hidden buffer to receive message buffer 17 0-1 update status from tx_rtr to tx_once_rtr 30-15 schedule a message for trans- mission 20-1 vcc to other modules termination can bus line 120 120 vcc rs gnd bus_l bus_h tx rx ref transceiver chip gnd 3 7 6 2 8 5 4 1 gnd cantx canrx cr16can core bus figure 72. external transceiver connection (iso-high-speed) table 40 min. clock frequency requirements baud rate min. clock frequency 1mbit/sec 15.25mhz 500kbit/sec 7.625mhz 250kbit/sec 3,81mhz
115 www.national.com sample point positioned at 62.5% of bit time bit time = 125ns x (1 + 4 + 3 3) = (1 0.375) m s busclock = 16mhz / (2 x (1 + 4 + 3)) = 1mbit/s (nominal) example 2 psc = psc[5:0] + 1 = 2 + 2 = 4 tseg1 = tseg1[3:0] + 1 = 1 + 1 = 2 tseg2 = tseg2[2:0] + 1 = 0 + 1 = 1 sjw = tseg2 = 1 ? sample point positioned at 75% of bit time ? bit time = 250ns x (1 + 2 + 1 1) = (1 0.25) m s ? busclock = 16mhz / (2 x (1 + 4 + 3)) = 1mbit/s (nominal) 20.10.5 acceptance filter considerations the cr16can provides two acceptance filter masks gmsk and bmsk as described in acceptance filtering on page 95, global mask registers (gmsk gmskb and gmskx) on page 110 and basic mask registers (bmsk bmskb and bmskx) on page 110. these masks allow filtering of up to 32 bits of the message object, which includes the standard identifier, the extended identifier as well as the frame control bits rtr, srr and ide. 20.10.6 remote frames remote frames can be automatically processed by the cr16can interface. however, to fully enable that feature, the rtr/xrtr bits (for both standard and extended frames) within the bmsk and/or gmsk register need to be set to dont care. this is because a remote frame with the rtr bit being set to 1 should trigger the transmission of a data frame with the rtr bit set to 0 and therefore the id bits of the received message need to pass through the acceptance filter. the same applies to transmitting remote frames and switching to receive the corresponding data frames.
www.national.com 116 21.0 analog comparators the dual analog comparator (acmp2) module contains two independent analog comparators with all necessary control logic. each comparator unit compares the analog input volt- ages applied to two input pins and determines which voltage is higher. the comparison results can be placed on two out- put pins and/or read by the software from a register. figure 73 is a block diagram of the dual analog comparator module. the two comparators are designated comparator 1 (cmp1) and comparator 2 (cmp2). each comparator has a positive and a negative input, called cmp1p and cmp1n for compar- ator 1 and cmp2p and cmp2n for comparator 2. an option- al output, cmp1o for comparator 1 or cmp2o for comparator 2, allows the external hardware to read the com- parison results. if the positive input is greater than the nega- tive input, the result is a logic 1. otherwise, the result is a logic 0. these same results are available to the software by reading the cmpctrl register. cmp1op and cmp2op are the direct outputs of the analog comparator. these signals are connected to the channels of the multi-wake-up module. 21.1 analog comparator control/ status register (cmpctrl) the cmpctrl register is a byte-wide, read/write register that controls the comparator module and contains the com- parison results. the control bits are read/write bits and the re- sult bits are read-only bits. this register is cleared upon reset. the register format is shown below. cmp1rd comparator 1 read. this read-only bit con- tains the output of comparator 1 when the comparator is enabled (cmp1en=1). cmp1rd is set to 1 when the voltage on cmp1p is greater than the voltage on cmp1n. this bit is always 0 when comparator 1 is dis- abled. cmp2rd comparator 2 read. this read-only bit con- tains the output of comparator 2 when the comparator is enabled (cmp2en=1). cmp2rd is set to 1 when the voltage on cmp2p is greater than the voltage on cmp2n. this bit is always 0 when comparator 2 is dis- abled. cmp1en comparator 1 enable. this read/write bit en- ables (1) or disables (0) comparator 1. cmp2en comparator 2 enable. this read/write bit en- ables (1) or disables (0) comparator 2. cmp1oe comparator 1 output enable. this read/write bit, when set to 1, enables the use of the cmp1o pin as the output of comparator 1 when comparator 1 is enabled (cmp1en=1). if comparator 1 is disabled (cmp1en=0), setting the cmp1oe bit results in a logic 0 on the cmp1o output pin. cmp2oe comparator 2 output enable. this read/write bit, when set to 1, enables the use of the cmp2o pin as the output of comparator 2 when comparator 2 is enabled (cmp2en=1). if comparator 2 is disabled (cmp2en=0), setting the cmp2oe bit results in a logic 0 on the cmp2o output pin. 21.2 analog comparator usage the comparator i/o pins are alternate functions of the port l pins. in order for a comparator to operate, its two input pins must be configured to operate as inputs in the alternate func- tion mode. using a comparator's output pin is optional. if it is to be used, it must be configured to operate as an output in the alternate function mode. the comparison result bits in the cmpctrl register are available to the cpu whether or not the output pin is enabled. note: there is a setup time for the comparator. the program- mer needs to add at least one nop instruction between en- abling the comparator and reading back the comparison result if the parts is running above 24mhz. the comparators uses dc current whenever they are en- abled. therefore, in order to reduce power consumption, it is recommended that the comparators be disabled when they are not needed, especially before entering any of the power save modes. 7 6 5 4 3 2 1 0 reserved cmp2oe cmp1oe cmp2en cmp1en cmp2rd cmp1rd
117 www.national.com figure 73. dual analog comparator block diagram + _ cmp1 cmp1en cmp1oe + _ cmp2 cmp2en cmp2oe control + status cmp1p cmp2p cmp1n cmp2n cmp1o cmp2o cmp1op cmp2op
www.national.com 118 22.0 a/d converter the a/d converter (adc) module is a 12-channel, multi- plexed-input, analog-to-digital converter. the a/d converter receives an analog voltage on an input pin and converts that voltage into an 8-bit digital value using successive approxi- mation. the cpu can then read the result from a memory- mapped register. the module supports four automated oper- ating modes, providing single-channel or 4-channel scanned operation in single-conversion or continuous mode. figure 74 is a block diagram of the a/d converter module. the analog input signal is selected from the analog inputs us- ing a 12-channel analog multiplexer. the input pins are alter- nate functions of port i. a sample-and-hold circuit samples the analog voltage prior to conversion and holds it stable throughout the conversion pro- cess. a programmable initial delay period allows the sampled voltage to stabilize before the conversion process begins. the input voltage range is from 0v to v ref (the a/d reference voltage). the device has a separate pin, v ref , for the refer- ence voltage. a capacitor should be connected between the v ref and the a vcc pin in order to minimize noise. the recommended value for this capacitor is about 0.47 m f. the internal analog-to-digital converter block is based on a successive approximation algorithm, which compares the sampled voltage against an internally generated sequence of analog voltages. the result is a linear conversion of the ana- log voltage to an unsigned 8-bit value ranging from 00 hex for 0.0 volts to ff hex for v ref . the clock used by the converter block is generated by a clock divider that scales down the system clock by a programmable factor. the conversion algorithm requires ten a/d converter clock cycles, or 10 microseconds at the maximum allowed a/ d converter clock rate of 2 mhz. conversion can start after the power supply is stable and ad- cen set for 30 m s. the conversion results are stored in a 4-level data buffer. de- pending on the operating mode, the buffer can hold the re- sults of four successive conversions from a single channel or four conversions from adjacent channels scanned in se- quence. 22.1 operating modes the a/d converter can be configured to operate in any one of four modes: single channel, single conversion single channel, continuous conversion 4-channel scan, single conversion 4-channel scan, continuous conversion the configuration is set by the scan and cont fields in the adc control 2 register (adccnt2), as indicated in table 41. the a/d converter must be disabled when switch- ing to a different mode. 22.1.1 single channel, single conversion mode in the single channel, single conversion mode, the a/d con- verter performs a single conversion using a specified chan- nel. the software starts a conversion by setting the start bit in the adccnt2 register. upon completion of the conversion, the a/d converter places the result in register addata0, clears the start bit, and sets the eoc (end of conversion) bit in the adcst register. if the a/d converter interrupt is en- abled, an interrupt to the cpu is generated at this time. table 41 adc operation modes scan cont mode 00 0 single channel, single conversion 00 1 single channel, continuous conversion 01 0 4 channels scan, single conversion 01 1 4 channel scan, continuous conversion figure 74. a/d converter block diagram 12:1 analog mux sample & hold configuration status & control data buffer clock divider peripheral bus clk clk v ref ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 analog to digital converter ch8 ch9 ch10 ch11 4
119 www.national.com 22.1.2 single channel, continuous conversion mode in the single channel, continuous conversion mode, the a/d converter performs conversions repeatedly using the same specified channel. the software starts a conversion sequence by setting the start bit. the a/d converter performs four a/d conversions in sequence using the same channel, pausing only for the programmable sampling delay time used in all conversion op- erations. it loads the four results into the a/d data registers in sequence, starting with addata0 and ending with addata3. after it loads all four registers, it sets the eoc (end of conver- sion) bit. if the a/d converter interrupt is enabled, an inter- rupt to the cpu is generated at this time. the start bit remains set until cleared by the software. if the software does not clear the start bit, the a/d converter continues performing conversions using the same input channel, storing the results in addata0 following addata3. to prevent an overrun error, the software must read the re- sults from the data registers before the a/d converter writes the next result into addata0 following addata3. when the software clears the start bit, the a/d converter first completes the conversion currently in progress, then stops and sets the eoc bit. a 2-bit buffer pointer in the adcst register points to the register containing the final re- sult. 22.1.3 4-channel scan, single conversion mode in the 4-channel scan, single conversion mode, the a/d con- verter performs four conversions using four adjacent input channels. the software starts the conversion sequence by setting the start bit. the a/d converter performs four a/d conversions in sequence using four adjacent channels, starting with the specified channel and pausing only for the programmable sampling delay time. it loads the four results into the a/d data registers in sequence, starting with addata0 and ending with addata3. after it loads all four registers, it clears the start bit and sets the eoc (end of conversion) bit. if the a/ d converter interrupt is enabled, an interrupt to the cpu is generated at this time. 22.1.4 channel scan, continuous conversion mode in the 4-channel scan, continuous conversion mode, the a/d converter performs conversions repeatedly using four adja- cent input channels. the software starts conversion operations by setting the start bit. the a/d converter performs four a/d conversions in sequence using four adjacent channels, starting with the specified channel and pausing only for the programmable sampling delay time. it loads the four results into the a/d data registers in sequence, starting with addata0 and ending with addata3. after it loads all four registers, it sets the eoc (end of conversion) bit. if the a/d converter interrupt is en- abled, an interrupt to the cpu is generated at this time. the start bit remains set until cleared by the software. if the software does not clear the start bit, the a/d converter continues performing conversions, repeating the same se- quence using the same four input channels and the same se- quence of data registers. to prevent an overrun error, the software must read the results from the data registers before the a/d converter writes the next result into addata0. when the software clears the start bit, the a/d converter first completes the 4-channel conversion sequence currently in progress, then stops and sets the eoc bit. 22.2 a/d converter registers the software controls the a/d converter and reads the a/d results by accessing the adc registers. there are eight such registers: adc status register (adcst) adc control 1 register (adccnt1) adc control 2 register (adccnt2) adc control 3 register (adccnt3) adc data registers (addata0 through addata3) 22.2.1 adc status register (adcst) the adcst register is a byte-wide register that indicates the current status of the a/d converter. one bit in this register, the ovf flag bit, is cleared by writing a 1 to its bit position. the other bits are read-only bits, so the values written to them are ignored. upon reset, the register is set to 30 hex. the register format is shown below. eoc end of conversion. this read-only bit reports the status of the most recent a/d converter op- eration. when cleared to 0, it indicates that the conversion is not complete. when set to 1, it in- dicates that the conversion is complete. the hardware sets this bit when it places the con- version results in the buffer and clears it when any of the data registers are read. busy adc busy. this read-only bit is set to 1 when the a/d converter is busy converting data and is cleared to 0 when the a/d converter is idle or disabled. ovf overflow. the hardware sets this bit to 1 when the a/d converter finishes a conversion and at- tempts to store the results in one of the data registers (addata0-addata3) while the regis- ter is full. when this happens, the a/d convert- er overwrites the data in the data register, sets the ovf flag, and continues operating. the ovf flag remains set until cleared by the software. the software clears the flag by writ- ing a 1 to it. writing a 0 to this bit has no effect. bufptr buffer pointer. this 2-bit, read-only field identi- fies the data register that was most recently written with new data: 00 = addata0 01 = addata1 10 = addata2 11 = addata3 this register is initialized to 11 when a new conversion is started (when adccnt2.start is changed from 0 to 1) and is automatically in- cremented every time a result is written to buff- ers addata0-addata3. the result is a four- 7 6 5 4 3 2 1 0 reserved bufptr reserved ovf busy eoc
www.national.com 120 entry cyclic fifo buffer, with bufptr pointing to the last entry written by the a/d converter. 22.2.2 adc control 1 register (adccnt1) the adccnt1 register is a byte-wide, read/write register used to enable the a/d converter and its interrupts, and also to control the reference voltage source. when writing to this register, all reserved bits must be written with 0 for the a/d converter to function properly. changing any bits other than adcen (bit 0) is not allowed while the a/d converter is ac- tive (adcst.busy or adccnt2.start set). upon reset, all non-reserved bits are cleared to 0. the register format is shown below. adcen a/d converter enable. setting this bit enables the a/d converter and allows a conversion to be started by setting the start bit (adccnt2.start). clearing the adcen bit disables the a/d converter, terminates any conversion in progress, and clears the adc status flags (adcst.eoc, adcst.busy, adcst.ovf, and adccnt2.start). inte interrupt enable. this bit enables (1) or dis- ables (0) a/d converter interrupts. if enabled, and interrupt occurs at the end of a conversion sequence or when the adc data buffer is full, depending on the operating mode. all reserved bits must be written with 0 for adc to operate properly. 22.2.3 adc control 2 register (adccnt2) the adccnt2 register is a byte-wide, read/write register used to specify the a/d converter operating mode and to start conversion operations. all register fields other than the start bit should be changed only while the a/d converter is inactive (start=0). data written to the scan and cont fields is ignored if the start bit is already set. upon reset, the non-reserved bits of this register are cleared to 0. the register format is shown below. channel channel select. this 4-bit field selects one of the twelve analog input channels as follows: 0000 = ach0 0001 = ach1 0010 = ach2 0011 = ach3 0100 = ach4 0101 = ach5 0110 = ach6 0111 = ach7 1000 = ach8 1001 = ach9 1010 = ach10 1011 = ach11 11xx = reserved cont continuous conversion. when cleared to 0, the a/d converter stops operating upon comple- tion of the programmed conversion cycle (a sin- gle conversion or a sequence of four conversions on four channels). when set to 1, the a/d converter operates continuously by re- peating the programmed conversion cycle. scan scan mode. this 2-bit field selects the single- conversion mode or 4-channel scan mode as follows: 00 = single-conversion mode 01 = 4-channel scan mode 1x = reserved start start conversion. the software sets this bit to 1 to start a conversion or a 4-channel conver- sion cycle. in the continuous mode, this bit re- mains set until cleared by the software. in the single (non-continuous) mode, the hardware clears this bit upon completion of the pro- grammed conversion cycle. the software should not attempt to set this bit while the a/d converter is busy (adcst.busy=1). 22.2.4 adc control 3 register (adccnt3) the adccnt3 register is a byte-wide, read/write register used to specify the analog sampling time delay and the di- vide-by factor for generating the adc clock. this register should be written only when the a/d converter is disabled (adccnt1.adcen=0). upon reset, the non-reserved bits of the adccnt3 register are cleared to 0. the register format is shown below. cdiv clock divide. this 3-bit field sets the divide-by factor for generating the a/d converter clock from the system clock. the frequency of the a/ d converter clock is equal to the system clock divided by the programmed factor. the result- ing a/d converter clock frequency must be less than or equal to 2 mhz. the divide-by factor is defined as follows: 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 other = reserved delay sampling time delay. this 3-bit field defines the number of a/d converter clock cycles of delay from the time that the input channel is se- lected until the analog voltage is sampled. the programmed delay should be sufficient, depen- dent on the source impedance, to allow the sampled signal to reach its final level before the conversion begins. the delay is defined as fol- lows: 000 = 1 a/d converter clock cycle 001 = 2 a/d converter clock cycles 010 = 4 a/d converter clock cycles 011 = 8 a/d converter clock cycles 100 = 16 a/d converter clock cycles 101 = 32 a/d converter clock cycles 7 6 5 4 3 2 1 0 reserved inte reserved adcen 7 6 5 4 3 2 1 0 start scan cont channel 7 6 5 4 3 2 1 0 reserved pwren delay cdiv
121 www.national.com 110 = 64 a/d converter clock cycles 111 = reserved pwren power down enable. c ontrols the condition when the adc is powered down. when pwren is cleared (0), the adc powers down upon reset. when pwren is set (1), the adc powers down when the adcen bit is low. 22.2.5 adc data registers (addata0-addata3) the four adc data registers (addata0 through addata3) are byte-wide, read/write registers that hold the conversion results, which are stored sequentially starting with addata0 and ending with addata3. the results held in these registers are valid only after the adcst.eoc flag is set. upon reset, the contents of these registers are undefined. the value read from a data register is a linear mapping of the analog input voltage to an 8-bit value. the value 00 hex rep- resents 0.0 volts and the value ff hex represents the refer- ence voltage, v ref . 22.3 a/d converter programming the software should set the a/d converter configuration be- fore it enables the a/d converter module. the configuration consists of the following settings: adc clock rate: adccnt3.cdiv sampling delay: adccnt3.delay interrupt enable (if required): adccnt1.inte the adc clock is created by scaling down the system clock. the fastest allowable clock for the a/d converter is 2 mhz. therefore, for the fastest possible operation of the a/d con- verter, use the smallest available divide-by factor that results in a clock frequency of 1 mhz or lower. the available divide- by factors are 1, 2, 4, 8, 16, and 32. for example, if the system clock is 10 mhz, use a divide-by factor of 16. in that case, the a/d converter clock frequency is 625 khz, the clock period is 1.6 microseconds, and the a/ d conversion time is 16 microseconds (ten clock a/d con- verter clock cycles). the programmable sampling time delay should be made small for faster operation, but large enough to allow the input voltage to settle. the internal resistance and capacitance of the a/d converter, together with the source resistance of the device that drives the a/d input determine the charge-up time required for the voltage to settle. figure 75 shows a schemat- ic of the charge-up circuit. for the values of r ain and c ain , see section 25.0. interrupts or polling can be used to read the a/d converter results. for interrupts, the a/d converter interrupt must be enabled by setting the adccnt1.inte bit. the interrupt is cleared automatically when any one of the data registers (addata0-addata3) is read. for polling, the software reads the adcst.eoc bit to determine whether the conversion se- quence is completed. once the a/d converter configuration has been set up, the software can use the following procedure to perform an a/d conversion sequence: 1. enable the a/d converter by setting the adccnt1.ad- cen bit and wait 30 m s before performing any conver- sion. 2. select the operating mode and channel by writing to the scan, cont, and channel fields of the adccnt2 register. at the same time, start the conversion by setting the start bit in the same register. 3. wait until the conversion is finished, either by polling or using the a/d converter interrupt. 4. read the conversion results from the data registers, addata0 through addata3 (or just addata0 in the sin- gle-channel, single-conversion mode). 5. in the continuous conversion modes, repeat step 3 and step 4 for as long as samples are needed. then stop the a/d converter by clearing either the start bit (adccnt2.start) or the a/d converter enable bit (adccnt1.adcen). to minimize power consumption, the a/d converter should be disabled when it is not needed, especially before entering a power save mode. figure 75. sample-and-hold charge-up schematic a/d converter analog multiplexer sample & hold r ain c ain input signal r source
www.national.com 122 23.0 memory map the compactrisc architecture supports a uniform linear ad- dress space of 2 megabytes. the device implementation of this architecture uses only the lowest 128k bytes of address space, ranging from 0000 to 1ffff hex. table 42 is a mem- ory map showing the types of memory and peripherals that occupy this memory space. address ranges not listed in the table are reserved and should not be read or written. table 43 is a detailed memory map showing the specific memory address of the memory, i/o ports, and registers. the table shows the starting address, the size, and a brief de- scription of each memory block and register. for detailed in- formation on using these memory locations, see the applicable sections in the data sheet. all addresses not listed in the table are reserved and should not be read or written. an attempt to access an unlisted ad- dress will have unpredictable results. each byte-wide register occupies a single address and can be accessed only in a byte-wide transaction. each word-wide register occupies two consecutive memory addresses and can be accessed only in a word-wide transaction. both the byte-wide and word-wide registers reside at word boundaries table 42 device memory map address range (hex) description biu zone 0000-bfff flash program memory (48k bytes) zone 0 c000-cfff static ram (4k bytes) n/a e000-e5ff isp memory(1.5k bytes) zone 1 e800-efff lower endurance flash eeprom data memory (2k bytes) n/a f000-f07f high endurance flash eeprom data memory (128 bytes) f400-f7ff can buffers and registers (1k bytes) f800-faff biu peripherals (768 bytes) fb00-fb06 port b registers i/o expansion fb00-fbff i/o expansion + ports pb & pc (256 bytes) fb10-fb16 port c registers fc00-ffff peripherals and other i/o ports (1k bytes) n/a fc40-fc8a clock, power management, and wake-up registers fca0-fca8 port g registers fcc0-fcc8 port h registers ff00-ff08 port l registers fd20-fd28 port f registers fe00-fe1e interrupt control unit registers fe40-fe4e usart 1 registers fe60-fe66 microwire registers fe80-fe8e usart 2 registers fec0-feca access.bus registers fee0-fee8 port i registers ff20-ff2a timer and watchdog registers ff40-ff50 multi-function timer1 registers ff60-ff70 multi-function timer2 registers ff80-ffa4 versatile timer unit registers ffc0-ffd0 a/d converter registers ffe0-ffe0 analog comparator register 10000-1bfff flash program memory (48k bytes) zone 0
123 www.national.com (even addresses). thus, each byte-wide register uses only the lowest eight bits of the internal data bus. most device registers are read/write registers. however, some registers are read-only or write-only, as indicated in the table. an attempt to read a write-only register or to write a read-only register will have unpredictable results. when the software writes to a register in which one or more bits are reserved, it must write a zero to each reserved bit un- less indicated otherwise in the description of the register. reading a reserved bit returns an undefined value. table 43 device detailed memory map register name size register address (hex) access type contents 48k 0000 flash eeprom program memory 4k c000 on-chip ram 2k e800 low endurance flash eeprom data memory 1.5k e000 isp memory 128 f000 high endurance flash eeprom data memory cmb0_cntstat word f400 read/write can message buffer 0 status register cmb0_tstp word f402 read/write can message buffer 0 time stamp register cmb0_data3 word f404 read/write can message buffer 0 data 3 register cmb0_data2 word f406 read/write can message buffer 0 data 2 register cmb0_data1 word f408 read/write can message buffer 0 data 1 register cmb0_data0 word f40a read/write can message buffer 0 data 0 register cmb0_id0 word f40c read/write can message buffer 0 identifier 0 register cmb0_id1 word f40e read/write can message buffer 0 identifier 1 register cmb1 8-word f410 read/write can message buffer 1 register cmb2 8-word f420 read/write can message buffer 2 register cmb3 8-word f430 read/write can message buffer 3 register cmb4 8-word f440 read/write can message buffer 4 register cmb5 8-word f450 read/write can message buffer 5 register cmb6 8-word f460 read/write can message buffer 6 register cmb7 8-word f470 read/write can message buffer 7 register cmb8 8-word f480 read/write can message buffer 8 register cmb9 8-word f490 read/write can message buffer 9 register cmb10 8-word f4a0 read/write can message buffer 10 register cmb11 8-word f4b0 read/write can message buffer 11 register cmb12 8-word f4c0 read/write can message buffer 12 register cmb13 8-word f4d0 read/write can message buffer 13 register cmb14 8-word f4e0 read/write can message buffer 14 register cgcr word f500 read/write can global configuration register ctim word f502 read/write can timing register gmskx and gmsk word f504 read/write can global mask registers gmskx and gmskb word f508 read/write can basic mask registers cien word f50c read/write can interrupt enabled register cipnd word f50e read/write can interrupt pending register ciclr word f510 read/write can interrupt clear register cicen word f512 read/write can interrupt code enable register cstpnd word f514 read/write can status pending register canec word f516 read/write can error counter register cediag word f518 read/write can error diagnostic register ctmr word f51a read/write can timer register
www.national.com 124 bcfg byte f900 read/write biu configuration register iocfg word f902 read/write i/o zone configuration register szcfg0 word f904 read/write static zone 0 configuration register szcfg1 word f906 read/write static zone 1 configuration register mcfg byte f910 read/write module configuration register mstat byte f914 read only module status register flctrl1 byte f930 read/write flash eeprom program memory control register 1 flsec byte f932 read/write flash eeprom program memory security register ispkey byte f934 read/write isp memory write key register flctrl2 word f936 read/write flash eeprom program memory control register 2 dmcsr byte f940 read/write eeprom data memory control and status register dmpslr byte f942 read/write eeprom data memory prescaler register dmstart byte f944 read/write data memory start time reload register dmtran byte f946 read/write data memory transition time reload register dmprog byte f948 read/write data memory programming time reload register dmerase byte f94a read/write data memory erase time reload register dmend byte f94c read/write data memory end time reload register dmpcnt byte f94e read/write data memory prescaler count register dmcnt word f950 read/write data memory timer count register dmkey byte f954 read/write eeprom data memory write key register flcsr byte f960 read/write flash eeprom program memory control and status register flpslr byte f962 read/write flash eeprom program memory prescaler register flstart byte f964 read/write program memory start time reload register fltran byte f966 read/write program memory transition time reload register flprog byte f968 read/write program memory programming time reload register flerase byte f96a read/write program memory erase time reload register flend byte f96c read/write program memory end time reload register flpcnt byte f96e read/write program memory prescaler count reload register flcnt1 byte f970 read/write program memory timer count register 1 flcnt2 byte f972 read/write program memory timer count register 2 pgmkey byte f974 read/write flash eeprom program memory write key register pbdir byte fb00 read/write port b direction register pbdin byte fb02 read only port b data input register pbdout byte fb04 read/write port b data output register pbwkpu byte fb06 read/write port b weak pull-up register pcdir byte fb10 read/write port c direction register pcdin byte fb12 read only port c data input register pcdout byte fb14 read/write port c data output register pcwkpu byte fb16 read/write port c weak pull-up register crctrl byte fc40 read/write clock and reset control register prssc byte fc42 read/write slow clock prescaler register prssc1 byte fc44 read/write prescaler slow clock 1 register pmcsr byte fc60 read/write power management control/status register wkedg word fc80 read/write wake-up edge detection register table 43 device detailed memory map register name size register address (hex) access type contents
125 www.national.com wkena word fc82 read/write wake-up enable register wkict1 word fc84 read/write wake-up interrupt control register 1 wkictl2 word fc86 read set wake-up interrupt control register 2 wkpnd word fc88 write only wake-up pending register wkpcl word fc8a read/write wake-up pending clear register pgalt byte fca0 read/write port g alternate function register pgdir byte fca2 read/write port g direction register pgdin byte fca4 read only port g data input register pgdout byte fca6 read/write port g data output register pgwkpu byte fca8 read/write port g weak pull-up register phalt byte fcc0 read/write port h alternate function register phdir byte fcc2 read/write port h direction register phdin byte fcc4 read only port h data input register phdout byte fcc6 read/write port h data output register phwkup byte fcc8 read/write port h weak pull-up register pfalt byte fd20 read/write port f alternate function register pfdir byte fd22 read/write port f direction register pfdin byte fd24 read only port f data input register pfdout byte fd26 read/write port f data output register pfwkpu byte fd28 read/write port f weak pull-up register ivct byte fe00 read only interrupt vector register nmistat byte fe02 read only nmi status register exnmi byte fe04 read/write external nmi control/status register istat0 word fe0a read only interrupt status register 0 istat1 word fe0c read only interrupt status register 1 ienam0 word fe0e read/write interrupt and enable mask register 0 ienam1 word fe10 read/write interrupt and enable mask register 1 idbg word fe1a read/write interrupt debug register u1tbuf byte fe40 read/write usart 1 transmit data buffer u1rbuf byte fe42 read only usart 1 receive data buffer u1ictrl byte fe44 read/write usart 1 interrupt control register u1stat byte fe46 read only usart 1 status register u1frs byte fe48 read/write usart 1 frame select register u1mdsl byte fe4a read/write usart 1 mode select register u1baud byte fe4c read/write usart 1 baud rate divisor register u1psr byte fe4e read/write usart 1 baud rate prescaler mwdat byte fe60 read/write microwire data register mwctl byte fe62 read/write microwire control register mwstat word fe64 read/write microwire status register u2tbuf byte fe80 read/write usart 2 transmit data buffer u2rbuf byte fe82 read only usart 2 receive data buffer u2ictrl byte fe84 read/write usart 2 interrupt control register u2stat byte fe86 read only usart 2 status register u2frs byte fe88 read/write usart 2 frame select register u2mdsl byte fe8a read/write usart 2 mode select register table 43 device detailed memory map register name size register address (hex) access type contents
www.national.com 126 acbsda byte fec0 read/write acb serial data register u2baud byte fe8c read/write usart 2 baud rate divisor register u2psr byte fe8e read/write usart 2 baud rate prescaler acbst byte fec2 read/write acb status register acbcst byte fec4 read/write acb control status register acbctl1 byte fec6 read/write acb control 1 register acbaddr byte fec8 read/write acb own address register acbctl2 byte feca read/write acb control 2 register pialt byte fee0 read/write port i alternate function register pidir byte fee2 read/write port i direction register pidin byte fee4 read only port i data input register pidout byte fee6 read/write port i data output register piwkpu byte fee8 read/write port i weak pull-up register plalt byte ff00 read/write port l alternate function register pldir byte ff02 read/write port l direction register pldin byte ff04 read only port l data input register pldout byte ff06 read/write port l data output register plwkpu byte ff08 read/write port l weak pull-up register twcfg byte ff20 read/write timer and watchdog configuration register twcp byte ff22 read/write timer and watchdog clock prescaler register twmt0 word ff24 read/write twm timer 0 register t0csr byte ff26 read/write twmt0 control and status register wdcnt byte ff28 write only watchdog count register wdsdm byte ff2a write only watchdog service data match register t1cnt1 word ff40 read/write t1 timer/counter i register t1cra word ff42 read/write t1 reload/capture a register t1crb word ff44 read/write t1 reload/capture b register t1cnt2 word ff46 read/write t1 timer/counter ii register t1prsc byte ff48 read/write t1 clock prescaler register t1ckc byte ff4a read/write t1 clock unit control register t1ctrl byte ff4c read/write t1 timer mode control register t1ictl byte ff4e read/write t1 timer interrupt control register t1iclr byte ff50 read/write t1 timer interrupt clear register t2cnt2 word ff60 read/write t2 timer/counter i register t2cra word ff62 read/write t2 reload/capture a register t2crb word ff64 read/write t2 reload/capture b register t2cnt2 word ff66 read/write t2 timer/counter ii register t2prsc byte ff68 read/write t2 clock prescaler register t2ckc byte ff6a read/write t2 clock unit control register t2ctrl byte ff6c read/write t2 timer mode control register t2ictl byte ff6e read/write t2 timer interrupt control register t2iclr byte ff70 read/write t2 timer interrupt clear register mode word ff80 read/write mode control register table 43 device detailed memory map register name size register address (hex) access type contents
127 www.national.com io1ctl word ff82 read/write i/o control register 1 io2ctl word ff84 read/write i/o control register 2 intctl word ff86 read/write interrupt control register intpnd word ff88 read/write interrupt pending register clk1ps word ff8a read/write clock prescaler register 1 count1 word ff8c read/write counter register 1 percap1 word ff8e read/write period/capture register 1 dtycap1 word ff90 read/write duty cycle/capture register 1 count2 word ff92 read/write count register 2 percap2 word ff94 read/write period/capture register 2 dtycap2 word ff96 read/write duty cycle/capture register 2 clk2ps word ff98 read/write clock prescaler register 2 count3 word ff9a read/write count register 3 percap3 word ff9c read/write period/capture register 3 dtycap3 word ff9e read/write duty cycle/capture register 3 count4 word ffa0 read/write count register 4 percap4 word ffa2 read/write period/capture register 4 dtycap4 word ffa4 read/write duty cycle/capture register 4 adcst byte ffc0 read/write a/d converter status register adccnt1 byte ffc2 read/write a/d converter control 1 register adccnt2 byte ffc4 read/write a/d converter control 2 register adccnt3 byte ffc6 read/write a/d converter control 3 register addata0 byte ffca read only a/d converter data 0 register addata1 byte ffcc read only a/d converter data 1 register addata2 byte ffce read only a/d converter data 2 register addata3 byte ffd0 read only a/d converter data 3 register cmpctrl byte ffe0 read/write analog comparator control/status register table 43 device detailed memory map register name size register address (hex) access type contents
www.national.com 128 24.0 register layouts the following tables show the functions of the bit fields of the device registers. for more information on using these register s, see the detailed description of the applicable function elsewhere in this data sheet. 24.1 register layout can memory registers 1514131211109876543210 cmbn.id1 xi28 id10 xi27 id9 xi26 id8 xi25 id7 xi24 id6 xi23 id5 xi22 id4 xi21 id3 xi20 id2 xi19 id1 xi18 id0 srr rtr ide xi17 xi16 xi15 cmbn.id0 xi14 xi13 xi12 xi11 xi10 xi9 xi8 xi7 xi6 xi5 xi4 xi3 xi2 xi1 xi0 rtr cmbn.data0 data 1.7 data 1.6 data 1.5 data 1.4 data 1.3 data 1.2 data 1.1 data 1.0 data 2.7 data 2.6 data 2.5 data 2.4 data 2.3 data 2.2 data 2.1 data 2.0 cmbn.data1 data 3.7 data 3.6 data 3.5 data 3.4 data 3.3 data 3.2 data 3.1 data 3.0 data 4.7 data 4.6 data 4.5 data 4.4 data 4.3 data 4.2 data 4.1 data 4.0 cmbn.data2 data 5.7 data 5.6 data 5.5 data 5.4 data 5.3 data 5.2 data 5.1 data 5.0 data 6.7 data 6.6 data 6.5 data 6.4 data 6.3 data 6.2 data 6.1 data 6.0 cmbn.data3 data 7.7 data 7.6 data 7.5 data 7.4 data 7.3 data 7.2 data 7.1 data 7.0 data 8.7 data 8.6 data 8.5 data 8.4 data 8.3 data 8.2 data 8.1 data 8.0 cmbn.tstp tstp15 tstp14 tstp13 tstp12 tstp11 tstp10 tstp9 tstp8 tstp7 tstp6 tstp5 tstp4 tstp3 tstp2 tstp1 tstp0 cmbn.cntstat dlc3 dlc2 dlc1 dlc0 reserved pri3 pri2 pri1 pri0 st3 st2 st1 st0 can control/ status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cgcr reserved eit diagen internal loopback ignack lo ddir tstpen bufflock crx ctx canen ctim psc[6:0] sjw[1:0] tseg1[3:0] tseg2[2:0] gmskb gm[28:18] rtr ide gm[17:15] gmskx gm[14:0] xrtr bmskb bm[28:18] rtr ide bm[17:15] bmskx bm[14:0] xrtr cien eien ien[14:0] cipnd eipnd ipnd[14:0] ciclr eiclr iclr[14:0] cicen eicen icen[14:0] cstpnd reserved ns[2:0] irq ist[3:0] canec rec[7:0] tec[7:0] cediag reserved drive mon crc stuff txe ebid[5:0] efid[3:0] ctmr ctmr[15:0]
129 www.national.com system configuration registers 76 5 4 3 210 mcfg reserved clk2oe reserved clk1oe clkoe reserved mstat reserved pgmbusy reserved oenv1 oenv0 biu registers 15 12 11 10 9 8 7 6 5 4 3 2 1 0 bcfg reserved ewr iocfg reserved ipst res bw reserved hold wait szcfg0 reserved fre ipre ipst res bw reserved hold wait szcfg1 reserved fre ipre ipst res bw reserved hold wait isp registers15 1312 109 876543210 flctrl1 reserved bootarea flctrl2 empty reserved codearea flsec reserved fromwr fromrd ispkey reserved ispkyval flash data memory registers 15 14 10 9 8 7 6 5 4 3 2 1 0 dmcsr reserved erase dmbusy zerows reserved dmpslr reserved ftdiv dmstart reserved ftstart dmtran reserved fttran dmprog reserved ftprog dmerase reserved fter dmend reserved ftend dmpcnt reserved ftpcnt dmcnt reserved ftcnt dmkey reserved dmkeyval
www.national.com 130 flash eeprom program memory registers 76543210 flcsr merase reserved pmlfull pmbusy pmer reserved flpslr ftdiv flstart ftstart fltran fttran flprog ftprog flerase fter flend ftend flpcnt ftpcnt flcnt1 ftcntl (0:7) flcnt2 reserved ftcntl (8:9) pgmkey pmkeyval gpio registers 7 6 5 4 3 2 1 0 pxalt px pins alternate function enable pxdir px port direction pxdin px port output data pxdout px port input data pxwpu px port weak pull-up enable icu31l registers15 1211 876543210 ivct reserved 0 0 intvect nmistat reserved ext exnmi reserved enlck pin en istat0 ist(15:0) istat1 ist(31:16) ienam0 iena(15:0) ienam1 iena(31:16) idbg reserved irqvect intvect
131 www.national.com miwu16 registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wkedg wked wkena wken wkictl1 wkintr7 wkintr6 wkintr5 wkintr4 wkintr3 wkintr2 wkintr1 wkintr0 wkictl2 wkintr15 wkintr14 wkintr13 wkintr12 wkintr11 wkintr10 wkintr9 wkintr8 wkpnd wkpd wkpcl wkcl dual clock + reset registers 7 6 5 4 3 2 1 0 crctrl reserved por sclk prssc scdiv prssc1 scdiv2 scdiv1 power management register 7 6 5 4 3 2 1 0 pmcsr olfc ohfc wbpsm reserved halt idle dhf psm usart registers76543210 untbuf untbuf unrbuf unrbuf unictrl uneei uneri uneti reserved unrbf untbe unstat reserved unxmip unrb9 unbkd unerr undoe unfe unpe unfrs reserved unpen unpsel unxb9 unstp unchar unmdsl reserved uncks unbrk unatn unmod unbaud undiv[7]: undiv[0] unpsr unpsc undiv[10]: undiv[8] mwspi16 registers 15 9 8 7 6 5 4 3 2 1 0 mwdat mwdat mwctl mcdv midl mskm meiw meir meio mech mmod mmns men mwstat reserved movr mrbf mbsy
www.national.com 132 acb registers765432 1 0 acbsda data acbst slvstp sdast ber negack stastr nmatch master xmit acbcst reserved tgscl tsda gmatch match bb busy acbctl1 stastre nminte gcmen ack reserved inten stop start acbaddr saen addr acbctl2 sclfrq enable timer registers 15 8 7 6 5 4 3 2 1 0 tncnt1 tncnt1 tncra tncra tncrb tncrb tncnt2 tncnt2 tnprsc reserved clkps tnckc reserved c2csel c1csel tnctrl reserved tnaout tnben tnaen tnbedg tnaedg mdsel tnictl tndien tncien tnbien tnaien tndpnd tncpnd tnbpnd tnapnd tniclr reserved tndclr tncclr tnbclr tnaclr
133 www.national.com vtu registers 151413121110 9876543210 mode tmod4 t8run t7run tmod3 t6run t5run tmod2 t4run t3run tmod1 t2run t1run io1ctl p4pol c4edg p3pol c3edg p2pol c2edg p1pol c1edg io2ctl p8pol c8edg p7pol c7edg p6pol c6edg p5pol c5edg intctl i4den i4cen i4ben i4aen i3den i3cen i3ben i3aen i2den i2cen i2ben i2aen i1den i1cen i1ben i1aen intpnd i4dpd i4cpd i4bpd i4apd i3dpd i3cpd i3bpd i3apd i2dpd i2cpd i2bpd i2apd i1dpd i1cpd i1bpd i1apd clk1ps c2prsc c1prsc count1 cnt1 percap1 pcap1 dtycap1 dcap1 count2 cnt2 percap2 pcap2 dtycap2 dcap2 clk2ps c4prsc c3prsc count3 cnt3 percap3 pcap3 dtycap3 dcap3 count4 cnt4 percap4 pcap4 dtycap4 dcap4 twm registers 15 8 7 6 5 4 3 2 1 0 twcfg reserved wdsdme wdct0i lwdcnt ltwmt0 ltwcp ltwcfg twcp reserved mdiv timer0 preset t0csr reserved t0inte tc rst wdcnt preset wdsdm rstdata
www.national.com 134 a/d registers 7 6 5 4 3 2 1 0 adcst reserved bufptr reserved ovf busy eoc adccnt1 reserved reserved inte reserved adcen adccnt2 start scan cont channel adccnt3 reserved pwren delay cdiv a d data 0 r e s u lt 1 data a d data 1 r e s u lt 2 data a d data 2 r e s u lt 3 data a d data 3 r e s u lt 4 data analog comp. registers7 6543210 cmpctrl reserved cmp2oe cmp1oe cmp2en cmp1en cmp2rd cmp1rd
135 www.national.com 25.0 electrical and thermal characteristics absolute maximum ratings if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. note: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electrical specifications are not ensured when operating the device at absolute maximum ratings. * the latch-up tolerance on ac- cess bus pins 14 and 15 exceeds 150ma. thermal characteristics dc electrical characteristics: C40c ta +85c (also supports -40c to +125c) supply voltage (v cc ) 7v voltage at any pin * C0.6v to v cc +0.6v esd protection level 2 kv (human body model) total current into v cc pin (source) 200 ma total current out of gnd pin (sink) 200 ma storage temperature range C65c to +150c characteristics symbol value unit average junction temperature t j t a + (p d x ~ ja )c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 80-pin quad flat pack (qfp) ~ ja 49.8 c/w total power dissipation 1 p d p int + p i/o or k t j + 273c w device internal power dissipation p int i dd x v dd w i/o pin power dissipation 2 p i/o user-determined w a constant 3 k p d x (t a + 273c) + ~ ja x p d 2 w, c 1. this is an approximate value, neglecting p i/o . 2. for most applications p i/o << p int and can be neglected. 3. k is a constant pertaining to the device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j iterntively for any value of t a . symbol parameter conditions min max units operating voltage 4.5 5.5 v v ih logical 1 cmos input voltage (except acb & clocks) 0.8vcc vcc + 0.5 v v il logical 0 cmos input voltage (except acb & clocks) -0.5 0.2vcc v v ihacb sda, scl logical 1 cmos input voltage 0.7vcc v v ilacb sda, scl logical 0 cmos input voltage 0.3vcc v vxl low level input voltage osc external x1 clock 0 0.2vcc v vxh high level input voltage osc external x1 clock 0.5vcc vcc v vxl2 x2cki logical 0 input voltage external x2 clock 0.3 v vxh2 x2cki logical 1 input voltage external x2clock 1.2 v v hys hysteresis loop width a 0.1vcc v i oh logical 1 cmos output current v oh = 3.8v, vcc=4.5v -1.6 ma i ol logical 0 cmos output current v ol = 0.45v, vcc=4.5v 1.6 ma
www.national.com 136 a/d converter characteristics v cc = 5v, ta = 25c i olacb sda, scl logical 0 cmos output current v ol = 0.4v, vcc=4.5v 3.0 ma i ohw weak pull-up current v oh = 3.8v, vcc=4.5v -10 m a i il reset pin weak pull-down current v il = 0.9v, vcc=4.5v 0.4 m a i l high impedance input leakage current 0v vin vcc - 2.0 2.0 j m a i o (off) output leakage current (i/o pins in input mode) 0v vout vcc - 2.0 2.0 j m a icca1 digital supply current active mode b vcc= 5.5v 115 ma iccprog digital supply current active mode c vcc= 5.5v 138 ma icca2 digital supply current active mode d vcc = 5.5v 70 ma iccps digital supply current power save mode e vcc= 5.5v 11 ma iccid digital supply current idle mode f vcc = 5.5v 200 m a iccq digital supply current halt mode f vcc = 5.5v 24 k m a iacc analog supply current active mode g vcc= 5.5v 3.6 ma a. guaranteed by design b. run from internal memory, iout=0ma, x1cki=24mhz, not programming flash memory c. same conditions as icca1 but programming or erasing one of the flash memory arrays d. cpu executing an wait instruction, iout=0ma, x1cki=24mhz, peripherals not active e. running from internal memory, iout=0ma, x1cki=24mhz, x2cki=32.768khz f. iout=0ma, x1cki=vcc, x2cki=32.768khz g. adc and analog comparators enabled j. i l adn i o are 2.0 m a at 85c and 5.0 m a at 125c k. i ccq is 24 m a at 85c and 60 m a at 125c symbol parameter conditions a a. all parameters specified for f osc =2 mhz, v dd = 5.0v 10% unless otherwise noted. min typ max units n il integral error b b. integral (non-linearity) error the maximum difference between the best-fit straight line reference and the actual conversion curves. v ref = v cc 0.5 lsb n dl differential error c c. differential (non-linearity) error the maximum difference between the best-fit step size of 1 lsb and any actual step size. v ref = v cc 1.0 lsb v absolute absolute error v ref = v cc 1.5 lsb v in input voltage range v ref < v cc - 0.1 0 v ref v v refex external reference voltage 3.0 v dd v i vref v ref input current v ref = 5v 1.2 ma i al analog input leakage current v ref = v cc 1 m a r ain analog input resistance d d. the resistance between the device input and the internal analog input capacitance. 200 w c ain analog input capacitance e e. the input signal is measured across the internal capacitance. f. conversion result never decreases with an increase in input voltage and has no missing codes. 5pf t adcclk conversion clock period 500 ns c refex external vref bypass capacitance 0.47 m f t act first conversion after vcc stable 30 m s m monotonic monotonicity f guaranteed symbol parameter conditions min max units
137 www.national.com analog comparator characteristics flash eeprom program memory programming symbol parameter conditions min typ max units v os input offset voltage vcc = 5v, 0.4v v in v cc C 1.5v 25 mv v cm input common mode voltage range 0.4 v cc -1.5 v i cs dc supply current per comparator (when enabled) v cc =5.5v 250 m a response time 1v step / 100mv overdrive 1 m s symbol parameter conditions min max units t pwp programming pulse width a a. the programming pulse width is determined by the following equation: t pwp = t clk x (ftdiv+1) x (ftprog+1), where t clk is the system clock period, ftdiv is the contents of the flpslr register and ftprog is the contents of the flprog register. 30 40 m s t ewp erase pulse width b b. the erase pulse width is determined by the following equation: t ewp = t clk x (ftdiv+1) x 4 x (fter+1), where t clk is the system clock period, ftdiv is the contents of the flpslr register and fter is the contents of the flerase register. 4-ms t sdp charge pump power-up delay c c. the program/erase start delay time is determined by the following equation: t sdp = t clk x (ftdiv+1) x (ftstart+1), where t clk is the system clock period, ftdiv is the contents of the flpslr register and ftstart is the contents of the flstart register. 10 - m s t ttp program/erase transition time d d. the program/erase transition time is determined by the following equation: t ttp = t clk x (ftdiv+1) x (fttran+1), where t clk is the system clock period, ftdiv is the contents of the flpslr register and fttran is the contents of the fltran register. 5- m s t pa h programming address hold, new address setup time 2-clock cycles t pep charge pump enable hold time 1 - clock cycles t edp charge pump power hold time e e. the program/erase end delay time is determined by the following equation: t edp = t clk x (ftdiv+1) x (ftend+1), where t clk is the system clock period, ftdiv is the contents of the flpslr register and ftend is the contents of the flend register. 5 m s t chvp cumulative program high voltage period for each row after erase. f f. cumulative program high voltage period for each row after erase t chvp is the accumulated duration a flash cell is exposed to the programming voltage after the last erase cycle. it is the sum of all t hv after the last erase. -25ms data retention 100 - years - 100k cycles
www.national.com 138 flash eeprom data programming flash eeprom isp-memory programming symbol parameter conditions min max units re-programming time a a. one re-programming cycle involves one erase pulse followed by programming of four bytes. 1.32 - ms t pwd programming pulse width b b. the programming pulse width is determined by the following equation: t pwd = t clk x (ftdiv+1) x (ftprog+1), where t clk is the system clock period, ftdiv is the contents of the dmpslr register and ftprog is the contents of the dmprog register. 30 40 m s t ewd erase pulse width c c. the erase pulse width is determined by the following equation: t ewd = t clk x (ftdiv+1) x 4 x (fter+1), where t clk is the system clock period, ftdiv is the contents of the dmpslr register and fter is the contents of the dmerase register. 4-ms t sdd charge pump power-up time d d. the program/erase start delay time is determined by the following equation: t sdd = t clk x (ftdiv+1) x (ftstart+1), where t clk is the system clock period, ftdiv is the contents of the dmpslr register and ftstart is the contents of the dmstart register. 10 - m s t ttd program/erase transition time e e. the program/erase transition time is determined by the following equation: t ttd = t clk x (ftdiv+1) x (fttran+1), where t clk is the system clock period, ftdiv is the contents of the dmpslr register and fttran is the contents of the dmtran register. 5- m s t ped charge pump enable hold time 1 - clock cycles t edd charge pump power hold time f f. the program/erase end delay time is determined by the following equation: t edd = t clk x (ftdiv+1) x (ftend+1), where t clk is the system clock period, ftdiv is the contents of the dmpslr register and ftend is the contents of the dmend register. 5- m s write/erase endurance (high endurance) 100,000 - cycles write/erase endurance (low endurance) 25,000 - cycles data retention 100 - years symbol parameter conditions min max units t pwi programming pulse with a a. programming timing is controlled by the flash eeprom data memory interface 30 40 m s t ewi erase pulse width b b. erase timing is controlled by the flash eeprom data memory interface 4-ms data retention 100 - years - 100k cycles
139 www.national.com output signal levels all output signals are powered by the digital supply (v cc ). table 44 summarizes the states of the output signals during the reset state (when v cc power exists in the reset state) and during the power save mode. the reset and nmi input pins are active during the power save mode. in order to guarantee that the power save cur- rent not exceed 1ma, these inputs must be driven to a volt- age lower than 0.5v or higher than v cc -0.5v. an input voltage between 0.5v and (v cc -0.5v) may result in power consumption exceeding 1 ma. t sd t tt t pw t pw t pe t ed t pp row select/ start charge pump select charge pump/ programming pulse figure 76. flash eeprom memory programming timing (sample sequence for programming two words into flash eeprom program memory enable programming vo lt a ge table 44 output pins during reset and power-save signals on a pin reset state (with vcc) power save mode comments pf[0:7] tri-state previous state i/o ports will maintain their values when entering power-save mode pg[0:7] tri-state previous state pi[0:7] tri-state previous state pl[0:7] tri-state previous state pb[0:7] tri-state previous state pc[0:7] tri-state previous state
www.national.com 140 25.0.1 timing waveforms figure 77. clock waveforms ac-1 t clkp clk t clkh t clkl t clkf t clkr output valid output hold output signal input signal input setup input hold control signal 1 control signal 2 output active/inactive time output active/inactive time t x2h t x2l x2 t x2p t x1h t x1l x1 t x1p
141 www.national.com figure 78. ise & nmi signal timing figure 79. non-power-on reset figure 80. usart asynchronous mode timing figure 81. usart synchronous mode timing clk ise nmi t ih t is t ih t is t iw t iw clk reset t rst clk txdn 1 2 1 2 1 2 1 2 1 2 1 2 t is t ih rxdn t cov1 t cov1 ckxn txdn rxdn t clkx t txd t rxs t rxh
www.national.com 142 figure 82. port signals timing figure 83. microwire transaction timing, normal mode, midl bit = 0 clk buzclk ports b, c (output) 1 2 1 2 1 2 1 2 1 2 1 2 t cov2 t cov2 t is t ih t cov1 t of ports b, c (input) t cov1 msb t mskp t mskh t mskl t mdis t mdih t mcss t mdof mskn data in mdidon mcsn lsb lsb t mdof t mdov t mdoh msb t msks t mskhd t mcsh (slave) mdodin (slave) (master) lsb msb t mskd
143 www.national.com figure 84. microwire transaction timing, normal mode, midl bit = 1 figure 85. microwire transaction timing, alternate mode, midl bit = 0 msb t mskp t mskl t mskh t mdis t mdih t mcss t mdof mskn data in mdidon mcsn lsb t mdof t mdov t mdoh t msks t mskhd t mcsh (slave) mdodin (slave) (master) msb msb lsb lsb t mskh t mskl t mdis t mdih t mcss mskn data in mdidon mcsn t msks t mskhd t mcsh (slave) t mskp msb lsb t mdof t mdof t mdov t mdoh (slave) mdodin (master) msb lsb msb lsb
www.national.com 144 figure 86. microwire transaction timing, alternate mode, midl bit = 1 figure 87. microwire transaction timing, data echoed to output, normal mode, midl bit = 0, mech bit = 1, slave t mskp t mskl t mskh t mdis t mdih t mcss t mdof mskn mdidon mcsn t mdof t mcsh t mdov t mdoh t msks t mskhd (slave only) lsb msb (slave) mdodin (master) msb lsb msb lsb t skd data in t mskp t mskh t mskl t mdih t mcss t mdonf mskn mdodin mdidon mcsn di lsb t mdof do msb t msks t mskhd t mcsh t mitop t mitop t mdis di msb (slave) (slave) do lsb
145 www.national.com figure 88. acb signals (sda and scl) rise time and fall timing figure 89. acb start and stop condition timing sda t sdar 0.7v cc 0.3v cc t sdaf 0.7v cc 0.3v cc scl t sclr 0.7v cc 0.3v cc t sclf 0.7v cc 0.3v cc note: in the timing tables the parameter name is added with an o for output signal timing and i for input signal timing. sda scl t cstos t buf t dlcs t cstrh start condition stop condition note: in the timing tables the parameter name is added with an o for output signal timing and i for input signal timing.
www.national.com 146 figure 90. acb start conditioning timing figure 91. acb data bits timing figure 92. versatile-timer-unit input timing figure 93. versatile-timer-unit input timing sda scl t cstrs t dhcs start condition t cstrh note: in the timing tables the parameter name is added with an o for output signal timing and i for input signal timing. scl sda t dlcso t sclhigho t scllowo t sdavo t sdaho note: in the timing tables the parameter name is added with an o for output signal timing and i for input signal timing unless the parameter alresdy includes the suffix. clk tiox t tiol t tioh clk tiox t tiol t tioh
147 www.national.com 25.0.2 timing tables table 45 output signals symbol figure description reference min (ns) max (ns) tclk a 77 clk clock period r.e. clk to next r.e. clk 44.67 64000 a t clkh 77 clk high time at 2.0v (both edges) 17.87 t clkl 77 clk low time at 0.8v (both edges) 17.87 t clkr 77 clk rise time on r.e. clk 0.8v to 2.0v 3 t clkf 77 clk fall time on f.e. clk 2.0v to 0.8v 3 t cov1 cmos output valid all signals with prop. delay from clk r.e. after r.e. clk 35 usart output signals t txd 84 txdn output valid after r.e. clkxn 35 microwire / spi output signals t mskh 86 microwire clock high at 2.0v (both edges) 80 t mskl 86 microwire clock low at 0.8v (both edges) 80 t mskp 86 microwire clock period mnidl bit = 0: r.e. msk to next r.e. mskn 200 87 mnidl bit = 1: f.e. msk to next f.e. mskn t mskd 86 msk leading edge delayed (master only) data out bit #7 valid 0.5 t msk 1.5 t msk t mdof 86 microwire data float b (slave only) after r.e. mcsn 56 t mdoh 86 microwire data out hold normal mode: after f.e. msk 0.0 alternate mode: after r.e. msk t mdonf 90 microwire data no float (slave only) after f.e. mwcs 056 t mdov 86 microwire data out valid normal mode: after f.e. msk 56 alternate mode: after r.e. msk t mitop mdodi to mdido (slave only) propagation time value is the same in all clocking modes of the microwire 56 90 can output signals t cantx cantx output valid after r.e. clkxn 13 access.bus output signals t bufo 89 bus free time between stop and start condition t sclhigho t cstoso 89 scl setup time before stop condition t sclhigho t cstrho 89 scl hold time after start condition t sclhigho t cstrso 90 scl setup time before start condition t sclhigho t dhcso 90 data high setup time before scl r.e. t sclhigho -t sdaro t dlcso 89 data low setup time before scl r.e. t sclhigho -t sdafo t sclfo 88 scl signal fall time 300 c t sclro 88 scl signal rise time - d t scllowo 91 scl low time after scl f.e. k*t clk - 1 e t sclhigho 91 scl high time after scl r.e. k*t clk - 1 e
www.national.com 148 t sdafo 88 sda signal fall time 300 t sdaro 88 sda signal rise time - t sdaho 91 sda hold time after scl f.e. 7*t clk - t sclfo t sdavo 91 sda valid time after scl f.e. 7*tclk+ trd a. tclk is the actual clock period of the cpu clock used in the system. the value of tclk is system dependent. the maximum cycle time of 64000ns is for power save mode; in active mode, the maximum cycle time is limited to 250ns by the high frequency oscillator. b. guaranteed by design, but not fully tested. c. assuming signals capacitance up to 400pf. d. depends on the signals capacitance and the pull-up value. must be less than 1ms. e. k is as defined in acbctl2.sclfrq. table 46 input signal requirements symbol figure description reference min (ns) max (ns) t x1p 77 x1 period r.e. x1 to next r.e. x1 41.67 t x1h 77 x1 high time, external clock at 2v level (both edges) 0.5 tclk - 4 t x1l 77 x1 low time, external clock at 0.8v level (both edges) 0.5 tclk - 4 t x2p 77 x2 period a r.e. x2 to next r.e. x2 10,000 t x2h 77 x2 high time, external clock at 2v level (both edges) 0.5 tclk - 500 t x2l 77 x2 low time, external clock at 0.8v level (both edges) 0.5 tclk - 500 t is 81 input setup time ise before r.e. clk 12 t ih 81 input hold time ise , nmi , rxd1, rxd2 after r.e. clk 0 t rst 82 reset time reset active to reset end 4tclk input signals input pulse width 1*tclk+13 usart input signals t is 80 input setup time rxdn (asynchronous mode) before r.e. clk 12 t ih 80 input hold time rxdn (asynchronous mode) after r.e. clk 0 t clkx 81 ckxn input period (synchronous mode) 200 t rxs 81 rdxn setup time (synchronous mode) before f.e. ckx in synchronous mode 4 t rxh 81 rdxn hold time (synchronous mode) after f.e. ckx in synchronous mode 2 microwire / spi input signals t mskh 83 microwire clock high at 2.0v (both edges) 80 t mskl 83 microwire clock low at 0.8v (both edges) 80 t mskp 83 microwire clock period mnidl bit = 0; r.e. msk to next r.e. msk 200 84 midl bit = 1; f.e. msk to next f.e. msk t mskh 83 msk hold (slave only) after mcs becomes inactive 40 t msks 83 msk setup (slave only) before mcs becomes active 80 table 45 output signals symbol figure description reference min (ns) max (ns)
149 www.national.com t mcsh 83 mcs hold (slave only) midl bit = 0: after f.e. msk 40 84 midl bit = 1: after r.e. msk t mcss 83 mcs setup (slave only) midl bit = 0: before r.e. msk 80 84 midl bit = 1: before f.e. msk t mdih 83 microwire data in hold (master) normal mode: after r.e. msk 0 85 alternate mode: after f.e. msk 83 microwire data in hold (slave) normal mode: after r.e. msk 40 85 alternate mode: after f.e. msk t mdis 83 microwire data in setup normal mode: before r.e. msk 80 85 alternate mode: before f.e. msk can input signals t is canrx input setup time) before r.e. clk 12 t ih canrx input hold time after r.e. clk 0 access.bus input signals t bufi 89 bus free time between stop and start condition t sclhigho t cstosi 89 scl setup time before stop condition 8*t clk - t sclri t cstrhi 89 scl hold time after start condition 8*t clk - t sclri t cstrsi 90 scl setup time before start condition 8*t clk - t sclri t dhcsi 90 data high setup time before scl r.e. 2*t clk t dlcsi 89 data low setup time before scl r.e. 2*t clk t sclfi 88 scl signal rise time 300 t sclri 88 scl signal fall time 1000 t scllowi 91 scl low time after scl f.e. 16*t clk t sclhighi 91 scl high time after scl r.e. 16*t clk t sdari 88 sda signal rise time 300 t sdafi 88 sda signal fall time 1000 t sdahi 91 sda hold time after scl f.e. 0 t sdasi 91 sda setup time before scl r.e. 2*t clk multi-function timer input signals ttah 92 tna high time r.e. clk t clk +5 ttal 92 tna low time r.e. clk t clk +5 ttbh 92 tnb high time r.e. clk t clk +5 ttbl 92 tnb low time r.e. clk t clk +5 versatile timer input signals ttioh 96 tiox input high time re clk 1.5t clk +5ns ttiol 96 tiox input low time re clk 1.5t clk +5ns a. only when operating with an external square wave on x2cki; otherwise a 32khz crystal network must be used between x2cki and x2cko. if the slow clock is internally generated from the fast clock, it may not exceed this given limit. table 46 input signal requirements symbol figure description reference min (ns) max (ns)
www.national.com 150 26.0 appendix the following document describes problems identified in the cr16 modules. 26.1 8/16-bit microwire/spi (mwspi16) 26.1.1 mwspi16 problem description according to the specification, the mskn clock output in mas- ter mode should have the value of the mnidl bit of the mwnctl register, even when the module is disabled. how- ever, the mskn pin is enabled and the module is disabled. thus, even if the mnidl bit is set, the mskn clock will change to a low level as soon as the module is disabled. if any slave is selected at this time, i will interpret this unwanted transition as a shift clock. 26.1.2 mwspi16 problem cause even if the module is disabled and the alternate function of the mskn pin is enabled, the module can st ill infl uence the mskn pin and drives the default value 0. 26.1.3 mwspi16 problem solutions when the mskn idle level of 1 is to be used, the following procedure should be followed when the module is disabled: 1. set the mskn pin to high level in the corresponding port data output register. 2. configure the mskn pin to an output in the correspond- ing port direction register. 3. disable the alternate function of the mskn pin in the cor- responding port alternate function register. 4. disable the mwspi16 module. 26.2 timing and watchdog module 26.2.1 timing and watchdog module problem description the available window for a valid watchdog service varies with the twm configuration and the operating mode of the r16mcs9. therefore it is not possible to generally provide the limits for the maximum service window. however, the lim- its for the minimum service window is guaranteed and should be used. 26.2.2 timing and watchdog module problem cause the timing and watchdog module uses two different clock signals for its operation, the slow system clock as well as the fast system clock. the slow system clock can either be generated by an exter- nal 32 khz quartz or it can be derived from the fast system clock by means of a prescaler counter in the clk2res mod- ules. the twm can operate off a maximum slow system clock of 100 khz. the watchdog counter (down-counter) is either clocked directly by the slow system (t0in) or it is decremented every time the counter t0 underflows (t0out). the fast system clock is used for accesses to twm registers, which build the user interface of the twm. these user inter- face registers include all memory-mapped registers of the twm. every time the user (cr16b core) writes to a twm configu- ration register or to the watchdog service data match reg- ister, this high speed operation must be synchronized to the internal twm logic running at the slow clock rate. this syn- chronization process takes a variable number of low speed clock cycles, depending on the ratio between the low-speed and the high-speed system clock and the phase shift be- tween the two clock signals. the more the two frequencies differ from each other, the longer it takes the synchronization process. in other words, write operations to the twm registers take a certain number of low-speed clock cycles to show the desired effects to the twm logic. this fact is especially critical for the write operation for the watchdog service, as it affects the allowed window for a valid watchdog service. if the device runs in active mode, the synchronization pro- cess can take up to four watchdog counter clock cycles. this limits the available watchdog service to the window shown in figure 94: if the device runs in power save mode, the synchronization process can take up to eight watchdog counter clock cy- cles. this limits the available watchdog service to the win- dow shown in figure 95: figure 94. watchdog services windows in active mode
151 www.national.com 26.2.3 timing and watchdog module problem solutions in order to guarantee a valid watchdog service under all circumstances, the watchdog should only be serviced within the guaranteed minimum valid window, as illustrated in figure 94 and figure 95 in the previous section. figure 95. watchdog services windows in power save mode
www.national.com 152 27.0 device pinouts the cr16mct9/cr16mct5/cr16hct9/cr16hct5 are available in the 80-pin pqfp packa g e. fi g ure 96 shows the pin assi g nments for this packa g e. figure 96. 80-pin pqfp package connection diagram top view order number cr16mct9vjex, cr16mct9vjexy, cr16mct5vjexy, see ns package number vje80a 41 x2cko x2cki pi0 vcc gnd pf1 pi1 pi3 gnd pf0 reset x1cko x1cki pi2 61 1 21 pf4 pf3 pf2 agnd/nc vref/nc pi7 gnd avcc/nc pl4 pi6 vcc pl1 pl0 pl3 gnd pl7 pl6 pl5 sda scl vcc pb7 env0 ph7 gnd canrx pb6 pb0 pb1 pb3 pb4 cantx ph4 ph5 ph6 gnd pb2 pb5 pl2 pc7 pc4 pi5 pi4 nmi ph0 ph3 ph2 ph1 pg2 pg1 pg0 pg4 pg3 pf7 pf5 pg5 pg7 pg6 pf6 env1 pc3 pc0 pc1 pc2 pc5 pc6 ? suffix x in the nsid is defined below: temperature ran g es: x = 7 is -40 c to +125 c = 8 is -40 c to +85 c = 9 is 0 c to +70 c ? suffix y in the nsid defines the rom code. cr16hct9vjex, cr16hct9vjexy, cr16hct5vjexy,
national semiconductor corporation tel: 1-800-272-9959 fax: 1-800-737-7018 email: support@nsc.com national semiconductor europe fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 francais tel: +33 (0) 1 41 91 8790 national semiconductor japan ltd. tel: 81-3-5639-7560 fax: 81-3-5639-7507 www.national.com national semiconductor asia pacific customer response group tel: 65-254-4466 fax: 65-250-4466 email: ap.support@nsc.com 28.0 ph y sical dimensions inches (millimeters) unless otherwise noted 80 lead molded plastic quad flat package order number cr16mct9vjex, cr16mct9vjexy, or cr16mct5vjexy, see ns package number vje80a cr16hct9vjex, cr16hct9vjexy, or cr16hct5vjexy

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